celox 0.11.0

Celox HDL Simulator
Documentation 
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#[path = "test_utils/mod.rs"]
#[macro_use]
mod test_utils;

all_backends! {

    // Dual-port RAM: write via port A, read via port B (BUFFER_OUT=false, combinational read)
    fn test_ram_write_read(sim) {
        @case "std_ram::test_ram_write_read";
    }

    // Overwrite same address and verify latest value
    fn test_ram_overwrite(sim) {
        @case "std_ram::test_ram_overwrite";
    }

    // RAM with USE_RESET=true: clear via i_clr
    fn test_ram_reset_and_clear(sim) {
        @case "std_ram::test_ram_reset_and_clear";
    }
}