celox 0.10.1

Celox HDL Simulator
Documentation 
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#[test(Top)]
module Top {
    inst clk: $tb::clock_gen;
    var observed: logic<8>;
    initial {
        clk.next(4);
        $assert(observed == 8'd3);
        $finish();
    }
    initial {
        observed = 0;
        for _i in 0..3 {
            clk.next(1);
            observed += 1;
        }
        clk.next(2);
        $assert(1'd0, "finish must stop every process");
    }
}