pub mod backend;
mod error;
mod event_buffer;
pub mod parallel;
mod reflection;
pub mod scheduler;
mod simulation;
mod state_file;
mod testbench;
mod vcd;
pub use error::{SimulatorErrorCode, comb_fatal_code, comb_fatal_site};
pub use event_buffer::RuntimeEventBuffer;
pub use reflection::{
DesignReflection, ReflectionScope, ReflectionScopeId, ReflectionSignal, ReflectionSignalId,
SignalDirection,
};
pub use simulation::{
EventInfo, ProcessRefs, ScheduleParts, SimulationExecutor, SimulationSnapshot, SimulationState,
};
pub use state_file::{
ScheduleRecord, ScheduledEvent, StateDifference, StateFile, StateFileError, StateObject,
StateRole, format_state_value,
};
pub use testbench::bind_testbench_program;
pub use vcd::{VcdExternalSignalDesc, VcdSignalDesc, VcdStatistics, VcdWriter};
pub type AbsoluteAddr = celox_design::StateAddr;
pub type MemoryLayout = celox_state_layout::MemoryLayout<AbsoluteAddr>;
#[derive(
Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, serde::Serialize, serde::Deserialize,
)]
pub struct SignalArrayLayout {
pub element_width: usize,
pub element_count: usize,
pub element_stride: usize,
pub plane_size: usize,
}
#[derive(
Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, serde::Serialize, serde::Deserialize,
)]
pub struct SignalRef {
pub offset: usize,
pub width: usize,
pub is_4state: bool,
pub array_layout: Option<SignalArrayLayout>,
}