#[doc = "Register `ADC12CTL0` reader"]
pub type R = crate::R<Adc12ctl0Spec>;
#[doc = "Register `ADC12CTL0` writer"]
pub type W = crate::W<Adc12ctl0Spec>;
#[doc = "Field `ADC12SC` reader - ADC12 Start Conversion"]
pub type Adc12scR = crate::BitReader;
#[doc = "Field `ADC12SC` writer - ADC12 Start Conversion"]
pub type Adc12scW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12ENC` reader - ADC12 Enable Conversion"]
pub type Adc12encR = crate::BitReader;
#[doc = "Field `ADC12ENC` writer - ADC12 Enable Conversion"]
pub type Adc12encW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12TOVIE` reader - ADC12 Timer Overflow interrupt enable"]
pub type Adc12tovieR = crate::BitReader;
#[doc = "Field `ADC12TOVIE` writer - ADC12 Timer Overflow interrupt enable"]
pub type Adc12tovieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12OVIE` reader - ADC12 Overflow interrupt enable"]
pub type Adc12ovieR = crate::BitReader;
#[doc = "Field `ADC12OVIE` writer - ADC12 Overflow interrupt enable"]
pub type Adc12ovieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12ON` reader - ADC12 On/enable"]
pub type Adc12onR = crate::BitReader;
#[doc = "Field `ADC12ON` writer - ADC12 On/enable"]
pub type Adc12onW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12REFON` reader - ADC12 Reference on"]
pub type Adc12refonR = crate::BitReader;
#[doc = "Field `ADC12REFON` writer - ADC12 Reference on"]
pub type Adc12refonW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12REF2_5V` reader - ADC12 Ref 0:1.5V / 1:2.5V"]
pub type Adc12ref2_5vR = crate::BitReader;
#[doc = "Field `ADC12REF2_5V` writer - ADC12 Ref 0:1.5V / 1:2.5V"]
pub type Adc12ref2_5vW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12MSC` reader - ADC12 Multiple SampleConversion"]
pub type Adc12mscR = crate::BitReader;
#[doc = "Field `ADC12MSC` writer - ADC12 Multiple SampleConversion"]
pub type Adc12mscW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 Sample Hold 0 Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12sht0 {
#[doc = "0: ADC12 Sample Hold 0 Select Bit: 0"]
Adc12sht0_0 = 0,
#[doc = "1: ADC12 Sample Hold 0 Select Bit: 1"]
Adc12sht0_1 = 1,
#[doc = "2: ADC12 Sample Hold 0 Select Bit: 2"]
Adc12sht0_2 = 2,
#[doc = "3: ADC12 Sample Hold 0 Select Bit: 3"]
Adc12sht0_3 = 3,
#[doc = "4: ADC12 Sample Hold 0 Select Bit: 4"]
Adc12sht0_4 = 4,
#[doc = "5: ADC12 Sample Hold 0 Select Bit: 5"]
Adc12sht0_5 = 5,
#[doc = "6: ADC12 Sample Hold 0 Select Bit: 6"]
Adc12sht0_6 = 6,
#[doc = "7: ADC12 Sample Hold 0 Select Bit: 7"]
Adc12sht0_7 = 7,
#[doc = "8: ADC12 Sample Hold 0 Select Bit: 8"]
Adc12sht0_8 = 8,
#[doc = "9: ADC12 Sample Hold 0 Select Bit: 9"]
Adc12sht0_9 = 9,
#[doc = "10: ADC12 Sample Hold 0 Select Bit: 10"]
Adc12sht0_10 = 10,
#[doc = "11: ADC12 Sample Hold 0 Select Bit: 11"]
Adc12sht0_11 = 11,
#[doc = "12: ADC12 Sample Hold 0 Select Bit: 12"]
Adc12sht0_12 = 12,
#[doc = "13: ADC12 Sample Hold 0 Select Bit: 13"]
Adc12sht0_13 = 13,
#[doc = "14: ADC12 Sample Hold 0 Select Bit: 14"]
Adc12sht0_14 = 14,
#[doc = "15: ADC12 Sample Hold 0 Select Bit: 15"]
Adc12sht0_15 = 15,
}
impl From<Adc12sht0> for u8 {
#[inline(always)]
fn from(variant: Adc12sht0) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12sht0 {
type Ux = u8;
}
impl crate::IsEnum for Adc12sht0 {}
#[doc = "Field `ADC12SHT0` reader - ADC12 Sample Hold 0 Select Bit: 0"]
pub type Adc12sht0R = crate::FieldReader<Adc12sht0>;
impl Adc12sht0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12sht0 {
match self.bits {
0 => Adc12sht0::Adc12sht0_0,
1 => Adc12sht0::Adc12sht0_1,
2 => Adc12sht0::Adc12sht0_2,
3 => Adc12sht0::Adc12sht0_3,
4 => Adc12sht0::Adc12sht0_4,
5 => Adc12sht0::Adc12sht0_5,
6 => Adc12sht0::Adc12sht0_6,
7 => Adc12sht0::Adc12sht0_7,
8 => Adc12sht0::Adc12sht0_8,
9 => Adc12sht0::Adc12sht0_9,
10 => Adc12sht0::Adc12sht0_10,
11 => Adc12sht0::Adc12sht0_11,
12 => Adc12sht0::Adc12sht0_12,
13 => Adc12sht0::Adc12sht0_13,
14 => Adc12sht0::Adc12sht0_14,
15 => Adc12sht0::Adc12sht0_15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 0"]
#[inline(always)]
pub fn is_adc12sht0_0(&self) -> bool {
*self == Adc12sht0::Adc12sht0_0
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 1"]
#[inline(always)]
pub fn is_adc12sht0_1(&self) -> bool {
*self == Adc12sht0::Adc12sht0_1
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 2"]
#[inline(always)]
pub fn is_adc12sht0_2(&self) -> bool {
*self == Adc12sht0::Adc12sht0_2
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 3"]
#[inline(always)]
pub fn is_adc12sht0_3(&self) -> bool {
*self == Adc12sht0::Adc12sht0_3
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 4"]
#[inline(always)]
pub fn is_adc12sht0_4(&self) -> bool {
*self == Adc12sht0::Adc12sht0_4
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 5"]
#[inline(always)]
pub fn is_adc12sht0_5(&self) -> bool {
*self == Adc12sht0::Adc12sht0_5
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 6"]
#[inline(always)]
pub fn is_adc12sht0_6(&self) -> bool {
*self == Adc12sht0::Adc12sht0_6
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 7"]
#[inline(always)]
pub fn is_adc12sht0_7(&self) -> bool {
*self == Adc12sht0::Adc12sht0_7
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 8"]
#[inline(always)]
pub fn is_adc12sht0_8(&self) -> bool {
*self == Adc12sht0::Adc12sht0_8
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 9"]
#[inline(always)]
pub fn is_adc12sht0_9(&self) -> bool {
*self == Adc12sht0::Adc12sht0_9
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 10"]
#[inline(always)]
pub fn is_adc12sht0_10(&self) -> bool {
*self == Adc12sht0::Adc12sht0_10
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 11"]
#[inline(always)]
pub fn is_adc12sht0_11(&self) -> bool {
*self == Adc12sht0::Adc12sht0_11
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 12"]
#[inline(always)]
pub fn is_adc12sht0_12(&self) -> bool {
*self == Adc12sht0::Adc12sht0_12
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 13"]
#[inline(always)]
pub fn is_adc12sht0_13(&self) -> bool {
*self == Adc12sht0::Adc12sht0_13
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 14"]
#[inline(always)]
pub fn is_adc12sht0_14(&self) -> bool {
*self == Adc12sht0::Adc12sht0_14
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 15"]
#[inline(always)]
pub fn is_adc12sht0_15(&self) -> bool {
*self == Adc12sht0::Adc12sht0_15
}
}
#[doc = "Field `ADC12SHT0` writer - ADC12 Sample Hold 0 Select Bit: 0"]
pub type Adc12sht0W<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12sht0, crate::Safe>;
impl<'a, REG> Adc12sht0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Sample Hold 0 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht0_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_0)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 1"]
#[inline(always)]
pub fn adc12sht0_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_1)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 2"]
#[inline(always)]
pub fn adc12sht0_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_2)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 3"]
#[inline(always)]
pub fn adc12sht0_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_3)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 4"]
#[inline(always)]
pub fn adc12sht0_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_4)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 5"]
#[inline(always)]
pub fn adc12sht0_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_5)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 6"]
#[inline(always)]
pub fn adc12sht0_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_6)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 7"]
#[inline(always)]
pub fn adc12sht0_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_7)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 8"]
#[inline(always)]
pub fn adc12sht0_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_8)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 9"]
#[inline(always)]
pub fn adc12sht0_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_9)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 10"]
#[inline(always)]
pub fn adc12sht0_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_10)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 11"]
#[inline(always)]
pub fn adc12sht0_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_11)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 12"]
#[inline(always)]
pub fn adc12sht0_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_12)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 13"]
#[inline(always)]
pub fn adc12sht0_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_13)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 14"]
#[inline(always)]
pub fn adc12sht0_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_14)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 15"]
#[inline(always)]
pub fn adc12sht0_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_15)
}
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12sht1 {
#[doc = "0: ADC12 Sample Hold 1 Select Bit: 0"]
Adc12sht1_0 = 0,
#[doc = "1: ADC12 Sample Hold 1 Select Bit: 1"]
Adc12sht1_1 = 1,
#[doc = "2: ADC12 Sample Hold 1 Select Bit: 2"]
Adc12sht1_2 = 2,
#[doc = "3: ADC12 Sample Hold 1 Select Bit: 3"]
Adc12sht1_3 = 3,
#[doc = "4: ADC12 Sample Hold 1 Select Bit: 4"]
Adc12sht1_4 = 4,
#[doc = "5: ADC12 Sample Hold 1 Select Bit: 5"]
Adc12sht1_5 = 5,
#[doc = "6: ADC12 Sample Hold 1 Select Bit: 6"]
Adc12sht1_6 = 6,
#[doc = "7: ADC12 Sample Hold 1 Select Bit: 7"]
Adc12sht1_7 = 7,
#[doc = "8: ADC12 Sample Hold 1 Select Bit: 8"]
Adc12sht1_8 = 8,
#[doc = "9: ADC12 Sample Hold 1 Select Bit: 9"]
Adc12sht1_9 = 9,
#[doc = "10: ADC12 Sample Hold 1 Select Bit: 10"]
Adc12sht1_10 = 10,
#[doc = "11: ADC12 Sample Hold 1 Select Bit: 11"]
Adc12sht1_11 = 11,
#[doc = "12: ADC12 Sample Hold 1 Select Bit: 12"]
Adc12sht1_12 = 12,
#[doc = "13: ADC12 Sample Hold 1 Select Bit: 13"]
Adc12sht1_13 = 13,
#[doc = "14: ADC12 Sample Hold 1 Select Bit: 14"]
Adc12sht1_14 = 14,
#[doc = "15: ADC12 Sample Hold 1 Select Bit: 15"]
Adc12sht1_15 = 15,
}
impl From<Adc12sht1> for u8 {
#[inline(always)]
fn from(variant: Adc12sht1) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12sht1 {
type Ux = u8;
}
impl crate::IsEnum for Adc12sht1 {}
#[doc = "Field `ADC12SHT1` reader - ADC12 Sample Hold 1 Select Bit: 0"]
pub type Adc12sht1R = crate::FieldReader<Adc12sht1>;
impl Adc12sht1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12sht1 {
match self.bits {
0 => Adc12sht1::Adc12sht1_0,
1 => Adc12sht1::Adc12sht1_1,
2 => Adc12sht1::Adc12sht1_2,
3 => Adc12sht1::Adc12sht1_3,
4 => Adc12sht1::Adc12sht1_4,
5 => Adc12sht1::Adc12sht1_5,
6 => Adc12sht1::Adc12sht1_6,
7 => Adc12sht1::Adc12sht1_7,
8 => Adc12sht1::Adc12sht1_8,
9 => Adc12sht1::Adc12sht1_9,
10 => Adc12sht1::Adc12sht1_10,
11 => Adc12sht1::Adc12sht1_11,
12 => Adc12sht1::Adc12sht1_12,
13 => Adc12sht1::Adc12sht1_13,
14 => Adc12sht1::Adc12sht1_14,
15 => Adc12sht1::Adc12sht1_15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 0"]
#[inline(always)]
pub fn is_adc12sht1_0(&self) -> bool {
*self == Adc12sht1::Adc12sht1_0
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 1"]
#[inline(always)]
pub fn is_adc12sht1_1(&self) -> bool {
*self == Adc12sht1::Adc12sht1_1
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 2"]
#[inline(always)]
pub fn is_adc12sht1_2(&self) -> bool {
*self == Adc12sht1::Adc12sht1_2
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 3"]
#[inline(always)]
pub fn is_adc12sht1_3(&self) -> bool {
*self == Adc12sht1::Adc12sht1_3
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 4"]
#[inline(always)]
pub fn is_adc12sht1_4(&self) -> bool {
*self == Adc12sht1::Adc12sht1_4
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 5"]
#[inline(always)]
pub fn is_adc12sht1_5(&self) -> bool {
*self == Adc12sht1::Adc12sht1_5
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 6"]
#[inline(always)]
pub fn is_adc12sht1_6(&self) -> bool {
*self == Adc12sht1::Adc12sht1_6
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 7"]
#[inline(always)]
pub fn is_adc12sht1_7(&self) -> bool {
*self == Adc12sht1::Adc12sht1_7
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 8"]
#[inline(always)]
pub fn is_adc12sht1_8(&self) -> bool {
*self == Adc12sht1::Adc12sht1_8
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 9"]
#[inline(always)]
pub fn is_adc12sht1_9(&self) -> bool {
*self == Adc12sht1::Adc12sht1_9
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 10"]
#[inline(always)]
pub fn is_adc12sht1_10(&self) -> bool {
*self == Adc12sht1::Adc12sht1_10
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 11"]
#[inline(always)]
pub fn is_adc12sht1_11(&self) -> bool {
*self == Adc12sht1::Adc12sht1_11
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 12"]
#[inline(always)]
pub fn is_adc12sht1_12(&self) -> bool {
*self == Adc12sht1::Adc12sht1_12
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 13"]
#[inline(always)]
pub fn is_adc12sht1_13(&self) -> bool {
*self == Adc12sht1::Adc12sht1_13
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 14"]
#[inline(always)]
pub fn is_adc12sht1_14(&self) -> bool {
*self == Adc12sht1::Adc12sht1_14
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 15"]
#[inline(always)]
pub fn is_adc12sht1_15(&self) -> bool {
*self == Adc12sht1::Adc12sht1_15
}
}
#[doc = "Field `ADC12SHT1` writer - ADC12 Sample Hold 1 Select Bit: 0"]
pub type Adc12sht1W<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12sht1, crate::Safe>;
impl<'a, REG> Adc12sht1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Sample Hold 1 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht1_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_0)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 1"]
#[inline(always)]
pub fn adc12sht1_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_1)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 2"]
#[inline(always)]
pub fn adc12sht1_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_2)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 3"]
#[inline(always)]
pub fn adc12sht1_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_3)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 4"]
#[inline(always)]
pub fn adc12sht1_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_4)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 5"]
#[inline(always)]
pub fn adc12sht1_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_5)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 6"]
#[inline(always)]
pub fn adc12sht1_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_6)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 7"]
#[inline(always)]
pub fn adc12sht1_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_7)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 8"]
#[inline(always)]
pub fn adc12sht1_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_8)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 9"]
#[inline(always)]
pub fn adc12sht1_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_9)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 10"]
#[inline(always)]
pub fn adc12sht1_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_10)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 11"]
#[inline(always)]
pub fn adc12sht1_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_11)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 12"]
#[inline(always)]
pub fn adc12sht1_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_12)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 13"]
#[inline(always)]
pub fn adc12sht1_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_13)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 14"]
#[inline(always)]
pub fn adc12sht1_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_14)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 15"]
#[inline(always)]
pub fn adc12sht1_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_15)
}
}
impl R {
#[doc = "Bit 0 - ADC12 Start Conversion"]
#[inline(always)]
pub fn adc12sc(&self) -> Adc12scR {
Adc12scR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ADC12 Enable Conversion"]
#[inline(always)]
pub fn adc12enc(&self) -> Adc12encR {
Adc12encR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - ADC12 Timer Overflow interrupt enable"]
#[inline(always)]
pub fn adc12tovie(&self) -> Adc12tovieR {
Adc12tovieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - ADC12 Overflow interrupt enable"]
#[inline(always)]
pub fn adc12ovie(&self) -> Adc12ovieR {
Adc12ovieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ADC12 On/enable"]
#[inline(always)]
pub fn adc12on(&self) -> Adc12onR {
Adc12onR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ADC12 Reference on"]
#[inline(always)]
pub fn adc12refon(&self) -> Adc12refonR {
Adc12refonR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - ADC12 Ref 0:1.5V / 1:2.5V"]
#[inline(always)]
pub fn adc12ref2_5v(&self) -> Adc12ref2_5vR {
Adc12ref2_5vR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - ADC12 Multiple SampleConversion"]
#[inline(always)]
pub fn adc12msc(&self) -> Adc12mscR {
Adc12mscR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 Sample Hold 0 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht0(&self) -> Adc12sht0R {
Adc12sht0R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:15 - ADC12 Sample Hold 1 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht1(&self) -> Adc12sht1R {
Adc12sht1R::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bit 0 - ADC12 Start Conversion"]
#[inline(always)]
pub fn adc12sc(&mut self) -> Adc12scW<'_, Adc12ctl0Spec> {
Adc12scW::new(self, 0)
}
#[doc = "Bit 1 - ADC12 Enable Conversion"]
#[inline(always)]
pub fn adc12enc(&mut self) -> Adc12encW<'_, Adc12ctl0Spec> {
Adc12encW::new(self, 1)
}
#[doc = "Bit 2 - ADC12 Timer Overflow interrupt enable"]
#[inline(always)]
pub fn adc12tovie(&mut self) -> Adc12tovieW<'_, Adc12ctl0Spec> {
Adc12tovieW::new(self, 2)
}
#[doc = "Bit 3 - ADC12 Overflow interrupt enable"]
#[inline(always)]
pub fn adc12ovie(&mut self) -> Adc12ovieW<'_, Adc12ctl0Spec> {
Adc12ovieW::new(self, 3)
}
#[doc = "Bit 4 - ADC12 On/enable"]
#[inline(always)]
pub fn adc12on(&mut self) -> Adc12onW<'_, Adc12ctl0Spec> {
Adc12onW::new(self, 4)
}
#[doc = "Bit 5 - ADC12 Reference on"]
#[inline(always)]
pub fn adc12refon(&mut self) -> Adc12refonW<'_, Adc12ctl0Spec> {
Adc12refonW::new(self, 5)
}
#[doc = "Bit 6 - ADC12 Ref 0:1.5V / 1:2.5V"]
#[inline(always)]
pub fn adc12ref2_5v(&mut self) -> Adc12ref2_5vW<'_, Adc12ctl0Spec> {
Adc12ref2_5vW::new(self, 6)
}
#[doc = "Bit 7 - ADC12 Multiple SampleConversion"]
#[inline(always)]
pub fn adc12msc(&mut self) -> Adc12mscW<'_, Adc12ctl0Spec> {
Adc12mscW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 Sample Hold 0 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht0(&mut self) -> Adc12sht0W<'_, Adc12ctl0Spec> {
Adc12sht0W::new(self, 8)
}
#[doc = "Bits 12:15 - ADC12 Sample Hold 1 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht1(&mut self) -> Adc12sht1W<'_, Adc12ctl0Spec> {
Adc12sht1W::new(self, 12)
}
}
#[doc = "ADC12+ Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ctl0Spec;
impl crate::RegisterSpec for Adc12ctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ctl0::R`](R) reader structure"]
impl crate::Readable for Adc12ctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ctl0::W`](W) writer structure"]
impl crate::Writable for Adc12ctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12CTL0 to value 0"]
impl crate::Resettable for Adc12ctl0Spec {}