cc430f5137 0.1.0

Peripheral access API for CC430F5137 microcontroller
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133

#[doc = "Register `UCA0IRTCTL` reader"]
pub type R = crate::R<Uca0irtctlSpec>;
#[doc = "Register `UCA0IRTCTL` writer"]
pub type W = crate::W<Uca0irtctlSpec>;
#[doc = "Field `UCIREN` reader - IRDA Encoder/Decoder enable"]
pub type UcirenR = crate::BitReader;
#[doc = "Field `UCIREN` writer - IRDA Encoder/Decoder enable"]
pub type UcirenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCIRTXCLK` reader - IRDA Transmit Pulse Clock Select"]
pub type UcirtxclkR = crate::BitReader;
#[doc = "Field `UCIRTXCLK` writer - IRDA Transmit Pulse Clock Select"]
pub type UcirtxclkW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCIRTXPL0` reader - IRDA Transmit Pulse Length 0"]
pub type Ucirtxpl0R = crate::BitReader;
#[doc = "Field `UCIRTXPL0` writer - IRDA Transmit Pulse Length 0"]
pub type Ucirtxpl0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCIRTXPL1` reader - IRDA Transmit Pulse Length 1"]
pub type Ucirtxpl1R = crate::BitReader;
#[doc = "Field `UCIRTXPL1` writer - IRDA Transmit Pulse Length 1"]
pub type Ucirtxpl1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCIRTXPL2` reader - IRDA Transmit Pulse Length 2"]
pub type Ucirtxpl2R = crate::BitReader;
#[doc = "Field `UCIRTXPL2` writer - IRDA Transmit Pulse Length 2"]
pub type Ucirtxpl2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCIRTXPL3` reader - IRDA Transmit Pulse Length 3"]
pub type Ucirtxpl3R = crate::BitReader;
#[doc = "Field `UCIRTXPL3` writer - IRDA Transmit Pulse Length 3"]
pub type Ucirtxpl3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCIRTXPL4` reader - IRDA Transmit Pulse Length 4"]
pub type Ucirtxpl4R = crate::BitReader;
#[doc = "Field `UCIRTXPL4` writer - IRDA Transmit Pulse Length 4"]
pub type Ucirtxpl4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCIRTXPL5` reader - IRDA Transmit Pulse Length 5"]
pub type Ucirtxpl5R = crate::BitReader;
#[doc = "Field `UCIRTXPL5` writer - IRDA Transmit Pulse Length 5"]
pub type Ucirtxpl5W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - IRDA Encoder/Decoder enable"]
    #[inline(always)]
    pub fn uciren(&self) -> UcirenR {
        UcirenR::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - IRDA Transmit Pulse Clock Select"]
    #[inline(always)]
    pub fn ucirtxclk(&self) -> UcirtxclkR {
        UcirtxclkR::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - IRDA Transmit Pulse Length 0"]
    #[inline(always)]
    pub fn ucirtxpl0(&self) -> Ucirtxpl0R {
        Ucirtxpl0R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - IRDA Transmit Pulse Length 1"]
    #[inline(always)]
    pub fn ucirtxpl1(&self) -> Ucirtxpl1R {
        Ucirtxpl1R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - IRDA Transmit Pulse Length 2"]
    #[inline(always)]
    pub fn ucirtxpl2(&self) -> Ucirtxpl2R {
        Ucirtxpl2R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - IRDA Transmit Pulse Length 3"]
    #[inline(always)]
    pub fn ucirtxpl3(&self) -> Ucirtxpl3R {
        Ucirtxpl3R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - IRDA Transmit Pulse Length 4"]
    #[inline(always)]
    pub fn ucirtxpl4(&self) -> Ucirtxpl4R {
        Ucirtxpl4R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7 - IRDA Transmit Pulse Length 5"]
    #[inline(always)]
    pub fn ucirtxpl5(&self) -> Ucirtxpl5R {
        Ucirtxpl5R::new(((self.bits >> 7) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - IRDA Encoder/Decoder enable"]
    #[inline(always)]
    pub fn uciren(&mut self) -> UcirenW<'_, Uca0irtctlSpec> {
        UcirenW::new(self, 0)
    }
    #[doc = "Bit 1 - IRDA Transmit Pulse Clock Select"]
    #[inline(always)]
    pub fn ucirtxclk(&mut self) -> UcirtxclkW<'_, Uca0irtctlSpec> {
        UcirtxclkW::new(self, 1)
    }
    #[doc = "Bit 2 - IRDA Transmit Pulse Length 0"]
    #[inline(always)]
    pub fn ucirtxpl0(&mut self) -> Ucirtxpl0W<'_, Uca0irtctlSpec> {
        Ucirtxpl0W::new(self, 2)
    }
    #[doc = "Bit 3 - IRDA Transmit Pulse Length 1"]
    #[inline(always)]
    pub fn ucirtxpl1(&mut self) -> Ucirtxpl1W<'_, Uca0irtctlSpec> {
        Ucirtxpl1W::new(self, 3)
    }
    #[doc = "Bit 4 - IRDA Transmit Pulse Length 2"]
    #[inline(always)]
    pub fn ucirtxpl2(&mut self) -> Ucirtxpl2W<'_, Uca0irtctlSpec> {
        Ucirtxpl2W::new(self, 4)
    }
    #[doc = "Bit 5 - IRDA Transmit Pulse Length 3"]
    #[inline(always)]
    pub fn ucirtxpl3(&mut self) -> Ucirtxpl3W<'_, Uca0irtctlSpec> {
        Ucirtxpl3W::new(self, 5)
    }
    #[doc = "Bit 6 - IRDA Transmit Pulse Length 4"]
    #[inline(always)]
    pub fn ucirtxpl4(&mut self) -> Ucirtxpl4W<'_, Uca0irtctlSpec> {
        Ucirtxpl4W::new(self, 6)
    }
    #[doc = "Bit 7 - IRDA Transmit Pulse Length 5"]
    #[inline(always)]
    pub fn ucirtxpl5(&mut self) -> Ucirtxpl5W<'_, Uca0irtctlSpec> {
        Ucirtxpl5W::new(self, 7)
    }
}
#[doc = "USCI A0 IrDA Transmit Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0irtctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0irtctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0irtctlSpec;
impl crate::RegisterSpec for Uca0irtctlSpec {
    type Ux = u8;
}
#[doc = "`read()` method returns [`uca0irtctl::R`](R) reader structure"]
impl crate::Readable for Uca0irtctlSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0irtctl::W`](W) writer structure"]
impl crate::Writable for Uca0irtctlSpec {
    type Safety = crate::Safe;
}
#[doc = "`reset()` method sets UCA0IRTCTL to value 0"]
impl crate::Resettable for Uca0irtctlSpec {}