cc430f5137 0.1.0

Peripheral access API for CC430F5137 microcontroller
#[doc = "Register `CBCTL1` reader"]
pub type R = crate::R<Cbctl1Spec>;
#[doc = "Register `CBCTL1` writer"]
pub type W = crate::W<Cbctl1Spec>;
#[doc = "Field `CBOUT` reader - Comp. B Output"]
pub type CboutR = crate::BitReader;
#[doc = "Field `CBOUT` writer - Comp. B Output"]
pub type CboutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CBOUTPOL` reader - Comp. B Output Polarity"]
pub type CboutpolR = crate::BitReader;
#[doc = "Field `CBOUTPOL` writer - Comp. B Output Polarity"]
pub type CboutpolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CBF` reader - Comp. B Enable Output Filter"]
pub type CbfR = crate::BitReader;
#[doc = "Field `CBF` writer - Comp. B Enable Output Filter"]
pub type CbfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CBIES` reader - Comp. B Interrupt Edge Select"]
pub type CbiesR = crate::BitReader;
#[doc = "Field `CBIES` writer - Comp. B Interrupt Edge Select"]
pub type CbiesW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CBSHORT` reader - Comp. B Input Short"]
pub type CbshortR = crate::BitReader;
#[doc = "Field `CBSHORT` writer - Comp. B Input Short"]
pub type CbshortW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CBEX` reader - Comp. B Exchange Inputs"]
pub type CbexR = crate::BitReader;
#[doc = "Field `CBEX` writer - Comp. B Exchange Inputs"]
pub type CbexW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Comp. B Filter delay Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cbfdly {
    #[doc = "0: Comp. B Filter delay 0 : 450ns"]
    Cbfdly0 = 0,
    #[doc = "1: Comp. B Filter delay 1 : 900ns"]
    Cbfdly1 = 1,
    #[doc = "2: Comp. B Filter delay 2 : 1800ns"]
    Cbfdly2 = 2,
    #[doc = "3: Comp. B Filter delay 3 : 3600ns"]
    Cbfdly3 = 3,
}
impl From<Cbfdly> for u8 {
    #[inline(always)]
    fn from(variant: Cbfdly) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for Cbfdly {
    type Ux = u8;
}
impl crate::IsEnum for Cbfdly {}
#[doc = "Field `CBFDLY` reader - Comp. B Filter delay Bit 0"]
pub type CbfdlyR = crate::FieldReader<Cbfdly>;
impl CbfdlyR {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> Cbfdly {
        match self.bits {
            0 => Cbfdly::Cbfdly0,
            1 => Cbfdly::Cbfdly1,
            2 => Cbfdly::Cbfdly2,
            3 => Cbfdly::Cbfdly3,
            _ => unreachable!(),
        }
    }
    #[doc = "Comp. B Filter delay 0 : 450ns"]
    #[inline(always)]
    pub fn is_cbfdly_0(&self) -> bool {
        *self == Cbfdly::Cbfdly0
    }
    #[doc = "Comp. B Filter delay 1 : 900ns"]
    #[inline(always)]
    pub fn is_cbfdly_1(&self) -> bool {
        *self == Cbfdly::Cbfdly1
    }
    #[doc = "Comp. B Filter delay 2 : 1800ns"]
    #[inline(always)]
    pub fn is_cbfdly_2(&self) -> bool {
        *self == Cbfdly::Cbfdly2
    }
    #[doc = "Comp. B Filter delay 3 : 3600ns"]
    #[inline(always)]
    pub fn is_cbfdly_3(&self) -> bool {
        *self == Cbfdly::Cbfdly3
    }
}
#[doc = "Field `CBFDLY` writer - Comp. B Filter delay Bit 0"]
pub type CbfdlyW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cbfdly, crate::Safe>;
impl<'a, REG> CbfdlyW<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    #[doc = "Comp. B Filter delay 0 : 450ns"]
    #[inline(always)]
    pub fn cbfdly_0(self) -> &'a mut crate::W<REG> {
        self.variant(Cbfdly::Cbfdly0)
    }
    #[doc = "Comp. B Filter delay 1 : 900ns"]
    #[inline(always)]
    pub fn cbfdly_1(self) -> &'a mut crate::W<REG> {
        self.variant(Cbfdly::Cbfdly1)
    }
    #[doc = "Comp. B Filter delay 2 : 1800ns"]
    #[inline(always)]
    pub fn cbfdly_2(self) -> &'a mut crate::W<REG> {
        self.variant(Cbfdly::Cbfdly2)
    }
    #[doc = "Comp. B Filter delay 3 : 3600ns"]
    #[inline(always)]
    pub fn cbfdly_3(self) -> &'a mut crate::W<REG> {
        self.variant(Cbfdly::Cbfdly3)
    }
}
#[doc = "Comp. B Power Mode Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cbpwrmd {
    #[doc = "0: Comp. B Power Mode 0 : High speed"]
    Cbpwrmd0 = 0,
    #[doc = "1: Comp. B Power Mode 1 : Normal"]
    Cbpwrmd1 = 1,
    #[doc = "2: Comp. B Power Mode 2 : Ultra-Low"]
    Cbpwrmd2 = 2,
    #[doc = "3: Comp. B Power Mode 3 : Reserved"]
    Cbpwrmd3 = 3,
}
impl From<Cbpwrmd> for u8 {
    #[inline(always)]
    fn from(variant: Cbpwrmd) -> Self {
        variant as _
    }
}
impl crate::FieldSpec for Cbpwrmd {
    type Ux = u8;
}
impl crate::IsEnum for Cbpwrmd {}
#[doc = "Field `CBPWRMD` reader - Comp. B Power Mode Bit 0"]
pub type CbpwrmdR = crate::FieldReader<Cbpwrmd>;
impl CbpwrmdR {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> Cbpwrmd {
        match self.bits {
            0 => Cbpwrmd::Cbpwrmd0,
            1 => Cbpwrmd::Cbpwrmd1,
            2 => Cbpwrmd::Cbpwrmd2,
            3 => Cbpwrmd::Cbpwrmd3,
            _ => unreachable!(),
        }
    }
    #[doc = "Comp. B Power Mode 0 : High speed"]
    #[inline(always)]
    pub fn is_cbpwrmd_0(&self) -> bool {
        *self == Cbpwrmd::Cbpwrmd0
    }
    #[doc = "Comp. B Power Mode 1 : Normal"]
    #[inline(always)]
    pub fn is_cbpwrmd_1(&self) -> bool {
        *self == Cbpwrmd::Cbpwrmd1
    }
    #[doc = "Comp. B Power Mode 2 : Ultra-Low"]
    #[inline(always)]
    pub fn is_cbpwrmd_2(&self) -> bool {
        *self == Cbpwrmd::Cbpwrmd2
    }
    #[doc = "Comp. B Power Mode 3 : Reserved"]
    #[inline(always)]
    pub fn is_cbpwrmd_3(&self) -> bool {
        *self == Cbpwrmd::Cbpwrmd3
    }
}
#[doc = "Field `CBPWRMD` writer - Comp. B Power Mode Bit 0"]
pub type CbpwrmdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cbpwrmd, crate::Safe>;
impl<'a, REG> CbpwrmdW<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
    REG::Ux: From<u8>,
{
    #[doc = "Comp. B Power Mode 0 : High speed"]
    #[inline(always)]
    pub fn cbpwrmd_0(self) -> &'a mut crate::W<REG> {
        self.variant(Cbpwrmd::Cbpwrmd0)
    }
    #[doc = "Comp. B Power Mode 1 : Normal"]
    #[inline(always)]
    pub fn cbpwrmd_1(self) -> &'a mut crate::W<REG> {
        self.variant(Cbpwrmd::Cbpwrmd1)
    }
    #[doc = "Comp. B Power Mode 2 : Ultra-Low"]
    #[inline(always)]
    pub fn cbpwrmd_2(self) -> &'a mut crate::W<REG> {
        self.variant(Cbpwrmd::Cbpwrmd2)
    }
    #[doc = "Comp. B Power Mode 3 : Reserved"]
    #[inline(always)]
    pub fn cbpwrmd_3(self) -> &'a mut crate::W<REG> {
        self.variant(Cbpwrmd::Cbpwrmd3)
    }
}
#[doc = "Field `CBON` reader - Comp. B enable"]
pub type CbonR = crate::BitReader;
#[doc = "Field `CBON` writer - Comp. B enable"]
pub type CbonW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CBMRVL` reader - Comp. B CBMRV Level"]
pub type CbmrvlR = crate::BitReader;
#[doc = "Field `CBMRVL` writer - Comp. B CBMRV Level"]
pub type CbmrvlW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CBMRVS` reader - Comp. B Output selects between VREF0 or VREF1"]
pub type CbmrvsR = crate::BitReader;
#[doc = "Field `CBMRVS` writer - Comp. B Output selects between VREF0 or VREF1"]
pub type CbmrvsW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - Comp. B Output"]
    #[inline(always)]
    pub fn cbout(&self) -> CboutR {
        CboutR::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Comp. B Output Polarity"]
    #[inline(always)]
    pub fn cboutpol(&self) -> CboutpolR {
        CboutpolR::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Comp. B Enable Output Filter"]
    #[inline(always)]
    pub fn cbf(&self) -> CbfR {
        CbfR::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Comp. B Interrupt Edge Select"]
    #[inline(always)]
    pub fn cbies(&self) -> CbiesR {
        CbiesR::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - Comp. B Input Short"]
    #[inline(always)]
    pub fn cbshort(&self) -> CbshortR {
        CbshortR::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - Comp. B Exchange Inputs"]
    #[inline(always)]
    pub fn cbex(&self) -> CbexR {
        CbexR::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bits 6:7 - Comp. B Filter delay Bit 0"]
    #[inline(always)]
    pub fn cbfdly(&self) -> CbfdlyR {
        CbfdlyR::new(((self.bits >> 6) & 3) as u8)
    }
    #[doc = "Bits 8:9 - Comp. B Power Mode Bit 0"]
    #[inline(always)]
    pub fn cbpwrmd(&self) -> CbpwrmdR {
        CbpwrmdR::new(((self.bits >> 8) & 3) as u8)
    }
    #[doc = "Bit 10 - Comp. B enable"]
    #[inline(always)]
    pub fn cbon(&self) -> CbonR {
        CbonR::new(((self.bits >> 10) & 1) != 0)
    }
    #[doc = "Bit 11 - Comp. B CBMRV Level"]
    #[inline(always)]
    pub fn cbmrvl(&self) -> CbmrvlR {
        CbmrvlR::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 12 - Comp. B Output selects between VREF0 or VREF1"]
    #[inline(always)]
    pub fn cbmrvs(&self) -> CbmrvsR {
        CbmrvsR::new(((self.bits >> 12) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Comp. B Output"]
    #[inline(always)]
    pub fn cbout(&mut self) -> CboutW<'_, Cbctl1Spec> {
        CboutW::new(self, 0)
    }
    #[doc = "Bit 1 - Comp. B Output Polarity"]
    #[inline(always)]
    pub fn cboutpol(&mut self) -> CboutpolW<'_, Cbctl1Spec> {
        CboutpolW::new(self, 1)
    }
    #[doc = "Bit 2 - Comp. B Enable Output Filter"]
    #[inline(always)]
    pub fn cbf(&mut self) -> CbfW<'_, Cbctl1Spec> {
        CbfW::new(self, 2)
    }
    #[doc = "Bit 3 - Comp. B Interrupt Edge Select"]
    #[inline(always)]
    pub fn cbies(&mut self) -> CbiesW<'_, Cbctl1Spec> {
        CbiesW::new(self, 3)
    }
    #[doc = "Bit 4 - Comp. B Input Short"]
    #[inline(always)]
    pub fn cbshort(&mut self) -> CbshortW<'_, Cbctl1Spec> {
        CbshortW::new(self, 4)
    }
    #[doc = "Bit 5 - Comp. B Exchange Inputs"]
    #[inline(always)]
    pub fn cbex(&mut self) -> CbexW<'_, Cbctl1Spec> {
        CbexW::new(self, 5)
    }
    #[doc = "Bits 6:7 - Comp. B Filter delay Bit 0"]
    #[inline(always)]
    pub fn cbfdly(&mut self) -> CbfdlyW<'_, Cbctl1Spec> {
        CbfdlyW::new(self, 6)
    }
    #[doc = "Bits 8:9 - Comp. B Power Mode Bit 0"]
    #[inline(always)]
    pub fn cbpwrmd(&mut self) -> CbpwrmdW<'_, Cbctl1Spec> {
        CbpwrmdW::new(self, 8)
    }
    #[doc = "Bit 10 - Comp. B enable"]
    #[inline(always)]
    pub fn cbon(&mut self) -> CbonW<'_, Cbctl1Spec> {
        CbonW::new(self, 10)
    }
    #[doc = "Bit 11 - Comp. B CBMRV Level"]
    #[inline(always)]
    pub fn cbmrvl(&mut self) -> CbmrvlW<'_, Cbctl1Spec> {
        CbmrvlW::new(self, 11)
    }
    #[doc = "Bit 12 - Comp. B Output selects between VREF0 or VREF1"]
    #[inline(always)]
    pub fn cbmrvs(&mut self) -> CbmrvsW<'_, Cbctl1Spec> {
        CbmrvsW::new(self, 12)
    }
}
#[doc = "Comparator B Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cbctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cbctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cbctl1Spec;
impl crate::RegisterSpec for Cbctl1Spec {
    type Ux = u16;
}
#[doc = "`read()` method returns [`cbctl1::R`](R) reader structure"]
impl crate::Readable for Cbctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`cbctl1::W`](W) writer structure"]
impl crate::Writable for Cbctl1Spec {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CBCTL1 to value 0"]
impl crate::Resettable for Cbctl1Spec {}