cc2650/crypto/
aesdatain1.rs

1#[doc = r" Value to write to the register"]
2pub struct W {
3    bits: u32,
4}
5impl super::AESDATAIN1 {
6    #[doc = r" Writes to the register"]
7    #[inline]
8    pub fn write<F>(&self, f: F)
9    where
10        F: FnOnce(&mut W) -> &mut W,
11    {
12        let mut w = W::reset_value();
13        f(&mut w);
14        self.register.set(w.bits);
15    }
16}
17#[doc = r" Proxy"]
18pub struct _DATAW<'a> {
19    w: &'a mut W,
20}
21impl<'a> _DATAW<'a> {
22    #[doc = r" Writes raw bits to the field"]
23    #[inline]
24    pub unsafe fn bits(self, value: u32) -> &'a mut W {
25        const MASK: u32 = 4294967295;
26        const OFFSET: u8 = 0;
27        self.w.bits &= !((MASK as u32) << OFFSET);
28        self.w.bits |= ((value & MASK) as u32) << OFFSET;
29        self.w
30    }
31}
32impl W {
33    #[doc = r" Reset value of the register"]
34    #[inline]
35    pub fn reset_value() -> W {
36        W { bits: 0 }
37    }
38    #[doc = r" Writes raw bits to the register"]
39    #[inline]
40    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
41        self.bits = bits;
42        self
43    }
44    #[doc = "Bits 0:31 - Data registers for input block data to the Crypto peripheral. These bits = AES Input Data\\[63:32\\] of \\[127:0\\] For normal operations, this register is not used, since data input and output is transferred from and to the AES engine via DMA. For a Host write operation, these registers must be written with the 128-bit input block for the next AES operation. Writing at a word-aligned offset within this address range will store the word (4 bytes) of data into the corresponding position of 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is used for the next AES operation. If the last data block is not completely filled with valid data (see notes below), it is allowed to write only the words with valid data. Next AES operation is triggered by writing to AESCTL.INPUT_RDY. Note: AES typically operates on 128 bits block multiple input data. The CTR, GCM and CCM modes form an exception. The last block of a CTR-mode message may contain less than 128 bits (refer to \\[NIST 800-38A\\]): 0 < n <= 128 bits. For GCM/CCM, the last block of both AAD and message data may contain less than 128 bits (refer to \\[NIST 800-38D\\]). The Crypto peripheral automatically pads or masks misaligned ending data blocks with zeroes for GCM, CCM and CBC-MAC. For CTR mode, the remaining data in an unaligned data block is ignored."]
45    #[inline]
46    pub fn data(&mut self) -> _DATAW {
47        _DATAW { w: self }
48    }
49}
cc2650/crypto/aesdatain1.rs

cc2650/crypto/
aesdatain1.rs
