1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - I2C master slave address This register consists of eight bits, seven address bits (A6-A0), and a receive and send bit, which determines if the next operation is a receive (high) or transmit (low)."]
5 pub sa: SA,
6 _reserved_1_ctrl: [u8; 4usize],
7 #[doc = "0x08 - I2C master data This register contains the data to be transmitted when in the master transmit state and the data received when in the master receive state."]
8 pub dr: DR,
9 #[doc = "0x0c - I2C master timer period This register specifies the period of the SCL clock."]
10 pub tpr: TPR,
11 #[doc = "0x10 - I2C master interrupt mask This register controls whether a raw interrupt is promoted to a controller interrupt."]
12 pub imr: IMR,
13 #[doc = "0x14 - I2C master raw interrupt status This register specifies whether an interrupt is pending."]
14 pub ris: RIS,
15 #[doc = "0x18 - I2C master masked interrupt status This register specifies whether an interrupt was signaled."]
16 pub mis: MIS,
17 #[doc = "0x1c - I2C master interrupt clear This register clears the raw and masked interrupts."]
18 pub icr: ICR,
19 #[doc = "0x20 - I2C master configuration This register configures the mode (master or slave) and sets the interface for test mode loopback."]
20 pub cr: CR,
21}
22impl RegisterBlock {
23 #[doc = "0x04 - I2C master control and status This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C master slave address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in master receiver mode, the ACK bit is normally set, causing the I2C bus controller to automatically transmit an acknowledge after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter."]
24 #[inline(always)]
25 pub fn stat(&self) -> &STAT {
26 unsafe { &*(((self as *const Self) as *const u8).add(4usize) as *const STAT) }
27 }
28 #[doc = "0x04 - I2C master control and status This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C master slave address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in master receiver mode, the ACK bit is normally set, causing the I2C bus controller to automatically transmit an acknowledge after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter."]
29 #[inline(always)]
30 pub fn stat_mut(&self) -> &mut STAT {
31 unsafe { &mut *(((self as *const Self) as *mut u8).add(4usize) as *mut STAT) }
32 }
33 #[doc = "0x04 - I2C master control and status This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C master slave address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in master receiver mode, the ACK bit is normally set, causing the I2C bus controller to automatically transmit an acknowledge after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter."]
34 #[inline(always)]
35 pub fn ctrl(&self) -> &CTRL {
36 unsafe { &*(((self as *const Self) as *const u8).add(4usize) as *const CTRL) }
37 }
38 #[doc = "0x04 - I2C master control and status This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C master slave address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in master receiver mode, the ACK bit is normally set, causing the I2C bus controller to automatically transmit an acknowledge after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter."]
39 #[inline(always)]
40 pub fn ctrl_mut(&self) -> &mut CTRL {
41 unsafe { &mut *(((self as *const Self) as *mut u8).add(4usize) as *mut CTRL) }
42 }
43}
44#[doc = "I2C master slave address This register consists of eight bits, seven address bits (A6-A0), and a receive and send bit, which determines if the next operation is a receive (high) or transmit (low).\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [sa](sa) module"]
45pub type SA = crate::Reg<u32, _SA>;
46#[allow(missing_docs)]
47#[doc(hidden)]
48pub struct _SA;
49#[doc = "`read()` method returns [sa::R](sa::R) reader structure"]
50impl crate::Readable for SA {}
51#[doc = "`write(|w| ..)` method takes [sa::W](sa::W) writer structure"]
52impl crate::Writable for SA {}
53#[doc = "I2C master slave address This register consists of eight bits, seven address bits (A6-A0), and a receive and send bit, which determines if the next operation is a receive (high) or transmit (low)."]
54pub mod sa;
55#[doc = "I2C master control and status This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C master slave address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in master receiver mode, the ACK bit is normally set, causing the I2C bus controller to automatically transmit an acknowledge after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [ctrl](ctrl) module"]
56pub type CTRL = crate::Reg<u32, _CTRL>;
57#[allow(missing_docs)]
58#[doc(hidden)]
59pub struct _CTRL;
60#[doc = "`read()` method returns [ctrl::R](ctrl::R) reader structure"]
61impl crate::Readable for CTRL {}
62#[doc = "`write(|w| ..)` method takes [ctrl::W](ctrl::W) writer structure"]
63impl crate::Writable for CTRL {}
64#[doc = "I2C master control and status This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C master slave address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in master receiver mode, the ACK bit is normally set, causing the I2C bus controller to automatically transmit an acknowledge after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter."]
65pub mod ctrl;
66#[doc = "I2C master control and status This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C master slave address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in master receiver mode, the ACK bit is normally set, causing the I2C bus controller to automatically transmit an acknowledge after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [stat](stat) module"]
67pub type STAT = crate::Reg<u32, _STAT>;
68#[allow(missing_docs)]
69#[doc(hidden)]
70pub struct _STAT;
71#[doc = "`read()` method returns [stat::R](stat::R) reader structure"]
72impl crate::Readable for STAT {}
73#[doc = "`write(|w| ..)` method takes [stat::W](stat::W) writer structure"]
74impl crate::Writable for STAT {}
75#[doc = "I2C master control and status This register accesses status bits when read and control bits when written. When read, the status register indicates the state of the I2C bus controller. When written, the control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition. To generate a single transmit cycle, the I2C master slave address (I2CMSA) register is written with the desired address, the R/S bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an interrupt becomes active and the data may be read from the I2CMDR register. When the I2C module operates in master receiver mode, the ACK bit is normally set, causing the I2C bus controller to automatically transmit an acknowledge after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter."]
76pub mod stat;
77#[doc = "I2C master data This register contains the data to be transmitted when in the master transmit state and the data received when in the master receive state.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [dr](dr) module"]
78pub type DR = crate::Reg<u32, _DR>;
79#[allow(missing_docs)]
80#[doc(hidden)]
81pub struct _DR;
82#[doc = "`read()` method returns [dr::R](dr::R) reader structure"]
83impl crate::Readable for DR {}
84#[doc = "`write(|w| ..)` method takes [dr::W](dr::W) writer structure"]
85impl crate::Writable for DR {}
86#[doc = "I2C master data This register contains the data to be transmitted when in the master transmit state and the data received when in the master receive state."]
87pub mod dr;
88#[doc = "I2C master timer period This register specifies the period of the SCL clock.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [tpr](tpr) module"]
89pub type TPR = crate::Reg<u32, _TPR>;
90#[allow(missing_docs)]
91#[doc(hidden)]
92pub struct _TPR;
93#[doc = "`read()` method returns [tpr::R](tpr::R) reader structure"]
94impl crate::Readable for TPR {}
95#[doc = "`write(|w| ..)` method takes [tpr::W](tpr::W) writer structure"]
96impl crate::Writable for TPR {}
97#[doc = "I2C master timer period This register specifies the period of the SCL clock."]
98pub mod tpr;
99#[doc = "I2C master interrupt mask This register controls whether a raw interrupt is promoted to a controller interrupt.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [imr](imr) module"]
100pub type IMR = crate::Reg<u32, _IMR>;
101#[allow(missing_docs)]
102#[doc(hidden)]
103pub struct _IMR;
104#[doc = "`read()` method returns [imr::R](imr::R) reader structure"]
105impl crate::Readable for IMR {}
106#[doc = "`write(|w| ..)` method takes [imr::W](imr::W) writer structure"]
107impl crate::Writable for IMR {}
108#[doc = "I2C master interrupt mask This register controls whether a raw interrupt is promoted to a controller interrupt."]
109pub mod imr;
110#[doc = "I2C master raw interrupt status This register specifies whether an interrupt is pending.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [ris](ris) module"]
111pub type RIS = crate::Reg<u32, _RIS>;
112#[allow(missing_docs)]
113#[doc(hidden)]
114pub struct _RIS;
115#[doc = "`read()` method returns [ris::R](ris::R) reader structure"]
116impl crate::Readable for RIS {}
117#[doc = "`write(|w| ..)` method takes [ris::W](ris::W) writer structure"]
118impl crate::Writable for RIS {}
119#[doc = "I2C master raw interrupt status This register specifies whether an interrupt is pending."]
120pub mod ris;
121#[doc = "I2C master masked interrupt status This register specifies whether an interrupt was signaled.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [mis](mis) module"]
122pub type MIS = crate::Reg<u32, _MIS>;
123#[allow(missing_docs)]
124#[doc(hidden)]
125pub struct _MIS;
126#[doc = "`read()` method returns [mis::R](mis::R) reader structure"]
127impl crate::Readable for MIS {}
128#[doc = "`write(|w| ..)` method takes [mis::W](mis::W) writer structure"]
129impl crate::Writable for MIS {}
130#[doc = "I2C master masked interrupt status This register specifies whether an interrupt was signaled."]
131pub mod mis;
132#[doc = "I2C master interrupt clear This register clears the raw and masked interrupts.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [icr](icr) module"]
133pub type ICR = crate::Reg<u32, _ICR>;
134#[allow(missing_docs)]
135#[doc(hidden)]
136pub struct _ICR;
137#[doc = "`read()` method returns [icr::R](icr::R) reader structure"]
138impl crate::Readable for ICR {}
139#[doc = "`write(|w| ..)` method takes [icr::W](icr::W) writer structure"]
140impl crate::Writable for ICR {}
141#[doc = "I2C master interrupt clear This register clears the raw and masked interrupts."]
142pub mod icr;
143#[doc = "I2C master configuration This register configures the mode (master or slave) and sets the interface for test mode loopback.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [cr](cr) module"]
144pub type CR = crate::Reg<u32, _CR>;
145#[allow(missing_docs)]
146#[doc(hidden)]
147pub struct _CR;
148#[doc = "`read()` method returns [cr::R](cr::R) reader structure"]
149impl crate::Readable for CR {}
150#[doc = "`write(|w| ..)` method takes [cr::W](cr::W) writer structure"]
151impl crate::Writable for CR {}
152#[doc = "I2C master configuration This register configures the mode (master or slave) and sets the interface for test mode loopback."]
153pub mod cr;