cc2538/flash_ctrl/
diecfg0.rs

1#[doc = "Reader of register DIECFG0"]
2pub type R = crate::R<u32, super::DIECFG0>;
3#[doc = "Writer for register DIECFG0"]
4pub type W = crate::W<u32, super::DIECFG0>;
5#[doc = "Register DIECFG0 `reset()`'s with value 0"]
6impl crate::ResetValue for super::DIECFG0 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `CHIPID`"]
14pub type CHIPID_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `CHIPID`"]
16pub struct CHIPID_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> CHIPID_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u16) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
24        self.w
25    }
26}
27#[doc = "Reader of field `Reserved16`"]
28pub type RESERVED16_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `Reserved16`"]
30pub struct RESERVED16_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> RESERVED16_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x1f << 11)) | (((value as u32) & 0x1f) << 11);
38        self.w
39    }
40}
41#[doc = "Reader of field `CLK_SEL_GATE_EN_N`"]
42pub type CLK_SEL_GATE_EN_N_R = crate::R<bool, bool>;
43#[doc = "Write proxy for field `CLK_SEL_GATE_EN_N`"]
44pub struct CLK_SEL_GATE_EN_N_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> CLK_SEL_GATE_EN_N_W<'a> {
48    #[doc = r"Sets the field bit"]
49    #[inline(always)]
50    pub fn set_bit(self) -> &'a mut W {
51        self.bit(true)
52    }
53    #[doc = r"Clears the field bit"]
54    #[inline(always)]
55    pub fn clear_bit(self) -> &'a mut W {
56        self.bit(false)
57    }
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub fn bit(self, value: bool) -> &'a mut W {
61        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
62        self.w
63    }
64}
65#[doc = "Reader of field `SRAM_SIZE`"]
66pub type SRAM_SIZE_R = crate::R<u8, u8>;
67#[doc = "Write proxy for field `SRAM_SIZE`"]
68pub struct SRAM_SIZE_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> SRAM_SIZE_W<'a> {
72    #[doc = r"Writes raw bits to the field"]
73    #[inline(always)]
74    pub unsafe fn bits(self, value: u8) -> &'a mut W {
75        self.w.bits = (self.w.bits & !(0x07 << 7)) | (((value as u32) & 0x07) << 7);
76        self.w
77    }
78}
79#[doc = "Reader of field `FLASH_SIZE`"]
80pub type FLASH_SIZE_R = crate::R<u8, u8>;
81#[doc = "Write proxy for field `FLASH_SIZE`"]
82pub struct FLASH_SIZE_W<'a> {
83    w: &'a mut W,
84}
85impl<'a> FLASH_SIZE_W<'a> {
86    #[doc = r"Writes raw bits to the field"]
87    #[inline(always)]
88    pub unsafe fn bits(self, value: u8) -> &'a mut W {
89        self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
90        self.w
91    }
92}
93#[doc = "Reader of field `USB_ENABLE`"]
94pub type USB_ENABLE_R = crate::R<bool, bool>;
95#[doc = "Write proxy for field `USB_ENABLE`"]
96pub struct USB_ENABLE_W<'a> {
97    w: &'a mut W,
98}
99impl<'a> USB_ENABLE_W<'a> {
100    #[doc = r"Sets the field bit"]
101    #[inline(always)]
102    pub fn set_bit(self) -> &'a mut W {
103        self.bit(true)
104    }
105    #[doc = r"Clears the field bit"]
106    #[inline(always)]
107    pub fn clear_bit(self) -> &'a mut W {
108        self.bit(false)
109    }
110    #[doc = r"Writes raw bits to the field"]
111    #[inline(always)]
112    pub fn bit(self, value: bool) -> &'a mut W {
113        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
114        self.w
115    }
116}
117#[doc = "Reader of field `MASS_ERASE_ENABLE`"]
118pub type MASS_ERASE_ENABLE_R = crate::R<bool, bool>;
119#[doc = "Write proxy for field `MASS_ERASE_ENABLE`"]
120pub struct MASS_ERASE_ENABLE_W<'a> {
121    w: &'a mut W,
122}
123impl<'a> MASS_ERASE_ENABLE_W<'a> {
124    #[doc = r"Sets the field bit"]
125    #[inline(always)]
126    pub fn set_bit(self) -> &'a mut W {
127        self.bit(true)
128    }
129    #[doc = r"Clears the field bit"]
130    #[inline(always)]
131    pub fn clear_bit(self) -> &'a mut W {
132        self.bit(false)
133    }
134    #[doc = r"Writes raw bits to the field"]
135    #[inline(always)]
136    pub fn bit(self, value: bool) -> &'a mut W {
137        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
138        self.w
139    }
140}
141#[doc = "Reader of field `LOCK_FWT_N`"]
142pub type LOCK_FWT_N_R = crate::R<bool, bool>;
143#[doc = "Write proxy for field `LOCK_FWT_N`"]
144pub struct LOCK_FWT_N_W<'a> {
145    w: &'a mut W,
146}
147impl<'a> LOCK_FWT_N_W<'a> {
148    #[doc = r"Sets the field bit"]
149    #[inline(always)]
150    pub fn set_bit(self) -> &'a mut W {
151        self.bit(true)
152    }
153    #[doc = r"Clears the field bit"]
154    #[inline(always)]
155    pub fn clear_bit(self) -> &'a mut W {
156        self.bit(false)
157    }
158    #[doc = r"Writes raw bits to the field"]
159    #[inline(always)]
160    pub fn bit(self, value: bool) -> &'a mut W {
161        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
162        self.w
163    }
164}
165#[doc = "Reader of field `LOCK_IP_N`"]
166pub type LOCK_IP_N_R = crate::R<bool, bool>;
167#[doc = "Write proxy for field `LOCK_IP_N`"]
168pub struct LOCK_IP_N_W<'a> {
169    w: &'a mut W,
170}
171impl<'a> LOCK_IP_N_W<'a> {
172    #[doc = r"Sets the field bit"]
173    #[inline(always)]
174    pub fn set_bit(self) -> &'a mut W {
175        self.bit(true)
176    }
177    #[doc = r"Clears the field bit"]
178    #[inline(always)]
179    pub fn clear_bit(self) -> &'a mut W {
180        self.bit(false)
181    }
182    #[doc = r"Writes raw bits to the field"]
183    #[inline(always)]
184    pub fn bit(self, value: bool) -> &'a mut W {
185        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
186        self.w
187    }
188}
189impl R {
190    #[doc = "Bits 16:31 - 31:16\\] Register copy of configuration bits Three clock cycles after reset is released, this bit field is equal to the field with the same name in the information page."]
191    #[inline(always)]
192    pub fn chipid(&self) -> CHIPID_R {
193        CHIPID_R::new(((self.bits >> 16) & 0xffff) as u16)
194    }
195    #[doc = "Bits 11:15 - 15:11\\] Unused"]
196    #[inline(always)]
197    pub fn reserved16(&self) -> RESERVED16_R {
198        RESERVED16_R::new(((self.bits >> 11) & 0x1f) as u8)
199    }
200    #[doc = "Bit 10 - 10:10\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
201    #[inline(always)]
202    pub fn clk_sel_gate_en_n(&self) -> CLK_SEL_GATE_EN_N_R {
203        CLK_SEL_GATE_EN_N_R::new(((self.bits >> 10) & 0x01) != 0)
204    }
205    #[doc = "Bits 7:9 - 9:7\\] Register copy of configuration bits Three clock cycles after reset is released, this bit field is equal to the field with the same name in the information page."]
206    #[inline(always)]
207    pub fn sram_size(&self) -> SRAM_SIZE_R {
208        SRAM_SIZE_R::new(((self.bits >> 7) & 0x07) as u8)
209    }
210    #[doc = "Bits 4:6 - 6:4\\] Register copy of configuration bits Three clock cycles after reset is released, this bit field is equal to the field with the same name in the information page."]
211    #[inline(always)]
212    pub fn flash_size(&self) -> FLASH_SIZE_R {
213        FLASH_SIZE_R::new(((self.bits >> 4) & 0x07) as u8)
214    }
215    #[doc = "Bit 3 - 3:3\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
216    #[inline(always)]
217    pub fn usb_enable(&self) -> USB_ENABLE_R {
218        USB_ENABLE_R::new(((self.bits >> 3) & 0x01) != 0)
219    }
220    #[doc = "Bit 2 - 2:2\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
221    #[inline(always)]
222    pub fn mass_erase_enable(&self) -> MASS_ERASE_ENABLE_R {
223        MASS_ERASE_ENABLE_R::new(((self.bits >> 2) & 0x01) != 0)
224    }
225    #[doc = "Bit 1 - 1:1\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
226    #[inline(always)]
227    pub fn lock_fwt_n(&self) -> LOCK_FWT_N_R {
228        LOCK_FWT_N_R::new(((self.bits >> 1) & 0x01) != 0)
229    }
230    #[doc = "Bit 0 - 0:0\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
231    #[inline(always)]
232    pub fn lock_ip_n(&self) -> LOCK_IP_N_R {
233        LOCK_IP_N_R::new((self.bits & 0x01) != 0)
234    }
235}
236impl W {
237    #[doc = "Bits 16:31 - 31:16\\] Register copy of configuration bits Three clock cycles after reset is released, this bit field is equal to the field with the same name in the information page."]
238    #[inline(always)]
239    pub fn chipid(&mut self) -> CHIPID_W {
240        CHIPID_W { w: self }
241    }
242    #[doc = "Bits 11:15 - 15:11\\] Unused"]
243    #[inline(always)]
244    pub fn reserved16(&mut self) -> RESERVED16_W {
245        RESERVED16_W { w: self }
246    }
247    #[doc = "Bit 10 - 10:10\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
248    #[inline(always)]
249    pub fn clk_sel_gate_en_n(&mut self) -> CLK_SEL_GATE_EN_N_W {
250        CLK_SEL_GATE_EN_N_W { w: self }
251    }
252    #[doc = "Bits 7:9 - 9:7\\] Register copy of configuration bits Three clock cycles after reset is released, this bit field is equal to the field with the same name in the information page."]
253    #[inline(always)]
254    pub fn sram_size(&mut self) -> SRAM_SIZE_W {
255        SRAM_SIZE_W { w: self }
256    }
257    #[doc = "Bits 4:6 - 6:4\\] Register copy of configuration bits Three clock cycles after reset is released, this bit field is equal to the field with the same name in the information page."]
258    #[inline(always)]
259    pub fn flash_size(&mut self) -> FLASH_SIZE_W {
260        FLASH_SIZE_W { w: self }
261    }
262    #[doc = "Bit 3 - 3:3\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
263    #[inline(always)]
264    pub fn usb_enable(&mut self) -> USB_ENABLE_W {
265        USB_ENABLE_W { w: self }
266    }
267    #[doc = "Bit 2 - 2:2\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
268    #[inline(always)]
269    pub fn mass_erase_enable(&mut self) -> MASS_ERASE_ENABLE_W {
270        MASS_ERASE_ENABLE_W { w: self }
271    }
272    #[doc = "Bit 1 - 1:1\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
273    #[inline(always)]
274    pub fn lock_fwt_n(&mut self) -> LOCK_FWT_N_W {
275        LOCK_FWT_N_W { w: self }
276    }
277    #[doc = "Bit 0 - 0:0\\] Register copy of configuration bits Three clock cycles after reset is released, this bit is equal to the field with the same name in the information page."]
278    #[inline(always)]
279    pub fn lock_ip_n(&mut self) -> LOCK_IP_N_W {
280        LOCK_IP_N_W { w: self }
281    }
282}
cc2538/flash_ctrl/diecfg0.rs

cc2538/flash_ctrl/
diecfg0.rs
