1#[doc = "Reader of register ALTCLR"]
2pub type R = crate::R<u32, super::ALTCLR>;
3#[doc = "Writer for register ALTCLR"]
4pub type W = crate::W<u32, super::ALTCLR>;
5#[doc = "Register ALTCLR `reset()`'s with value 0"]
6impl crate::ResetValue for super::ALTCLR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `CLR`"]
14pub type CLR_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `CLR`"]
16pub struct CLR_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> CLR_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u32) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
24 self.w
25 }
26}
27impl R {
28 #[doc = "Bits 0:31 - 31:0\\] Channel \\[n\\] alternate clear 0: No effect 1: Setting a bit clears the corresponding SET\\[n\\] bit in the DMAALTSET register meaning that channel \\[n\\] is using the primary control structure. Note: For Ping-Pong and Scatter-Gather cycle types, the uDMA controller automatically sets these bits to select the alternate channel control data structure."]
29 #[inline(always)]
30 pub fn clr(&self) -> CLR_R {
31 CLR_R::new((self.bits & 0xffff_ffff) as u32)
32 }
33}
34impl W {
35 #[doc = "Bits 0:31 - 31:0\\] Channel \\[n\\] alternate clear 0: No effect 1: Setting a bit clears the corresponding SET\\[n\\] bit in the DMAALTSET register meaning that channel \\[n\\] is using the primary control structure. Note: For Ping-Pong and Scatter-Gather cycle types, the uDMA controller automatically sets these bits to select the alternate channel control data structure."]
36 #[inline(always)]
37 pub fn clr(&mut self) -> CLR_W {
38 CLR_W { w: self }
39 }
40}