cc2538_pac/flash_ctrl/
faddr.rs

1#[doc = "Register `FADDR` reader"]
2pub type R = crate::R<FaddrSpec>;
3#[doc = "Register `FADDR` writer"]
4pub type W = crate::W<FaddrSpec>;
5#[doc = "Field `FADDR` reader - Bit number \\[16:9\\]
6selects one of 256 pages for page erase. Bit number \\[8:7\\]
7selects one of the 4 row in a given page Bit number \\[6:1\\]
8selects one of the 64-bit wide locations in a give row. Bit number \\[0\\]
9will select upper/lower 32-bits in a given 64-bit location - 64Kbytes --> Bits \\[16:14\\]
10will always be 0. - 128Kbytes --> Bits \\[16:15\\]
11will always be 0. - 256Kbytes --> Bit \\[16\\]
12will always be 0. - 384/512Kbytes --> All bits written and valid. Writes to this register will be ignored when any of FCTL.WRITE and FCTL.ERASE is set. FADDR should be written with byte addressable location of the Flash to be programmed. Read back value always reflects a 32-bit aligned address. When the register is read back, the value that was written to FADDR gets right shift by 2 to indicate 32-bit aligned address. In other words lower 2 bits are discarded while reading back the register. Out of range address results in roll over. There is no status signal generated by flash controller to indicate this. Firmware is responsible to managing the addresses correctly."]
13pub type FaddrR = crate::FieldReader<u32>;
14#[doc = "Field `FADDR` writer - Bit number \\[16:9\\]
15selects one of 256 pages for page erase. Bit number \\[8:7\\]
16selects one of the 4 row in a given page Bit number \\[6:1\\]
17selects one of the 64-bit wide locations in a give row. Bit number \\[0\\]
18will select upper/lower 32-bits in a given 64-bit location - 64Kbytes --> Bits \\[16:14\\]
19will always be 0. - 128Kbytes --> Bits \\[16:15\\]
20will always be 0. - 256Kbytes --> Bit \\[16\\]
21will always be 0. - 384/512Kbytes --> All bits written and valid. Writes to this register will be ignored when any of FCTL.WRITE and FCTL.ERASE is set. FADDR should be written with byte addressable location of the Flash to be programmed. Read back value always reflects a 32-bit aligned address. When the register is read back, the value that was written to FADDR gets right shift by 2 to indicate 32-bit aligned address. In other words lower 2 bits are discarded while reading back the register. Out of range address results in roll over. There is no status signal generated by flash controller to indicate this. Firmware is responsible to managing the addresses correctly."]
22pub type FaddrW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
23impl R {
24    #[doc = "Bits 0:16 - Bit number \\[16:9\\]
25selects one of 256 pages for page erase. Bit number \\[8:7\\]
26selects one of the 4 row in a given page Bit number \\[6:1\\]
27selects one of the 64-bit wide locations in a give row. Bit number \\[0\\]
28will select upper/lower 32-bits in a given 64-bit location - 64Kbytes --> Bits \\[16:14\\]
29will always be 0. - 128Kbytes --> Bits \\[16:15\\]
30will always be 0. - 256Kbytes --> Bit \\[16\\]
31will always be 0. - 384/512Kbytes --> All bits written and valid. Writes to this register will be ignored when any of FCTL.WRITE and FCTL.ERASE is set. FADDR should be written with byte addressable location of the Flash to be programmed. Read back value always reflects a 32-bit aligned address. When the register is read back, the value that was written to FADDR gets right shift by 2 to indicate 32-bit aligned address. In other words lower 2 bits are discarded while reading back the register. Out of range address results in roll over. There is no status signal generated by flash controller to indicate this. Firmware is responsible to managing the addresses correctly."]
32    #[inline(always)]
33    pub fn faddr(&self) -> FaddrR {
34        FaddrR::new(self.bits & 0x0001_ffff)
35    }
36}
37impl W {
38    #[doc = "Bits 0:16 - Bit number \\[16:9\\]
39selects one of 256 pages for page erase. Bit number \\[8:7\\]
40selects one of the 4 row in a given page Bit number \\[6:1\\]
41selects one of the 64-bit wide locations in a give row. Bit number \\[0\\]
42will select upper/lower 32-bits in a given 64-bit location - 64Kbytes --> Bits \\[16:14\\]
43will always be 0. - 128Kbytes --> Bits \\[16:15\\]
44will always be 0. - 256Kbytes --> Bit \\[16\\]
45will always be 0. - 384/512Kbytes --> All bits written and valid. Writes to this register will be ignored when any of FCTL.WRITE and FCTL.ERASE is set. FADDR should be written with byte addressable location of the Flash to be programmed. Read back value always reflects a 32-bit aligned address. When the register is read back, the value that was written to FADDR gets right shift by 2 to indicate 32-bit aligned address. In other words lower 2 bits are discarded while reading back the register. Out of range address results in roll over. There is no status signal generated by flash controller to indicate this. Firmware is responsible to managing the addresses correctly."]
46    #[inline(always)]
47    pub fn faddr(&mut self) -> FaddrW<FaddrSpec> {
48        FaddrW::new(self, 0)
49    }
50}
51#[doc = "Flash address The register sets the address to be written in flash memory. See the bitfield descriptions for formatting information.\n\nYou can [`read`](crate::Reg::read) this register and get [`faddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`faddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
52pub struct FaddrSpec;
53impl crate::RegisterSpec for FaddrSpec {
54    type Ux = u32;
55}
56#[doc = "`read()` method returns [`faddr::R`](R) reader structure"]
57impl crate::Readable for FaddrSpec {}
58#[doc = "`write(|w| ..)` method takes [`faddr::W`](W) writer structure"]
59impl crate::Writable for FaddrSpec {
60    type Safety = crate::Unsafe;
61    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63}
64#[doc = "`reset()` method sets FADDR to value 0"]
65impl crate::Resettable for FaddrSpec {
66    const RESET_VALUE: u32 = 0;
67}
cc2538_pac/flash_ctrl/faddr.rs

cc2538_pac/flash_ctrl/
faddr.rs
