cc2538_pac/udma/
chmap3.rs

1#[doc = "Register `CHMAP3` reader"]
2pub type R = crate::R<Chmap3Spec>;
3#[doc = "Register `CHMAP3` writer"]
4pub type W = crate::W<Chmap3Spec>;
5#[doc = "Field `CH24SEL` reader - uDMA channel 24 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
6pub type Ch24selR = crate::FieldReader;
7#[doc = "Field `CH24SEL` writer - uDMA channel 24 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
8pub type Ch24selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `CH25SEL` reader - uDMA channel 25 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
10pub type Ch25selR = crate::FieldReader;
11#[doc = "Field `CH25SEL` writer - uDMA channel 25 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
12pub type Ch25selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `CH26SEL` reader - uDMA channel 26 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
14pub type Ch26selR = crate::FieldReader;
15#[doc = "Field `CH26SEL` writer - uDMA channel 26 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
16pub type Ch26selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17#[doc = "Field `CH27SEL` reader - uDMA channel 27 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
18pub type Ch27selR = crate::FieldReader;
19#[doc = "Field `CH27SEL` writer - uDMA channel 27 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
20pub type Ch27selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `CH28SEL` reader - uDMA channel 28 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
22pub type Ch28selR = crate::FieldReader;
23#[doc = "Field `CH28SEL` writer - uDMA channel 28 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
24pub type Ch28selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25#[doc = "Field `CH29SEL` reader - uDMA channel 29 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
26pub type Ch29selR = crate::FieldReader;
27#[doc = "Field `CH29SEL` writer - uDMA channel 29 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
28pub type Ch29selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29#[doc = "Field `CH30SEL` reader - uDMA channel 30 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
30pub type Ch30selR = crate::FieldReader;
31#[doc = "Field `CH30SEL` writer - uDMA channel 30 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
32pub type Ch30selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
33#[doc = "Field `CH31SEL` reader - uDMA channel 31 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
34pub type Ch31selR = crate::FieldReader;
35#[doc = "Field `CH31SEL` writer - uDMA channel 31 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
36pub type Ch31selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
37impl R {
38    #[doc = "Bits 0:3 - uDMA channel 24 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
39    #[inline(always)]
40    pub fn ch24sel(&self) -> Ch24selR {
41        Ch24selR::new((self.bits & 0x0f) as u8)
42    }
43    #[doc = "Bits 4:7 - uDMA channel 25 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
44    #[inline(always)]
45    pub fn ch25sel(&self) -> Ch25selR {
46        Ch25selR::new(((self.bits >> 4) & 0x0f) as u8)
47    }
48    #[doc = "Bits 8:11 - uDMA channel 26 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
49    #[inline(always)]
50    pub fn ch26sel(&self) -> Ch26selR {
51        Ch26selR::new(((self.bits >> 8) & 0x0f) as u8)
52    }
53    #[doc = "Bits 12:15 - uDMA channel 27 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
54    #[inline(always)]
55    pub fn ch27sel(&self) -> Ch27selR {
56        Ch27selR::new(((self.bits >> 12) & 0x0f) as u8)
57    }
58    #[doc = "Bits 16:19 - uDMA channel 28 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
59    #[inline(always)]
60    pub fn ch28sel(&self) -> Ch28selR {
61        Ch28selR::new(((self.bits >> 16) & 0x0f) as u8)
62    }
63    #[doc = "Bits 20:23 - uDMA channel 29 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
64    #[inline(always)]
65    pub fn ch29sel(&self) -> Ch29selR {
66        Ch29selR::new(((self.bits >> 20) & 0x0f) as u8)
67    }
68    #[doc = "Bits 24:27 - uDMA channel 30 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
69    #[inline(always)]
70    pub fn ch30sel(&self) -> Ch30selR {
71        Ch30selR::new(((self.bits >> 24) & 0x0f) as u8)
72    }
73    #[doc = "Bits 28:31 - uDMA channel 31 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
74    #[inline(always)]
75    pub fn ch31sel(&self) -> Ch31selR {
76        Ch31selR::new(((self.bits >> 28) & 0x0f) as u8)
77    }
78}
79impl W {
80    #[doc = "Bits 0:3 - uDMA channel 24 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
81    #[inline(always)]
82    pub fn ch24sel(&mut self) -> Ch24selW<Chmap3Spec> {
83        Ch24selW::new(self, 0)
84    }
85    #[doc = "Bits 4:7 - uDMA channel 25 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
86    #[inline(always)]
87    pub fn ch25sel(&mut self) -> Ch25selW<Chmap3Spec> {
88        Ch25selW::new(self, 4)
89    }
90    #[doc = "Bits 8:11 - uDMA channel 26 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
91    #[inline(always)]
92    pub fn ch26sel(&mut self) -> Ch26selW<Chmap3Spec> {
93        Ch26selW::new(self, 8)
94    }
95    #[doc = "Bits 12:15 - uDMA channel 27 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
96    #[inline(always)]
97    pub fn ch27sel(&mut self) -> Ch27selW<Chmap3Spec> {
98        Ch27selW::new(self, 12)
99    }
100    #[doc = "Bits 16:19 - uDMA channel 28 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
101    #[inline(always)]
102    pub fn ch28sel(&mut self) -> Ch28selW<Chmap3Spec> {
103        Ch28selW::new(self, 16)
104    }
105    #[doc = "Bits 20:23 - uDMA channel 29 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
106    #[inline(always)]
107    pub fn ch29sel(&mut self) -> Ch29selW<Chmap3Spec> {
108        Ch29selW::new(self, 20)
109    }
110    #[doc = "Bits 24:27 - uDMA channel 30 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
111    #[inline(always)]
112    pub fn ch30sel(&mut self) -> Ch30selW<Chmap3Spec> {
113        Ch30selW::new(self, 24)
114    }
115    #[doc = "Bits 28:31 - uDMA channel 31 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
116    #[inline(always)]
117    pub fn ch31sel(&mut self) -> Ch31selW<Chmap3Spec> {
118        Ch31selW::new(self, 28)
119    }
120}
121#[doc = "DMA channel map select 3 Each 4-bit field of the CHMAP3 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section.\n\nYou can [`read`](crate::Reg::read) this register and get [`chmap3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chmap3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct Chmap3Spec;
123impl crate::RegisterSpec for Chmap3Spec {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`chmap3::R`](R) reader structure"]
127impl crate::Readable for Chmap3Spec {}
128#[doc = "`write(|w| ..)` method takes [`chmap3::W`](W) writer structure"]
129impl crate::Writable for Chmap3Spec {
130    type Safety = crate::Unsafe;
131    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets CHMAP3 to value 0"]
135impl crate::Resettable for Chmap3Spec {
136    const RESET_VALUE: u32 = 0;
137}
cc2538_pac/udma/chmap3.rs

cc2538_pac/udma/
chmap3.rs
