cc2538_pac/udma/
chmap0.rs

1#[doc = "Register `CHMAP0` reader"]
2pub type R = crate::R<Chmap0Spec>;
3#[doc = "Register `CHMAP0` writer"]
4pub type W = crate::W<Chmap0Spec>;
5#[doc = "Field `CH0SEL` reader - uDMA channel 0 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
6pub type Ch0selR = crate::FieldReader;
7#[doc = "Field `CH0SEL` writer - uDMA channel 0 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
8pub type Ch0selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `CH1SEL` reader - uDMA channel 1 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
10pub type Ch1selR = crate::FieldReader;
11#[doc = "Field `CH1SEL` writer - uDMA channel 1 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
12pub type Ch1selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `CH2SEL` reader - uDMA channel 2 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
14pub type Ch2selR = crate::FieldReader;
15#[doc = "Field `CH2SEL` writer - uDMA channel 2 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
16pub type Ch2selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17#[doc = "Field `CH3SEL` reader - uDMA channel 3 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
18pub type Ch3selR = crate::FieldReader;
19#[doc = "Field `CH3SEL` writer - uDMA channel 3 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
20pub type Ch3selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `CH4SEL` reader - uDMA channel 4 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
22pub type Ch4selR = crate::FieldReader;
23#[doc = "Field `CH4SEL` writer - uDMA channel 4 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
24pub type Ch4selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25#[doc = "Field `CH5SEL` reader - uDMA channel 5 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
26pub type Ch5selR = crate::FieldReader;
27#[doc = "Field `CH5SEL` writer - uDMA channel 5 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
28pub type Ch5selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29#[doc = "Field `CH6SEL` reader - uDMA channel 6 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
30pub type Ch6selR = crate::FieldReader;
31#[doc = "Field `CH6SEL` writer - uDMA channel 6 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
32pub type Ch6selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
33#[doc = "Field `CH7SEL` reader - uDMA channel 7 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
34pub type Ch7selR = crate::FieldReader;
35#[doc = "Field `CH7SEL` writer - uDMA channel 7 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
36pub type Ch7selW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
37impl R {
38    #[doc = "Bits 0:3 - uDMA channel 0 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
39    #[inline(always)]
40    pub fn ch0sel(&self) -> Ch0selR {
41        Ch0selR::new((self.bits & 0x0f) as u8)
42    }
43    #[doc = "Bits 4:7 - uDMA channel 1 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
44    #[inline(always)]
45    pub fn ch1sel(&self) -> Ch1selR {
46        Ch1selR::new(((self.bits >> 4) & 0x0f) as u8)
47    }
48    #[doc = "Bits 8:11 - uDMA channel 2 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
49    #[inline(always)]
50    pub fn ch2sel(&self) -> Ch2selR {
51        Ch2selR::new(((self.bits >> 8) & 0x0f) as u8)
52    }
53    #[doc = "Bits 12:15 - uDMA channel 3 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
54    #[inline(always)]
55    pub fn ch3sel(&self) -> Ch3selR {
56        Ch3selR::new(((self.bits >> 12) & 0x0f) as u8)
57    }
58    #[doc = "Bits 16:19 - uDMA channel 4 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
59    #[inline(always)]
60    pub fn ch4sel(&self) -> Ch4selR {
61        Ch4selR::new(((self.bits >> 16) & 0x0f) as u8)
62    }
63    #[doc = "Bits 20:23 - uDMA channel 5 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
64    #[inline(always)]
65    pub fn ch5sel(&self) -> Ch5selR {
66        Ch5selR::new(((self.bits >> 20) & 0x0f) as u8)
67    }
68    #[doc = "Bits 24:27 - uDMA channel 6 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
69    #[inline(always)]
70    pub fn ch6sel(&self) -> Ch6selR {
71        Ch6selR::new(((self.bits >> 24) & 0x0f) as u8)
72    }
73    #[doc = "Bits 28:31 - uDMA channel 7 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
74    #[inline(always)]
75    pub fn ch7sel(&self) -> Ch7selR {
76        Ch7selR::new(((self.bits >> 28) & 0x0f) as u8)
77    }
78}
79impl W {
80    #[doc = "Bits 0:3 - uDMA channel 0 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
81    #[inline(always)]
82    pub fn ch0sel(&mut self) -> Ch0selW<Chmap0Spec> {
83        Ch0selW::new(self, 0)
84    }
85    #[doc = "Bits 4:7 - uDMA channel 1 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
86    #[inline(always)]
87    pub fn ch1sel(&mut self) -> Ch1selW<Chmap0Spec> {
88        Ch1selW::new(self, 4)
89    }
90    #[doc = "Bits 8:11 - uDMA channel 2 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
91    #[inline(always)]
92    pub fn ch2sel(&mut self) -> Ch2selW<Chmap0Spec> {
93        Ch2selW::new(self, 8)
94    }
95    #[doc = "Bits 12:15 - uDMA channel 3 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
96    #[inline(always)]
97    pub fn ch3sel(&mut self) -> Ch3selW<Chmap0Spec> {
98        Ch3selW::new(self, 12)
99    }
100    #[doc = "Bits 16:19 - uDMA channel 4 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
101    #[inline(always)]
102    pub fn ch4sel(&mut self) -> Ch4selW<Chmap0Spec> {
103        Ch4selW::new(self, 16)
104    }
105    #[doc = "Bits 20:23 - uDMA channel 5 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
106    #[inline(always)]
107    pub fn ch5sel(&mut self) -> Ch5selW<Chmap0Spec> {
108        Ch5selW::new(self, 20)
109    }
110    #[doc = "Bits 24:27 - uDMA channel 6 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
111    #[inline(always)]
112    pub fn ch6sel(&mut self) -> Ch6selW<Chmap0Spec> {
113        Ch6selW::new(self, 24)
114    }
115    #[doc = "Bits 28:31 - uDMA channel 7 source select See section titled \"Channel Assignments\" in Micro Direct Memory Access chapter."]
116    #[inline(always)]
117    pub fn ch7sel(&mut self) -> Ch7selW<Chmap0Spec> {
118        Ch7selW::new(self, 28)
119    }
120}
121#[doc = "DMA channel map select 0 Each 4-bit field of the CHMAP0 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section.\n\nYou can [`read`](crate::Reg::read) this register and get [`chmap0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chmap0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct Chmap0Spec;
123impl crate::RegisterSpec for Chmap0Spec {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`chmap0::R`](R) reader structure"]
127impl crate::Readable for Chmap0Spec {}
128#[doc = "`write(|w| ..)` method takes [`chmap0::W`](W) writer structure"]
129impl crate::Writable for Chmap0Spec {
130    type Safety = crate::Unsafe;
131    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets CHMAP0 to value 0"]
135impl crate::Resettable for Chmap0Spec {
136    const RESET_VALUE: u32 = 0;
137}
cc2538_pac/udma/chmap0.rs

cc2538_pac/udma/
chmap0.rs
