cc2538_pac/uart0/
lctl.rs

1#[doc = "Register `LCTL` reader"]
2pub type R = crate::R<LctlSpec>;
3#[doc = "Register `LCTL` writer"]
4pub type W = crate::W<LctlSpec>;
5#[doc = "Field `MASTER` reader - LIN master enable 1: The UART operates as a LIN master. 0: The UART operates as a LIN slave."]
6pub type MasterR = crate::BitReader;
7#[doc = "Field `MASTER` writer - LIN master enable 1: The UART operates as a LIN master. 0: The UART operates as a LIN slave."]
8pub type MasterW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `BLEN` reader - Sync break length 0x3: Sync break length is 16T bits 0x2: Sync break length is 15T bits 0x1: Sync break length is 14T bits 0x0: Sync break length is 13T bits (default)"]
10pub type BlenR = crate::FieldReader;
11#[doc = "Field `BLEN` writer - Sync break length 0x3: Sync break length is 16T bits 0x2: Sync break length is 15T bits 0x1: Sync break length is 14T bits 0x0: Sync break length is 13T bits (default)"]
12pub type BlenW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13impl R {
14    #[doc = "Bit 0 - LIN master enable 1: The UART operates as a LIN master. 0: The UART operates as a LIN slave."]
15    #[inline(always)]
16    pub fn master(&self) -> MasterR {
17        MasterR::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bits 4:5 - Sync break length 0x3: Sync break length is 16T bits 0x2: Sync break length is 15T bits 0x1: Sync break length is 14T bits 0x0: Sync break length is 13T bits (default)"]
20    #[inline(always)]
21    pub fn blen(&self) -> BlenR {
22        BlenR::new(((self.bits >> 4) & 3) as u8)
23    }
24}
25impl W {
26    #[doc = "Bit 0 - LIN master enable 1: The UART operates as a LIN master. 0: The UART operates as a LIN slave."]
27    #[inline(always)]
28    pub fn master(&mut self) -> MasterW<LctlSpec> {
29        MasterW::new(self, 0)
30    }
31    #[doc = "Bits 4:5 - Sync break length 0x3: Sync break length is 16T bits 0x2: Sync break length is 15T bits 0x1: Sync break length is 14T bits 0x0: Sync break length is 13T bits (default)"]
32    #[inline(always)]
33    pub fn blen(&mut self) -> BlenW<LctlSpec> {
34        BlenW::new(self, 4)
35    }
36}
37#[doc = "UART LIN control The LCTL register is the configures the operation of the UART when in LIN mode.\n\nYou can [`read`](crate::Reg::read) this register and get [`lctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
38pub struct LctlSpec;
39impl crate::RegisterSpec for LctlSpec {
40    type Ux = u32;
41}
42#[doc = "`read()` method returns [`lctl::R`](R) reader structure"]
43impl crate::Readable for LctlSpec {}
44#[doc = "`write(|w| ..)` method takes [`lctl::W`](W) writer structure"]
45impl crate::Writable for LctlSpec {
46    type Safety = crate::Unsafe;
47    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
48    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
49}
50#[doc = "`reset()` method sets LCTL to value 0"]
51impl crate::Resettable for LctlSpec {
52    const RESET_VALUE: u32 = 0;
53}
cc2538_pac/uart0/lctl.rs

cc2538_pac/uart0/
lctl.rs
