1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 stat: Stat,
5 cfg: Cfg,
6 ctlbase: Ctlbase,
7 altbase: Altbase,
8 waitstat: Waitstat,
9 swreq: Swreq,
10 useburstset: Useburstset,
11 useburstclr: Useburstclr,
12 reqmaskset: Reqmaskset,
13 reqmaskclr: Reqmaskclr,
14 enaset: Enaset,
15 enaclr: Enaclr,
16 altset: Altset,
17 altclr: Altclr,
18 prioset: Prioset,
19 prioclr: Prioclr,
20 _reserved16: [u8; 0x0c],
21 errclr: Errclr,
22 _reserved17: [u8; 0x04b0],
23 chasgn: Chasgn,
24 chis: Chis,
25 _reserved19: [u8; 0x08],
26 chmap0: Chmap0,
27 chmap1: Chmap1,
28 chmap2: Chmap2,
29 chmap3: Chmap3,
30}
31impl RegisterBlock {
32 #[doc = "0x00 - DMA status The STAT register returns the status of the uDMA controller. This register cannot be read when the uDMA controller is in the reset state."]
33 #[inline(always)]
34 pub const fn stat(&self) -> &Stat {
35 &self.stat
36 }
37 #[doc = "0x04 - DMA configuration The CFG register controls the configuration of the uDMA controller."]
38 #[inline(always)]
39 pub const fn cfg(&self) -> &Cfg {
40 &self.cfg
41 }
42 #[doc = "0x08 - DMA channel control base pointer The CTLBASE register must be configured so that the base pointer points to a location in system memory. The amount of system memory that must be assigned to the uDMA controller depends on the number of uDMA channels used and whether the alternate channel control data structure is used. See Section 10.2.5 for details about the Channel Control Table. The base address must be aligned on a 1024-byte boundary. This register cannot be read when the uDMA controller is in the reset state."]
43 #[inline(always)]
44 pub const fn ctlbase(&self) -> &Ctlbase {
45 &self.ctlbase
46 }
47 #[doc = "0x0c - DMA alternate channel control base pointer The ALTBASE register returns the base address of the alternate channel control data. This register removes the necessity for application software to calculate the base address of the alternate channel control structures. This register cannot be read when the uDMA controller is in the reset state."]
48 #[inline(always)]
49 pub const fn altbase(&self) -> &Altbase {
50 &self.altbase
51 }
52 #[doc = "0x10 - DMA channel wait-on-request status This read-only register indicates that the uDMA channel is waiting on a request. A peripheral can hold off the uDMA from performing a single request until the peripheral is ready for a burst request to enhance the uDMA performance. The use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. This register cannot be read when the uDMA controller is in the reset state."]
53 #[inline(always)]
54 pub const fn waitstat(&self) -> &Waitstat {
55 &self.waitstat
56 }
57 #[doc = "0x14 - DMA channel software request Each bit of the SWREQ register represents the corresponding uDMA channel. Setting a bit generates a request for the specified uDMA channel."]
58 #[inline(always)]
59 pub const fn swreq(&self) -> &Swreq {
60 &self.swreq
61 }
62 #[doc = "0x18 - DMA channel useburst set Each bit of the USEBURSTSET register represents the corresponding uDMA channel. Setting a bit disables the channel single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST. If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET\\[n\\]
63bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than the arbitration (burst) size, the uDMA controller automatically clears the corresponding SET\\[n\\]
64bit, allowing the remaining items to transfer using single requests. To resume transfers using burst requests, the corresponding bit must be set again. A bit must not be set if the corresponding peripheral does not support the burst request model."]
65 #[inline(always)]
66 pub const fn useburstset(&self) -> &Useburstset {
67 &self.useburstset
68 }
69 #[doc = "0x1c - DMA channel useburst clear Each bit of the USEBURSTCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
70bit in the USEBURSTSET register."]
71 #[inline(always)]
72 pub const fn useburstclr(&self) -> &Useburstclr {
73 &self.useburstclr
74 }
75 #[doc = "0x20 - DMA channel request mask set Each bit of the REQMASKSET register represents the corresponding uDMA channel. Setting a bit disables uDMA requests for the channel. Reading the register returns the request mask status. When a uDMA channel request is masked, that means the peripheral can no longer request uDMA transfers. The channel can then be used for software-initiated transfers."]
76 #[inline(always)]
77 pub const fn reqmaskset(&self) -> &Reqmaskset {
78 &self.reqmaskset
79 }
80 #[doc = "0x24 - DMA channel request mask clear Each bit of the REQMASKCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
81bit in the REQMASKSET register."]
82 #[inline(always)]
83 pub const fn reqmaskclr(&self) -> &Reqmaskclr {
84 &self.reqmaskclr
85 }
86 #[doc = "0x28 - DMA channel enable set Each bit of the ENASET register represents the corresponding uDMA channel. Setting a bit enables the corresponding uDMA channel. Reading the register returns the enable status of the channels. If a channel is enabled but the request mask is set (REQMASKSET), then the channel can be used for software-initiated transfers."]
87 #[inline(always)]
88 pub const fn enaset(&self) -> &Enaset {
89 &self.enaset
90 }
91 #[doc = "0x2c - DMA channel enable clear Each bit of the ENACLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
92bit in the ENASET register."]
93 #[inline(always)]
94 pub const fn enaclr(&self) -> &Enaclr {
95 &self.enaclr
96 }
97 #[doc = "0x30 - DMA channel primary alternate set Each bit of the ALTSET register represents the corresponding uDMA channel. Setting a bit configures the uDMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding uDMA channel."]
98 #[inline(always)]
99 pub const fn altset(&self) -> &Altset {
100 &self.altset
101 }
102 #[doc = "0x34 - DMA channel primary alternate clear Each bit of the ALTCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
103bit in the ALTSET register."]
104 #[inline(always)]
105 pub const fn altclr(&self) -> &Altclr {
106 &self.altclr
107 }
108 #[doc = "0x38 - DMA channel priority set Each bit of the PRIOSET register represents the corresponding uDMA channel. Setting a bit configures the uDMA channel to have a high priority level. Reading the register returns the status of the channel priority mask."]
109 #[inline(always)]
110 pub const fn prioset(&self) -> &Prioset {
111 &self.prioset
112 }
113 #[doc = "0x3c - DMA channel priority clear Each bit of the DMAPRIOCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
114bit in the PRIOSET register."]
115 #[inline(always)]
116 pub const fn prioclr(&self) -> &Prioclr {
117 &self.prioclr
118 }
119 #[doc = "0x4c - DMA bus error clear The ERRCLR register is used to read and clear the uDMA bus error status. The error status is set if the uDMA controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that channel is automatically disabled by the uDMA controller. The other channels are unaffected."]
120 #[inline(always)]
121 pub const fn errclr(&self) -> &Errclr {
122 &self.errclr
123 }
124 #[doc = "0x500 - DMA channel assignment Each bit of the CHASGN register represents the corresponding uDMA channel. Setting a bit selects the secondary channel assignment as specified in the section \"Channel Assignments\""]
125 #[inline(always)]
126 pub const fn chasgn(&self) -> &Chasgn {
127 &self.chasgn
128 }
129 #[doc = "0x504 - DMA channel interrupt status Each bit of the CHIS register represents the corresponding uDMA channel. A bit is set when that uDMA channel causes a completion interrupt. The bits are cleared by writing 1."]
130 #[inline(always)]
131 pub const fn chis(&self) -> &Chis {
132 &self.chis
133 }
134 #[doc = "0x510 - DMA channel map select 0 Each 4-bit field of the CHMAP0 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section."]
135 #[inline(always)]
136 pub const fn chmap0(&self) -> &Chmap0 {
137 &self.chmap0
138 }
139 #[doc = "0x514 - DMA channel map select 1 Each 4-bit field of the CHMAP1 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section."]
140 #[inline(always)]
141 pub const fn chmap1(&self) -> &Chmap1 {
142 &self.chmap1
143 }
144 #[doc = "0x518 - DMA channel map select 2 Each 4-bit field of the CHMAP2 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section."]
145 #[inline(always)]
146 pub const fn chmap2(&self) -> &Chmap2 {
147 &self.chmap2
148 }
149 #[doc = "0x51c - DMA channel map select 3 Each 4-bit field of the CHMAP3 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section."]
150 #[inline(always)]
151 pub const fn chmap3(&self) -> &Chmap3 {
152 &self.chmap3
153 }
154}
155#[doc = "STAT (r) register accessor: DMA status The STAT register returns the status of the uDMA controller. This register cannot be read when the uDMA controller is in the reset state.\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
156module"]
157#[doc(alias = "STAT")]
158pub type Stat = crate::Reg<stat::StatSpec>;
159#[doc = "DMA status The STAT register returns the status of the uDMA controller. This register cannot be read when the uDMA controller is in the reset state."]
160pub mod stat;
161#[doc = "CFG (w) register accessor: DMA configuration The CFG register controls the configuration of the uDMA controller.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg`]
162module"]
163#[doc(alias = "CFG")]
164pub type Cfg = crate::Reg<cfg::CfgSpec>;
165#[doc = "DMA configuration The CFG register controls the configuration of the uDMA controller."]
166pub mod cfg;
167#[doc = "CTLBASE (rw) register accessor: DMA channel control base pointer The CTLBASE register must be configured so that the base pointer points to a location in system memory. The amount of system memory that must be assigned to the uDMA controller depends on the number of uDMA channels used and whether the alternate channel control data structure is used. See Section 10.2.5 for details about the Channel Control Table. The base address must be aligned on a 1024-byte boundary. This register cannot be read when the uDMA controller is in the reset state.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctlbase::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctlbase::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctlbase`]
168module"]
169#[doc(alias = "CTLBASE")]
170pub type Ctlbase = crate::Reg<ctlbase::CtlbaseSpec>;
171#[doc = "DMA channel control base pointer The CTLBASE register must be configured so that the base pointer points to a location in system memory. The amount of system memory that must be assigned to the uDMA controller depends on the number of uDMA channels used and whether the alternate channel control data structure is used. See Section 10.2.5 for details about the Channel Control Table. The base address must be aligned on a 1024-byte boundary. This register cannot be read when the uDMA controller is in the reset state."]
172pub mod ctlbase;
173#[doc = "ALTBASE (r) register accessor: DMA alternate channel control base pointer The ALTBASE register returns the base address of the alternate channel control data. This register removes the necessity for application software to calculate the base address of the alternate channel control structures. This register cannot be read when the uDMA controller is in the reset state.\n\nYou can [`read`](crate::Reg::read) this register and get [`altbase::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@altbase`]
174module"]
175#[doc(alias = "ALTBASE")]
176pub type Altbase = crate::Reg<altbase::AltbaseSpec>;
177#[doc = "DMA alternate channel control base pointer The ALTBASE register returns the base address of the alternate channel control data. This register removes the necessity for application software to calculate the base address of the alternate channel control structures. This register cannot be read when the uDMA controller is in the reset state."]
178pub mod altbase;
179#[doc = "WAITSTAT (r) register accessor: DMA channel wait-on-request status This read-only register indicates that the uDMA channel is waiting on a request. A peripheral can hold off the uDMA from performing a single request until the peripheral is ready for a burst request to enhance the uDMA performance. The use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. This register cannot be read when the uDMA controller is in the reset state.\n\nYou can [`read`](crate::Reg::read) this register and get [`waitstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@waitstat`]
180module"]
181#[doc(alias = "WAITSTAT")]
182pub type Waitstat = crate::Reg<waitstat::WaitstatSpec>;
183#[doc = "DMA channel wait-on-request status This read-only register indicates that the uDMA channel is waiting on a request. A peripheral can hold off the uDMA from performing a single request until the peripheral is ready for a burst request to enhance the uDMA performance. The use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. This register cannot be read when the uDMA controller is in the reset state."]
184pub mod waitstat;
185#[doc = "SWREQ (w) register accessor: DMA channel software request Each bit of the SWREQ register represents the corresponding uDMA channel. Setting a bit generates a request for the specified uDMA channel.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swreq::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swreq`]
186module"]
187#[doc(alias = "SWREQ")]
188pub type Swreq = crate::Reg<swreq::SwreqSpec>;
189#[doc = "DMA channel software request Each bit of the SWREQ register represents the corresponding uDMA channel. Setting a bit generates a request for the specified uDMA channel."]
190pub mod swreq;
191#[doc = "USEBURSTSET (rw) register accessor: DMA channel useburst set Each bit of the USEBURSTSET register represents the corresponding uDMA channel. Setting a bit disables the channel single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST. If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET\\[n\\]
192bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than the arbitration (burst) size, the uDMA controller automatically clears the corresponding SET\\[n\\]
193bit, allowing the remaining items to transfer using single requests. To resume transfers using burst requests, the corresponding bit must be set again. A bit must not be set if the corresponding peripheral does not support the burst request model.\n\nYou can [`read`](crate::Reg::read) this register and get [`useburstset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`useburstset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@useburstset`]
194module"]
195#[doc(alias = "USEBURSTSET")]
196pub type Useburstset = crate::Reg<useburstset::UseburstsetSpec>;
197#[doc = "DMA channel useburst set Each bit of the USEBURSTSET register represents the corresponding uDMA channel. Setting a bit disables the channel single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST. If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET\\[n\\]
198bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than the arbitration (burst) size, the uDMA controller automatically clears the corresponding SET\\[n\\]
199bit, allowing the remaining items to transfer using single requests. To resume transfers using burst requests, the corresponding bit must be set again. A bit must not be set if the corresponding peripheral does not support the burst request model."]
200pub mod useburstset;
201#[doc = "USEBURSTCLR (w) register accessor: DMA channel useburst clear Each bit of the USEBURSTCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
202bit in the USEBURSTSET register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`useburstclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@useburstclr`]
203module"]
204#[doc(alias = "USEBURSTCLR")]
205pub type Useburstclr = crate::Reg<useburstclr::UseburstclrSpec>;
206#[doc = "DMA channel useburst clear Each bit of the USEBURSTCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
207bit in the USEBURSTSET register."]
208pub mod useburstclr;
209#[doc = "REQMASKSET (rw) register accessor: DMA channel request mask set Each bit of the REQMASKSET register represents the corresponding uDMA channel. Setting a bit disables uDMA requests for the channel. Reading the register returns the request mask status. When a uDMA channel request is masked, that means the peripheral can no longer request uDMA transfers. The channel can then be used for software-initiated transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`reqmaskset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reqmaskset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reqmaskset`]
210module"]
211#[doc(alias = "REQMASKSET")]
212pub type Reqmaskset = crate::Reg<reqmaskset::ReqmasksetSpec>;
213#[doc = "DMA channel request mask set Each bit of the REQMASKSET register represents the corresponding uDMA channel. Setting a bit disables uDMA requests for the channel. Reading the register returns the request mask status. When a uDMA channel request is masked, that means the peripheral can no longer request uDMA transfers. The channel can then be used for software-initiated transfers."]
214pub mod reqmaskset;
215#[doc = "REQMASKCLR (w) register accessor: DMA channel request mask clear Each bit of the REQMASKCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
216bit in the REQMASKSET register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reqmaskclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reqmaskclr`]
217module"]
218#[doc(alias = "REQMASKCLR")]
219pub type Reqmaskclr = crate::Reg<reqmaskclr::ReqmaskclrSpec>;
220#[doc = "DMA channel request mask clear Each bit of the REQMASKCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
221bit in the REQMASKSET register."]
222pub mod reqmaskclr;
223#[doc = "ENASET (rw) register accessor: DMA channel enable set Each bit of the ENASET register represents the corresponding uDMA channel. Setting a bit enables the corresponding uDMA channel. Reading the register returns the enable status of the channels. If a channel is enabled but the request mask is set (REQMASKSET), then the channel can be used for software-initiated transfers.\n\nYou can [`read`](crate::Reg::read) this register and get [`enaset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enaset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enaset`]
224module"]
225#[doc(alias = "ENASET")]
226pub type Enaset = crate::Reg<enaset::EnasetSpec>;
227#[doc = "DMA channel enable set Each bit of the ENASET register represents the corresponding uDMA channel. Setting a bit enables the corresponding uDMA channel. Reading the register returns the enable status of the channels. If a channel is enabled but the request mask is set (REQMASKSET), then the channel can be used for software-initiated transfers."]
228pub mod enaset;
229#[doc = "ENACLR (w) register accessor: DMA channel enable clear Each bit of the ENACLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
230bit in the ENASET register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enaclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enaclr`]
231module"]
232#[doc(alias = "ENACLR")]
233pub type Enaclr = crate::Reg<enaclr::EnaclrSpec>;
234#[doc = "DMA channel enable clear Each bit of the ENACLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
235bit in the ENASET register."]
236pub mod enaclr;
237#[doc = "ALTSET (rw) register accessor: DMA channel primary alternate set Each bit of the ALTSET register represents the corresponding uDMA channel. Setting a bit configures the uDMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding uDMA channel.\n\nYou can [`read`](crate::Reg::read) this register and get [`altset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`altset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@altset`]
238module"]
239#[doc(alias = "ALTSET")]
240pub type Altset = crate::Reg<altset::AltsetSpec>;
241#[doc = "DMA channel primary alternate set Each bit of the ALTSET register represents the corresponding uDMA channel. Setting a bit configures the uDMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding uDMA channel."]
242pub mod altset;
243#[doc = "ALTCLR (w) register accessor: DMA channel primary alternate clear Each bit of the ALTCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
244bit in the ALTSET register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`altclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@altclr`]
245module"]
246#[doc(alias = "ALTCLR")]
247pub type Altclr = crate::Reg<altclr::AltclrSpec>;
248#[doc = "DMA channel primary alternate clear Each bit of the ALTCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
249bit in the ALTSET register."]
250pub mod altclr;
251#[doc = "PRIOSET (rw) register accessor: DMA channel priority set Each bit of the PRIOSET register represents the corresponding uDMA channel. Setting a bit configures the uDMA channel to have a high priority level. Reading the register returns the status of the channel priority mask.\n\nYou can [`read`](crate::Reg::read) this register and get [`prioset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prioset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prioset`]
252module"]
253#[doc(alias = "PRIOSET")]
254pub type Prioset = crate::Reg<prioset::PriosetSpec>;
255#[doc = "DMA channel priority set Each bit of the PRIOSET register represents the corresponding uDMA channel. Setting a bit configures the uDMA channel to have a high priority level. Reading the register returns the status of the channel priority mask."]
256pub mod prioset;
257#[doc = "PRIOCLR (w) register accessor: DMA channel priority clear Each bit of the DMAPRIOCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
258bit in the PRIOSET register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prioclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prioclr`]
259module"]
260#[doc(alias = "PRIOCLR")]
261pub type Prioclr = crate::Reg<prioclr::PrioclrSpec>;
262#[doc = "DMA channel priority clear Each bit of the DMAPRIOCLR register represents the corresponding uDMA channel. Setting a bit clears the corresponding SET\\[n\\]
263bit in the PRIOSET register."]
264pub mod prioclr;
265#[doc = "ERRCLR (rw) register accessor: DMA bus error clear The ERRCLR register is used to read and clear the uDMA bus error status. The error status is set if the uDMA controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that channel is automatically disabled by the uDMA controller. The other channels are unaffected.\n\nYou can [`read`](crate::Reg::read) this register and get [`errclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@errclr`]
266module"]
267#[doc(alias = "ERRCLR")]
268pub type Errclr = crate::Reg<errclr::ErrclrSpec>;
269#[doc = "DMA bus error clear The ERRCLR register is used to read and clear the uDMA bus error status. The error status is set if the uDMA controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that channel is automatically disabled by the uDMA controller. The other channels are unaffected."]
270pub mod errclr;
271#[doc = "CHASGN (rw) register accessor: DMA channel assignment Each bit of the CHASGN register represents the corresponding uDMA channel. Setting a bit selects the secondary channel assignment as specified in the section \"Channel Assignments\"\n\nYou can [`read`](crate::Reg::read) this register and get [`chasgn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chasgn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chasgn`]
272module"]
273#[doc(alias = "CHASGN")]
274pub type Chasgn = crate::Reg<chasgn::ChasgnSpec>;
275#[doc = "DMA channel assignment Each bit of the CHASGN register represents the corresponding uDMA channel. Setting a bit selects the secondary channel assignment as specified in the section \"Channel Assignments\""]
276pub mod chasgn;
277#[doc = "CHIS (rw) register accessor: DMA channel interrupt status Each bit of the CHIS register represents the corresponding uDMA channel. A bit is set when that uDMA channel causes a completion interrupt. The bits are cleared by writing 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`chis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chis`]
278module"]
279#[doc(alias = "CHIS")]
280pub type Chis = crate::Reg<chis::ChisSpec>;
281#[doc = "DMA channel interrupt status Each bit of the CHIS register represents the corresponding uDMA channel. A bit is set when that uDMA channel causes a completion interrupt. The bits are cleared by writing 1."]
282pub mod chis;
283#[doc = "CHMAP0 (rw) register accessor: DMA channel map select 0 Each 4-bit field of the CHMAP0 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section.\n\nYou can [`read`](crate::Reg::read) this register and get [`chmap0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chmap0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chmap0`]
284module"]
285#[doc(alias = "CHMAP0")]
286pub type Chmap0 = crate::Reg<chmap0::Chmap0Spec>;
287#[doc = "DMA channel map select 0 Each 4-bit field of the CHMAP0 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section."]
288pub mod chmap0;
289#[doc = "CHMAP1 (rw) register accessor: DMA channel map select 1 Each 4-bit field of the CHMAP1 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section.\n\nYou can [`read`](crate::Reg::read) this register and get [`chmap1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chmap1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chmap1`]
290module"]
291#[doc(alias = "CHMAP1")]
292pub type Chmap1 = crate::Reg<chmap1::Chmap1Spec>;
293#[doc = "DMA channel map select 1 Each 4-bit field of the CHMAP1 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section."]
294pub mod chmap1;
295#[doc = "CHMAP2 (rw) register accessor: DMA channel map select 2 Each 4-bit field of the CHMAP2 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section.\n\nYou can [`read`](crate::Reg::read) this register and get [`chmap2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chmap2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chmap2`]
296module"]
297#[doc(alias = "CHMAP2")]
298pub type Chmap2 = crate::Reg<chmap2::Chmap2Spec>;
299#[doc = "DMA channel map select 2 Each 4-bit field of the CHMAP2 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section."]
300pub mod chmap2;
301#[doc = "CHMAP3 (rw) register accessor: DMA channel map select 3 Each 4-bit field of the CHMAP3 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section.\n\nYou can [`read`](crate::Reg::read) this register and get [`chmap3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chmap3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chmap3`]
302module"]
303#[doc(alias = "CHMAP3")]
304pub type Chmap3 = crate::Reg<chmap3::Chmap3Spec>;
305#[doc = "DMA channel map select 3 Each 4-bit field of the CHMAP3 register configures the uDMA channel assignment as specified in the uDMA channel assignment table in the \"Channel Assignments\" section."]
306pub mod chmap3;