1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 addr: Addr,
5 pow: Pow,
6 iif: Iif,
7 _reserved3: [u8; 0x04],
8 oif: Oif,
9 _reserved4: [u8; 0x04],
10 cif: Cif,
11 iie: Iie,
12 _reserved6: [u8; 0x04],
13 oie: Oie,
14 _reserved7: [u8; 0x04],
15 cie: Cie,
16 frml: Frml,
17 frmh: Frmh,
18 index: Index,
19 ctrl: Ctrl,
20 maxi: Maxi,
21 cs0_csil: Cs0Csil,
22 csih: Csih,
23 maxo: Maxo,
24 csol: Csol,
25 csoh: Csoh,
26 cnt0_cntl: Cnt0Cntl,
27 cnth: Cnth,
28 _reserved20: [u8; 0x20],
29 f0: F0,
30 _reserved21: [u8; 0x04],
31 f1: F1,
32 _reserved22: [u8; 0x04],
33 f2: F2,
34 _reserved23: [u8; 0x04],
35 f3: F3,
36 _reserved24: [u8; 0x04],
37 f4: F4,
38 _reserved25: [u8; 0x04],
39 f5: F5,
40}
41impl RegisterBlock {
42 #[doc = "0x00 - Function address"]
43 #[inline(always)]
44 pub const fn addr(&self) -> &Addr {
45 &self.addr
46 }
47 #[doc = "0x04 - Power management and control register"]
48 #[inline(always)]
49 pub const fn pow(&self) -> &Pow {
50 &self.pow
51 }
52 #[doc = "0x08 - Interrupt flags for endpoint 0 and IN endpoints 1-5"]
53 #[inline(always)]
54 pub const fn iif(&self) -> &Iif {
55 &self.iif
56 }
57 #[doc = "0x10 - Interrupt flags for OUT endpoints 1-5"]
58 #[inline(always)]
59 pub const fn oif(&self) -> &Oif {
60 &self.oif
61 }
62 #[doc = "0x18 - Common USB interrupt flags"]
63 #[inline(always)]
64 pub const fn cif(&self) -> &Cif {
65 &self.cif
66 }
67 #[doc = "0x1c - Interrupt enable mask for IN endpoints 1-5 and endpoint 0"]
68 #[inline(always)]
69 pub const fn iie(&self) -> &Iie {
70 &self.iie
71 }
72 #[doc = "0x24 - Interrupt enable mask for OUT endpoints 1-5"]
73 #[inline(always)]
74 pub const fn oie(&self) -> &Oie {
75 &self.oie
76 }
77 #[doc = "0x2c - Common USB interrupt enable mask"]
78 #[inline(always)]
79 pub const fn cie(&self) -> &Cie {
80 &self.cie
81 }
82 #[doc = "0x30 - Frame number (low byte)"]
83 #[inline(always)]
84 pub const fn frml(&self) -> &Frml {
85 &self.frml
86 }
87 #[doc = "0x34 - Frame number (high byte)"]
88 #[inline(always)]
89 pub const fn frmh(&self) -> &Frmh {
90 &self.frmh
91 }
92 #[doc = "0x38 - Index register for selecting the endpoint status and control registers"]
93 #[inline(always)]
94 pub const fn index(&self) -> &Index {
95 &self.index
96 }
97 #[doc = "0x3c - USB peripheral control register"]
98 #[inline(always)]
99 pub const fn ctrl(&self) -> &Ctrl {
100 &self.ctrl
101 }
102 #[doc = "0x40 - Indexed register: For USB_INDEX = 1-5: Maximum packet size for IN endpoint {1-5}"]
103 #[inline(always)]
104 pub const fn maxi(&self) -> &Maxi {
105 &self.maxi
106 }
107 #[doc = "0x44 - Indexed register: For USB_INDEX = 0: Endpoint 0 control and status For USB_INDEX = 1-5: IN endpoint {1-5} control and status (low byte)"]
108 #[inline(always)]
109 pub const fn cs0_csil(&self) -> &Cs0Csil {
110 &self.cs0_csil
111 }
112 #[doc = "0x48 - Indexed register: For USB_INDEX = 1-5: IN endpoint {1-5} control and status (high byte)"]
113 #[inline(always)]
114 pub const fn csih(&self) -> &Csih {
115 &self.csih
116 }
117 #[doc = "0x4c - Indexed register: For USB_INDEX = 1-5: Maximum packet size for OUT endpoint {1-5}"]
118 #[inline(always)]
119 pub const fn maxo(&self) -> &Maxo {
120 &self.maxo
121 }
122 #[doc = "0x50 - Indexed register: For USB_INDEX = 1-5: OUT endpoint {1-5} control and status (low byte)"]
123 #[inline(always)]
124 pub const fn csol(&self) -> &Csol {
125 &self.csol
126 }
127 #[doc = "0x54 - Indexed register: For USB_INDEX = 1-5: OUT endpoint {1-5} control and status (high byte)"]
128 #[inline(always)]
129 pub const fn csoh(&self) -> &Csoh {
130 &self.csoh
131 }
132 #[doc = "0x58 - Indexed register: For USB_INDEX = 0: Number of received bytes in the endpoint 0 FIFO For USB_INDEX = 1-5: Number of received bytes in the OUT endpoint {1-5} FIFO (low byte)"]
133 #[inline(always)]
134 pub const fn cnt0_cntl(&self) -> &Cnt0Cntl {
135 &self.cnt0_cntl
136 }
137 #[doc = "0x5c - Indexed register: For USB_INDEX = 1-5: Number of received in the OUT endpoint {1-5} FIFO (high byte)"]
138 #[inline(always)]
139 pub const fn cnth(&self) -> &Cnth {
140 &self.cnth
141 }
142 #[doc = "0x80 - Endpoint 0 FIFO"]
143 #[inline(always)]
144 pub const fn f0(&self) -> &F0 {
145 &self.f0
146 }
147 #[doc = "0x88 - IN/OUT endpoint 1 FIFO"]
148 #[inline(always)]
149 pub const fn f1(&self) -> &F1 {
150 &self.f1
151 }
152 #[doc = "0x90 - IN/OUT endpoint 2 FIFO"]
153 #[inline(always)]
154 pub const fn f2(&self) -> &F2 {
155 &self.f2
156 }
157 #[doc = "0x98 - IN/OUT endpoint 3 FIFO"]
158 #[inline(always)]
159 pub const fn f3(&self) -> &F3 {
160 &self.f3
161 }
162 #[doc = "0xa0 - IN/OUT endpoint 4 FIFO"]
163 #[inline(always)]
164 pub const fn f4(&self) -> &F4 {
165 &self.f4
166 }
167 #[doc = "0xa8 - IN/OUT endpoint 5 FIFO"]
168 #[inline(always)]
169 pub const fn f5(&self) -> &F5 {
170 &self.f5
171 }
172}
173#[doc = "ADDR (rw) register accessor: Function address\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`]
174module"]
175#[doc(alias = "ADDR")]
176pub type Addr = crate::Reg<addr::AddrSpec>;
177#[doc = "Function address"]
178pub mod addr;
179#[doc = "POW (rw) register accessor: Power management and control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pow::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pow::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pow`]
180module"]
181#[doc(alias = "POW")]
182pub type Pow = crate::Reg<pow::PowSpec>;
183#[doc = "Power management and control register"]
184pub mod pow;
185#[doc = "IIF (r) register accessor: Interrupt flags for endpoint 0 and IN endpoints 1-5\n\nYou can [`read`](crate::Reg::read) this register and get [`iif::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iif`]
186module"]
187#[doc(alias = "IIF")]
188pub type Iif = crate::Reg<iif::IifSpec>;
189#[doc = "Interrupt flags for endpoint 0 and IN endpoints 1-5"]
190pub mod iif;
191#[doc = "OIF (r) register accessor: Interrupt flags for OUT endpoints 1-5\n\nYou can [`read`](crate::Reg::read) this register and get [`oif::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oif`]
192module"]
193#[doc(alias = "OIF")]
194pub type Oif = crate::Reg<oif::OifSpec>;
195#[doc = "Interrupt flags for OUT endpoints 1-5"]
196pub mod oif;
197#[doc = "CIF (r) register accessor: Common USB interrupt flags\n\nYou can [`read`](crate::Reg::read) this register and get [`cif::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cif`]
198module"]
199#[doc(alias = "CIF")]
200pub type Cif = crate::Reg<cif::CifSpec>;
201#[doc = "Common USB interrupt flags"]
202pub mod cif;
203#[doc = "IIE (rw) register accessor: Interrupt enable mask for IN endpoints 1-5 and endpoint 0\n\nYou can [`read`](crate::Reg::read) this register and get [`iie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iie`]
204module"]
205#[doc(alias = "IIE")]
206pub type Iie = crate::Reg<iie::IieSpec>;
207#[doc = "Interrupt enable mask for IN endpoints 1-5 and endpoint 0"]
208pub mod iie;
209#[doc = "OIE (rw) register accessor: Interrupt enable mask for OUT endpoints 1-5\n\nYou can [`read`](crate::Reg::read) this register and get [`oie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oie`]
210module"]
211#[doc(alias = "OIE")]
212pub type Oie = crate::Reg<oie::OieSpec>;
213#[doc = "Interrupt enable mask for OUT endpoints 1-5"]
214pub mod oie;
215#[doc = "CIE (rw) register accessor: Common USB interrupt enable mask\n\nYou can [`read`](crate::Reg::read) this register and get [`cie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cie`]
216module"]
217#[doc(alias = "CIE")]
218pub type Cie = crate::Reg<cie::CieSpec>;
219#[doc = "Common USB interrupt enable mask"]
220pub mod cie;
221#[doc = "FRML (r) register accessor: Frame number (low byte)\n\nYou can [`read`](crate::Reg::read) this register and get [`frml::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frml`]
222module"]
223#[doc(alias = "FRML")]
224pub type Frml = crate::Reg<frml::FrmlSpec>;
225#[doc = "Frame number (low byte)"]
226pub mod frml;
227#[doc = "FRMH (r) register accessor: Frame number (high byte)\n\nYou can [`read`](crate::Reg::read) this register and get [`frmh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frmh`]
228module"]
229#[doc(alias = "FRMH")]
230pub type Frmh = crate::Reg<frmh::FrmhSpec>;
231#[doc = "Frame number (high byte)"]
232pub mod frmh;
233#[doc = "INDEX (rw) register accessor: Index register for selecting the endpoint status and control registers\n\nYou can [`read`](crate::Reg::read) this register and get [`index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@index`]
234module"]
235#[doc(alias = "INDEX")]
236pub type Index = crate::Reg<index::IndexSpec>;
237#[doc = "Index register for selecting the endpoint status and control registers"]
238pub mod index;
239#[doc = "CTRL (rw) register accessor: USB peripheral control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
240module"]
241#[doc(alias = "CTRL")]
242pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
243#[doc = "USB peripheral control register"]
244pub mod ctrl;
245#[doc = "MAXI (rw) register accessor: Indexed register: For USB_INDEX = 1-5: Maximum packet size for IN endpoint {1-5}\n\nYou can [`read`](crate::Reg::read) this register and get [`maxi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`maxi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maxi`]
246module"]
247#[doc(alias = "MAXI")]
248pub type Maxi = crate::Reg<maxi::MaxiSpec>;
249#[doc = "Indexed register: For USB_INDEX = 1-5: Maximum packet size for IN endpoint {1-5}"]
250pub mod maxi;
251#[doc = "CS0_CSIL (rw) register accessor: Indexed register: For USB_INDEX = 0: Endpoint 0 control and status For USB_INDEX = 1-5: IN endpoint {1-5} control and status (low byte)\n\nYou can [`read`](crate::Reg::read) this register and get [`cs0_csil::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cs0_csil::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs0_csil`]
252module"]
253#[doc(alias = "CS0_CSIL")]
254pub type Cs0Csil = crate::Reg<cs0_csil::Cs0CsilSpec>;
255#[doc = "Indexed register: For USB_INDEX = 0: Endpoint 0 control and status For USB_INDEX = 1-5: IN endpoint {1-5} control and status (low byte)"]
256pub mod cs0_csil;
257#[doc = "CSIH (rw) register accessor: Indexed register: For USB_INDEX = 1-5: IN endpoint {1-5} control and status (high byte)\n\nYou can [`read`](crate::Reg::read) this register and get [`csih::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csih::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csih`]
258module"]
259#[doc(alias = "CSIH")]
260pub type Csih = crate::Reg<csih::CsihSpec>;
261#[doc = "Indexed register: For USB_INDEX = 1-5: IN endpoint {1-5} control and status (high byte)"]
262pub mod csih;
263#[doc = "MAXO (rw) register accessor: Indexed register: For USB_INDEX = 1-5: Maximum packet size for OUT endpoint {1-5}\n\nYou can [`read`](crate::Reg::read) this register and get [`maxo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`maxo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maxo`]
264module"]
265#[doc(alias = "MAXO")]
266pub type Maxo = crate::Reg<maxo::MaxoSpec>;
267#[doc = "Indexed register: For USB_INDEX = 1-5: Maximum packet size for OUT endpoint {1-5}"]
268pub mod maxo;
269#[doc = "CSOL (rw) register accessor: Indexed register: For USB_INDEX = 1-5: OUT endpoint {1-5} control and status (low byte)\n\nYou can [`read`](crate::Reg::read) this register and get [`csol::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csol::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csol`]
270module"]
271#[doc(alias = "CSOL")]
272pub type Csol = crate::Reg<csol::CsolSpec>;
273#[doc = "Indexed register: For USB_INDEX = 1-5: OUT endpoint {1-5} control and status (low byte)"]
274pub mod csol;
275#[doc = "CSOH (rw) register accessor: Indexed register: For USB_INDEX = 1-5: OUT endpoint {1-5} control and status (high byte)\n\nYou can [`read`](crate::Reg::read) this register and get [`csoh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csoh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csoh`]
276module"]
277#[doc(alias = "CSOH")]
278pub type Csoh = crate::Reg<csoh::CsohSpec>;
279#[doc = "Indexed register: For USB_INDEX = 1-5: OUT endpoint {1-5} control and status (high byte)"]
280pub mod csoh;
281#[doc = "CNT0_CNTL (r) register accessor: Indexed register: For USB_INDEX = 0: Number of received bytes in the endpoint 0 FIFO For USB_INDEX = 1-5: Number of received bytes in the OUT endpoint {1-5} FIFO (low byte)\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt0_cntl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt0_cntl`]
282module"]
283#[doc(alias = "CNT0_CNTL")]
284pub type Cnt0Cntl = crate::Reg<cnt0_cntl::Cnt0CntlSpec>;
285#[doc = "Indexed register: For USB_INDEX = 0: Number of received bytes in the endpoint 0 FIFO For USB_INDEX = 1-5: Number of received bytes in the OUT endpoint {1-5} FIFO (low byte)"]
286pub mod cnt0_cntl;
287#[doc = "CNTH (r) register accessor: Indexed register: For USB_INDEX = 1-5: Number of received in the OUT endpoint {1-5} FIFO (high byte)\n\nYou can [`read`](crate::Reg::read) this register and get [`cnth::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnth`]
288module"]
289#[doc(alias = "CNTH")]
290pub type Cnth = crate::Reg<cnth::CnthSpec>;
291#[doc = "Indexed register: For USB_INDEX = 1-5: Number of received in the OUT endpoint {1-5} FIFO (high byte)"]
292pub mod cnth;
293#[doc = "F0 (rw) register accessor: Endpoint 0 FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`f0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`f0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@f0`]
294module"]
295pub type F0 = crate::Reg<f0::F0Spec>;
296#[doc = "Endpoint 0 FIFO"]
297pub mod f0;
298#[doc = "F1 (rw) register accessor: IN/OUT endpoint 1 FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`f1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`f1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@f1`]
299module"]
300pub type F1 = crate::Reg<f1::F1Spec>;
301#[doc = "IN/OUT endpoint 1 FIFO"]
302pub mod f1;
303#[doc = "F2 (rw) register accessor: IN/OUT endpoint 2 FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`f2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`f2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@f2`]
304module"]
305pub type F2 = crate::Reg<f2::F2Spec>;
306#[doc = "IN/OUT endpoint 2 FIFO"]
307pub mod f2;
308#[doc = "F3 (rw) register accessor: IN/OUT endpoint 3 FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`f3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`f3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@f3`]
309module"]
310pub type F3 = crate::Reg<f3::F3Spec>;
311#[doc = "IN/OUT endpoint 3 FIFO"]
312pub mod f3;
313#[doc = "F4 (rw) register accessor: IN/OUT endpoint 4 FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`f4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`f4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@f4`]
314module"]
315pub type F4 = crate::Reg<f4::F4Spec>;
316#[doc = "IN/OUT endpoint 4 FIFO"]
317pub mod f4;
318#[doc = "F5 (rw) register accessor: IN/OUT endpoint 5 FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`f5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`f5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@f5`]
319module"]
320pub type F5 = crate::Reg<f5::F5Spec>;
321#[doc = "IN/OUT endpoint 5 FIFO"]
322pub mod f5;