#[doc = "Register `DMAC_CH1_CTRL` reader"]
pub struct R(crate::R<DMAC_CH1_CTRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMAC_CH1_CTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMAC_CH1_CTRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMAC_CH1_CTRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMAC_CH1_CTRL` writer"]
pub struct W(crate::W<DMAC_CH1_CTRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMAC_CH1_CTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMAC_CH1_CTRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMAC_CH1_CTRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PRIO` reader - Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests."]
pub struct PRIO_R(crate::FieldReader<bool, bool>);
impl PRIO_R {
pub(crate) fn new(bits: bool) -> Self {
PRIO_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PRIO_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PRIO` writer - Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests."]
pub struct PRIO_W<'a> {
w: &'a mut W,
}
impl<'a> PRIO_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
#[doc = "Field `EN` reader - Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested."]
pub struct EN_R(crate::FieldReader<bool, bool>);
impl EN_R {
pub(crate) fn new(bits: bool) -> Self {
EN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for EN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `EN` writer - Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested."]
pub struct EN_W<'a> {
w: &'a mut W,
}
impl<'a> EN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
impl R {
#[doc = "Bit 1 - Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests."]
#[inline(always)]
pub fn prio(&self) -> PRIO_R {
PRIO_R::new(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 0 - Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested."]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 1 - Channel priority 0: Low 1: High If both channels have the same priority, access of the channels to the external port is arbitrated using the round robin scheme. If one channel has a high priority and another one low, the channel with the high priority is served first, in case of simultaneous access requests."]
#[inline(always)]
pub fn prio(&mut self) -> PRIO_W {
PRIO_W { w: self }
}
#[doc = "Bit 0 - Channel enable 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested."]
#[inline(always)]
pub fn en(&mut self) -> EN_W {
EN_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Channel control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac_ch1_ctrl](index.html) module"]
pub struct DMAC_CH1_CTRL_SPEC;
impl crate::RegisterSpec for DMAC_CH1_CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmac_ch1_ctrl::R](R) reader structure"]
impl crate::Readable for DMAC_CH1_CTRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmac_ch1_ctrl::W](W) writer structure"]
impl crate::Writable for DMAC_CH1_CTRL_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets DMAC_CH1_CTRL to value 0"]
impl crate::Resettable for DMAC_CH1_CTRL_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}