#[doc = "Reader of register CFSR"]
pub type R = crate::R<u32, super::CFSR>;
#[doc = "Writer for register CFSR"]
pub type W = crate::W<u32, super::CFSR>;
#[doc = "Register CFSR `reset()`'s with value 0"]
impl crate::ResetValue for super::CFSR {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "Reader of field `RESERVED26`"]
pub type RESERVED26_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `RESERVED26`"]
pub struct RESERVED26_W<'a> {
w: &'a mut W,
}
impl<'a> RESERVED26_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x3f << 26)) | (((value as u32) & 0x3f) << 26);
self.w
}
}
#[doc = "Reader of field `DIVBYZERO`"]
pub type DIVBYZERO_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `DIVBYZERO`"]
pub struct DIVBYZERO_W<'a> {
w: &'a mut W,
}
impl<'a> DIVBYZERO_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
self.w
}
}
#[doc = "Reader of field `UNALIGNED`"]
pub type UNALIGNED_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `UNALIGNED`"]
pub struct UNALIGNED_W<'a> {
w: &'a mut W,
}
impl<'a> UNALIGNED_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
self.w
}
}
#[doc = "Reader of field `RESERVED20`"]
pub type RESERVED20_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `RESERVED20`"]
pub struct RESERVED20_W<'a> {
w: &'a mut W,
}
impl<'a> RESERVED20_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
self.w
}
}
#[doc = "Reader of field `NOCP`"]
pub type NOCP_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `NOCP`"]
pub struct NOCP_W<'a> {
w: &'a mut W,
}
impl<'a> NOCP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
self.w
}
}
#[doc = "Reader of field `INVPC`"]
pub type INVPC_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `INVPC`"]
pub struct INVPC_W<'a> {
w: &'a mut W,
}
impl<'a> INVPC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
self.w
}
}
#[doc = "Reader of field `INVSTATE`"]
pub type INVSTATE_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `INVSTATE`"]
pub struct INVSTATE_W<'a> {
w: &'a mut W,
}
impl<'a> INVSTATE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
self.w
}
}
#[doc = "Reader of field `UNDEFINSTR`"]
pub type UNDEFINSTR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `UNDEFINSTR`"]
pub struct UNDEFINSTR_W<'a> {
w: &'a mut W,
}
impl<'a> UNDEFINSTR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
self.w
}
}
#[doc = "Reader of field `BFARVALID`"]
pub type BFARVALID_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `BFARVALID`"]
pub struct BFARVALID_W<'a> {
w: &'a mut W,
}
impl<'a> BFARVALID_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
self.w
}
}
#[doc = "Reader of field `RESERVED13`"]
pub type RESERVED13_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `RESERVED13`"]
pub struct RESERVED13_W<'a> {
w: &'a mut W,
}
impl<'a> RESERVED13_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 13)) | (((value as u32) & 0x03) << 13);
self.w
}
}
#[doc = "Reader of field `STKERR`"]
pub type STKERR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `STKERR`"]
pub struct STKERR_W<'a> {
w: &'a mut W,
}
impl<'a> STKERR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
self.w
}
}
#[doc = "Reader of field `UNSTKERR`"]
pub type UNSTKERR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `UNSTKERR`"]
pub struct UNSTKERR_W<'a> {
w: &'a mut W,
}
impl<'a> UNSTKERR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
self.w
}
}
#[doc = "Reader of field `IMPRECISERR`"]
pub type IMPRECISERR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `IMPRECISERR`"]
pub struct IMPRECISERR_W<'a> {
w: &'a mut W,
}
impl<'a> IMPRECISERR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
self.w
}
}
#[doc = "Reader of field `PRECISERR`"]
pub type PRECISERR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `PRECISERR`"]
pub struct PRECISERR_W<'a> {
w: &'a mut W,
}
impl<'a> PRECISERR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
self.w
}
}
#[doc = "Reader of field `IBUSERR`"]
pub type IBUSERR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `IBUSERR`"]
pub struct IBUSERR_W<'a> {
w: &'a mut W,
}
impl<'a> IBUSERR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
self.w
}
}
#[doc = "Reader of field `MMARVALID`"]
pub type MMARVALID_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `MMARVALID`"]
pub struct MMARVALID_W<'a> {
w: &'a mut W,
}
impl<'a> MMARVALID_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
self.w
}
}
#[doc = "Reader of field `RESERVED5`"]
pub type RESERVED5_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `RESERVED5`"]
pub struct RESERVED5_W<'a> {
w: &'a mut W,
}
impl<'a> RESERVED5_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
self.w
}
}
#[doc = "Reader of field `MSTKERR`"]
pub type MSTKERR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `MSTKERR`"]
pub struct MSTKERR_W<'a> {
w: &'a mut W,
}
impl<'a> MSTKERR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
self.w
}
}
#[doc = "Reader of field `MUNSTKERR`"]
pub type MUNSTKERR_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `MUNSTKERR`"]
pub struct MUNSTKERR_W<'a> {
w: &'a mut W,
}
impl<'a> MUNSTKERR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
self.w
}
}
#[doc = "Reader of field `RESERVED2`"]
pub type RESERVED2_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `RESERVED2`"]
pub struct RESERVED2_W<'a> {
w: &'a mut W,
}
impl<'a> RESERVED2_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
self.w
}
}
#[doc = "Reader of field `DACCVIOL`"]
pub type DACCVIOL_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `DACCVIOL`"]
pub struct DACCVIOL_W<'a> {
w: &'a mut W,
}
impl<'a> DACCVIOL_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
self.w
}
}
#[doc = "Reader of field `IACCVIOL`"]
pub type IACCVIOL_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `IACCVIOL`"]
pub struct IACCVIOL_W<'a> {
w: &'a mut W,
}
impl<'a> IACCVIOL_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
self.w
}
}
impl R {
#[doc = "Bits 26:31 - 31:26\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved26(&self) -> RESERVED26_R {
RESERVED26_R::new(((self.bits >> 26) & 0x3f) as u8)
}
#[doc = "Bit 25 - 25:25\\]
When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0."]
#[inline(always)]
pub fn divbyzero(&self) -> DIVBYZERO_R {
DIVBYZERO_R::new(((self.bits >> 25) & 0x01) != 0)
}
#[doc = "Bit 24 - 24:24\\]
When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP."]
#[inline(always)]
pub fn unaligned(&self) -> UNALIGNED_R {
UNALIGNED_R::new(((self.bits >> 24) & 0x01) != 0)
}
#[doc = "Bits 20:23 - 23:20\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved20(&self) -> RESERVED20_R {
RESERVED20_R::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bit 19 - 19:19\\]
Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions."]
#[inline(always)]
pub fn nocp(&self) -> NOCP_R {
NOCP_R::new(((self.bits >> 19) & 0x01) != 0)
}
#[doc = "Bit 18 - 18:18\\]
Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC."]
#[inline(always)]
pub fn invpc(&self) -> INVPC_R {
INVPC_R::new(((self.bits >> 18) & 0x01) != 0)
}
#[doc = "Bit 17 - 17:17\\]
Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state."]
#[inline(always)]
pub fn invstate(&self) -> INVSTATE_R {
INVSTATE_R::new(((self.bits >> 17) & 0x01) != 0)
}
#[doc = "Bit 16 - 16:16\\]
This bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction."]
#[inline(always)]
pub fn undefinstr(&self) -> UNDEFINSTR_R {
UNDEFINSTR_R::new(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bit 15 - 15:15\\]
This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten."]
#[inline(always)]
pub fn bfarvalid(&self) -> BFARVALID_R {
BFARVALID_R::new(((self.bits >> 15) & 0x01) != 0)
}
#[doc = "Bits 13:14 - 14:13\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved13(&self) -> RESERVED13_R {
RESERVED13_R::new(((self.bits >> 13) & 0x03) as u8)
}
#[doc = "Bit 12 - 12:12\\]
Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written."]
#[inline(always)]
pub fn stkerr(&self) -> STKERR_R {
STKERR_R::new(((self.bits >> 12) & 0x01) != 0)
}
#[doc = "Bit 11 - 11:11\\]
Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written."]
#[inline(always)]
pub fn unstkerr(&self) -> UNSTKERR_R {
UNSTKERR_R::new(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bit 10 - 10:10\\]
Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written."]
#[inline(always)]
pub fn impreciserr(&self) -> IMPRECISERR_R {
IMPRECISERR_R::new(((self.bits >> 10) & 0x01) != 0)
}
#[doc = "Bit 9 - 9:9\\]
Precise data bus error return."]
#[inline(always)]
pub fn preciserr(&self) -> PRECISERR_R {
PRECISERR_R::new(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bit 8 - 8:8\\]
Instruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written."]
#[inline(always)]
pub fn ibuserr(&self) -> IBUSERR_R {
IBUSERR_R::new(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 7 - 7:7\\]
Memory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten."]
#[inline(always)]
pub fn mmarvalid(&self) -> MMARVALID_R {
MMARVALID_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bits 5:6 - 6:5\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved5(&self) -> RESERVED5_R {
RESERVED5_R::new(((self.bits >> 5) & 0x03) as u8)
}
#[doc = "Bit 4 - 4:4\\]
Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written."]
#[inline(always)]
pub fn mstkerr(&self) -> MSTKERR_R {
MSTKERR_R::new(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 3 - 3:3\\]
Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written."]
#[inline(always)]
pub fn munstkerr(&self) -> MUNSTKERR_R {
MUNSTKERR_R::new(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bit 2 - 2:2\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved2(&self) -> RESERVED2_R {
RESERVED2_R::new(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bit 1 - 1:1\\]
Data access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access."]
#[inline(always)]
pub fn daccviol(&self) -> DACCVIOL_R {
DACCVIOL_R::new(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 0 - 0:0\\]
Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written."]
#[inline(always)]
pub fn iaccviol(&self) -> IACCVIOL_R {
IACCVIOL_R::new((self.bits & 0x01) != 0)
}
}
impl W {
#[doc = "Bits 26:31 - 31:26\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved26(&mut self) -> RESERVED26_W {
RESERVED26_W { w: self }
}
#[doc = "Bit 25 - 25:25\\]
When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0."]
#[inline(always)]
pub fn divbyzero(&mut self) -> DIVBYZERO_W {
DIVBYZERO_W { w: self }
}
#[doc = "Bit 24 - 24:24\\]
When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP."]
#[inline(always)]
pub fn unaligned(&mut self) -> UNALIGNED_W {
UNALIGNED_W { w: self }
}
#[doc = "Bits 20:23 - 23:20\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved20(&mut self) -> RESERVED20_W {
RESERVED20_W { w: self }
}
#[doc = "Bit 19 - 19:19\\]
Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions."]
#[inline(always)]
pub fn nocp(&mut self) -> NOCP_W {
NOCP_W { w: self }
}
#[doc = "Bit 18 - 18:18\\]
Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC."]
#[inline(always)]
pub fn invpc(&mut self) -> INVPC_W {
INVPC_W { w: self }
}
#[doc = "Bit 17 - 17:17\\]
Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state."]
#[inline(always)]
pub fn invstate(&mut self) -> INVSTATE_W {
INVSTATE_W { w: self }
}
#[doc = "Bit 16 - 16:16\\]
This bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction."]
#[inline(always)]
pub fn undefinstr(&mut self) -> UNDEFINSTR_W {
UNDEFINSTR_W { w: self }
}
#[doc = "Bit 15 - 15:15\\]
This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten."]
#[inline(always)]
pub fn bfarvalid(&mut self) -> BFARVALID_W {
BFARVALID_W { w: self }
}
#[doc = "Bits 13:14 - 14:13\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved13(&mut self) -> RESERVED13_W {
RESERVED13_W { w: self }
}
#[doc = "Bit 12 - 12:12\\]
Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written."]
#[inline(always)]
pub fn stkerr(&mut self) -> STKERR_W {
STKERR_W { w: self }
}
#[doc = "Bit 11 - 11:11\\]
Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written."]
#[inline(always)]
pub fn unstkerr(&mut self) -> UNSTKERR_W {
UNSTKERR_W { w: self }
}
#[doc = "Bit 10 - 10:10\\]
Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written."]
#[inline(always)]
pub fn impreciserr(&mut self) -> IMPRECISERR_W {
IMPRECISERR_W { w: self }
}
#[doc = "Bit 9 - 9:9\\]
Precise data bus error return."]
#[inline(always)]
pub fn preciserr(&mut self) -> PRECISERR_W {
PRECISERR_W { w: self }
}
#[doc = "Bit 8 - 8:8\\]
Instruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written."]
#[inline(always)]
pub fn ibuserr(&mut self) -> IBUSERR_W {
IBUSERR_W { w: self }
}
#[doc = "Bit 7 - 7:7\\]
Memory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten."]
#[inline(always)]
pub fn mmarvalid(&mut self) -> MMARVALID_W {
MMARVALID_W { w: self }
}
#[doc = "Bits 5:6 - 6:5\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved5(&mut self) -> RESERVED5_W {
RESERVED5_W { w: self }
}
#[doc = "Bit 4 - 4:4\\]
Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written."]
#[inline(always)]
pub fn mstkerr(&mut self) -> MSTKERR_W {
MSTKERR_W { w: self }
}
#[doc = "Bit 3 - 3:3\\]
Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written."]
#[inline(always)]
pub fn munstkerr(&mut self) -> MUNSTKERR_W {
MUNSTKERR_W { w: self }
}
#[doc = "Bit 2 - 2:2\\]
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline(always)]
pub fn reserved2(&mut self) -> RESERVED2_W {
RESERVED2_W { w: self }
}
#[doc = "Bit 1 - 1:1\\]
Data access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access."]
#[inline(always)]
pub fn daccviol(&mut self) -> DACCVIOL_W {
DACCVIOL_W { w: self }
}
#[doc = "Bit 0 - 0:0\\]
Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written."]
#[inline(always)]
pub fn iaccviol(&mut self) -> IACCVIOL_W {
IACCVIOL_W { w: self }
}
}