cc13x2-cc26x2-pac 0.1.0

Peripheral access API for cc13x2 and cc26x2 microcontrollers
Documentation
#[doc = r" Value read from the register"]
pub struct R {
    bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
    bits: u32,
}
impl super::MISC_TRIM {
    #[doc = r" Modifies the contents of the register"]
    #[inline]
    pub fn modify<F>(&self, f: F)
    where
        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
    {
        let bits = self.register.get();
        let r = R { bits: bits };
        let mut w = W { bits: bits };
        f(&r, &mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Reads the contents of the register"]
    #[inline]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
    #[doc = r" Writes to the register"]
    #[inline]
    pub fn write<F>(&self, f: F)
    where
        F: FnOnce(&mut W) -> &mut W,
    {
        let mut w = W::reset_value();
        f(&mut w);
        self.register.set(w.bits);
    }
    #[doc = r" Writes the reset value to the register"]
    #[inline]
    pub fn reset(&self) {
        self.write(|w| w)
    }
}
#[doc = r" Value of the field"]
pub struct TRIM_RECHARGE_COMP_OFFSETR {
    bits: u8,
}
impl TRIM_RECHARGE_COMP_OFFSETR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct TRIM_RECHARGE_COMP_REFLEVELR {
    bits: u8,
}
impl TRIM_RECHARGE_COMP_REFLEVELR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct TEMPVSLOPER {
    bits: u8,
}
impl TEMPVSLOPER {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Proxy"]
pub struct _TRIM_RECHARGE_COMP_OFFSETW<'a> {
    w: &'a mut W,
}
impl<'a> _TRIM_RECHARGE_COMP_OFFSETW<'a> {
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 31;
        const OFFSET: u8 = 12;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = r" Proxy"]
pub struct _TRIM_RECHARGE_COMP_REFLEVELW<'a> {
    w: &'a mut W,
}
impl<'a> _TRIM_RECHARGE_COMP_REFLEVELW<'a> {
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 15;
        const OFFSET: u8 = 8;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
#[doc = r" Proxy"]
pub struct _TEMPVSLOPEW<'a> {
    w: &'a mut W,
}
impl<'a> _TEMPVSLOPEW<'a> {
    #[doc = r" Writes raw bits to the field"]
    #[inline]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        const MASK: u8 = 255;
        const OFFSET: u8 = 0;
        self.w.bits &= !((MASK as u32) << OFFSET);
        self.w.bits |= ((value & MASK) as u32) << OFFSET;
        self.w
    }
}
impl R {
    #[doc = r" Value of the register as raw bits"]
    #[inline]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 12:16 - 16:12\\] Internal. Only to be used through TI provided API."]
    #[inline]
    pub fn trim_recharge_comp_offset(&self) -> TRIM_RECHARGE_COMP_OFFSETR {
        let bits = {
            const MASK: u8 = 31;
            const OFFSET: u8 = 12;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        TRIM_RECHARGE_COMP_OFFSETR { bits }
    }
    #[doc = "Bits 8:11 - 11:8\\] Internal. Only to be used through TI provided API."]
    #[inline]
    pub fn trim_recharge_comp_reflevel(&self) -> TRIM_RECHARGE_COMP_REFLEVELR {
        let bits = {
            const MASK: u8 = 15;
            const OFFSET: u8 = 8;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        TRIM_RECHARGE_COMP_REFLEVELR { bits }
    }
    #[doc = "Bits 0:7 - 7:0\\] Signed byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits."]
    #[inline]
    pub fn tempvslope(&self) -> TEMPVSLOPER {
        let bits = {
            const MASK: u8 = 255;
            const OFFSET: u8 = 0;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        TEMPVSLOPER { bits }
    }
}
impl W {
    #[doc = r" Reset value of the register"]
    #[inline]
    pub fn reset_value() -> W {
        W { bits: 4294836283 }
    }
    #[doc = r" Writes raw bits to the register"]
    #[inline]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
    #[doc = "Bits 12:16 - 16:12\\] Internal. Only to be used through TI provided API."]
    #[inline]
    pub fn trim_recharge_comp_offset(&mut self) -> _TRIM_RECHARGE_COMP_OFFSETW {
        _TRIM_RECHARGE_COMP_OFFSETW { w: self }
    }
    #[doc = "Bits 8:11 - 11:8\\] Internal. Only to be used through TI provided API."]
    #[inline]
    pub fn trim_recharge_comp_reflevel(&mut self) -> _TRIM_RECHARGE_COMP_REFLEVELW {
        _TRIM_RECHARGE_COMP_REFLEVELW { w: self }
    }
    #[doc = "Bits 0:7 - 7:0\\] Signed byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits."]
    #[inline]
    pub fn tempvslope(&mut self) -> _TEMPVSLOPEW {
        _TEMPVSLOPEW { w: self }
    }
}