Struct cc13x2_cc26x2_hal::prcm::i2sclkctl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved4(&self) -> RESERVED4R

Bits 4:31 - 31:4] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn smpl_on_posedge(&self) -> SMPL_ON_POSEDGER

Bit 3 - 3:3] On the I2S serial interface, data and WCLK is sampled and clocked out on opposite edges of BCLK. 0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge. 1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge. For changes to take effect, CLKLOADCTL.LOAD needs to be written

pub fn wclk_phase(&self) -> WCLK_PHASER

Bits 1:2 - 2:1] Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV). 0: Single phase 1: Dual phase 2: User Defined 3: Reserved/Undefined For changes to take effect, CLKLOADCTL.LOAD needs to be written

pub fn en(&self) -> ENR

Bit 0 - 0:0] 0: MCLK, BCLK and WCLK will be static low 1: Enables the generation of MCLK, BCLK and WCLK For changes to take effect, CLKLOADCTL.LOAD needs to be written