#!/bin/kcpfpg
?uploadbin
?register adc_snap_bram 0x10000 0x4000
?register gbe0_rxs_ss_bram 0x14000 0x2000
?register requant_gains 0x16000 0x1000
?register spec_a_vacc 0x17000 0x4000
?register spec_b_vacc 0x1b000 0x4000
?register lmx_ctrl 0x1f000 0x4
?register adc16_controller 0x1f004 0x100
?register adc16_wb_ram1 0x1f104 0x1000
?register adc16_wb_ram2 0x20104 0x1000
?register adc16_wb_ram0 0x21104 0x1000
?register adc_snap_ctrl 0x22104 0x4
?register adc_snap_status 0x22108 0x4
?register adc_snap_trig 0x2210c 0x4
?register arm 0x22110 0x4
?register ch_1_sel 0x22114 0x4
?register ch_2_sel 0x22118 0x4
?register dest_ip 0x2211c 0x4
?register dest_port 0x22120 0x4
?register fft_overflow_cnt 0x22124 0x4
?register fft_shift 0x22128 0x4
?register gbe0_rxctr 0x2212c 0x4
?register gbe0_rxeofctr 0x22130 0x4
?register gbe0_rxs_ss_ctrl 0x22134 0x4
?register gbe0_rxs_ss_status 0x22138 0x4
?register gbe1_linkup 0x2213c 0x4
?register gbe1_tx_overflow 0x22140 0x4
?register master_rst 0x22144 0x4
?register pps_cnt 0x22148 0x4
?register pps_trig 0x2214c 0x4
?register requant_a_overflow 0x22150 0x4
?register requant_b_overflow 0x22154 0x4
?register tx_en 0x22158 0x4
?register vacc_trig 0x2215c 0x4
?register adc16_use_synth 0x22160 0x4
?register sys_block 0x22164 0x20
?register sys_board_id 0x22164 0x4
?register sys_rev 0x22168 0x4
?register sys_rev_rcs 0x22170 0x4
?register sys_scratchpad 0x22174 0x4
?register sys_clkcounter 0x22178 0x4
?register gbe0 0x22184 0xf000
?register gbe1 0x31184 0xf000
?meta SNAP xps:xsg hw_sys SNAP:xc7k160t
?meta SNAP xps:xsg clk_src adc0_clk
?meta SNAP xps:xsg clk_rate 250
?meta SNAP xps:xsg use_microblaze on
?meta SNAP xps:xsg sample_period 1
?meta SNAP xps:xsg synthesis_tool XST
?meta adc_snap/bram xps:bram arith_type Unsigned
?meta adc_snap/bram xps:bram addr_width 12
?meta adc_snap/bram xps:bram data_width 32
?meta adc_snap/bram xps:bram reg_prim_output off
?meta adc_snap/bram xps:bram reg_core_output off
?meta adc_snap/bram xps:bram optimization Minimum_Area
?meta adc_snap/bram xps:bram data_bin_pt 0
?meta adc_snap/bram xps:bram init_vals [0:2^12-1]
?meta adc_snap/bram xps:bram sample_rate 1
?meta gbe0/rxs/ss/bram xps:bram arith_type Unsigned
?meta gbe0/rxs/ss/bram xps:bram addr_width 9
?meta gbe0/rxs/ss/bram xps:bram data_width 128
?meta gbe0/rxs/ss/bram xps:bram reg_prim_output off
?meta gbe0/rxs/ss/bram xps:bram reg_core_output off
?meta gbe0/rxs/ss/bram xps:bram optimization Minimum_Area
?meta gbe0/rxs/ss/bram xps:bram data_bin_pt 0
?meta gbe0/rxs/ss/bram xps:bram init_vals [0:2^9-1]
?meta gbe0/rxs/ss/bram xps:bram sample_rate 1
?meta requant_gains xps:bram arith_type Unsigned
?meta requant_gains xps:bram addr_width 11
?meta requant_gains xps:bram data_width 16
?meta requant_gains xps:bram reg_prim_output off
?meta requant_gains xps:bram reg_core_output off
?meta requant_gains xps:bram optimization Minimum_Area
?meta requant_gains xps:bram data_bin_pt 0
?meta requant_gains xps:bram init_vals [0:2^10-1]
?meta requant_gains xps:bram sample_rate 1
?meta spec_a_vacc xps:bram arith_type Unsigned
?meta spec_a_vacc xps:bram addr_width 11
?meta spec_a_vacc xps:bram data_width 64
?meta spec_a_vacc xps:bram reg_prim_output off
?meta spec_a_vacc xps:bram reg_core_output off
?meta spec_a_vacc xps:bram optimization Minimum_Area
?meta spec_a_vacc xps:bram data_bin_pt 0
?meta spec_a_vacc xps:bram init_vals [0:2^10-1]
?meta spec_a_vacc xps:bram sample_rate 1
?meta spec_b_vacc xps:bram arith_type Unsigned
?meta spec_b_vacc xps:bram addr_width 11
?meta spec_b_vacc xps:bram data_width 64
?meta spec_b_vacc xps:bram reg_prim_output off
?meta spec_b_vacc xps:bram reg_core_output off
?meta spec_b_vacc xps:bram optimization Minimum_Area
?meta spec_b_vacc xps:bram data_bin_pt 0
?meta spec_b_vacc xps:bram init_vals [0:2^10-1]
?meta spec_b_vacc xps:bram sample_rate 1
?meta snap_adc xps:snap_adc sample_rate 500
?meta snap_adc xps:snap_adc snap_inputs 6
?meta snap_adc xps:snap_adc adc_resolution 8
?meta adc_snap/ctrl xps:sw_reg io_dir From\_Processor
?meta adc_snap/ctrl xps:sw_reg io_delay 0
?meta adc_snap/ctrl xps:sw_reg init_val 0
?meta adc_snap/ctrl xps:sw_reg sample_period 1
?meta adc_snap/ctrl xps:sw_reg names reg
?meta adc_snap/ctrl xps:sw_reg bitwidths 32
?meta adc_snap/ctrl xps:sw_reg bin_pts 0
?meta adc_snap/ctrl xps:sw_reg arith_types 0
?meta adc_snap/ctrl xps:sw_reg sim_port off
?meta adc_snap/ctrl xps:sw_reg show_format on
?meta adc_snap/status xps:sw_reg io_dir To\_Processor
?meta adc_snap/status xps:sw_reg io_delay 0
?meta adc_snap/status xps:sw_reg init_val 0
?meta adc_snap/status xps:sw_reg sample_period 1
?meta adc_snap/status xps:sw_reg names reg
?meta adc_snap/status xps:sw_reg bitwidths 32
?meta adc_snap/status xps:sw_reg bin_pts 0
?meta adc_snap/status xps:sw_reg arith_types 0
?meta adc_snap/status xps:sw_reg sim_port off
?meta adc_snap/status xps:sw_reg show_format on
?meta adc_snap_trig xps:sw_reg io_dir From\_Processor
?meta adc_snap_trig xps:sw_reg io_delay 0
?meta adc_snap_trig xps:sw_reg init_val 0
?meta adc_snap_trig xps:sw_reg sample_period 1
?meta adc_snap_trig xps:sw_reg names reg
?meta adc_snap_trig xps:sw_reg bitwidths 1
?meta adc_snap_trig xps:sw_reg bin_pts 0
?meta adc_snap_trig xps:sw_reg arith_types 2
?meta adc_snap_trig xps:sw_reg sim_port on
?meta adc_snap_trig xps:sw_reg show_format off
?meta arm xps:sw_reg io_dir From\_Processor
?meta arm xps:sw_reg io_delay 0
?meta arm xps:sw_reg init_val 0
?meta arm xps:sw_reg sample_period 1
?meta arm xps:sw_reg names reg
?meta arm xps:sw_reg bitwidths 1
?meta arm xps:sw_reg bin_pts 0
?meta arm xps:sw_reg arith_types 2
?meta arm xps:sw_reg sim_port on
?meta arm xps:sw_reg show_format off
?meta ch_1_sel xps:sw_reg io_dir From\_Processor
?meta ch_1_sel xps:sw_reg io_delay 0
?meta ch_1_sel xps:sw_reg init_val 0
?meta ch_1_sel xps:sw_reg sample_period 1
?meta ch_1_sel xps:sw_reg names reg
?meta ch_1_sel xps:sw_reg bitwidths 3
?meta ch_1_sel xps:sw_reg bin_pts 0
?meta ch_1_sel xps:sw_reg arith_types 0
?meta ch_1_sel xps:sw_reg sim_port on
?meta ch_1_sel xps:sw_reg show_format off
?meta ch_2_sel xps:sw_reg io_dir From\_Processor
?meta ch_2_sel xps:sw_reg io_delay 0
?meta ch_2_sel xps:sw_reg init_val 0
?meta ch_2_sel xps:sw_reg sample_period 1
?meta ch_2_sel xps:sw_reg names reg
?meta ch_2_sel xps:sw_reg bitwidths 3
?meta ch_2_sel xps:sw_reg bin_pts 0
?meta ch_2_sel xps:sw_reg arith_types 0
?meta ch_2_sel xps:sw_reg sim_port on
?meta ch_2_sel xps:sw_reg show_format off
?meta dest_ip xps:sw_reg io_dir From\_Processor
?meta dest_ip xps:sw_reg io_delay 0
?meta dest_ip xps:sw_reg init_val 0
?meta dest_ip xps:sw_reg sample_period 1
?meta dest_ip xps:sw_reg names reg
?meta dest_ip xps:sw_reg bitwidths 32
?meta dest_ip xps:sw_reg bin_pts 0
?meta dest_ip xps:sw_reg arith_types 0
?meta dest_ip xps:sw_reg sim_port on
?meta dest_ip xps:sw_reg show_format on
?meta dest_port xps:sw_reg io_dir From\_Processor
?meta dest_port xps:sw_reg io_delay 0
?meta dest_port xps:sw_reg init_val 0
?meta dest_port xps:sw_reg sample_period 1
?meta dest_port xps:sw_reg names reg
?meta dest_port xps:sw_reg bitwidths 16
?meta dest_port xps:sw_reg bin_pts 0
?meta dest_port xps:sw_reg arith_types 0
?meta dest_port xps:sw_reg sim_port on
?meta dest_port xps:sw_reg show_format on
?meta fft_overflow_cnt xps:sw_reg io_dir To\_Processor
?meta fft_overflow_cnt xps:sw_reg io_delay 0
?meta fft_overflow_cnt xps:sw_reg init_val 0
?meta fft_overflow_cnt xps:sw_reg sample_period 1
?meta fft_overflow_cnt xps:sw_reg names reg
?meta fft_overflow_cnt xps:sw_reg bitwidths 32
?meta fft_overflow_cnt xps:sw_reg bin_pts 0
?meta fft_overflow_cnt xps:sw_reg arith_types 0
?meta fft_overflow_cnt xps:sw_reg sim_port on
?meta fft_overflow_cnt xps:sw_reg show_format on
?meta fft_shift xps:sw_reg io_dir From\_Processor
?meta fft_shift xps:sw_reg io_delay 0
?meta fft_shift xps:sw_reg init_val 0
?meta fft_shift xps:sw_reg sample_period 1
?meta fft_shift xps:sw_reg names reg
?meta fft_shift xps:sw_reg bitwidths 32
?meta fft_shift xps:sw_reg bin_pts 0
?meta fft_shift xps:sw_reg arith_types 0
?meta fft_shift xps:sw_reg sim_port on
?meta fft_shift xps:sw_reg show_format off
?meta gbe0/rxctr xps:sw_reg io_dir To\_Processor
?meta gbe0/rxctr xps:sw_reg io_delay 1
?meta gbe0/rxctr xps:sw_reg init_val 0
?meta gbe0/rxctr xps:sw_reg sample_period 1
?meta gbe0/rxctr xps:sw_reg names reg
?meta gbe0/rxctr xps:sw_reg bitwidths 16
?meta gbe0/rxctr xps:sw_reg bin_pts 0
?meta gbe0/rxctr xps:sw_reg arith_types 0
?meta gbe0/rxctr xps:sw_reg sim_port off
?meta gbe0/rxctr xps:sw_reg show_format on
?meta gbe0/rxeofctr xps:sw_reg io_dir To\_Processor
?meta gbe0/rxeofctr xps:sw_reg io_delay 1
?meta gbe0/rxeofctr xps:sw_reg init_val 0
?meta gbe0/rxeofctr xps:sw_reg sample_period 1
?meta gbe0/rxeofctr xps:sw_reg names reg
?meta gbe0/rxeofctr xps:sw_reg bitwidths 16
?meta gbe0/rxeofctr xps:sw_reg bin_pts 0
?meta gbe0/rxeofctr xps:sw_reg arith_types 0
?meta gbe0/rxeofctr xps:sw_reg sim_port off
?meta gbe0/rxeofctr xps:sw_reg show_format on
?meta gbe0/rxs/ss/ctrl xps:sw_reg io_dir From\_Processor
?meta gbe0/rxs/ss/ctrl xps:sw_reg io_delay 0
?meta gbe0/rxs/ss/ctrl xps:sw_reg init_val 0
?meta gbe0/rxs/ss/ctrl xps:sw_reg sample_period 1
?meta gbe0/rxs/ss/ctrl xps:sw_reg names reg
?meta gbe0/rxs/ss/ctrl xps:sw_reg bitwidths 32
?meta gbe0/rxs/ss/ctrl xps:sw_reg bin_pts 0
?meta gbe0/rxs/ss/ctrl xps:sw_reg arith_types 0
?meta gbe0/rxs/ss/ctrl xps:sw_reg sim_port off
?meta gbe0/rxs/ss/ctrl xps:sw_reg show_format on
?meta gbe0/rxs/ss/status xps:sw_reg io_dir To\_Processor
?meta gbe0/rxs/ss/status xps:sw_reg io_delay 0
?meta gbe0/rxs/ss/status xps:sw_reg init_val 0
?meta gbe0/rxs/ss/status xps:sw_reg sample_period 1
?meta gbe0/rxs/ss/status xps:sw_reg names reg
?meta gbe0/rxs/ss/status xps:sw_reg bitwidths 32
?meta gbe0/rxs/ss/status xps:sw_reg bin_pts 0
?meta gbe0/rxs/ss/status xps:sw_reg arith_types 0
?meta gbe0/rxs/ss/status xps:sw_reg sim_port off
?meta gbe0/rxs/ss/status xps:sw_reg show_format on
?meta gbe1_linkup xps:sw_reg io_dir To\_Processor
?meta gbe1_linkup xps:sw_reg io_delay 0
?meta gbe1_linkup xps:sw_reg init_val 0
?meta gbe1_linkup xps:sw_reg sample_period 1
?meta gbe1_linkup xps:sw_reg names reg
?meta gbe1_linkup xps:sw_reg bitwidths 1
?meta gbe1_linkup xps:sw_reg bin_pts 0
?meta gbe1_linkup xps:sw_reg arith_types 2
?meta gbe1_linkup xps:sw_reg sim_port on
?meta gbe1_linkup xps:sw_reg show_format off
?meta gbe1_tx_overflow xps:sw_reg io_dir To\_Processor
?meta gbe1_tx_overflow xps:sw_reg io_delay 0
?meta gbe1_tx_overflow xps:sw_reg init_val 0
?meta gbe1_tx_overflow xps:sw_reg sample_period 1
?meta gbe1_tx_overflow xps:sw_reg names reg
?meta gbe1_tx_overflow xps:sw_reg bitwidths 32
?meta gbe1_tx_overflow xps:sw_reg bin_pts 0
?meta gbe1_tx_overflow xps:sw_reg arith_types 0
?meta gbe1_tx_overflow xps:sw_reg sim_port on
?meta gbe1_tx_overflow xps:sw_reg show_format on
?meta master_rst xps:sw_reg io_dir From\_Processor
?meta master_rst xps:sw_reg io_delay 0
?meta master_rst xps:sw_reg init_val 0
?meta master_rst xps:sw_reg sample_period 1
?meta master_rst xps:sw_reg names reg
?meta master_rst xps:sw_reg bitwidths 1
?meta master_rst xps:sw_reg bin_pts 0
?meta master_rst xps:sw_reg arith_types 2
?meta master_rst xps:sw_reg sim_port on
?meta master_rst xps:sw_reg show_format off
?meta pps_cnt xps:sw_reg io_dir To\_Processor
?meta pps_cnt xps:sw_reg io_delay 0
?meta pps_cnt xps:sw_reg init_val 0
?meta pps_cnt xps:sw_reg sample_period 1
?meta pps_cnt xps:sw_reg names reg
?meta pps_cnt xps:sw_reg bitwidths 32
?meta pps_cnt xps:sw_reg bin_pts 0
?meta pps_cnt xps:sw_reg arith_types 0
?meta pps_cnt xps:sw_reg sim_port on
?meta pps_cnt xps:sw_reg show_format on
?meta pps_trig xps:sw_reg io_dir From\_Processor
?meta pps_trig xps:sw_reg io_delay 0
?meta pps_trig xps:sw_reg init_val 0
?meta pps_trig xps:sw_reg sample_period 1
?meta pps_trig xps:sw_reg names reg
?meta pps_trig xps:sw_reg bitwidths 1
?meta pps_trig xps:sw_reg bin_pts 0
?meta pps_trig xps:sw_reg arith_types 2
?meta pps_trig xps:sw_reg sim_port on
?meta pps_trig xps:sw_reg show_format off
?meta requant_a_overflow xps:sw_reg io_dir To\_Processor
?meta requant_a_overflow xps:sw_reg io_delay 0
?meta requant_a_overflow xps:sw_reg init_val 0
?meta requant_a_overflow xps:sw_reg sample_period 1
?meta requant_a_overflow xps:sw_reg names reg
?meta requant_a_overflow xps:sw_reg bitwidths 32
?meta requant_a_overflow xps:sw_reg bin_pts 0
?meta requant_a_overflow xps:sw_reg arith_types 0
?meta requant_a_overflow xps:sw_reg sim_port on
?meta requant_a_overflow xps:sw_reg show_format on
?meta requant_b_overflow xps:sw_reg io_dir To\_Processor
?meta requant_b_overflow xps:sw_reg io_delay 0
?meta requant_b_overflow xps:sw_reg init_val 0
?meta requant_b_overflow xps:sw_reg sample_period 1
?meta requant_b_overflow xps:sw_reg names reg
?meta requant_b_overflow xps:sw_reg bitwidths 32
?meta requant_b_overflow xps:sw_reg bin_pts 0
?meta requant_b_overflow xps:sw_reg arith_types 0
?meta requant_b_overflow xps:sw_reg sim_port on
?meta requant_b_overflow xps:sw_reg show_format on
?meta tx_en xps:sw_reg io_dir From\_Processor
?meta tx_en xps:sw_reg io_delay 0
?meta tx_en xps:sw_reg init_val 0
?meta tx_en xps:sw_reg sample_period 1
?meta tx_en xps:sw_reg names reg
?meta tx_en xps:sw_reg bitwidths 32
?meta tx_en xps:sw_reg bin_pts 0
?meta tx_en xps:sw_reg arith_types 2
?meta tx_en xps:sw_reg sim_port on
?meta tx_en xps:sw_reg show_format off
?meta vacc_trig xps:sw_reg io_dir From\_Processor
?meta vacc_trig xps:sw_reg io_delay 0
?meta vacc_trig xps:sw_reg init_val 0
?meta vacc_trig xps:sw_reg sample_period 1
?meta vacc_trig xps:sw_reg names reg
?meta vacc_trig xps:sw_reg bitwidths 1
?meta vacc_trig xps:sw_reg bin_pts 0
?meta vacc_trig xps:sw_reg arith_types 2
?meta vacc_trig xps:sw_reg sim_port on
?meta vacc_trig xps:sw_reg show_format off
?meta gbe0 xps:ten_gbe flavour sfp+
?meta gbe0 xps:ten_gbe slot 0
?meta gbe0 xps:ten_gbe port_r1 0
?meta gbe0 xps:ten_gbe port_r2_cx4 0
?meta gbe0 xps:ten_gbe port_r2_sfpp 0
?meta gbe0 xps:ten_gbe rx_dist_ram off
?meta gbe0 xps:ten_gbe large_frames off
?meta gbe0 xps:ten_gbe show_param on
?meta gbe0 xps:ten_gbe pre_emph_r2 0.74
?meta gbe0 xps:ten_gbe pre_emph 3
?meta gbe0 xps:ten_gbe post_emph_r2 0.18
?meta gbe0 xps:ten_gbe rxeqmix_r2 7
?meta gbe0 xps:ten_gbe swing_r2 940
?meta gbe0 xps:ten_gbe swing 800
?meta gbe0 xps:ten_gbe fab_en on
?meta gbe0 xps:ten_gbe fab_mac 2207781620256
?meta gbe0 xps:ten_gbe fab_ip 3232235524
?meta gbe0 xps:ten_gbe fab_udp 8511
?meta gbe0 xps:ten_gbe fab_gate 1
?meta gbe0 xps:ten_gbe cpu_rx_en on
?meta gbe0 xps:ten_gbe cpu_tx_en on
?meta gbe0 xps:ten_gbe ttl 255
?meta gbe0 xps:ten_gbe promisc_mode off
?meta gbe0 xps:ten_gbe debug_ctr_width 16
?meta gbe0 xps:ten_gbe txctr off
?meta gbe0 xps:ten_gbe txerrctr off
?meta gbe0 xps:ten_gbe txerrctr_len 100
?meta gbe0 xps:ten_gbe txofctr off
?meta gbe0 xps:ten_gbe txfullctr off
?meta gbe0 xps:ten_gbe txvldctr off
?meta gbe0 xps:ten_gbe txsnaplen 0\_-\_no\_snap
?meta gbe0 xps:ten_gbe rxctr on
?meta gbe0 xps:ten_gbe rxerrctr off
?meta gbe0 xps:ten_gbe rxerrctr_len 100
?meta gbe0 xps:ten_gbe rxofctr off
?meta gbe0 xps:ten_gbe rxbadctr off
?meta gbe0 xps:ten_gbe rxvldctr off
?meta gbe0 xps:ten_gbe rxeofctr on
?meta gbe0 xps:ten_gbe rxsnaplen 512
?meta gbe1 xps:ten_gbe flavour sfp+
?meta gbe1 xps:ten_gbe slot 0
?meta gbe1 xps:ten_gbe port_r1 1
?meta gbe1 xps:ten_gbe port_r2_cx4 0
?meta gbe1 xps:ten_gbe port_r2_sfpp 0
?meta gbe1 xps:ten_gbe rx_dist_ram off
?meta gbe1 xps:ten_gbe large_frames on
?meta gbe1 xps:ten_gbe show_param on
?meta gbe1 xps:ten_gbe pre_emph_r2 1.07
?meta gbe1 xps:ten_gbe pre_emph 3
?meta gbe1 xps:ten_gbe post_emph_r2 0.18
?meta gbe1 xps:ten_gbe rxeqmix_r2 7
?meta gbe1 xps:ten_gbe swing_r2 940
?meta gbe1 xps:ten_gbe swing 800
?meta gbe1 xps:ten_gbe fab_en on
?meta gbe1 xps:ten_gbe fab_mac 2207781620257
?meta gbe1 xps:ten_gbe fab_ip 3232235525
?meta gbe1 xps:ten_gbe fab_udp 3000
?meta gbe1 xps:ten_gbe fab_gate 1
?meta gbe1 xps:ten_gbe cpu_rx_en on
?meta gbe1 xps:ten_gbe cpu_tx_en on
?meta gbe1 xps:ten_gbe ttl 255
?meta gbe1 xps:ten_gbe promisc_mode off
?meta gbe1 xps:ten_gbe debug_ctr_width 32
?meta gbe1 xps:ten_gbe txctr off
?meta gbe1 xps:ten_gbe txerrctr off
?meta gbe1 xps:ten_gbe txerrctr_len 100
?meta gbe1 xps:ten_gbe txofctr off
?meta gbe1 xps:ten_gbe txfullctr off
?meta gbe1 xps:ten_gbe txvldctr off
?meta gbe1 xps:ten_gbe txsnaplen 0\_-\_no\_snap
?meta gbe1 xps:ten_gbe rxctr off
?meta gbe1 xps:ten_gbe rxerrctr off
?meta gbe1 xps:ten_gbe rxerrctr_len 100
?meta gbe1 xps:ten_gbe rxofctr off
?meta gbe1 xps:ten_gbe rxbadctr off
?meta gbe1 xps:ten_gbe rxvldctr off
?meta gbe1 xps:ten_gbe rxeofctr off
?meta gbe1 xps:ten_gbe rxsnaplen 0\_-\_no\_snap
?meta gbe0/rxs casper:bitsnap io_names [led_up\_led_rx\_data_in\_valid_in\_ip_in\_eof_in\_bad_frame\_overrun]
?meta gbe0/rxs casper:bitsnap io_widths [1\_1\_64\_1\_32\_1\_1\_1]
?meta gbe0/rxs casper:bitsnap io_bps [0\_0\_0\_0\_0\_0\_0\_0]
?meta gbe0/rxs casper:bitsnap io_types [2\_2\_0\_2\_0\_2\_2\_2]
?meta gbe0/rxs casper:bitsnap show_format on
?meta gbe0/rxs casper:bitsnap snap_storage bram
?meta gbe0/rxs casper:bitsnap snap_dram_dimm 2
?meta gbe0/rxs casper:bitsnap snap_dram_clock 250
?meta gbe0/rxs casper:bitsnap snap_nsamples 9
?meta gbe0/rxs casper:bitsnap snap_data_width 128
?meta gbe0/rxs casper:bitsnap snap_offset off
?meta gbe0/rxs casper:bitsnap snap_circap off
?meta gbe0/rxs casper:bitsnap snap_value off
?meta gbe0/rxs casper:bitsnap snap_ext_arm off
?meta gbe0/rxs casper:bitsnap snap_ext_circ off
?meta gbe0/rxs casper:bitsnap snap_provide_outputs on
?meta gbe0/rxs casper:bitsnap snap_use_dsp48 on
?meta gbe0/rxs casper:bitsnap snap_delay 5
?meta gbe0/rxs casper:bitsnap extra_names [notused]
?meta gbe0/rxs casper:bitsnap extra_widths 32
?meta gbe0/rxs casper:bitsnap extra_bps 0
?meta gbe0/rxs casper:bitsnap extra_types 0
?meta fft_wideband_real1 casper:fft_wideband_real n_streams 2
?meta fft_wideband_real1 casper:fft_wideband_real fftsize 12
?meta fft_wideband_real1 casper:fft_wideband_real n_inputs 1
?meta fft_wideband_real1 casper:fft_wideband_real input_bit_width 18
?meta fft_wideband_real1 casper:fft_wideband_real bin_pt_in 17
?meta fft_wideband_real1 casper:fft_wideband_real coeff_bit_width 18
?meta fft_wideband_real1 casper:fft_wideband_real unscramble on
?meta fft_wideband_real1 casper:fft_wideband_real async off
?meta fft_wideband_real1 casper:fft_wideband_real floating_point off
?meta fft_wideband_real1 casper:fft_wideband_real float_type single
?meta fft_wideband_real1 casper:fft_wideband_real exp_width 8
?meta fft_wideband_real1 casper:fft_wideband_real frac_width 24
?meta fft_wideband_real1 casper:fft_wideband_real add_latency 4
?meta fft_wideband_real1 casper:fft_wideband_real mult_latency 2
?meta fft_wideband_real1 casper:fft_wideband_real bram_latency 2
?meta fft_wideband_real1 casper:fft_wideband_real conv_latency 1
?meta fft_wideband_real1 casper:fft_wideband_real input_latency 0
?meta fft_wideband_real1 casper:fft_wideband_real biplex_direct_latency 0
?meta fft_wideband_real1 casper:fft_wideband_real add_pipe_latency 0
?meta fft_wideband_real1 casper:fft_wideband_real mult_pipe_latency 0
?meta fft_wideband_real1 casper:fft_wideband_real quantization Round\_\_(unbiased:\_+/-\_Inf)
?meta fft_wideband_real1 casper:fft_wideband_real overflow Saturate
?meta fft_wideband_real1 casper:fft_wideband_real delays_bit_limit 8
?meta fft_wideband_real1 casper:fft_wideband_real coeffs_bit_limit 9
?meta fft_wideband_real1 casper:fft_wideband_real coeff_sharing on
?meta fft_wideband_real1 casper:fft_wideband_real coeff_decimation on
?meta fft_wideband_real1 casper:fft_wideband_real coeff_generation on
?meta fft_wideband_real1 casper:fft_wideband_real cal_bits 1
?meta fft_wideband_real1 casper:fft_wideband_real n_bits_rotation 25
?meta fft_wideband_real1 casper:fft_wideband_real mult_spec 2
?meta fft_wideband_real1 casper:fft_wideband_real max_fanout 4
?meta fft_wideband_real1 casper:fft_wideband_real bitgrowth off
?meta fft_wideband_real1 casper:fft_wideband_real max_bits 19
?meta fft_wideband_real1 casper:fft_wideband_real hardcode_shifts off
?meta fft_wideband_real1 casper:fft_wideband_real shift_schedule []
?meta fft_wideband_real1 casper:fft_wideband_real dsp48_adders off
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x n_inputs 1
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x fftsize 11
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x input_bit_width 18
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x bin_pt_in 17
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x coeff_bit_width 18
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x async off
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x floating_point off
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x float_type single
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x exp_width 8
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x frac_width 24
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x add_latency 4
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x mult_latency 2
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x bram_latency 2
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x conv_latency 1
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x add_pipe_latency 0
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x mult_pipe_latency 0
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x quantization Round\_\_(unbiased:\_+/-\_Inf)
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x overflow Saturate
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x delays_bit_limit 8
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x coeffs_bit_limit 9
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x coeff_sharing on
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x coeff_decimation on
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x max_fanout 4
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x mult_spec [2\_2\_2\_2\_2\_2\_2\_2\_2\_2\_2]
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x bitgrowth off
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x max_bits 19
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x hardcode_shifts off
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x shift_schedule [1\_1\_1\_1\_1\_1\_1\_1\_1\_1\_1]
?meta fft_wideband_real1/fft_biplex_real_4x casper:fft_biplex_real_4x dsp48_adders off
?meta pfb_fir_real casper:pfb_fir_real pfbsize 12
?meta pfb_fir_real casper:pfb_fir_real totaltaps 9
?meta pfb_fir_real casper:pfb_fir_real windowtype hamming
?meta pfb_fir_real casper:pfb_fir_real n_inputs 1
?meta pfb_fir_real casper:pfb_fir_real makebiplex on
?meta pfb_fir_real casper:pfb_fir_real bitwidthin 8
?meta pfb_fir_real casper:pfb_fir_real bitwidthout 18
?meta pfb_fir_real casper:pfb_fir_real coeffbitwidth 18
?meta pfb_fir_real casper:pfb_fir_real coeffdistmem off
?meta pfb_fir_real casper:pfb_fir_real add_latency 1
?meta pfb_fir_real casper:pfb_fir_real mult_latency 2
?meta pfb_fir_real casper:pfb_fir_real bram_latency 2
?meta pfb_fir_real casper:pfb_fir_real fan_latency 1
?meta pfb_fir_real casper:pfb_fir_real conv_latency 1
?meta pfb_fir_real casper:pfb_fir_real quantization Round\_\_(unbiased:\_Even\_Values)
?meta pfb_fir_real casper:pfb_fir_real fwidth 1
?meta pfb_fir_real casper:pfb_fir_real mult_spec 2
?meta pfb_fir_real casper:pfb_fir_real adder_folding on
?meta pfb_fir_real casper:pfb_fir_real adder_imp Fabric
?meta pfb_fir_real casper:pfb_fir_real coeffs_share off
?meta adc_snap casper:snapshot storage bram
?meta adc_snap casper:snapshot dram_dimm 2
?meta adc_snap casper:snapshot dram_clock 250
?meta adc_snap casper:snapshot nsamples 12
?meta adc_snap casper:snapshot data_width 32
?meta adc_snap casper:snapshot offset off
?meta adc_snap casper:snapshot circap off
?meta adc_snap casper:snapshot value off
?meta adc_snap casper:snapshot ext_arm off
?meta adc_snap casper:snapshot ext_circ off
?meta adc_snap casper:snapshot provide_outputs on
?meta adc_snap casper:snapshot use_dsp48 on
?meta gbe0/rxs/ss casper:snapshot storage bram
?meta gbe0/rxs/ss casper:snapshot dram_dimm 2
?meta gbe0/rxs/ss casper:snapshot dram_clock 250
?meta gbe0/rxs/ss casper:snapshot nsamples 9
?meta gbe0/rxs/ss casper:snapshot data_width 128
?meta gbe0/rxs/ss casper:snapshot offset off
?meta gbe0/rxs/ss casper:snapshot circap off
?meta gbe0/rxs/ss casper:snapshot value off
?meta gbe0/rxs/ss casper:snapshot ext_arm off
?meta gbe0/rxs/ss casper:snapshot ext_circ off
?meta gbe0/rxs/ss casper:snapshot provide_outputs off
?meta gbe0/rxs/ss casper:snapshot use_dsp48 on
?meta 77777 77777 tags casper:bitsnap,casper:fft_biplex_real_4x,casper:fft_wideband_real,casper:pfb_fir_real,casper:snapshot,xps:bram,xps:snap_adc,xps:sw_reg,xps:ten_gbe,xps:xsg
?meta 77777 77777 system grex_gateware
?meta 77777 77777 builddate 07-Jul-2023\_11:51:06
?meta 77777 77777 xlSgRoot /data/Xilinx/Vivado/2019.1/lib/lnx64.o/matlab/sysgen.mexa64
?meta 77777_git rcs /home/kiran/Desktop/gateware/grex_gateware.slx [kiran@maze] [git@github.com:GReX-Telescope/gateware.git] [6f6b638c2fcf792416533808346779dcce578141 - me@kiranshila.com - Wed, 29 Mar 2023 17:42:52 -0700] [On branch main - Your branch is up-to-date with 'origin/main'.] [' M grex_gateware.slx']
?meta 77777_git rcs /home/kiran/Desktop/gateware/mlib_devel [kiran@maze] [https://github.com/casper-astro/mlib_devel.git] [4a1c2cb984b015ec175006f3fbd1e94cba20a76d - mitch.burnett@byu.edu - Tue, 25 Oct 2022 10:42:32 -0600] [On branch m2019a - Your branch is up-to-date with 'origin/m2019a'.] [' M jasper_library/hdl_sources/onehundred_gbe/kutleng_skarab2_bsp_firmware']
?meta 77777 77777 md5_header d2e49876eefc231a39b0d4a95a9746fd
?meta 77777 77777 md5_bitstream 6dc4088af9eebcad7fcd9cd0a769ddcd
?meta 77777 77777 flash_write_checksum 45578_1988
?quit
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