caravel-hal 1.1.0

Hardware Abstraction Layer Crate for the Caravel management SoC.
Documentation 
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use caravel_pac::MprjWbIenaOutRegister;

pub struct Wishbone {
    reg: &'static MprjWbIenaOutRegister,
}

unsafe impl Send for Wishbone {}

impl Wishbone {
    /// Constructs the Wishbone bus driver.
    #[allow(clippy::new_without_default)]
    pub const fn new() -> Self {
        Self {
            reg: MprjWbIenaOutRegister::new(),
        }
    }

    /// Enable the Wishbone bus
    pub fn enable(&self) {
        unsafe {
            self.reg.value.write(1);
        }
    }

    /// Disable the Wishbone bus
    pub fn disable(&self) {
        unsafe {
            self.reg.value.write(0);
        }
    }
}