Enum capstone_sys::arm_sysreg

#[repr(u32)]
pub enum arm_sysreg {
    ARM_SYSREG_INVALID,
    ARM_SYSREG_SPSR_C,
    ARM_SYSREG_SPSR_X,
    ARM_SYSREG_SPSR_S,
    ARM_SYSREG_SPSR_F,
    ARM_SYSREG_CPSR_C,
    ARM_SYSREG_CPSR_X,
    ARM_SYSREG_CPSR_S,
    ARM_SYSREG_CPSR_F,
    ARM_SYSREG_APSR,
    ARM_SYSREG_APSR_G,
    ARM_SYSREG_APSR_NZCVQ,
    ARM_SYSREG_APSR_NZCVQG,
    ARM_SYSREG_IAPSR,
    ARM_SYSREG_IAPSR_G,
    ARM_SYSREG_IAPSR_NZCVQG,
    ARM_SYSREG_IAPSR_NZCVQ,
    ARM_SYSREG_EAPSR,
    ARM_SYSREG_EAPSR_G,
    ARM_SYSREG_EAPSR_NZCVQG,
    ARM_SYSREG_EAPSR_NZCVQ,
    ARM_SYSREG_XPSR,
    ARM_SYSREG_XPSR_G,
    ARM_SYSREG_XPSR_NZCVQG,
    ARM_SYSREG_XPSR_NZCVQ,
    ARM_SYSREG_IPSR,
    ARM_SYSREG_EPSR,
    ARM_SYSREG_IEPSR,
    ARM_SYSREG_MSP,
    ARM_SYSREG_PSP,
    ARM_SYSREG_PRIMASK,
    ARM_SYSREG_BASEPRI,
    ARM_SYSREG_BASEPRI_MAX,
    ARM_SYSREG_FAULTMASK,
    ARM_SYSREG_CONTROL,
    ARM_SYSREG_R8_USR,
    ARM_SYSREG_R9_USR,
    ARM_SYSREG_R10_USR,
    ARM_SYSREG_R11_USR,
    ARM_SYSREG_R12_USR,
    ARM_SYSREG_SP_USR,
    ARM_SYSREG_LR_USR,
    ARM_SYSREG_R8_FIQ,
    ARM_SYSREG_R9_FIQ,
    ARM_SYSREG_R10_FIQ,
    ARM_SYSREG_R11_FIQ,
    ARM_SYSREG_R12_FIQ,
    ARM_SYSREG_SP_FIQ,
    ARM_SYSREG_LR_FIQ,
    ARM_SYSREG_LR_IRQ,
    ARM_SYSREG_SP_IRQ,
    ARM_SYSREG_LR_SVC,
    ARM_SYSREG_SP_SVC,
    ARM_SYSREG_LR_ABT,
    ARM_SYSREG_SP_ABT,
    ARM_SYSREG_LR_UND,
    ARM_SYSREG_SP_UND,
    ARM_SYSREG_LR_MON,
    ARM_SYSREG_SP_MON,
    ARM_SYSREG_ELR_HYP,
    ARM_SYSREG_SP_HYP,
    ARM_SYSREG_SPSR_FIQ,
    ARM_SYSREG_SPSR_IRQ,
    ARM_SYSREG_SPSR_SVC,
    ARM_SYSREG_SPSR_ABT,
    ARM_SYSREG_SPSR_UND,
    ARM_SYSREG_SPSR_MON,
    ARM_SYSREG_SPSR_HYP,
}

Variants

ARM_SYSREG_INVALID

Special registers for MSR

ARM_SYSREG_SPSR_C

Special registers for MSR

ARM_SYSREG_SPSR_X

Special registers for MSR

ARM_SYSREG_SPSR_S

Special registers for MSR

ARM_SYSREG_SPSR_F

Special registers for MSR

ARM_SYSREG_CPSR_C

Special registers for MSR

ARM_SYSREG_CPSR_X

Special registers for MSR

ARM_SYSREG_CPSR_S

Special registers for MSR

ARM_SYSREG_CPSR_F

Special registers for MSR

ARM_SYSREG_APSR

Special registers for MSR

ARM_SYSREG_APSR_G

Special registers for MSR

ARM_SYSREG_APSR_NZCVQ

Special registers for MSR

ARM_SYSREG_APSR_NZCVQG

Special registers for MSR

ARM_SYSREG_IAPSR

Special registers for MSR

ARM_SYSREG_IAPSR_G

Special registers for MSR

ARM_SYSREG_IAPSR_NZCVQG

Special registers for MSR

ARM_SYSREG_IAPSR_NZCVQ

Special registers for MSR

ARM_SYSREG_EAPSR

Special registers for MSR

ARM_SYSREG_EAPSR_G

Special registers for MSR

ARM_SYSREG_EAPSR_NZCVQG

Special registers for MSR

ARM_SYSREG_EAPSR_NZCVQ

Special registers for MSR

ARM_SYSREG_XPSR

Special registers for MSR

ARM_SYSREG_XPSR_G

Special registers for MSR

ARM_SYSREG_XPSR_NZCVQG

Special registers for MSR

ARM_SYSREG_XPSR_NZCVQ

Special registers for MSR

ARM_SYSREG_IPSR

Special registers for MSR

ARM_SYSREG_EPSR

Special registers for MSR

ARM_SYSREG_IEPSR

Special registers for MSR

ARM_SYSREG_MSP

Special registers for MSR

ARM_SYSREG_PSP

Special registers for MSR

ARM_SYSREG_PRIMASK

Special registers for MSR

ARM_SYSREG_BASEPRI

Special registers for MSR

ARM_SYSREG_BASEPRI_MAX

Special registers for MSR

ARM_SYSREG_FAULTMASK

Special registers for MSR

ARM_SYSREG_CONTROL

Special registers for MSR

ARM_SYSREG_R8_USR

Special registers for MSR

ARM_SYSREG_R9_USR

Special registers for MSR

ARM_SYSREG_R10_USR

Special registers for MSR

ARM_SYSREG_R11_USR

Special registers for MSR

ARM_SYSREG_R12_USR

Special registers for MSR

ARM_SYSREG_SP_USR

Special registers for MSR

ARM_SYSREG_LR_USR

Special registers for MSR

ARM_SYSREG_R8_FIQ

Special registers for MSR

ARM_SYSREG_R9_FIQ

Special registers for MSR

ARM_SYSREG_R10_FIQ

Special registers for MSR

ARM_SYSREG_R11_FIQ

Special registers for MSR

ARM_SYSREG_R12_FIQ

Special registers for MSR

ARM_SYSREG_SP_FIQ

Special registers for MSR

ARM_SYSREG_LR_FIQ

Special registers for MSR

ARM_SYSREG_LR_IRQ

Special registers for MSR

ARM_SYSREG_SP_IRQ

Special registers for MSR

ARM_SYSREG_LR_SVC

Special registers for MSR

ARM_SYSREG_SP_SVC

Special registers for MSR

ARM_SYSREG_LR_ABT

Special registers for MSR

ARM_SYSREG_SP_ABT

Special registers for MSR

ARM_SYSREG_LR_UND

Special registers for MSR

ARM_SYSREG_SP_UND

Special registers for MSR

ARM_SYSREG_LR_MON

Special registers for MSR

ARM_SYSREG_SP_MON

Special registers for MSR

ARM_SYSREG_ELR_HYP

Special registers for MSR

ARM_SYSREG_SP_HYP

Special registers for MSR

ARM_SYSREG_SPSR_FIQ

Special registers for MSR

ARM_SYSREG_SPSR_IRQ

Special registers for MSR

ARM_SYSREG_SPSR_SVC

Special registers for MSR

ARM_SYSREG_SPSR_ABT

Special registers for MSR

ARM_SYSREG_SPSR_UND

Special registers for MSR

ARM_SYSREG_SPSR_MON

Special registers for MSR

ARM_SYSREG_SPSR_HYP

Special registers for MSR

Trait Implementations

impl Eq for arm_sysreg

impl Copy for arm_sysreg

impl PartialEq<arm_sysreg> for arm_sysreg

fn eq(&self, other: &arm_sysreg) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]

default fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Clone for arm_sysreg

fn clone(&self) -> arm_sysreg

Returns a copy of the value.

default fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for arm_sysreg

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl Hash for arm_sysreg

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given [Hasher].

default fn hash_slice<H>(data: &[Self], state: &mut H) where
    H: Hasher, 

Feeds a slice of this type into the given [Hasher].