cands_interface 0.1.20

This is an interface for DigitalServo USB CAN board.
Documentation 
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// Register Address Sections
pub const REG_SPI_CONFIG: u16 = 0x0000;
pub const REG_DEV_CONFIG: u16 = 0x0800;
pub const REG_MCAN: u16 = 0x1000;
pub const REG_MRAM: u16 = 0x8000;
  
// SPI Registers and Device ID Register Addresses: 0x0000 Prefix
pub const REG_SPI_DEVICE_ID0: u16 = 0x0000;
pub const REG_SPI_DEVICE_ID1: u16 = 0x0004;
pub const REG_SPI_REVISION: u16 = 0x0008;
pub const REG_SPI_STATUS: u16 = 0x000C;
pub const REG_SPI_ERROR_STATUS_MASK: u16 = 0x0010;
  
// Device Configuration Register Addresses: 0x0800 Prefix
pub const REG_DEV_MODES_AND_PINS: u16 = 0x0800;
pub const REG_DEV_TIMESTAMP_PRESCALER: u16 = 0x0804;
pub const REG_DEV_TEST_REGISTERS: u16 = 0x0808;
pub const REG_DEV_IR: u16 = 0x0820;
pub const REG_DEV_IE: u16 = 0x0830;
  
// MCAN Register Addresses: 0x1000 Prefix
pub const REG_MCAN_CREL: u16 = 0x1000;
pub const REG_MCAN_ENDN: u16 = 0x1004;
pub const REG_MCAN_CUST: u16 = 0x1008;
pub const REG_MCAN_DBTP: u16 = 0x100C;
pub const REG_MCAN_TEST: u16 = 0x1010;
pub const REG_MCAN_RWD: u16 = 0x1014;
pub const REG_MCAN_CCCR: u16 = 0x1018;
pub const REG_MCAN_NBTP: u16 = 0x101C;
pub const REG_MCAN_TSCC: u16 = 0x1020;
pub const REG_MCAN_TSCV: u16 = 0x1024;
pub const REG_MCAN_TOCC: u16 = 0x1028;
pub const REG_MCAN_TOCV: u16 = 0x102C;
pub const REG_MCAN_ECR: u16 = 0x1040;
pub const REG_MCAN_PSR: u16 = 0x1044;
pub const REG_MCAN_TDCR: u16 = 0x1048;
pub const REG_MCAN_IR: u16 = 0x1050;
pub const REG_MCAN_IE: u16 = 0x1054;
pub const REG_MCAN_ILS: u16 = 0x1058;
pub const REG_MCAN_ILE: u16 = 0x105C;
pub const REG_MCAN_GFC: u16 = 0x1080;
pub const REG_MCAN_SIDFC: u16 = 0x1084;
pub const REG_MCAN_XIDFC: u16 = 0x1088;
pub const REG_MCAN_XIDAM: u16 = 0x1090;
pub const REG_MCAN_HPMS: u16 = 0x1094;
pub const REG_MCAN_NDAT1: u16 = 0x1098;
pub const REG_MCAN_NDAT2: u16 = 0x109C;
pub const REG_MCAN_RXF0C: u16 = 0x10A0;
pub const REG_MCAN_RXF0S: u16 = 0x10A4;
pub const REG_MCAN_RXF0A: u16 = 0x10A8;
pub const REG_MCAN_RXBC: u16 = 0x10AC;
pub const REG_MCAN_RXF1C: u16 = 0x10B0;
pub const REG_MCAN_RXF1S: u16 = 0x10B4;
pub const REG_MCAN_RXF1A: u16 = 0x10B8;
pub const REG_MCAN_RXESC: u16 = 0x10BC;
pub const REG_MCAN_TXBC: u16 = 0x10C0;
pub const REG_MCAN_TXFQS: u16 = 0x10C4;
pub const REG_MCAN_TXESC: u16 = 0x10C8;
pub const REG_MCAN_TXBRP: u16 = 0x10CC;
pub const REG_MCAN_TXBAR: u16 = 0x10D0;
pub const REG_MCAN_TXBCR: u16 = 0x10D4;
pub const REG_MCAN_TXBTO: u16 = 0x10D8;
pub const REG_MCAN_TXBCF: u16 = 0x10DC;
pub const REG_MCAN_TXBTIE: u16 = 0x10E0;
pub const REG_MCAN_TXBCIE: u16 = 0x10E4;
pub const REG_MCAN_TXEFC: u16 = 0x10F0;
pub const REG_MCAN_TXEFS: u16 = 0x10F4;
pub const REG_MCAN_TXEFA: u16 = 0x10F8;

// DLC Value Defines: u32 = Used for RX and TX elements. The DLC[3:0] bit field
pub const MCAN_DLC_0B: u32 = 0x00000000;
pub const MCAN_DLC_1B: u32 = 0x00000001;
pub const MCAN_DLC_2B: u32 = 0x00000002;
pub const MCAN_DLC_3B: u32 = 0x00000003;
pub const MCAN_DLC_4B: u32 = 0x00000004;
pub const MCAN_DLC_5B: u32 = 0x00000005;
pub const MCAN_DLC_6B: u32 = 0x00000006;
pub const MCAN_DLC_7B: u32 = 0x00000007;
pub const MCAN_DLC_8B: u32 = 0x00000008;
pub const MCAN_DLC_12B: u32 = 0x00000009;
pub const MCAN_DLC_16B: u32 = 0x0000000A;
pub const MCAN_DLC_20B: u32 = 0x0000000B;
pub const MCAN_DLC_24B: u32 = 0x0000000C;
pub const MCAN_DLC_32B: u32 = 0x0000000D;
pub const MCAN_DLC_48B: u32 = 0x0000000E;
pub const MCAN_DLC_64B: u32 = 0x0000000F;
  
// MCAN Register Bit Field Defines
  
// DBTP
pub const REG_BITS_MCAN_DBTP_TDC_EN: u32 = 0x00800000;
  
// TEST
pub const REG_BITS_MCAN_TEST_RX_DOM: u32 = 0x00000000;
pub const REG_BITS_MCAN_TEST_RX_REC: u32 = 0x00000080;
pub const REG_BITS_MCAN_TEST_TX_SP: u32 = 0x00000020;
pub const REG_BITS_MCAN_TEST_TX_DOM: u32 = 0x00000040;
pub const REG_BITS_MCAN_TEST_TX_REC: u32 = 0x00000060;
pub const REG_BITS_MCAN_TEST_LOOP_BACK: u32 = 0x00000010;
  
// CCCR
pub const REG_BITS_MCAN_CCCR_RESERVED_MASK: u32 = 0xFFFF0C00;
pub const REG_BITS_MCAN_CCCR_NISO_ISO: u32 = 0x00000000;
pub const REG_BITS_MCAN_CCCR_NISO_BOSCH: u32 = 0x00008000;
pub const REG_BITS_MCAN_CCCR_TXP: u32 = 0x00004000;
pub const REG_BITS_MCAN_CCCR_EFBI: u32 = 0x00002000;
pub const REG_BITS_MCAN_CCCR_PXHD_DIS: u32 = 0x00001000;
pub const REG_BITS_MCAN_CCCR_BRSE: u32 = 0x00000200;
pub const REG_BITS_MCAN_CCCR_FDOE: u32 = 0x00000100;
pub const REG_BITS_MCAN_CCCR_TEST: u32 = 0x00000080;
pub const REG_BITS_MCAN_CCCR_DAR_DIS: u32 = 0x00000040;
pub const REG_BITS_MCAN_CCCR_MON: u32 = 0x00000020;
pub const REG_BITS_MCAN_CCCR_CSR: u32 = 0x00000010;
pub const REG_BITS_MCAN_CCCR_CSA: u32 = 0x00000008;
pub const REG_BITS_MCAN_CCCR_ASM: u32 = 0x00000004;
pub const REG_BITS_MCAN_CCCR_CCE: u32 = 0x00000002;
pub const REG_BITS_MCAN_CCCR_INIT: u32 = 0x00000001;
  
// IE
pub const REG_BITS_MCAN_IE_ARAE: u32 = 0x20000000;
pub const REG_BITS_MCAN_IE_PEDE: u32 = 0x10000000;
pub const REG_BITS_MCAN_IE_PEAE: u32 = 0x08000000;
pub const REG_BITS_MCAN_IE_WDIE: u32 = 0x04000000;
pub const REG_BITS_MCAN_IE_BOE: u32 = 0x02000000;
pub const REG_BITS_MCAN_IE_EWE: u32 = 0x01000000;
pub const REG_BITS_MCAN_IE_EPE: u32 = 0x00800000;
pub const REG_BITS_MCAN_IE_ELOE: u32 = 0x00400000;
pub const REG_BITS_MCAN_IE_BEUE: u32 = 0x00200000;
pub const REG_BITS_MCAN_IE_BECE: u32 = 0x00100000;
pub const REG_BITS_MCAN_IE_DRXE: u32 = 0x00080000;
pub const REG_BITS_MCAN_IE_TOOE: u32 = 0x00040000;
pub const REG_BITS_MCAN_IE_MRAFE: u32 = 0x00020000;
pub const REG_BITS_MCAN_IE_TSWE: u32 = 0x00010000;
pub const REG_BITS_MCAN_IE_TEFLE: u32 = 0x00008000;
pub const REG_BITS_MCAN_IE_TEFFE: u32 = 0x00004000;
pub const REG_BITS_MCAN_IE_TEFWE: u32 = 0x00002000;
pub const REG_BITS_MCAN_IE_TEFNE: u32 = 0x00001000;
pub const REG_BITS_MCAN_IE_TFEE: u32 = 0x00000800;
pub const REG_BITS_MCAN_IE_TCFE: u32 = 0x00000400;
pub const REG_BITS_MCAN_IE_TCE: u32 = 0x00000200;
pub const REG_BITS_MCAN_IE_HPME: u32 = 0x00000100;
pub const REG_BITS_MCAN_IE_RF1LE: u32 = 0x00000080;
pub const REG_BITS_MCAN_IE_RF1FE: u32 = 0x00000040;
pub const REG_BITS_MCAN_IE_RF1WE: u32 = 0x00000020;
pub const REG_BITS_MCAN_IE_RF1NE: u32 = 0x00000010;
pub const REG_BITS_MCAN_IE_RF0LE: u32 = 0x00000008;
pub const REG_BITS_MCAN_IE_RF0FE: u32 = 0x00000004;
pub const REG_BITS_MCAN_IE_RF0WE: u32 = 0x00000002;
pub const REG_BITS_MCAN_IE_RF0NE: u32 = 0x00000001;
  
// IR
pub const REG_BITS_MCAN_IR_ARA: u32 = 0x20000000;
pub const REG_BITS_MCAN_IR_PED: u32 = 0x10000000;
pub const REG_BITS_MCAN_IR_PEA: u32 = 0x08000000;
pub const REG_BITS_MCAN_IR_WDI: u32 = 0x04000000;
pub const REG_BITS_MCAN_IR_BO: u32 = 0x02000000;
pub const REG_BITS_MCAN_IR_EW: u32 = 0x01000000;
pub const REG_BITS_MCAN_IR_EP: u32 = 0x00800000;
pub const REG_BITS_MCAN_IR_ELO: u32 = 0x00400000;
pub const REG_BITS_MCAN_IR_BEU: u32 = 0x00200000;
pub const REG_BITS_MCAN_IR_BEC: u32 = 0x00100000;
pub const REG_BITS_MCAN_IR_DRX: u32 = 0x00080000;
pub const REG_BITS_MCAN_IR_TOO: u32 = 0x00040000;
pub const REG_BITS_MCAN_IR_MRAF: u32 = 0x00020000;
pub const REG_BITS_MCAN_IR_TSW: u32 = 0x00010000;
pub const REG_BITS_MCAN_IR_TEFL: u32 = 0x00008000;
pub const REG_BITS_MCAN_IR_TEFF: u32 = 0x00004000;
pub const REG_BITS_MCAN_IR_TEFW: u32 = 0x00002000;
pub const REG_BITS_MCAN_IR_TEFN: u32 = 0x00001000;
pub const REG_BITS_MCAN_IR_TFE: u32 = 0x00000800;
pub const REG_BITS_MCAN_IR_TCF: u32 = 0x00000400;
pub const REG_BITS_MCAN_IR_TC: u32 = 0x00000200;
pub const REG_BITS_MCAN_IR_HPM: u32 = 0x00000100;
pub const REG_BITS_MCAN_IR_RF1L: u32 = 0x00000080;
pub const REG_BITS_MCAN_IR_RF1F: u32 = 0x00000040;
pub const REG_BITS_MCAN_IR_RF1W: u32 = 0x00000020;
pub const REG_BITS_MCAN_IR_RF1N: u32 = 0x00000010;
pub const REG_BITS_MCAN_IR_RF0L: u32 = 0x00000008;
pub const REG_BITS_MCAN_IR_RF0F: u32 = 0x00000004;
pub const REG_BITS_MCAN_IR_RF0W: u32 = 0x00000002;
pub const REG_BITS_MCAN_IR_RF0N: u32 = 0x00000001;
  
// ILS
pub const REG_BITS_MCAN_IE_ARAL: u32 = 0x20000000;
pub const REG_BITS_MCAN_IE_PEDL: u32 = 0x10000000;
pub const REG_BITS_MCAN_IE_PEAL: u32 = 0x08000000;
pub const REG_BITS_MCAN_IE_WDIL: u32 = 0x04000000;
pub const REG_BITS_MCAN_IE_BOL: u32 = 0x02000000;
pub const REG_BITS_MCAN_IE_EWL: u32 = 0x01000000;
pub const REG_BITS_MCAN_IE_EPL: u32 = 0x00800000;
pub const REG_BITS_MCAN_IE_ELOL: u32 = 0x00400000;
pub const REG_BITS_MCAN_IE_BEUL: u32 = 0x00200000;
pub const REG_BITS_MCAN_IE_BECL: u32 = 0x00100000;
pub const REG_BITS_MCAN_IE_DRXL: u32 = 0x00080000;
pub const REG_BITS_MCAN_IE_TOOL: u32 = 0x00040000;
pub const REG_BITS_MCAN_IE_MRAFL: u32 = 0x00020000;
pub const REG_BITS_MCAN_IE_TSWL: u32 = 0x00010000;
pub const REG_BITS_MCAN_IE_TEFLL: u32 = 0x00008000;
pub const REG_BITS_MCAN_IE_TEFFL: u32 = 0x00004000;
pub const REG_BITS_MCAN_IE_TEFWL: u32 = 0x00002000;
pub const REG_BITS_MCAN_IE_TEFNL: u32 = 0x00001000;
pub const REG_BITS_MCAN_IE_TFEL: u32 = 0x00000800;
pub const REG_BITS_MCAN_IE_TCFL: u32 = 0x00000400;
pub const REG_BITS_MCAN_IE_TCL: u32 = 0x00000200;
pub const REG_BITS_MCAN_IE_HPML: u32 = 0x00000100;
pub const REG_BITS_MCAN_IE_RF1LL: u32 = 0x00000080;
pub const REG_BITS_MCAN_IE_RF1FL: u32 = 0x00000040;
pub const REG_BITS_MCAN_IE_RF1WL: u32 = 0x00000020;
pub const REG_BITS_MCAN_IE_RF1NL: u32 = 0x00000010;
pub const REG_BITS_MCAN_IE_RF0LL: u32 = 0x00000008;
pub const REG_BITS_MCAN_IE_RF0FL: u32 = 0x00000004;
pub const REG_BITS_MCAN_IE_RF0WL: u32 = 0x00000002;
pub const REG_BITS_MCAN_IE_RF0NL: u32 = 0x00000001;
  
// ILE
pub const REG_BITS_MCAN_ILE_EINT1: u32 = 0x00000002;
pub const REG_BITS_MCAN_ILE_EINT0: u32 = 0x00000001;
  
// GFC
pub const REG_BITS_MCAN_GFC_ANFS_FIFO0: u32 = 0x00000000;
pub const REG_BITS_MCAN_GFC_ANFS_FIFO1: u32 = 0x00000010;
pub const REG_BITS_MCAN_GFC_ANFE_FIFO0: u32 = 0x00000000;
pub const REG_BITS_MCAN_GFC_ANFE_FIFO1: u32 = 0x00000004;
pub const REG_BITS_MCAN_GFC_RRFS: u32 = 0x00000002;
pub const REG_BITS_MCAN_GFC_RRFE: u32 = 0x00000001;
pub const REG_BITS_MCAN_GFC_MASK: u32 = 0x0000003F;
  
// NDAT1
  
// NDAT2
  
// RXF0C
pub const REG_BITS_MCAN_RXF0C_F0OM_OVERWRITE: u32 = 0x80000000;
  
// RXESC
pub const REG_BITS_MCAN_RXESC_RBDS_8B: u32 = 0x00000000;
pub const REG_BITS_MCAN_RXESC_RBDS_12B: u32 = 0x00000100;
pub const REG_BITS_MCAN_RXESC_RBDS_16B: u32 = 0x00000200;
pub const REG_BITS_MCAN_RXESC_RBDS_20B: u32 = 0x00000300;
pub const REG_BITS_MCAN_RXESC_RBDS_24B: u32 = 0x00000400;
pub const REG_BITS_MCAN_RXESC_RBDS_32B: u32 = 0x00000500;
pub const REG_BITS_MCAN_RXESC_RBDS_48B: u32 = 0x00000600;
pub const REG_BITS_MCAN_RXESC_RBDS_64B: u32 = 0x00000700;
pub const REG_BITS_MCAN_RXESC_F1DS_8B: u32 = 0x00000000;
pub const REG_BITS_MCAN_RXESC_F1DS_12B: u32 = 0x00000010;
pub const REG_BITS_MCAN_RXESC_F1DS_16B: u32 = 0x00000020;
pub const REG_BITS_MCAN_RXESC_F1DS_20B: u32 = 0x00000030;
pub const REG_BITS_MCAN_RXESC_F1DS_24B: u32 = 0x00000040;
pub const REG_BITS_MCAN_RXESC_F1DS_32B: u32 = 0x00000050;
pub const REG_BITS_MCAN_RXESC_F1DS_48B: u32 = 0x00000060;
pub const REG_BITS_MCAN_RXESC_F1DS_64B: u32 = 0x00000070;
pub const REG_BITS_MCAN_RXESC_F0DS_8B: u32 = 0x00000000;
pub const REG_BITS_MCAN_RXESC_F0DS_12B: u32 = 0x00000001;
pub const REG_BITS_MCAN_RXESC_F0DS_16B: u32 = 0x00000002;
pub const REG_BITS_MCAN_RXESC_F0DS_20B: u32 = 0x00000003;
pub const REG_BITS_MCAN_RXESC_F0DS_24B: u32 = 0x00000004;
pub const REG_BITS_MCAN_RXESC_F0DS_32B: u32 = 0x00000005;
pub const REG_BITS_MCAN_RXESC_F0DS_48B: u32 = 0x00000006;
pub const REG_BITS_MCAN_RXESC_F0DS_64B: u32 = 0x00000007;
  
// TXBC
pub const REG_BITS_MCAN_TXBC_TFQM: u32 = 0x40000000;
  
// TXESC
pub const REG_BITS_MCAN_TXESC_TBDS_8: u32 = 0x00000000;
pub const REG_BITS_MCAN_TXESC_TBDS_12: u32 = 0x00000001;
pub const REG_BITS_MCAN_TXESC_TBDS_16: u32 = 0x00000002;
pub const REG_BITS_MCAN_TXESC_TBDS_20: u32 = 0x00000003;
pub const REG_BITS_MCAN_TXESC_TBDS_24: u32 = 0x00000004;
pub const REG_BITS_MCAN_TXESC_TBDS_32: u32 = 0x00000005;
pub const REG_BITS_MCAN_TXESC_TBDS_48: u32 = 0x00000006;
pub const REG_BITS_MCAN_TXESC_TBDS_64: u32 = 0x00000007;
  
// TSCC
pub const REG_BITS_MCAN_TSCC_PRESCALER_MASK: u32 = 0x000F0000;
pub const REG_BITS_MCAN_TSCC_COUNTER_ALWAYS_0: u32 = 0x00000000;
pub const REG_BITS_MCAN_TSCC_COUNTER_USE_TCP: u32 = 0x00000001;
pub const REG_BITS_MCAN_TSCC_COUNTER_EXTERNAL: u32 = 0x00000002;
  
// TXBAR
pub const REG_BITS_MCAN_TXBAR_AR31: u32 = 0x80000000;
pub const REG_BITS_MCAN_TXBAR_AR30: u32 = 0x40000000;
pub const REG_BITS_MCAN_TXBAR_AR29: u32 = 0x20000000;
pub const REG_BITS_MCAN_TXBAR_AR28: u32 = 0x10000000;
pub const REG_BITS_MCAN_TXBAR_AR27: u32 = 0x08000000;
pub const REG_BITS_MCAN_TXBAR_AR26: u32 = 0x04000000;
pub const REG_BITS_MCAN_TXBAR_AR25: u32 = 0x02000000;
pub const REG_BITS_MCAN_TXBAR_AR24: u32 = 0x01000000;
pub const REG_BITS_MCAN_TXBAR_AR23: u32 = 0x00800000;
pub const REG_BITS_MCAN_TXBAR_AR22: u32 = 0x00400000;
pub const REG_BITS_MCAN_TXBAR_AR21: u32 = 0x00200000;
pub const REG_BITS_MCAN_TXBAR_AR20: u32 = 0x00100000;
pub const REG_BITS_MCAN_TXBAR_AR19: u32 = 0x00080000;
pub const REG_BITS_MCAN_TXBAR_AR18: u32 = 0x00040000;
pub const REG_BITS_MCAN_TXBAR_AR17: u32 = 0x00020000;
pub const REG_BITS_MCAN_TXBAR_AR16: u32 = 0x00010000;
pub const REG_BITS_MCAN_TXBAR_AR15: u32 = 0x00008000;
pub const REG_BITS_MCAN_TXBAR_AR14: u32 = 0x00004000;
pub const REG_BITS_MCAN_TXBAR_AR13: u32 = 0x00002000;
pub const REG_BITS_MCAN_TXBAR_AR12: u32 = 0x00001000;
pub const REG_BITS_MCAN_TXBAR_AR11: u32 = 0x00000800;
pub const REG_BITS_MCAN_TXBAR_AR10: u32 = 0x00000400;
pub const REG_BITS_MCAN_TXBAR_AR9: u32 = 0x00000200;
pub const REG_BITS_MCAN_TXBAR_AR8: u32 = 0x00000100;
pub const REG_BITS_MCAN_TXBAR_AR7: u32 = 0x00000080;
pub const REG_BITS_MCAN_TXBAR_AR6: u32 = 0x00000040;
pub const REG_BITS_MCAN_TXBAR_AR5: u32 = 0x00000020;
pub const REG_BITS_MCAN_TXBAR_AR4: u32 = 0x00000010;
pub const REG_BITS_MCAN_TXBAR_AR3: u32 = 0x00000008;
pub const REG_BITS_MCAN_TXBAR_AR2: u32 = 0x00000004;
pub const REG_BITS_MCAN_TXBAR_AR1: u32 = 0x00000002;
pub const REG_BITS_MCAN_TXBAR_AR0: u32 = 0x00000001;
  
// TXBCR
pub const REG_BITS_MCAN_TXBCR_CR31: u32 = 0x80000000;
pub const REG_BITS_MCAN_TXBCR_CR30: u32 = 0x40000000;
pub const REG_BITS_MCAN_TXBCR_CR29: u32 = 0x20000000;
pub const REG_BITS_MCAN_TXBCR_CR28: u32 = 0x10000000;
pub const REG_BITS_MCAN_TXBCR_CR27: u32 = 0x08000000;
pub const REG_BITS_MCAN_TXBCR_CR26: u32 = 0x04000000;
pub const REG_BITS_MCAN_TXBCR_CR25: u32 = 0x02000000;
pub const REG_BITS_MCAN_TXBCR_CR24: u32 = 0x01000000;
pub const REG_BITS_MCAN_TXBCR_CR23: u32 = 0x00800000;
pub const REG_BITS_MCAN_TXBCR_CR22: u32 = 0x00400000;
pub const REG_BITS_MCAN_TXBCR_CR21: u32 = 0x00200000;
pub const REG_BITS_MCAN_TXBCR_CR20: u32 = 0x00100000;
pub const REG_BITS_MCAN_TXBCR_CR19: u32 = 0x00080000;
pub const REG_BITS_MCAN_TXBCR_CR18: u32 = 0x00040000;
pub const REG_BITS_MCAN_TXBCR_CR17: u32 = 0x00020000;
pub const REG_BITS_MCAN_TXBCR_CR16: u32 = 0x00010000;
pub const REG_BITS_MCAN_TXBCR_CR15: u32 = 0x00008000;
pub const REG_BITS_MCAN_TXBCR_CR14: u32 = 0x00004000;
pub const REG_BITS_MCAN_TXBCR_CR13: u32 = 0x00002000;
pub const REG_BITS_MCAN_TXBCR_CR12: u32 = 0x00001000;
pub const REG_BITS_MCAN_TXBCR_CR11: u32 = 0x00000800;
pub const REG_BITS_MCAN_TXBCR_CR10: u32 = 0x00000400;
pub const REG_BITS_MCAN_TXBCR_CR9: u32 = 0x00000200;
pub const REG_BITS_MCAN_TXBCR_CR8: u32 = 0x00000100;
pub const REG_BITS_MCAN_TXBCR_CR7: u32 = 0x00000080;
pub const REG_BITS_MCAN_TXBCR_CR6: u32 = 0x00000040;
pub const REG_BITS_MCAN_TXBCR_CR5: u32 = 0x00000020;
pub const REG_BITS_MCAN_TXBCR_CR4: u32 = 0x00000010;
pub const REG_BITS_MCAN_TXBCR_CR3: u32 = 0x00000008;
pub const REG_BITS_MCAN_TXBCR_CR2: u32 = 0x00000004;
pub const REG_BITS_MCAN_TXBCR_CR1: u32 = 0x00000002;
pub const REG_BITS_MCAN_TXBCR_CR0: u32 = 0x00000001;
  
// TXBTIE
pub const REG_BITS_MCAN_TXBTIE_TIE31: u32 = 0x80000000;
pub const REG_BITS_MCAN_TXBTIE_TIE30: u32 = 0x40000000;
pub const REG_BITS_MCAN_TXBTIE_TIE29: u32 = 0x20000000;
pub const REG_BITS_MCAN_TXBTIE_TIE28: u32 = 0x10000000;
pub const REG_BITS_MCAN_TXBTIE_TIE27: u32 = 0x08000000;
pub const REG_BITS_MCAN_TXBTIE_TIE26: u32 = 0x04000000;
pub const REG_BITS_MCAN_TXBTIE_TIE25: u32 = 0x02000000;
pub const REG_BITS_MCAN_TXBTIE_TIE24: u32 = 0x01000000;
pub const REG_BITS_MCAN_TXBTIE_TIE23: u32 = 0x00800000;
pub const REG_BITS_MCAN_TXBTIE_TIE22: u32 = 0x00400000;
pub const REG_BITS_MCAN_TXBTIE_TIE21: u32 = 0x00200000;
pub const REG_BITS_MCAN_TXBTIE_TIE20: u32 = 0x00100000;
pub const REG_BITS_MCAN_TXBTIE_TIE19: u32 = 0x00080000;
pub const REG_BITS_MCAN_TXBTIE_TIE18: u32 = 0x00040000;
pub const REG_BITS_MCAN_TXBTIE_TIE17: u32 = 0x00020000;
pub const REG_BITS_MCAN_TXBTIE_TIE16: u32 = 0x00010000;
pub const REG_BITS_MCAN_TXBTIE_TIE15: u32 = 0x00008000;
pub const REG_BITS_MCAN_TXBTIE_TIE14: u32 = 0x00004000;
pub const REG_BITS_MCAN_TXBTIE_TIE13: u32 = 0x00002000;
pub const REG_BITS_MCAN_TXBTIE_TIE12: u32 = 0x00001000;
pub const REG_BITS_MCAN_TXBTIE_TIE11: u32 = 0x00000800;
pub const REG_BITS_MCAN_TXBTIE_TIE10: u32 = 0x00000400;
pub const REG_BITS_MCAN_TXBTIE_TIE9: u32 = 0x00000200;
pub const REG_BITS_MCAN_TXBTIE_TIE8: u32 = 0x00000100;
pub const REG_BITS_MCAN_TXBTIE_TIE7: u32 = 0x00000080;
pub const REG_BITS_MCAN_TXBTIE_TIE6: u32 = 0x00000040;
pub const REG_BITS_MCAN_TXBTIE_TIE5: u32 = 0x00000020;
pub const REG_BITS_MCAN_TXBTIE_TIE4: u32 = 0x00000010;
pub const REG_BITS_MCAN_TXBTIE_TIE3: u32 = 0x00000008;
pub const REG_BITS_MCAN_TXBTIE_TIE2: u32 = 0x00000004;
pub const REG_BITS_MCAN_TXBTIE_TIE1: u32 = 0x00000002;
pub const REG_BITS_MCAN_TXBTIE_TIE0: u32 = 0x00000001;
  
// TXBCIE
pub const REG_BITS_MCAN_TXBCIE_CFIE31: u32 = 0x80000000;
pub const REG_BITS_MCAN_TXBCIE_CFIE30: u32 = 0x40000000;
pub const REG_BITS_MCAN_TXBCIE_CFIE29: u32 = 0x20000000;
pub const REG_BITS_MCAN_TXBCIE_CFIE28: u32 = 0x10000000;
pub const REG_BITS_MCAN_TXBCIE_CFIE27: u32 = 0x08000000;
pub const REG_BITS_MCAN_TXBCIE_CFIE26: u32 = 0x04000000;
pub const REG_BITS_MCAN_TXBCIE_CFIE25: u32 = 0x02000000;
pub const REG_BITS_MCAN_TXBCIE_CFIE24: u32 = 0x01000000;
pub const REG_BITS_MCAN_TXBCIE_CFIE23: u32 = 0x00800000;
pub const REG_BITS_MCAN_TXBCIE_CFIE22: u32 = 0x00400000;
pub const REG_BITS_MCAN_TXBCIE_CFIE21: u32 = 0x00200000;
pub const REG_BITS_MCAN_TXBCIE_CFIE20: u32 = 0x00100000;
pub const REG_BITS_MCAN_TXBCIE_CFIE19: u32 = 0x00080000;
pub const REG_BITS_MCAN_TXBCIE_CFIE18: u32 = 0x00040000;
pub const REG_BITS_MCAN_TXBCIE_CFIE17: u32 = 0x00020000;
pub const REG_BITS_MCAN_TXBCIE_CFIE16: u32 = 0x00010000;
pub const REG_BITS_MCAN_TXBCIE_CFIE15: u32 = 0x00008000;
pub const REG_BITS_MCAN_TXBCIE_CFIE14: u32 = 0x00004000;
pub const REG_BITS_MCAN_TXBCIE_CFIE13: u32 = 0x00002000;
pub const REG_BITS_MCAN_TXBCIE_CFIE12: u32 = 0x00001000;
pub const REG_BITS_MCAN_TXBCIE_CFIE11: u32 = 0x00000800;
pub const REG_BITS_MCAN_TXBCIE_CFIE10: u32 = 0x00000400;
pub const REG_BITS_MCAN_TXBCIE_CFIE9: u32 = 0x00000200;
pub const REG_BITS_MCAN_TXBCIE_CFIE8: u32 = 0x00000100;
pub const REG_BITS_MCAN_TXBCIE_CFIE7: u32 = 0x00000080;
pub const REG_BITS_MCAN_TXBCIE_CFIE6: u32 = 0x00000040;
pub const REG_BITS_MCAN_TXBCIE_CFIE5: u32 = 0x00000020;
pub const REG_BITS_MCAN_TXBCIE_CFIE4: u32 = 0x00000010;
pub const REG_BITS_MCAN_TXBCIE_CFIE3: u32 = 0x00000008;
pub const REG_BITS_MCAN_TXBCIE_CFIE2: u32 = 0x00000004;
pub const REG_BITS_MCAN_TXBCIE_CFIE1: u32 = 0x00000002;
pub const REG_BITS_MCAN_TXBCIE_CFIE0: u32 = 0x00000001;
  
// Device Register Bit Field Defines
  
// Modes of Operation and Pin Configuration Registers (0x0800)
// Generic masks
pub const REG_BITS_DEVICE_MODE_FORCED_SET_BITS: u32 = 0x00000020;
  
// Wake pin
pub const REG_BITS_DEVICE_MODE_WAKE_PIN_MASK: u32 = 0xC0000000;
pub const REG_BITS_DEVICE_MODE_WAKE_PIN_DIS: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_WAKE_PIN_RISING: u32 = 0x40000000;
pub const REG_BITS_DEVICE_MODE_WAKE_PIN_FALLING: u32 = 0x80000000;
pub const REG_BITS_DEVICE_MODE_WAKE_PIN_BOTHEDGES: u32 = 0xC0000000;
  
// WD_Timer (If applicable)
pub const REG_BITS_DEVICE_MODE_WD_TIMER_MASK: u32 = 0x30000000;
pub const REG_BITS_DEVICE_MODE_WD_TIMER_60MS: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_WD_TIMER_600MS: u32 = 0x10000000;
pub const REG_BITS_DEVICE_MODE_WD_TIMER_3S: u32 = 0x20000000;
pub const REG_BITS_DEVICE_MODE_WD_TIMER_6S: u32 = 0x30000000;
  
// WD_TIMER_CLK_REF
pub const REG_BITS_DEVICE_MODE_WD_CLK_MASK: u32 = 0x08000000;
pub const REG_BITS_DEVICE_MODE_WD_CLK_20MHZ: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_WD_CLK_40MHZ: u32 = 0x08000000;
  
// GPO2 Pin Configuration
pub const REG_BITS_DEVICE_MODE_GPO2_MASK: u32 = 0x00C00000;
pub const REG_BITS_DEVICE_MODE_GPO2_CAN_FAULT: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_GPO2_MCAN_INT0: u32 = 0x00400000;
pub const REG_BITS_DEVICE_MODE_GPO2_WDT: u32 = 0x00800000;
pub const REG_BITS_DEVICE_MODE_GPO2_NINT: u32 = 0x00C00000;
  
// Test Mode Enable Bit
pub const REG_BITS_DEVICE_MODE_TESTMODE_ENMASK: u32 = 0x00200000;
pub const REG_BITS_DEVICE_MODE_TESTMODE_EN: u32 = 0x00200000;
pub const REG_BITS_DEVICE_MODE_TESTMODE_DIS: u32 = 0x00000000;
  
// nWKRQ Pin GPO Voltage Rail COnfiguration
pub const REG_BITS_DEVICE_MODE_NWKRQ_VOLT_MASK: u32 = 0x00080000;
pub const REG_BITS_DEVICE_MODE_NWKRQ_VOLT_INTERNAL: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_NWKRQ_VOLT_VIO: u32 = 0x00080000;
  
// WD_BIT
pub const REG_BITS_DEVICE_MODE_WDT_RESET_BIT: u32 = 0x00040000;
  
// WD_ACTION
pub const REG_BITS_DEVICE_MODE_WDT_ACTION_MASK: u32 = 0x00020000;
pub const REG_BITS_DEVICE_MODE_WDT_ACTION_INT: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_WDT_ACTION_INH_PULSE: u32 = 0x00010000;
pub const REG_BITS_DEVICE_MODE_WDT_ACTION_WDT_PULSE: u32 = 0x00020000;
  
// CLKOUT/GPO1 Pin Mode Select
pub const REG_BITS_DEVICE_MODE_GPO1_MODE_MASK: u32 = 0x0000C000;
pub const REG_BITS_DEVICE_MODE_GPO1_MODE_GPO: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_GPO1_MODE_CLKOUT: u32 = 0x00004000;
pub const REG_BITS_DEVICE_MODE_GPO1_MODE_GPI: u32 = 0x00008000;
  
// Fail Safe Enable
pub const REG_BITS_DEVICE_MODE_FAIL_SAFE_MASK: u32 = 0x00002000 ;
pub const REG_BITS_DEVICE_MODE_FAIL_SAFE_EN: u32 = 0x00002000;
pub const REG_BITS_DEVICE_MODE_FAIL_SAFE_DIS: u32 = 0x00000000;
  
// CLKOUT Prescaler
pub const REG_BITS_DEVICE_MODE_CLKOUT_MASK: u32 = 0x00001000;
pub const REG_BITS_DEVICE_MODE_CLKOUT_DIV1: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_CLKOUT_DIV2: u32 = 0x00001000;
  
// GPO1 Function Select
pub const REG_BITS_DEVICE_MODE_GPO1_FUNC_MASK: u32 = 0x00000C00;
pub const REG_BITS_DEVICE_MODE_GPO1_FUNC_SPI_INT: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_GPO1_FUNC_MCAN_INT1: u32 = 0x00000400;
pub const REG_BITS_DEVICE_MODE_GPO1_FUNC_UVLO_THERM: u32 = 0x00000800;
  
// INH Pin Disable
pub const REG_BITS_DEVICE_MODE_INH_MASK: u32 = 0x00000200;
pub const REG_BITS_DEVICE_MODE_INH_DIS: u32 = 0x00000200;
pub const REG_BITS_DEVICE_MODE_INH_EN: u32 = 0x00000000;
  
// nWKRQ Pin Configuration
pub const REG_BITS_DEVICE_MODE_NWKRQ_CONFIG_MASK: u32 = 0x00000100;
pub const REG_BITS_DEVICE_MODE_NWKRQ_CONFIG_INH: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_NWKRQ_CONFIG_WKRQ: u32 = 0x00000100;
  
// Mode of Operation
pub const REG_BITS_DEVICE_MODE_DEVICEMODE_MASK: u32 = 0x000000C0;
pub const REG_BITS_DEVICE_MODE_DEVICEMODE_SLEEP: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_DEVICEMODE_STANDBY: u32 = 0x00000040;
pub const REG_BITS_DEVICE_MODE_DEVICEMODE_NORMAL: u32 = 0x00000080;
  
// WDT_EN
pub const REG_BITS_DEVICE_MODE_WDT_MASK: u32 = 0x00000008 ;
pub const REG_BITS_DEVICE_MODE_WDT_EN: u32 = 0x00000008;
pub const REG_BITS_DEVICE_MODE_WDT_DIS: u32 = 0x00000000;
  
// Dev Reset
pub const REG_BITS_DEVICE_MODE_DEVICE_RESET: u32 = 0x00000004;
  
// SWE_DIS: u32 = Sleep Wake Error Disable
pub const REG_BITS_DEVICE_MODE_SWE_MASK: u32 = 0x00000002;
pub const REG_BITS_DEVICE_MODE_SWE_DIS: u32 = 0x00000002;
pub const REG_BITS_DEVICE_MODE_SWE_EN: u32 = 0x00000000;
  
// Test Mode Configuration
pub const REG_BITS_DEVICE_MODE_TESTMODE_MASK: u32 = 0x00000001;
pub const REG_BITS_DEVICE_MODE_TESTMODE_PHY: u32 = 0x00000000;
pub const REG_BITS_DEVICE_MODE_TESTMODE_CONTROLLER: u32 = 0x00000001;
  
// Device Interrupt Register values (0x0820)
pub const REG_BITS_DEVICE_IR_CANLGND: u32 = 0x08000000;
pub const REG_BITS_DEVICE_IR_CANBUSOPEN: u32 = 0x04000000;
pub const REG_BITS_DEVICE_IR_CANBUSGND: u32 = 0x02000000;
pub const REG_BITS_DEVICE_IR_CANBUSBAT: u32 = 0x01000000;
  
//Reserved: u32 = 0x00800000
pub const REG_BITS_DEVICE_IR_UVSUP: u32 = 0x00400000;
pub const REG_BITS_DEVICE_IR_UVIO: u32 = 0x00200000;
pub const REG_BITS_DEVICE_IR_PWRON: u32 = 0x00100000;
pub const REG_BITS_DEVICE_IR_TSD: u32 = 0x00080000;
pub const REG_BITS_DEVICE_IR_WDTO: u32 = 0x00040000;
  
//Reserved: u32 = 0x00020000
pub const REG_BITS_DEVICE_IR_ECCERR: u32 = 0x00010000;
pub const REG_BITS_DEVICE_IR_CANINT: u32 = 0x00008000;
pub const REG_BITS_DEVICE_IR_LWU: u32 = 0x00004000;
pub const REG_BITS_DEVICE_IR_WKERR: u32 = 0x00002000;
pub const REG_BITS_DEVICE_IR_FRAME_OVF: u32 = 0x00001000;
  
//Reserved: u32 = 0x00000800
pub const REG_BITS_DEVICE_IR_CANSLNT: u32 = 0x00000400;
  
//Reserved: u32 = 0x00000200
pub const REG_BITS_DEVICE_IR_CANDOM: u32 = 0x00000100;
pub const REG_BITS_DEVICE_IR_GLOBALERR: u32 = 0x00000080;
pub const REG_BITS_DEVICE_IR_NWKRQ: u32 = 0x00000040;
pub const REG_BITS_DEVICE_IR_CANERR: u32 = 0x00000020;
pub const REG_BITS_DEVICE_IR_CANBUSFAULT: u32 = 0x00000010;
pub const REG_BITS_DEVICE_IR_SPIERR: u32 = 0x00000008;
pub const REG_BITS_DEVICE_IR_SWERR: u32 = 0x00000004;
pub const REG_BITS_DEVICE_IR_M_CAN_INT: u32 = 0x00000002;
pub const REG_BITS_DEVICE_IR_VTWD: u32 = 0x00000001;
  
// Device Interrupt Enable Values (0x0830)
pub const REG_BITS_DEVICE_IE_UVCCOUT: u32 = 0x00800000;
pub const REG_BITS_DEVICE_IE_UVSUP: u32 = 0x00400000;
pub const REG_BITS_DEVICE_IE_UVIO: u32 = 0x00200000;
pub const REG_BITS_DEVICE_IE_PWRON: u32 = 0x00100000;
pub const REG_BITS_DEVICE_IE_TSD: u32 = 0x00080000;
pub const REG_BITS_DEVICE_IE_WDTO: u32 = 0x00040000;
  
// Reserved
pub const REG_BITS_DEVICE_IE_ECCERR: u32 = 0x00010000;
pub const REG_BITS_DEVICE_IE_CANINT: u32 = 0x00008000;
pub const REG_BITS_DEVICE_IE_LWU: u32 = 0x00004000;
pub const REG_BITS_DEVICE_IE_WKERR: u32 = 0x00002000;
pub const REG_BITS_DEVICE_IE_FRAME_OVF: u32 = 0x00001000;
  
//Reserved: u32 = 0x00000800
pub const REG_BITS_DEVICE_IE_CANSLNT: u32 = 0x00000400;
  
//Reserved: u32 = 0x00000200
pub const REG_BITS_DEVICE_IE_CANDOM: u32 = 0x00000100;
  
// Reserved: u32 = 0x80-00
// This mask is the bitwise-inverse of the 0x0830 IE register's reserved bits. A reserved bit is read as high always. This masks the reserved bits out.
pub const REG_BITS_DEVICE_IE_MASK: u32 = 0x7F69D700;