calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
; BTOR description generated by Yosys 0.33+65 (git sha1 90124dce5, clang 15.0.0 -fPIC -Os) for module std_sync_reg.
1 sort bitvec 1
2 input 1 clk ; sync.sv:22.31-22.34
3 sort bitvec 32
4 input 3 in_0 ; sync.sv:16.31-16.35
5 input 3 in_1 ; sync.sv:17.31-17.35
6 input 1 read_en_0 ; sync.sv:18.31-18.40
7 input 1 read_en_1 ; sync.sv:19.31-19.40
8 input 1 reset ; sync.sv:23.31-23.36
9 input 1 write_en_0 ; sync.sv:20.31-20.41
10 input 1 write_en_1 ; sync.sv:21.31-21.41
11 state 3
12 output 11 out_0 ; sync.sv:25.31-25.36
13 state 3
14 output 13 out_1 ; sync.sv:26.31-26.36
15 state 3
16 output 15 peek ; sync.sv:31.31-31.35
17 state 1
18 output 17 read_done_0 ; sync.sv:29.31-29.42
19 state 1
20 output 19 read_done_1 ; sync.sv:30.31-30.42
21 state 1
22 output 21 write_done_0 ; sync.sv:27.31-27.43
23 state 1
24 output 23 write_done_1 ; sync.sv:28.31-28.43
25 state 1 is_full
26 xor 1 6 7
27 and 1 25 26
28 and 1 27 6
29 and 1 6 7
30 and 1 25 29
31 state 1 arbiter_r
32 not 1 31
33 and 1 30 32
34 or 1 28 33
35 uext 1 34 0 READ_0 ; sync.sv:40.79-40.85
36 and 1 27 7
37 and 1 30 31
38 or 1 36 37
39 uext 1 38 0 READ_1 ; sync.sv:40.87-40.93
40 uext 1 30 0 READ_MULT ; sync.sv:40.23-40.32
41 uext 1 27 0 READ_ONE_HOT ; sync.sv:40.9-40.21
42 not 1 25
43 xor 1 9 10
44 and 1 42 43
45 and 1 44 9
46 and 1 9 10
47 and 1 42 46
48 state 1 arbiter_w
49 not 1 48
50 and 1 47 49
51 or 1 45 50
52 uext 1 51 0 WRITE_0 ; sync.sv:40.61-40.68
53 and 1 44 10
54 and 1 47 48
55 or 1 53 54
56 uext 1 55 0 WRITE_1 ; sync.sv:40.70-40.77
57 uext 1 47 0 WRITE_MULT ; sync.sv:40.49-40.59
58 uext 1 44 0 WRITE_ONE_HOT ; sync.sv:40.34-40.47
59 state 3 state
60 input 3
61 ite 3 34 59 60
62 const 3 00000000000000000000000000000000
63 ite 3 8 62 61
64 next 3 11 63
65 input 3
66 ite 3 38 59 65
67 ite 3 8 62 66
68 next 3 13 67
69 ite 3 55 5 15
70 ite 3 51 4 69
71 ite 3 8 62 70
72 next 3 15 71
73 const 1 0
74 const 1 1
75 ite 1 34 74 73
76 ite 1 8 73 75
77 next 1 17 76
78 ite 1 38 74 73
79 ite 1 8 73 78
80 next 1 19 79
81 ite 1 51 74 73
82 ite 1 8 73 81
83 next 1 21 82
84 ite 1 55 74 73
85 ite 1 8 73 84
86 next 1 23 85
87 or 1 27 30
88 ite 1 87 73 25
89 or 1 44 47
90 ite 1 89 74 88
91 ite 1 8 73 90
92 next 1 25 91
93 ite 1 37 73 31
94 ite 1 33 74 93
95 ite 1 8 73 94
96 next 1 31 95
97 ite 1 54 73 48
98 ite 1 50 74 97
99 ite 1 8 73 98
100 next 1 48 99
101 input 3
102 ite 3 87 101 59
103 ite 3 55 5 102
104 ite 3 51 4 103
105 ite 3 8 62 104
106 next 3 59 105
; end of yosys output