calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
import "primitives/binary_operators.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    a = std_reg(32);
    b = std_reg(32);
    c = std_reg(32);
    d = std_reg(32);
    e = std_reg(32);
    lt = std_lt(32);
    gt = std_lt(32);
  }
  wires {
    static<10> group my_group {
      a.write_en = (%2 | lt.out) & %[1:5] ? 1'd1;
      b.write_en = (lt.out | gt.out) & %2 ? 1'd1;
      c.write_en = (%[5:7] | lt.out) & %4 ? 1'd1;
      d.write_en = !1'b1 ? 1'd1;
      e.write_en = lt.out ? 1'd1;
      a.in = 32'd1;
      b.in = 32'd2;
      c.in = 32'd3;
      d.in = 32'd4;
    }
  }
  control {
    my_group;
  }
}