calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121

import "primitives/core.futil";
import "primitives/memories/comb.futil";
import "primitives/sync.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    out = comb_mem_d1(32, 1, 3);
    val = std_reg(32);
    add_0 = std_add(32);
    no_use = std_reg(32);
    @generated barrier = std_sync_reg(32);
    @generated eq = std_eq(32);
    @generated wait_restore_reg = std_reg(1);
    @generated save = std_reg(32);
    @generated incr = std_add(32);
    @generated wait_reg = std_reg(1);
    @generated save0 = std_reg(32);
    @generated incr0 = std_add(32);
    @generated wait_reg0 = std_reg(1);
  }
  wires {
    group no_op {
      no_use.write_en = 1'd1;
      no_use.in = 32'd0;
      no_op[done] = no_use.done;
    }
    group calc_val {
      val.write_en = 1'd1;
      add_0.right = 32'd1;
      add_0.left = 32'd2;
      val.in = add_0.out;
      calc_val[done] = val.done;
    }
    group reg_to_mem {
      out.addr0 = 3'd0;
      out.write_data = val.out;
      out.write_en = 1'd1;
      reg_to_mem[done] = out.done;
    }
    group restore {
      barrier.write_en_0 = 1'd1;
      barrier.in_0 = 32'd0;
      restore[done] = barrier.write_done_0;
    }
    group wait_restore {
      wait_restore_reg.in = !eq.out ? 1'd1;
      wait_restore_reg.write_en = !eq.out ? 1'd1;
      wait_restore[done] = wait_restore_reg.done;
    }
    group clear_barrier {
      barrier.read_en_0 = 1'd1;
      clear_barrier[done] = barrier.read_done_0;
    }
    group incr_barrier {
      barrier.read_en_0 = 1'd1;
      incr.left = barrier.out_0;
      incr.right = 32'd1;
      save.in = barrier.read_done_0 ? incr.out;
      save.write_en = barrier.read_done_0;
      incr_barrier[done] = save.done;
    }
    group write_barrier {
      barrier.write_en_0 = 1'd1;
      barrier.in_0 = save.out;
      write_barrier[done] = barrier.write_done_0;
    }
    group wt {
      wait_reg.in = eq.out;
      wait_reg.write_en = eq.out ? 1'd1;
      wt[done] = wait_reg.done;
    }
    group incr_barrier0 {
      barrier.read_en_1 = 1'd1;
      incr0.left = barrier.out_1;
      incr0.right = 32'd1;
      save0.in = barrier.read_done_1 ? incr0.out;
      save0.write_en = barrier.read_done_1;
      incr_barrier0[done] = save0.done;
    }
    group write_barrier0 {
      barrier.write_en_1 = 1'd1;
      barrier.in_1 = save0.out;
      write_barrier0[done] = barrier.write_done_1;
    }
    group wt0 {
      wait_reg0.in = eq.out;
      wait_reg0.write_en = eq.out ? 1'd1;
      wt0[done] = wait_reg0.done;
    }
    eq.left = barrier.peek;
    eq.right = 32'd2;
  }
  control {
    seq {
      par {
        restore;
      }
      par {
        seq {
          no_op;
          seq {
            incr_barrier;
            write_barrier;
            wt;
            clear_barrier;
            restore;
          }
          reg_to_mem;
        }
        seq {
          calc_val;
          seq {
            incr_barrier0;
            write_barrier0;
            wt0;
            wait_restore;
          }
        }
      }
    }
  }
}