calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
import "primitives/pipelined.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    @external p = comb_mem_d1(3, 1, 1);
    incr = std_add(3);
    l = std_lt(3);
    r = std_reg(3);
    l2 = std_lt(3);
    r_cond = std_reg(1);
    @generated fsm = std_reg(2);
    @generated ud = undef(1);
    @generated adder = std_add(2);
    @generated ud0 = undef(1);
    @generated adder0 = std_add(2);
    @generated ud1 = undef(1);
    @generated adder1 = std_add(2);
    @generated signal_reg = std_reg(1);
  }
  wires {
    group B {
      p.write_data = 3'd0;
      p.write_en = 1'd1;
      p.addr0 = 1'd0;
      B[done] = p.done;
    }
    group C {
      r.in = incr.out;
      incr.left = r.out;
      incr.right = 3'd1;
      r.write_en = 1'd1;
      C[done] = r.done;
    }
    group early_reset_A2 {
      l.left = p.read_data;
      l.right = 3'd6;
      r_cond.in = l.out;
      r_cond.write_en = 1'd1;
      p.addr0 = 1'd0;
      adder0.left = fsm.out;
      adder0.right = 2'd1;
      fsm.write_en = 1'd1;
      fsm.in = fsm.out != 2'd0 ? adder0.out;
      fsm.in = fsm.out == 2'd0 ? 2'd0;
      early_reset_A2[done] = ud0.out;
    }
    group early_reset_static_seq {
      incr.left = fsm.out == 2'd0 ? p.read_data;
      incr.right = fsm.out == 2'd0 ? 3'd1;
      p.write_data = fsm.out == 2'd0 ? incr.out;
      p.write_en = fsm.out == 2'd0 ? 1'd1;
      p.addr0 = fsm.out == 2'd0 ? 1'd0;
      l.left = fsm.out == 2'd1 ? p.read_data;
      l.right = fsm.out == 2'd1 ? 3'd6;
      r_cond.in = fsm.out == 2'd1 ? l.out;
      r_cond.write_en = fsm.out == 2'd1 ? 1'd1;
      p.addr0 = fsm.out == 2'd1 ? 1'd0;
      adder1.left = fsm.out;
      adder1.right = 2'd1;
      fsm.write_en = 1'd1;
      fsm.in = fsm.out != 2'd1 ? adder1.out;
      fsm.in = fsm.out == 2'd1 ? 2'd0;
      early_reset_static_seq[done] = ud1.out;
    }
    group wrapper_early_reset_A2 {
      early_reset_A2[go] = 1'd1;
      signal_reg.write_en = fsm.out == 2'd0 & !signal_reg.out ? 1'd1;
      signal_reg.in = fsm.out == 2'd0 & !signal_reg.out ? 1'd1;
      wrapper_early_reset_A2[done] = fsm.out == 2'd0 & signal_reg.out ? 1'd1;
    }
    group while_wrapper_early_reset_static_seq {
      early_reset_static_seq[go] = 1'd1;
      while_wrapper_early_reset_static_seq[done] = !r_cond.out & fsm.out == 2'd0 ? 1'd1;
    }
    comb group comp {
      l2.left = r.out;
      l2.right = 3'd3;
    }
    signal_reg.write_en = fsm.out == 2'd0 & signal_reg.out ? 1'd1;
    signal_reg.in = fsm.out == 2'd0 & signal_reg.out ? 1'd0;
  }
  control {
    while l2.out with comp {
      seq {
        B;
        wrapper_early_reset_A2;
        while_wrapper_early_reset_static_seq;
        C;
      }
    }
  }
}