calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

import "primitives/core.futil";
import "primitives/memories/comb.futil";

component main() -> () {
  cells {
    mem = comb_mem_d1(32, 1, 1);
    eq = std_add(32);
    r = std_reg(1);
  }
  wires {
    comb group check {
      eq.left = mem.read_data;
      eq.right = 32'd1;
    }
    group incr {
      r.in = 1'd1;
      r.write_en = 1'd1;
      incr[done] = r.done;
    }
  }
  control {
    if eq.out with check {
      incr;
    }
  }
}