calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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// -p well-formed -b mlir
import "primitives/core.futil";
import "primitives/memories/comb.futil";
import "primitives/binary_operators.futil";
component main<"state_share"=1>(@foo(32) in: 32, @promotable(10) @go go: 1, @clk clk: 1, @reset reset: 1) -> (@promotable(0) out: 32, @done done: 1) {
  cells {
    @precious r = std_reg(32);
    @bar(32) le = std_le(32);
  }
  wires {
    group upd<"stable"=1> {
      upd[done] = r.done;
    }
    comb group cond<"promotable"=0> {
    }
  }
  control {
    @bound(32) while le.out with cond {
      @promotable(2) upd;
    }
  }
}