calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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[profile]
data=all:all:all

[Debug]
profile=true
timeline_trace=true
data_transfer_trace=fine

[Emulation]
debug_mode=batch
xtlm_aximm_log=true
xtlm_axis_log=true
user_pre_sim_script=../../../../../../../sim_script.tcl