calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

import "primitives/core.futil";
import "primitives/memories/comb.futil";
import "primitives/sync.futil";

// Move data from one array to another with the index as a synchronized
// register.
component main() -> () {
  cells {
    @external in = comb_mem_d1(32, 5, 3);
    @external out = comb_mem_d1(32, 5, 3);
    lt = std_lt(3);
    add = std_add(3);

    // Sync register used to communicate between threads
    imm = std_sync_reg(32);
    // Index of the input and output memory
    idx = std_reg(3);
  }
  wires {

    //// ANCHOR: write
    // Write value from `in[idx]` to sync intermediate.
    group write_imm {
      imm.write_en_0 = 1'd1;
      imm.in_0 = in.read_data;
      in.addr0 = idx.out;
      write_imm[done] = imm.write_done_0;
    }
    //// ANCHOR_END: write

    //// ANCHOR: read
    // Read value from sync intermediate and write to temp.
    group read_imm {
      imm.read_en_0 = 1'd1;
      out.write_en = imm.read_done_0;
      out.addr0 = idx.out;
      out.write_data = imm.out_0;
      read_imm[done] = out.done;
    }
    //// ANCHOR_END: read

    group incr_idx {
      add.left = 3'd1;
      add.right = idx.out;
      idx.in = add.out;
      idx.write_en = 1'd1;
      incr_idx[done] = idx.done;
    }

    comb group cmp {
      lt.left = idx.out;
      lt.right = 3'd5;
    }
  }
  control {
    //// ANCHOR: control
    while lt.out with cmp {
      seq {
        par {
          read_imm;
          write_imm;
        }
        incr_idx;
      }
    }
    //// ANCHOR_END: control
  }
}