1#![doc = "Peripheral access API for BS2X microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
2#![allow(non_camel_case_types)]
3#![allow(non_snake_case)]
4#![no_std]
5#![cfg_attr(docsrs, feature(doc_cfg))]
6#[doc = r"Number available in the NVIC for configuring priority"]
7pub const NVIC_PRIO_BITS: u8 = 3;
8#[allow(unused_imports)]
9use generic::*;
10#[doc = r"Common register and bit access and modify traits"]
11pub mod generic {
12 use core::marker;
13 #[doc = " Generic peripheral accessor"]
14 pub struct Periph<RB, const A: usize> {
15 _marker: marker::PhantomData<RB>,
16 }
17 unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
18 impl<RB, const A: usize> Periph<RB, A> {
19 #[doc = "Pointer to the register block"]
20 pub const PTR: *const RB = A as *const _;
21 #[doc = "Return the pointer to the register block"]
22 #[inline(always)]
23 pub const fn ptr() -> *const RB {
24 Self::PTR
25 }
26 #[doc = " Steal an instance of this peripheral"]
27 #[doc = ""]
28 #[doc = " # Safety"]
29 #[doc = ""]
30 #[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
31 #[doc = " that may race with any existing instances, for example by only"]
32 #[doc = " accessing read-only or write-only registers, or by consuming the"]
33 #[doc = " original peripheral and using critical sections to coordinate"]
34 #[doc = " access between multiple new instances."]
35 #[doc = ""]
36 #[doc = " Additionally, other software such as HALs may rely on only one"]
37 #[doc = " peripheral instance existing to ensure memory safety; ensure"]
38 #[doc = " no stolen instances are passed to such software."]
39 pub unsafe fn steal() -> Self {
40 Self {
41 _marker: marker::PhantomData,
42 }
43 }
44 }
45 impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
46 type Target = RB;
47 #[inline(always)]
48 fn deref(&self) -> &Self::Target {
49 unsafe { &*Self::PTR }
50 }
51 }
52 #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
53 pub trait RawReg:
54 Copy
55 + From<bool>
56 + core::ops::BitOr<Output = Self>
57 + core::ops::BitAnd<Output = Self>
58 + core::ops::BitOrAssign
59 + core::ops::BitAndAssign
60 + core::ops::Not<Output = Self>
61 + core::ops::Shl<u8, Output = Self>
62 {
63 #[doc = " Mask for bits of width `WI`"]
64 fn mask<const WI: u8>() -> Self;
65 #[doc = " `0`"]
66 const ZERO: Self;
67 #[doc = " `1`"]
68 const ONE: Self;
69 }
70 macro_rules! raw_reg {
71 ($ U : ty , $ size : literal , $ mask : ident) => {
72 impl RawReg for $U {
73 #[inline(always)]
74 fn mask<const WI: u8>() -> Self {
75 $mask::<WI>()
76 }
77 const ZERO: Self = 0;
78 const ONE: Self = 1;
79 }
80 const fn $mask<const WI: u8>() -> $U {
81 <$U>::MAX >> ($size - WI)
82 }
83 impl FieldSpec for $U {
84 type Ux = $U;
85 }
86 };
87 }
88 raw_reg!(u8, 8, mask_u8);
89 raw_reg!(u16, 16, mask_u16);
90 raw_reg!(u32, 32, mask_u32);
91 raw_reg!(u64, 64, mask_u64);
92 #[doc = " Raw register type"]
93 pub trait RegisterSpec {
94 #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
95 type Ux: RawReg;
96 }
97 #[doc = " Raw field type"]
98 pub trait FieldSpec: Sized {
99 #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
100 type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
101 }
102 #[doc = " Marker for fields with fixed values"]
103 pub trait IsEnum: FieldSpec {}
104 #[doc = " Trait implemented by readable registers to enable the `read` method."]
105 #[doc = ""]
106 #[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
107 pub trait Readable: RegisterSpec {}
108 #[doc = " Trait implemented by writeable registers."]
109 #[doc = ""]
110 #[doc = " This enables the `write`, `write_with_zero` and `reset` methods."]
111 #[doc = ""]
112 #[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
113 pub trait Writable: RegisterSpec {
114 #[doc = " Is it safe to write any bits to register"]
115 type Safety;
116 #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
117 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
118 #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
119 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
120 }
121 #[doc = " Reset value of the register."]
122 #[doc = ""]
123 #[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
124 #[doc = " register by using the `reset` method."]
125 pub trait Resettable: RegisterSpec {
126 #[doc = " Reset value of the register."]
127 const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
128 #[doc = " Reset value of the register."]
129 #[inline(always)]
130 fn reset_value() -> Self::Ux {
131 Self::RESET_VALUE
132 }
133 }
134 #[doc(hidden)]
135 pub mod raw {
136 use super::{BitM, FieldSpec, RegisterSpec, Unsafe, Writable, marker};
137 pub struct R<REG: RegisterSpec> {
138 pub(crate) bits: REG::Ux,
139 pub(super) _reg: marker::PhantomData<REG>,
140 }
141 pub struct W<REG: RegisterSpec> {
142 #[doc = "Writable bits"]
143 pub(crate) bits: REG::Ux,
144 pub(super) _reg: marker::PhantomData<REG>,
145 }
146 pub struct FieldReader<FI = u8>
147 where
148 FI: FieldSpec,
149 {
150 pub(crate) bits: FI::Ux,
151 _reg: marker::PhantomData<FI>,
152 }
153 impl<FI: FieldSpec> FieldReader<FI> {
154 #[doc = " Creates a new instance of the reader."]
155 #[allow(unused)]
156 #[inline(always)]
157 pub(crate) const fn new(bits: FI::Ux) -> Self {
158 Self {
159 bits,
160 _reg: marker::PhantomData,
161 }
162 }
163 }
164 pub struct BitReader<FI = bool> {
165 pub(crate) bits: bool,
166 _reg: marker::PhantomData<FI>,
167 }
168 impl<FI> BitReader<FI> {
169 #[doc = " Creates a new instance of the reader."]
170 #[allow(unused)]
171 #[inline(always)]
172 pub(crate) const fn new(bits: bool) -> Self {
173 Self {
174 bits,
175 _reg: marker::PhantomData,
176 }
177 }
178 }
179 #[must_use = "after creating `FieldWriter` you need to call field value setting method"]
180 pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
181 where
182 REG: Writable + RegisterSpec,
183 FI: FieldSpec,
184 {
185 pub(crate) w: &'a mut W<REG>,
186 pub(crate) o: u8,
187 _field: marker::PhantomData<(FI, Safety)>,
188 }
189 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
190 where
191 REG: Writable + RegisterSpec,
192 FI: FieldSpec,
193 {
194 #[doc = " Creates a new instance of the writer"]
195 #[allow(unused)]
196 #[inline(always)]
197 pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
198 Self {
199 w,
200 o,
201 _field: marker::PhantomData,
202 }
203 }
204 }
205 #[must_use = "after creating `BitWriter` you need to call bit setting method"]
206 pub struct BitWriter<'a, REG, FI = bool, M = BitM>
207 where
208 REG: Writable + RegisterSpec,
209 bool: From<FI>,
210 {
211 pub(crate) w: &'a mut W<REG>,
212 pub(crate) o: u8,
213 _field: marker::PhantomData<(FI, M)>,
214 }
215 impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
216 where
217 REG: Writable + RegisterSpec,
218 bool: From<FI>,
219 {
220 #[doc = " Creates a new instance of the writer"]
221 #[allow(unused)]
222 #[inline(always)]
223 pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
224 Self {
225 w,
226 o,
227 _field: marker::PhantomData,
228 }
229 }
230 }
231 }
232 #[doc = " Register reader."]
233 #[doc = ""]
234 #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
235 #[doc = " method."]
236 pub type R<REG> = raw::R<REG>;
237 impl<REG: RegisterSpec> R<REG> {
238 #[doc = " Reads raw bits from register."]
239 #[inline(always)]
240 pub const fn bits(&self) -> REG::Ux {
241 self.bits
242 }
243 }
244 impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
245 where
246 REG::Ux: PartialEq,
247 FI: Copy,
248 REG::Ux: From<FI>,
249 {
250 #[inline(always)]
251 fn eq(&self, other: &FI) -> bool {
252 self.bits.eq(®::Ux::from(*other))
253 }
254 }
255 #[doc = " Register writer."]
256 #[doc = ""]
257 #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
258 pub type W<REG> = raw::W<REG>;
259 impl<REG: Writable> W<REG> {
260 #[doc = " Writes raw bits to the register."]
261 #[doc = ""]
262 #[doc = " # Safety"]
263 #[doc = ""]
264 #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
265 #[inline(always)]
266 pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
267 self.bits = bits;
268 self
269 }
270 }
271 impl<REG> W<REG>
272 where
273 REG: Writable<Safety = Safe>,
274 {
275 #[doc = " Writes raw bits to the register."]
276 #[inline(always)]
277 pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
278 self.bits = bits;
279 self
280 }
281 }
282 #[doc = " Field reader."]
283 #[doc = ""]
284 #[doc = " Result of the `read` methods of fields."]
285 pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
286 #[doc = " Bit-wise field reader"]
287 pub type BitReader<FI = bool> = raw::BitReader<FI>;
288 impl<FI: FieldSpec> FieldReader<FI> {
289 #[doc = " Reads raw bits from field."]
290 #[inline(always)]
291 pub const fn bits(&self) -> FI::Ux {
292 self.bits
293 }
294 }
295 impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
296 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
297 core::fmt::Debug::fmt(&self.bits, f)
298 }
299 }
300 impl<FI> PartialEq<FI> for FieldReader<FI>
301 where
302 FI: FieldSpec + Copy,
303 {
304 #[inline(always)]
305 fn eq(&self, other: &FI) -> bool {
306 self.bits.eq(&FI::Ux::from(*other))
307 }
308 }
309 impl<FI> PartialEq<FI> for BitReader<FI>
310 where
311 FI: Copy,
312 bool: From<FI>,
313 {
314 #[inline(always)]
315 fn eq(&self, other: &FI) -> bool {
316 self.bits.eq(&bool::from(*other))
317 }
318 }
319 impl<FI> BitReader<FI> {
320 #[doc = " Value of the field as raw bits."]
321 #[inline(always)]
322 pub const fn bit(&self) -> bool {
323 self.bits
324 }
325 #[doc = " Returns `true` if the bit is clear (0)."]
326 #[inline(always)]
327 pub const fn bit_is_clear(&self) -> bool {
328 !self.bit()
329 }
330 #[doc = " Returns `true` if the bit is set (1)."]
331 #[inline(always)]
332 pub const fn bit_is_set(&self) -> bool {
333 self.bit()
334 }
335 }
336 impl<FI> core::fmt::Debug for BitReader<FI> {
337 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
338 core::fmt::Debug::fmt(&self.bits, f)
339 }
340 }
341 #[doc = " Marker for register/field writers which can take any value of specified width"]
342 pub struct Safe;
343 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
344 pub struct Unsafe;
345 #[doc = " Marker for field writers are safe to write in specified inclusive range"]
346 pub struct Range<const MIN: u64, const MAX: u64>;
347 #[doc = " Marker for field writers are safe to write in specified inclusive range"]
348 pub struct RangeFrom<const MIN: u64>;
349 #[doc = " Marker for field writers are safe to write in specified inclusive range"]
350 pub struct RangeTo<const MAX: u64>;
351 #[doc = " Write field Proxy"]
352 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
353 raw::FieldWriter<'a, REG, WI, FI, Safety>;
354 impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
355 where
356 REG: Writable + RegisterSpec,
357 FI: FieldSpec,
358 {
359 #[doc = " Field width"]
360 pub const WIDTH: u8 = WI;
361 #[doc = " Field width"]
362 #[inline(always)]
363 pub const fn width(&self) -> u8 {
364 WI
365 }
366 #[doc = " Field offset"]
367 #[inline(always)]
368 pub const fn offset(&self) -> u8 {
369 self.o
370 }
371 }
372 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
373 where
374 REG: Writable + RegisterSpec,
375 FI: FieldSpec,
376 REG::Ux: From<FI::Ux>,
377 {
378 #[doc = " Writes raw bits to the field"]
379 #[doc = ""]
380 #[doc = " # Safety"]
381 #[doc = ""]
382 #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
383 #[inline(always)]
384 pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
385 self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
386 self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
387 self.w
388 }
389 }
390 impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
391 where
392 REG: Writable + RegisterSpec,
393 FI: FieldSpec,
394 REG::Ux: From<FI::Ux>,
395 {
396 #[doc = " Writes raw bits to the field"]
397 #[inline(always)]
398 pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
399 unsafe { self.bits(value) }
400 }
401 }
402 impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
403 FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
404 where
405 REG: Writable + RegisterSpec,
406 FI: FieldSpec,
407 REG::Ux: From<FI::Ux>,
408 u64: From<FI::Ux>,
409 {
410 #[doc = " Writes raw bits to the field"]
411 #[inline(always)]
412 pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
413 {
414 let value = u64::from(value);
415 assert!(value >= MIN && value <= MAX);
416 }
417 unsafe { self.bits(value) }
418 }
419 }
420 impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
421 where
422 REG: Writable + RegisterSpec,
423 FI: FieldSpec,
424 REG::Ux: From<FI::Ux>,
425 u64: From<FI::Ux>,
426 {
427 #[doc = " Writes raw bits to the field"]
428 #[inline(always)]
429 pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
430 {
431 let value = u64::from(value);
432 assert!(value >= MIN);
433 }
434 unsafe { self.bits(value) }
435 }
436 }
437 impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
438 where
439 REG: Writable + RegisterSpec,
440 FI: FieldSpec,
441 REG::Ux: From<FI::Ux>,
442 u64: From<FI::Ux>,
443 {
444 #[doc = " Writes raw bits to the field"]
445 #[inline(always)]
446 pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
447 {
448 let value = u64::from(value);
449 assert!(value <= MAX);
450 }
451 unsafe { self.bits(value) }
452 }
453 }
454 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
455 where
456 REG: Writable + RegisterSpec,
457 FI: IsEnum,
458 REG::Ux: From<FI::Ux>,
459 {
460 #[doc = " Writes `variant` to the field"]
461 #[inline(always)]
462 pub fn variant(self, variant: FI) -> &'a mut W<REG> {
463 unsafe { self.bits(FI::Ux::from(variant)) }
464 }
465 }
466 macro_rules! bit_proxy {
467 ($ writer : ident , $ mwv : ident) => {
468 #[doc(hidden)]
469 pub struct $mwv;
470 #[doc = " Bit-wise write field proxy"]
471 pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
472 impl<'a, REG, FI> $writer<'a, REG, FI>
473 where
474 REG: Writable + RegisterSpec,
475 bool: From<FI>,
476 {
477 #[doc = " Field width"]
478 pub const WIDTH: u8 = 1;
479 #[doc = " Field width"]
480 #[inline(always)]
481 pub const fn width(&self) -> u8 {
482 Self::WIDTH
483 }
484 #[doc = " Field offset"]
485 #[inline(always)]
486 pub const fn offset(&self) -> u8 {
487 self.o
488 }
489 #[doc = " Writes bit to the field"]
490 #[inline(always)]
491 pub fn bit(self, value: bool) -> &'a mut W<REG> {
492 self.w.bits &= !(REG::Ux::ONE << self.o);
493 self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
494 self.w
495 }
496 #[doc = " Writes `variant` to the field"]
497 #[inline(always)]
498 pub fn variant(self, variant: FI) -> &'a mut W<REG> {
499 self.bit(bool::from(variant))
500 }
501 }
502 };
503 }
504 bit_proxy!(BitWriter, BitM);
505 bit_proxy!(BitWriter1S, Bit1S);
506 bit_proxy!(BitWriter0C, Bit0C);
507 bit_proxy!(BitWriter1C, Bit1C);
508 bit_proxy!(BitWriter0S, Bit0S);
509 bit_proxy!(BitWriter1T, Bit1T);
510 bit_proxy!(BitWriter0T, Bit0T);
511 impl<'a, REG, FI> BitWriter<'a, REG, FI>
512 where
513 REG: Writable + RegisterSpec,
514 bool: From<FI>,
515 {
516 #[doc = " Sets the field bit"]
517 #[inline(always)]
518 pub fn set_bit(self) -> &'a mut W<REG> {
519 self.w.bits |= REG::Ux::ONE << self.o;
520 self.w
521 }
522 #[doc = " Clears the field bit"]
523 #[inline(always)]
524 pub fn clear_bit(self) -> &'a mut W<REG> {
525 self.w.bits &= !(REG::Ux::ONE << self.o);
526 self.w
527 }
528 }
529 impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
530 where
531 REG: Writable + RegisterSpec,
532 bool: From<FI>,
533 {
534 #[doc = " Sets the field bit"]
535 #[inline(always)]
536 pub fn set_bit(self) -> &'a mut W<REG> {
537 self.w.bits |= REG::Ux::ONE << self.o;
538 self.w
539 }
540 }
541 impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
542 where
543 REG: Writable + RegisterSpec,
544 bool: From<FI>,
545 {
546 #[doc = " Clears the field bit"]
547 #[inline(always)]
548 pub fn clear_bit(self) -> &'a mut W<REG> {
549 self.w.bits &= !(REG::Ux::ONE << self.o);
550 self.w
551 }
552 }
553 impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
554 where
555 REG: Writable + RegisterSpec,
556 bool: From<FI>,
557 {
558 #[doc = "Clears the field bit by passing one"]
559 #[inline(always)]
560 pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
561 self.w.bits |= REG::Ux::ONE << self.o;
562 self.w
563 }
564 }
565 impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
566 where
567 REG: Writable + RegisterSpec,
568 bool: From<FI>,
569 {
570 #[doc = "Sets the field bit by passing zero"]
571 #[inline(always)]
572 pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
573 self.w.bits &= !(REG::Ux::ONE << self.o);
574 self.w
575 }
576 }
577 impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
578 where
579 REG: Writable + RegisterSpec,
580 bool: From<FI>,
581 {
582 #[doc = "Toggle the field bit by passing one"]
583 #[inline(always)]
584 pub fn toggle_bit(self) -> &'a mut W<REG> {
585 self.w.bits |= REG::Ux::ONE << self.o;
586 self.w
587 }
588 }
589 impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
590 where
591 REG: Writable + RegisterSpec,
592 bool: From<FI>,
593 {
594 #[doc = "Toggle the field bit by passing zero"]
595 #[inline(always)]
596 pub fn toggle_bit(self) -> &'a mut W<REG> {
597 self.w.bits &= !(REG::Ux::ONE << self.o);
598 self.w
599 }
600 }
601 #[doc = " This structure provides volatile access to registers."]
602 #[repr(transparent)]
603 pub struct Reg<REG: RegisterSpec> {
604 register: vcell::VolatileCell<REG::Ux>,
605 _marker: marker::PhantomData<REG>,
606 }
607 unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
608 impl<REG: RegisterSpec> Reg<REG> {
609 #[doc = " Returns the underlying memory address of register."]
610 #[doc = ""]
611 #[doc = " ```ignore"]
612 #[doc = " let reg_ptr = periph.reg.as_ptr();"]
613 #[doc = " ```"]
614 #[inline(always)]
615 pub fn as_ptr(&self) -> *mut REG::Ux {
616 self.register.as_ptr()
617 }
618 }
619 impl<REG: Readable> Reg<REG> {
620 #[doc = " Reads the contents of a `Readable` register."]
621 #[doc = ""]
622 #[doc = " You can read the raw contents of a register by using `bits`:"]
623 #[doc = " ```ignore"]
624 #[doc = " let bits = periph.reg.read().bits();"]
625 #[doc = " ```"]
626 #[doc = " or get the content of a particular field of a register:"]
627 #[doc = " ```ignore"]
628 #[doc = " let reader = periph.reg.read();"]
629 #[doc = " let bits = reader.field1().bits();"]
630 #[doc = " let flag = reader.field2().bit_is_set();"]
631 #[doc = " ```"]
632 #[inline(always)]
633 pub fn read(&self) -> R<REG> {
634 R {
635 bits: self.register.get(),
636 _reg: marker::PhantomData,
637 }
638 }
639 }
640 impl<REG: Resettable + Writable> Reg<REG> {
641 #[doc = " Writes the reset value to `Writable` register."]
642 #[doc = ""]
643 #[doc = " Resets the register to its initial state."]
644 #[inline(always)]
645 pub fn reset(&self) {
646 self.register.set(REG::RESET_VALUE)
647 }
648 #[doc = " Writes bits to a `Writable` register."]
649 #[doc = ""]
650 #[doc = " You can write raw bits into a register:"]
651 #[doc = " ```ignore"]
652 #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
653 #[doc = " ```"]
654 #[doc = " or write only the fields you need:"]
655 #[doc = " ```ignore"]
656 #[doc = " periph.reg.write(|w| w"]
657 #[doc = " .field1().bits(newfield1bits)"]
658 #[doc = " .field2().set_bit()"]
659 #[doc = " .field3().variant(VARIANT)"]
660 #[doc = " );"]
661 #[doc = " ```"]
662 #[doc = " or an alternative way of saying the same:"]
663 #[doc = " ```ignore"]
664 #[doc = " periph.reg.write(|w| {"]
665 #[doc = " w.field1().bits(newfield1bits);"]
666 #[doc = " w.field2().set_bit();"]
667 #[doc = " w.field3().variant(VARIANT)"]
668 #[doc = " });"]
669 #[doc = " ```"]
670 #[doc = " In the latter case, other fields will be set to their reset value."]
671 #[inline(always)]
672 pub fn write<F>(&self, f: F) -> REG::Ux
673 where
674 F: FnOnce(&mut W<REG>) -> &mut W<REG>,
675 {
676 let value = f(&mut W {
677 bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
678 | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
679 _reg: marker::PhantomData,
680 })
681 .bits;
682 self.register.set(value);
683 value
684 }
685 #[doc = " Writes bits to a `Writable` register and produce a value."]
686 #[doc = ""]
687 #[doc = " You can write raw bits into a register:"]
688 #[doc = " ```ignore"]
689 #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
690 #[doc = " ```"]
691 #[doc = " or write only the fields you need:"]
692 #[doc = " ```ignore"]
693 #[doc = " periph.reg.write_and(|w| {"]
694 #[doc = " w.field1().bits(newfield1bits)"]
695 #[doc = " .field2().set_bit()"]
696 #[doc = " .field3().variant(VARIANT);"]
697 #[doc = " });"]
698 #[doc = " ```"]
699 #[doc = " or an alternative way of saying the same:"]
700 #[doc = " ```ignore"]
701 #[doc = " periph.reg.write_and(|w| {"]
702 #[doc = " w.field1().bits(newfield1bits);"]
703 #[doc = " w.field2().set_bit();"]
704 #[doc = " w.field3().variant(VARIANT);"]
705 #[doc = " });"]
706 #[doc = " ```"]
707 #[doc = " In the latter case, other fields will be set to their reset value."]
708 #[doc = ""]
709 #[doc = " Values can be returned from the closure:"]
710 #[doc = " ```ignore"]
711 #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
712 #[doc = " ```"]
713 #[inline(always)]
714 pub fn from_write<F, T>(&self, f: F) -> T
715 where
716 F: FnOnce(&mut W<REG>) -> T,
717 {
718 let mut writer = W {
719 bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
720 | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
721 _reg: marker::PhantomData,
722 };
723 let result = f(&mut writer);
724 self.register.set(writer.bits);
725 result
726 }
727 }
728 impl<REG: Writable> Reg<REG> {
729 #[doc = " Writes 0 to a `Writable` register."]
730 #[doc = ""]
731 #[doc = " Similar to `write`, but unused bits will contain 0."]
732 #[doc = ""]
733 #[doc = " # Safety"]
734 #[doc = ""]
735 #[doc = " Unsafe to use with registers which don't allow to write 0."]
736 #[inline(always)]
737 pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
738 where
739 F: FnOnce(&mut W<REG>) -> &mut W<REG>,
740 {
741 let value = f(&mut W {
742 bits: REG::Ux::ZERO,
743 _reg: marker::PhantomData,
744 })
745 .bits;
746 self.register.set(value);
747 value
748 }
749 #[doc = " Writes 0 to a `Writable` register and produces a value."]
750 #[doc = ""]
751 #[doc = " Similar to `write`, but unused bits will contain 0."]
752 #[doc = ""]
753 #[doc = " # Safety"]
754 #[doc = ""]
755 #[doc = " Unsafe to use with registers which don't allow to write 0."]
756 #[inline(always)]
757 pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
758 where
759 F: FnOnce(&mut W<REG>) -> T,
760 {
761 let mut writer = W {
762 bits: REG::Ux::ZERO,
763 _reg: marker::PhantomData,
764 };
765 let result = f(&mut writer);
766 self.register.set(writer.bits);
767 result
768 }
769 }
770 impl<REG: Readable + Writable> Reg<REG> {
771 #[doc = " Modifies the contents of the register by reading and then writing it."]
772 #[doc = ""]
773 #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
774 #[doc = " ```ignore"]
775 #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
776 #[doc = " r.bits() | 3"]
777 #[doc = " ) });"]
778 #[doc = " ```"]
779 #[doc = " or"]
780 #[doc = " ```ignore"]
781 #[doc = " periph.reg.modify(|_, w| w"]
782 #[doc = " .field1().bits(newfield1bits)"]
783 #[doc = " .field2().set_bit()"]
784 #[doc = " .field3().variant(VARIANT)"]
785 #[doc = " );"]
786 #[doc = " ```"]
787 #[doc = " or an alternative way of saying the same:"]
788 #[doc = " ```ignore"]
789 #[doc = " periph.reg.modify(|_, w| {"]
790 #[doc = " w.field1().bits(newfield1bits);"]
791 #[doc = " w.field2().set_bit();"]
792 #[doc = " w.field3().variant(VARIANT)"]
793 #[doc = " });"]
794 #[doc = " ```"]
795 #[doc = " Other fields will have the value they had before the call to `modify`."]
796 #[inline(always)]
797 pub fn modify<F>(&self, f: F) -> REG::Ux
798 where
799 for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
800 {
801 let bits = self.register.get();
802 let value = f(
803 &R {
804 bits,
805 _reg: marker::PhantomData,
806 },
807 &mut W {
808 bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
809 | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
810 _reg: marker::PhantomData,
811 },
812 )
813 .bits;
814 self.register.set(value);
815 value
816 }
817 #[doc = " Modifies the contents of the register by reading and then writing it"]
818 #[doc = " and produces a value."]
819 #[doc = ""]
820 #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
821 #[doc = " ```ignore"]
822 #[doc = " let bits = periph.reg.modify(|r, w| {"]
823 #[doc = " let new_bits = r.bits() | 3;"]
824 #[doc = " unsafe {"]
825 #[doc = " w.bits(new_bits);"]
826 #[doc = " }"]
827 #[doc = ""]
828 #[doc = " new_bits"]
829 #[doc = " });"]
830 #[doc = " ```"]
831 #[doc = " or"]
832 #[doc = " ```ignore"]
833 #[doc = " periph.reg.modify(|_, w| {"]
834 #[doc = " w.field1().bits(newfield1bits)"]
835 #[doc = " .field2().set_bit()"]
836 #[doc = " .field3().variant(VARIANT);"]
837 #[doc = " });"]
838 #[doc = " ```"]
839 #[doc = " or an alternative way of saying the same:"]
840 #[doc = " ```ignore"]
841 #[doc = " periph.reg.modify(|_, w| {"]
842 #[doc = " w.field1().bits(newfield1bits);"]
843 #[doc = " w.field2().set_bit();"]
844 #[doc = " w.field3().variant(VARIANT);"]
845 #[doc = " });"]
846 #[doc = " ```"]
847 #[doc = " Other fields will have the value they had before the call to `modify`."]
848 #[inline(always)]
849 pub fn from_modify<F, T>(&self, f: F) -> T
850 where
851 for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
852 {
853 let bits = self.register.get();
854 let mut writer = W {
855 bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
856 _reg: marker::PhantomData,
857 };
858 let result = f(
859 &R {
860 bits,
861 _reg: marker::PhantomData,
862 },
863 &mut writer,
864 );
865 self.register.set(writer.bits);
866 result
867 }
868 }
869 impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
870 where
871 R<REG>: core::fmt::Debug,
872 {
873 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
874 core::fmt::Debug::fmt(&self.read(), f)
875 }
876 }
877}
878#[doc = r" Interrupt numbers, priority levels, and HART IDs."]
879pub mod interrupt {
880 #[cfg(target_arch = "riscv32")]
881 pub use riscv::interrupt::Exception;
882 #[cfg(target_arch = "riscv32")]
883 pub use riscv::interrupt::Interrupt as CoreInterrupt;
884 #[cfg(target_arch = "riscv32")]
885 pub use riscv::{
886 ExceptionNumber, HartIdNumber, InterruptNumber, PriorityNumber,
887 interrupt::{disable, enable, free, nested},
888 };
889 #[cfg(target_arch = "riscv32")]
890 pub type Trap = riscv::interrupt::Trap<CoreInterrupt, Exception>;
891 #[doc = r" Retrieves the cause of a trap in the current hart."]
892 #[doc = r""]
893 #[doc = r" If the raw cause is not a valid interrupt or exception for the target, it returns an error."]
894 #[inline]
895 #[cfg(target_arch = "riscv32")]
896 pub fn try_cause() -> riscv::result::Result<Trap> {
897 riscv::interrupt::try_cause()
898 }
899 #[doc = r" Retrieves the cause of a trap in the current hart (machine mode)."]
900 #[doc = r""]
901 #[doc = r" If the raw cause is not a valid interrupt or exception for the target, it panics."]
902 #[inline]
903 #[cfg(target_arch = "riscv32")]
904 pub fn cause() -> Trap {
905 try_cause().unwrap()
906 }
907 #[doc = r" External interrupts. These interrupts are handled by the external peripherals."]
908 #[cfg_attr(target_arch = "riscv32", riscv :: pac_enum (unsafe ExternalInterruptNumber))]
909 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
910 pub enum ExternalInterrupt {
911 #[doc = "26 - BT_INT0 (IRQ 26)"]
912 BT_INT0 = 26,
913 #[doc = "27 - BT_INT1 (IRQ 27)"]
914 BT_INT1 = 27,
915 #[doc = "28 - GADC_DONE (IRQ 28)"]
916 GADC_DONE = 28,
917 #[doc = "29 - GADC_ALARM (IRQ 29)"]
918 GADC_ALARM = 29,
919 #[doc = "32 - MCU_PCLR_LOCK (IRQ 32)"]
920 MCU_PCLR_LOCK = 32,
921 #[doc = "33 - ULP_GPIO (IRQ 33)"]
922 ULP_GPIO = 33,
923 #[doc = "34 - GPIO_0 (IRQ 34)"]
924 GPIO_0 = 34,
925 #[doc = "35 - GPIO_1 (IRQ 35)"]
926 GPIO_1 = 35,
927 #[doc = "36 - BT_TOGGLE_POS (IRQ 36)"]
928 BT_TOGGLE_POS = 36,
929 #[doc = "37 - BT_TOGGLE_NEG (IRQ 37)"]
930 BT_TOGGLE_NEG = 37,
931 #[doc = "38 - KEY_SCAN_LOW_POWER (IRQ 38)"]
932 KEY_SCAN_LOW_POWER = 38,
933 #[doc = "39 - UART_0 (IRQ 39)"]
934 UART_0 = 39,
935 #[doc = "40 - MCU_SIMO1P1_VSET (IRQ 40)"]
936 MCU_SIMO1P1_VSET = 40,
937 #[doc = "41 - UART_1 (IRQ 41)"]
938 UART_1 = 41,
939 #[doc = "42 - UART_2 (IRQ 42)"]
940 UART_2 = 42,
941 #[doc = "43 - QSPI0_2CS (IRQ 43)"]
942 QSPI0_2CS = 43,
943 #[doc = "44 - PDM (IRQ 44)"]
944 PDM = 44,
945 #[doc = "46 - KEY_SCAN (IRQ 46)"]
946 KEY_SCAN = 46,
947 #[doc = "47 - M_WAKEUP (IRQ 47)"]
948 M_WAKEUP = 47,
949 #[doc = "48 - M_SLEEP (IRQ 48)"]
950 M_SLEEP = 48,
951 #[doc = "49 - RTC_0 (IRQ 49)"]
952 RTC_0 = 49,
953 #[doc = "50 - RTC_1 (IRQ 50)"]
954 RTC_1 = 50,
955 #[doc = "51 - RTC_2 (IRQ 51)"]
956 RTC_2 = 51,
957 #[doc = "52 - RTC_3 (IRQ 52)"]
958 RTC_3 = 52,
959 #[doc = "53 - TIMER_0 (IRQ 53)"]
960 TIMER_0 = 53,
961 #[doc = "54 - TIMER_1 (IRQ 54)"]
962 TIMER_1 = 54,
963 #[doc = "55 - TIMER_2 (IRQ 55)"]
964 TIMER_2 = 55,
965 #[doc = "56 - TIMER_3 (IRQ 56)"]
966 TIMER_3 = 56,
967 #[doc = "57 - M_SDMA (IRQ 57)"]
968 M_SDMA = 57,
969 #[doc = "59 - SPI_M_S_0 (IRQ 59)"]
970 SPI_M_S_0 = 59,
971 #[doc = "60 - SPI_M_S_1 (IRQ 60)"]
972 SPI_M_S_1 = 60,
973 #[doc = "61 - SPI_M (IRQ 61)"]
974 SPI_M = 61,
975 #[doc = "63 - I2C_1 (IRQ 63)"]
976 I2C_1 = 63,
977 #[doc = "64 - BT_BB_BT (IRQ 64)"]
978 BT_BB_BT = 64,
979 #[doc = "65 - BT_BB_BLE (IRQ 65)"]
980 BT_BB_BLE = 65,
981 #[doc = "66 - BT_BB_GLE (IRQ 66)"]
982 BT_BB_GLE = 66,
983 #[doc = "67 - I2S (IRQ 67)"]
984 I2S = 67,
985 #[doc = "68 - RF_PRT (IRQ 68)"]
986 RF_PRT = 68,
987 #[doc = "69 - NFC (IRQ 69)"]
988 NFC = 69,
989 #[doc = "70 - SEC (IRQ 70)"]
990 SEC = 70,
991 #[doc = "71 - PWM_0 (IRQ 71)"]
992 PWM_0 = 71,
993 #[doc = "72 - PWM_1 (IRQ 72)"]
994 PWM_1 = 72,
995 #[doc = "73 - OSC_EN_WKUP (IRQ 73)"]
996 OSC_EN_WKUP = 73,
997 #[doc = "74 - OSC_EN_SLEEP (IRQ 74)"]
998 OSC_EN_SLEEP = 74,
999 #[doc = "78 - PMU_CMU_ERR (IRQ 78)"]
1000 PMU_CMU_ERR = 78,
1001 #[doc = "79 - ULP_INT (IRQ 79)"]
1002 ULP_INT = 79,
1003 #[doc = "85 - PMU2_CLK_32K_CALI (IRQ 85)"]
1004 PMU2_CLK_32K_CALI = 85,
1005 #[doc = "86 - ULP_WKUP_INT (IRQ 86)"]
1006 ULP_WKUP_INT = 86,
1007 #[doc = "87 - TSENSOR (IRQ 87)"]
1008 TSENSOR = 87,
1009 #[doc = "88 - QDEC (IRQ 88)"]
1010 QDEC = 88,
1011 #[doc = "89 - USB (IRQ 89)"]
1012 USB = 89,
1013 }
1014}
1015#[doc = "Main core global control - BCPU/MCPU reset status, chip reset, AON CRG"]
1016pub type GlbCtlM = crate::Periph<glb_ctl_m::RegisterBlock, 0x5700_0000>;
1017impl core::fmt::Debug for GlbCtlM {
1018 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1019 f.debug_struct("GlbCtlM").finish()
1020 }
1021}
1022#[doc = "Main core global control - BCPU/MCPU reset status, chip reset, AON CRG"]
1023pub mod glb_ctl_m {
1024 #[repr(C)]
1025 #[doc = "Register block"]
1026 pub struct RegisterBlock {
1027 _reserved0: [u8; 0x30],
1028 bcpu_reset_sts: BcpuResetSts,
1029 mcpu_reset_sts: McpuResetSts,
1030 _reserved2: [u8; 0x04],
1031 reset_sts_clear: ResetStsClear,
1032 _reserved3: [u8; 0xc0],
1033 aon_crg_cken_ctl: AonCrgCkenCtl,
1034 _reserved4: [u8; 0x0c],
1035 _reserved_4_chip_reset: [u8; 0x04],
1036 }
1037 impl RegisterBlock {
1038 #[doc = "0x30 - BCPU reset status register"]
1039 #[inline(always)]
1040 pub const fn bcpu_reset_sts(&self) -> &BcpuResetSts {
1041 &self.bcpu_reset_sts
1042 }
1043 #[doc = "0x34 - MCPU reset status register"]
1044 #[inline(always)]
1045 pub const fn mcpu_reset_sts(&self) -> &McpuResetSts {
1046 &self.mcpu_reset_sts
1047 }
1048 #[doc = "0x3c - Reset status clear register"]
1049 #[inline(always)]
1050 pub const fn reset_sts_clear(&self) -> &ResetStsClear {
1051 &self.reset_sts_clear
1052 }
1053 #[doc = "0x100 - AON CRG clock enable control"]
1054 #[inline(always)]
1055 pub const fn aon_crg_cken_ctl(&self) -> &AonCrgCkenCtl {
1056 &self.aon_crg_cken_ctl
1057 }
1058 #[doc = "0x110 - AON soft reset control"]
1059 #[inline(always)]
1060 pub const fn aon_soft_rst_ctl(&self) -> &AonSoftRstCtl {
1061 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(272).cast() }
1062 }
1063 #[doc = "0x110 - Chip reset control register"]
1064 #[inline(always)]
1065 pub const fn chip_reset(&self) -> &ChipReset {
1066 unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(272).cast() }
1067 }
1068 }
1069 #[doc = "BCPU_RESET_STS (rw) register accessor: BCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcpu_reset_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcpu_reset_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bcpu_reset_sts`] module"]
1070 #[doc(alias = "BCPU_RESET_STS")]
1071 pub type BcpuResetSts = crate::Reg<bcpu_reset_sts::BcpuResetStsSpec>;
1072 #[doc = "BCPU reset status register"]
1073 pub mod bcpu_reset_sts {
1074 #[doc = "Register `BCPU_RESET_STS` reader"]
1075 pub type R = crate::R<BcpuResetStsSpec>;
1076 #[doc = "Register `BCPU_RESET_STS` writer"]
1077 pub type W = crate::W<BcpuResetStsSpec>;
1078 #[doc = "Field `bcpu_reset_sts` reader - BCPU reset status"]
1079 pub type BcpuResetStsR = crate::FieldReader<u32>;
1080 impl R {
1081 #[doc = "Bits 0:31 - BCPU reset status"]
1082 #[inline(always)]
1083 pub fn bcpu_reset_sts(&self) -> BcpuResetStsR {
1084 BcpuResetStsR::new(self.bits)
1085 }
1086 }
1087 impl W {}
1088 #[doc = "BCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcpu_reset_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcpu_reset_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1089 pub struct BcpuResetStsSpec;
1090 impl crate::RegisterSpec for BcpuResetStsSpec {
1091 type Ux = u32;
1092 }
1093 #[doc = "`read()` method returns [`bcpu_reset_sts::R`](R) reader structure"]
1094 impl crate::Readable for BcpuResetStsSpec {}
1095 #[doc = "`write(|w| ..)` method takes [`bcpu_reset_sts::W`](W) writer structure"]
1096 impl crate::Writable for BcpuResetStsSpec {
1097 type Safety = crate::Unsafe;
1098 }
1099 #[doc = "`reset()` method sets BCPU_RESET_STS to value 0"]
1100 impl crate::Resettable for BcpuResetStsSpec {}
1101 }
1102 #[doc = "MCPU_RESET_STS (rw) register accessor: MCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mcpu_reset_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcpu_reset_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcpu_reset_sts`] module"]
1103 #[doc(alias = "MCPU_RESET_STS")]
1104 pub type McpuResetSts = crate::Reg<mcpu_reset_sts::McpuResetStsSpec>;
1105 #[doc = "MCPU reset status register"]
1106 pub mod mcpu_reset_sts {
1107 #[doc = "Register `MCPU_RESET_STS` reader"]
1108 pub type R = crate::R<McpuResetStsSpec>;
1109 #[doc = "Register `MCPU_RESET_STS` writer"]
1110 pub type W = crate::W<McpuResetStsSpec>;
1111 #[doc = "Field `mcpu_reset_sts` reader - MCPU reset status"]
1112 pub type McpuResetStsR = crate::FieldReader<u32>;
1113 impl R {
1114 #[doc = "Bits 0:31 - MCPU reset status"]
1115 #[inline(always)]
1116 pub fn mcpu_reset_sts(&self) -> McpuResetStsR {
1117 McpuResetStsR::new(self.bits)
1118 }
1119 }
1120 impl W {}
1121 #[doc = "MCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mcpu_reset_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcpu_reset_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1122 pub struct McpuResetStsSpec;
1123 impl crate::RegisterSpec for McpuResetStsSpec {
1124 type Ux = u32;
1125 }
1126 #[doc = "`read()` method returns [`mcpu_reset_sts::R`](R) reader structure"]
1127 impl crate::Readable for McpuResetStsSpec {}
1128 #[doc = "`write(|w| ..)` method takes [`mcpu_reset_sts::W`](W) writer structure"]
1129 impl crate::Writable for McpuResetStsSpec {
1130 type Safety = crate::Unsafe;
1131 }
1132 #[doc = "`reset()` method sets MCPU_RESET_STS to value 0"]
1133 impl crate::Resettable for McpuResetStsSpec {}
1134 }
1135 #[doc = "RESET_STS_CLEAR (rw) register accessor: Reset status clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_sts_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_sts_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_sts_clear`] module"]
1136 #[doc(alias = "RESET_STS_CLEAR")]
1137 pub type ResetStsClear = crate::Reg<reset_sts_clear::ResetStsClearSpec>;
1138 #[doc = "Reset status clear register"]
1139 pub mod reset_sts_clear {
1140 #[doc = "Register `RESET_STS_CLEAR` reader"]
1141 pub type R = crate::R<ResetStsClearSpec>;
1142 #[doc = "Register `RESET_STS_CLEAR` writer"]
1143 pub type W = crate::W<ResetStsClearSpec>;
1144 #[doc = "Field `rst_sts_clear` writer - Write 0xFF to clear all reset status bits"]
1145 pub type RstStsClearW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
1146 impl W {
1147 #[doc = "Bits 0:31 - Write 0xFF to clear all reset status bits"]
1148 #[inline(always)]
1149 pub fn rst_sts_clear(&mut self) -> RstStsClearW<'_, ResetStsClearSpec> {
1150 RstStsClearW::new(self, 0)
1151 }
1152 }
1153 #[doc = "Reset status clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_sts_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_sts_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1154 pub struct ResetStsClearSpec;
1155 impl crate::RegisterSpec for ResetStsClearSpec {
1156 type Ux = u32;
1157 }
1158 #[doc = "`read()` method returns [`reset_sts_clear::R`](R) reader structure"]
1159 impl crate::Readable for ResetStsClearSpec {}
1160 #[doc = "`write(|w| ..)` method takes [`reset_sts_clear::W`](W) writer structure"]
1161 impl crate::Writable for ResetStsClearSpec {
1162 type Safety = crate::Unsafe;
1163 }
1164 #[doc = "`reset()` method sets RESET_STS_CLEAR to value 0"]
1165 impl crate::Resettable for ResetStsClearSpec {}
1166 }
1167 #[doc = "AON_CRG_CKEN_CTL (rw) register accessor: AON CRG clock enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_crg_cken_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_crg_cken_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_crg_cken_ctl`] module"]
1168 #[doc(alias = "AON_CRG_CKEN_CTL")]
1169 pub type AonCrgCkenCtl = crate::Reg<aon_crg_cken_ctl::AonCrgCkenCtlSpec>;
1170 #[doc = "AON CRG clock enable control"]
1171 pub mod aon_crg_cken_ctl {
1172 #[doc = "Register `AON_CRG_CKEN_CTL` reader"]
1173 pub type R = crate::R<AonCrgCkenCtlSpec>;
1174 #[doc = "Register `AON_CRG_CKEN_CTL` writer"]
1175 pub type W = crate::W<AonCrgCkenCtlSpec>;
1176 #[doc = "Field `wdt_gate` reader - WDT clock gate control at bit\\[4\\]"]
1177 pub type WdtGateR = crate::BitReader;
1178 #[doc = "Field `wdt_gate` writer - WDT clock gate control at bit\\[4\\]"]
1179 pub type WdtGateW<'a, REG> = crate::BitWriter<'a, REG>;
1180 impl R {
1181 #[doc = "Bit 4 - WDT clock gate control at bit\\[4\\]"]
1182 #[inline(always)]
1183 pub fn wdt_gate(&self) -> WdtGateR {
1184 WdtGateR::new(((self.bits >> 4) & 1) != 0)
1185 }
1186 }
1187 impl W {
1188 #[doc = "Bit 4 - WDT clock gate control at bit\\[4\\]"]
1189 #[inline(always)]
1190 pub fn wdt_gate(&mut self) -> WdtGateW<'_, AonCrgCkenCtlSpec> {
1191 WdtGateW::new(self, 4)
1192 }
1193 }
1194 #[doc = "AON CRG clock enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_crg_cken_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_crg_cken_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1195 pub struct AonCrgCkenCtlSpec;
1196 impl crate::RegisterSpec for AonCrgCkenCtlSpec {
1197 type Ux = u32;
1198 }
1199 #[doc = "`read()` method returns [`aon_crg_cken_ctl::R`](R) reader structure"]
1200 impl crate::Readable for AonCrgCkenCtlSpec {}
1201 #[doc = "`write(|w| ..)` method takes [`aon_crg_cken_ctl::W`](W) writer structure"]
1202 impl crate::Writable for AonCrgCkenCtlSpec {
1203 type Safety = crate::Unsafe;
1204 }
1205 #[doc = "`reset()` method sets AON_CRG_CKEN_CTL to value 0"]
1206 impl crate::Resettable for AonCrgCkenCtlSpec {}
1207 }
1208 #[doc = "CHIP_RESET (rw) register accessor: Chip reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`chip_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chip_reset`] module"]
1209 #[doc(alias = "CHIP_RESET")]
1210 pub type ChipReset = crate::Reg<chip_reset::ChipResetSpec>;
1211 #[doc = "Chip reset control register"]
1212 pub mod chip_reset {
1213 #[doc = "Register `CHIP_RESET` reader"]
1214 pub type R = crate::R<ChipResetSpec>;
1215 #[doc = "Register `CHIP_RESET` writer"]
1216 pub type W = crate::W<ChipResetSpec>;
1217 #[doc = "Field `chip_reset_en` reader - Chip reset enable: 1=assert chip reset"]
1218 pub type ChipResetEnR = crate::BitReader;
1219 #[doc = "Field `chip_reset_en` writer - Chip reset enable: 1=assert chip reset"]
1220 pub type ChipResetEnW<'a, REG> = crate::BitWriter<'a, REG>;
1221 impl R {
1222 #[doc = "Bit 2 - Chip reset enable: 1=assert chip reset"]
1223 #[inline(always)]
1224 pub fn chip_reset_en(&self) -> ChipResetEnR {
1225 ChipResetEnR::new(((self.bits >> 2) & 1) != 0)
1226 }
1227 }
1228 impl W {
1229 #[doc = "Bit 2 - Chip reset enable: 1=assert chip reset"]
1230 #[inline(always)]
1231 pub fn chip_reset_en(&mut self) -> ChipResetEnW<'_, ChipResetSpec> {
1232 ChipResetEnW::new(self, 2)
1233 }
1234 }
1235 #[doc = "Chip reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`chip_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1236 pub struct ChipResetSpec;
1237 impl crate::RegisterSpec for ChipResetSpec {
1238 type Ux = u32;
1239 }
1240 #[doc = "`read()` method returns [`chip_reset::R`](R) reader structure"]
1241 impl crate::Readable for ChipResetSpec {}
1242 #[doc = "`write(|w| ..)` method takes [`chip_reset::W`](W) writer structure"]
1243 impl crate::Writable for ChipResetSpec {
1244 type Safety = crate::Unsafe;
1245 }
1246 #[doc = "`reset()` method sets CHIP_RESET to value 0"]
1247 impl crate::Resettable for ChipResetSpec {}
1248 }
1249 #[doc = "AON_SOFT_RST_CTL (rw) register accessor: AON soft reset control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_soft_rst_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_soft_rst_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_soft_rst_ctl`] module"]
1250 #[doc(alias = "AON_SOFT_RST_CTL")]
1251 pub type AonSoftRstCtl = crate::Reg<aon_soft_rst_ctl::AonSoftRstCtlSpec>;
1252 #[doc = "AON soft reset control"]
1253 pub mod aon_soft_rst_ctl {
1254 #[doc = "Register `AON_SOFT_RST_CTL` reader"]
1255 pub type R = crate::R<AonSoftRstCtlSpec>;
1256 #[doc = "Register `AON_SOFT_RST_CTL` writer"]
1257 pub type W = crate::W<AonSoftRstCtlSpec>;
1258 #[doc = "Field `wdt_soft_rst` reader - WDT soft reset at bit\\[1\\]"]
1259 pub type WdtSoftRstR = crate::BitReader;
1260 #[doc = "Field `wdt_soft_rst` writer - WDT soft reset at bit\\[1\\]"]
1261 pub type WdtSoftRstW<'a, REG> = crate::BitWriter<'a, REG>;
1262 impl R {
1263 #[doc = "Bit 1 - WDT soft reset at bit\\[1\\]"]
1264 #[inline(always)]
1265 pub fn wdt_soft_rst(&self) -> WdtSoftRstR {
1266 WdtSoftRstR::new(((self.bits >> 1) & 1) != 0)
1267 }
1268 }
1269 impl W {
1270 #[doc = "Bit 1 - WDT soft reset at bit\\[1\\]"]
1271 #[inline(always)]
1272 pub fn wdt_soft_rst(&mut self) -> WdtSoftRstW<'_, AonSoftRstCtlSpec> {
1273 WdtSoftRstW::new(self, 1)
1274 }
1275 }
1276 #[doc = "AON soft reset control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_soft_rst_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_soft_rst_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1277 pub struct AonSoftRstCtlSpec;
1278 impl crate::RegisterSpec for AonSoftRstCtlSpec {
1279 type Ux = u32;
1280 }
1281 #[doc = "`read()` method returns [`aon_soft_rst_ctl::R`](R) reader structure"]
1282 impl crate::Readable for AonSoftRstCtlSpec {}
1283 #[doc = "`write(|w| ..)` method takes [`aon_soft_rst_ctl::W`](W) writer structure"]
1284 impl crate::Writable for AonSoftRstCtlSpec {
1285 type Safety = crate::Unsafe;
1286 }
1287 #[doc = "`reset()` method sets AON_SOFT_RST_CTL to value 0"]
1288 impl crate::Resettable for AonSoftRstCtlSpec {}
1289 }
1290}
1291#[doc = "GPIO controller for GPIO\\[7:0\\]"]
1292pub type Gpio0 = crate::Periph<gpio0::RegisterBlock, 0x5701_0000>;
1293impl core::fmt::Debug for Gpio0 {
1294 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1295 f.debug_struct("Gpio0").finish()
1296 }
1297}
1298#[doc = "GPIO controller for GPIO\\[7:0\\]"]
1299pub mod gpio0 {
1300 #[repr(C)]
1301 #[doc = "Register block"]
1302 pub struct RegisterBlock {
1303 gpio_sw_out: GpioSwOut,
1304 gpio_sw_oen: GpioSwOen,
1305 _reserved2: [u8; 0x04],
1306 gpio_int_en: GpioIntEn,
1307 gpio_int_mask: GpioIntMask,
1308 gpio_int_type: GpioIntType,
1309 gpio_int_polarity: GpioIntPolarity,
1310 gpio_int_dedge: GpioIntDedge,
1311 gpio_int_debounce: GpioIntDebounce,
1312 gpio_int_raw: GpioIntRaw,
1313 gpio_intr: GpioIntr,
1314 gpio_int_eoi: GpioIntEoi,
1315 gpio_data_set: GpioDataSet,
1316 gpio_data_clr: GpioDataClr,
1317 }
1318 impl RegisterBlock {
1319 #[doc = "0x00 - GPIO data register"]
1320 #[inline(always)]
1321 pub const fn gpio_sw_out(&self) -> &GpioSwOut {
1322 &self.gpio_sw_out
1323 }
1324 #[doc = "0x04 - GPIO data direction register"]
1325 #[inline(always)]
1326 pub const fn gpio_sw_oen(&self) -> &GpioSwOen {
1327 &self.gpio_sw_oen
1328 }
1329 #[doc = "0x0c - GPIO interrupt enable register"]
1330 #[inline(always)]
1331 pub const fn gpio_int_en(&self) -> &GpioIntEn {
1332 &self.gpio_int_en
1333 }
1334 #[doc = "0x10 - GPIO interrupt mask register"]
1335 #[inline(always)]
1336 pub const fn gpio_int_mask(&self) -> &GpioIntMask {
1337 &self.gpio_int_mask
1338 }
1339 #[doc = "0x14 - GPIO interrupt type register"]
1340 #[inline(always)]
1341 pub const fn gpio_int_type(&self) -> &GpioIntType {
1342 &self.gpio_int_type
1343 }
1344 #[doc = "0x18 - GPIO interrupt polarity register"]
1345 #[inline(always)]
1346 pub const fn gpio_int_polarity(&self) -> &GpioIntPolarity {
1347 &self.gpio_int_polarity
1348 }
1349 #[doc = "0x1c - GPIO dual-edge interrupt enable register"]
1350 #[inline(always)]
1351 pub const fn gpio_int_dedge(&self) -> &GpioIntDedge {
1352 &self.gpio_int_dedge
1353 }
1354 #[doc = "0x20 - GPIO interrupt debounce control register"]
1355 #[inline(always)]
1356 pub const fn gpio_int_debounce(&self) -> &GpioIntDebounce {
1357 &self.gpio_int_debounce
1358 }
1359 #[doc = "0x24 - GPIO raw interrupt status register"]
1360 #[inline(always)]
1361 pub const fn gpio_int_raw(&self) -> &GpioIntRaw {
1362 &self.gpio_int_raw
1363 }
1364 #[doc = "0x28 - GPIO interrupt status register"]
1365 #[inline(always)]
1366 pub const fn gpio_intr(&self) -> &GpioIntr {
1367 &self.gpio_intr
1368 }
1369 #[doc = "0x2c - GPIO interrupt clear register"]
1370 #[inline(always)]
1371 pub const fn gpio_int_eoi(&self) -> &GpioIntEoi {
1372 &self.gpio_int_eoi
1373 }
1374 #[doc = "0x30 - GPIO data set register"]
1375 #[inline(always)]
1376 pub const fn gpio_data_set(&self) -> &GpioDataSet {
1377 &self.gpio_data_set
1378 }
1379 #[doc = "0x34 - GPIO data clear register"]
1380 #[inline(always)]
1381 pub const fn gpio_data_clr(&self) -> &GpioDataClr {
1382 &self.gpio_data_clr
1383 }
1384 }
1385 #[doc = "GPIO_SW_OUT (rw) register accessor: GPIO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_sw_out`] module"]
1386 #[doc(alias = "GPIO_SW_OUT")]
1387 pub type GpioSwOut = crate::Reg<gpio_sw_out::GpioSwOutSpec>;
1388 #[doc = "GPIO data register"]
1389 pub mod gpio_sw_out {
1390 #[doc = "Register `GPIO_SW_OUT` reader"]
1391 pub type R = crate::R<GpioSwOutSpec>;
1392 #[doc = "Register `GPIO_SW_OUT` writer"]
1393 pub type W = crate::W<GpioSwOutSpec>;
1394 #[doc = "Field `gpio_sw_out` reader - GPIO data. Output: written value drives I/O; Input: reads external port"]
1395 pub type GpioSwOutR = crate::FieldReader;
1396 #[doc = "Field `gpio_sw_out` writer - GPIO data. Output: written value drives I/O; Input: reads external port"]
1397 pub type GpioSwOutW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
1398 impl R {
1399 #[doc = "Bits 0:7 - GPIO data. Output: written value drives I/O; Input: reads external port"]
1400 #[inline(always)]
1401 pub fn gpio_sw_out(&self) -> GpioSwOutR {
1402 GpioSwOutR::new((self.bits & 0xff) as u8)
1403 }
1404 }
1405 impl W {
1406 #[doc = "Bits 0:7 - GPIO data. Output: written value drives I/O; Input: reads external port"]
1407 #[inline(always)]
1408 pub fn gpio_sw_out(&mut self) -> GpioSwOutW<'_, GpioSwOutSpec> {
1409 GpioSwOutW::new(self, 0)
1410 }
1411 }
1412 #[doc = "GPIO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1413 pub struct GpioSwOutSpec;
1414 impl crate::RegisterSpec for GpioSwOutSpec {
1415 type Ux = u32;
1416 }
1417 #[doc = "`read()` method returns [`gpio_sw_out::R`](R) reader structure"]
1418 impl crate::Readable for GpioSwOutSpec {}
1419 #[doc = "`write(|w| ..)` method takes [`gpio_sw_out::W`](W) writer structure"]
1420 impl crate::Writable for GpioSwOutSpec {
1421 type Safety = crate::Unsafe;
1422 }
1423 #[doc = "`reset()` method sets GPIO_SW_OUT to value 0"]
1424 impl crate::Resettable for GpioSwOutSpec {}
1425 }
1426 #[doc = "GPIO_SW_OEN (rw) register accessor: GPIO data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_oen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_oen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_sw_oen`] module"]
1427 #[doc(alias = "GPIO_SW_OEN")]
1428 pub type GpioSwOen = crate::Reg<gpio_sw_oen::GpioSwOenSpec>;
1429 #[doc = "GPIO data direction register"]
1430 pub mod gpio_sw_oen {
1431 #[doc = "Register `GPIO_SW_OEN` reader"]
1432 pub type R = crate::R<GpioSwOenSpec>;
1433 #[doc = "Register `GPIO_SW_OEN` writer"]
1434 pub type W = crate::W<GpioSwOenSpec>;
1435 #[doc = "GPIO direction: 0=output; 1=input (default)\n\nValue on reset: 255"]
1436 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1437 #[repr(u8)]
1438 pub enum GpioSwOen {
1439 #[doc = "0: Output direction"]
1440 Output = 0,
1441 #[doc = "1: Input direction"]
1442 Input = 1,
1443 }
1444 impl From<GpioSwOen> for u8 {
1445 #[inline(always)]
1446 fn from(variant: GpioSwOen) -> Self {
1447 variant as _
1448 }
1449 }
1450 impl crate::FieldSpec for GpioSwOen {
1451 type Ux = u8;
1452 }
1453 impl crate::IsEnum for GpioSwOen {}
1454 #[doc = "Field `gpio_sw_oen` reader - GPIO direction: 0=output; 1=input (default)"]
1455 pub type GpioSwOenR = crate::FieldReader<GpioSwOen>;
1456 impl GpioSwOenR {
1457 #[doc = "Get enumerated values variant"]
1458 #[inline(always)]
1459 pub const fn variant(&self) -> Option<GpioSwOen> {
1460 match self.bits {
1461 0 => Some(GpioSwOen::Output),
1462 1 => Some(GpioSwOen::Input),
1463 _ => None,
1464 }
1465 }
1466 #[doc = "Output direction"]
1467 #[inline(always)]
1468 pub fn is_output(&self) -> bool {
1469 *self == GpioSwOen::Output
1470 }
1471 #[doc = "Input direction"]
1472 #[inline(always)]
1473 pub fn is_input(&self) -> bool {
1474 *self == GpioSwOen::Input
1475 }
1476 }
1477 #[doc = "Field `gpio_sw_oen` writer - GPIO direction: 0=output; 1=input (default)"]
1478 pub type GpioSwOenW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioSwOen>;
1479 impl<'a, REG> GpioSwOenW<'a, REG>
1480 where
1481 REG: crate::Writable + crate::RegisterSpec,
1482 REG::Ux: From<u8>,
1483 {
1484 #[doc = "Output direction"]
1485 #[inline(always)]
1486 pub fn output(self) -> &'a mut crate::W<REG> {
1487 self.variant(GpioSwOen::Output)
1488 }
1489 #[doc = "Input direction"]
1490 #[inline(always)]
1491 pub fn input(self) -> &'a mut crate::W<REG> {
1492 self.variant(GpioSwOen::Input)
1493 }
1494 }
1495 impl R {
1496 #[doc = "Bits 0:7 - GPIO direction: 0=output; 1=input (default)"]
1497 #[inline(always)]
1498 pub fn gpio_sw_oen(&self) -> GpioSwOenR {
1499 GpioSwOenR::new((self.bits & 0xff) as u8)
1500 }
1501 }
1502 impl W {
1503 #[doc = "Bits 0:7 - GPIO direction: 0=output; 1=input (default)"]
1504 #[inline(always)]
1505 pub fn gpio_sw_oen(&mut self) -> GpioSwOenW<'_, GpioSwOenSpec> {
1506 GpioSwOenW::new(self, 0)
1507 }
1508 }
1509 #[doc = "GPIO data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_oen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_oen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1510 pub struct GpioSwOenSpec;
1511 impl crate::RegisterSpec for GpioSwOenSpec {
1512 type Ux = u32;
1513 }
1514 #[doc = "`read()` method returns [`gpio_sw_oen::R`](R) reader structure"]
1515 impl crate::Readable for GpioSwOenSpec {}
1516 #[doc = "`write(|w| ..)` method takes [`gpio_sw_oen::W`](W) writer structure"]
1517 impl crate::Writable for GpioSwOenSpec {
1518 type Safety = crate::Unsafe;
1519 }
1520 #[doc = "`reset()` method sets GPIO_SW_OEN to value 0xff"]
1521 impl crate::Resettable for GpioSwOenSpec {
1522 const RESET_VALUE: u32 = 0xff;
1523 }
1524 }
1525 #[doc = "GPIO_INT_EN (rw) register accessor: GPIO interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_en`] module"]
1526 #[doc(alias = "GPIO_INT_EN")]
1527 pub type GpioIntEn = crate::Reg<gpio_int_en::GpioIntEnSpec>;
1528 #[doc = "GPIO interrupt enable register"]
1529 pub mod gpio_int_en {
1530 #[doc = "Register `GPIO_INT_EN` reader"]
1531 pub type R = crate::R<GpioIntEnSpec>;
1532 #[doc = "Register `GPIO_INT_EN` writer"]
1533 pub type W = crate::W<GpioIntEnSpec>;
1534 #[doc = "Field `gpio_int_en` reader - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
1535 pub type GpioIntEnR = crate::FieldReader;
1536 #[doc = "Field `gpio_int_en` writer - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
1537 pub type GpioIntEnW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
1538 impl R {
1539 #[doc = "Bits 0:7 - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
1540 #[inline(always)]
1541 pub fn gpio_int_en(&self) -> GpioIntEnR {
1542 GpioIntEnR::new((self.bits & 0xff) as u8)
1543 }
1544 }
1545 impl W {
1546 #[doc = "Bits 0:7 - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
1547 #[inline(always)]
1548 pub fn gpio_int_en(&mut self) -> GpioIntEnW<'_, GpioIntEnSpec> {
1549 GpioIntEnW::new(self, 0)
1550 }
1551 }
1552 #[doc = "GPIO interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1553 pub struct GpioIntEnSpec;
1554 impl crate::RegisterSpec for GpioIntEnSpec {
1555 type Ux = u32;
1556 }
1557 #[doc = "`read()` method returns [`gpio_int_en::R`](R) reader structure"]
1558 impl crate::Readable for GpioIntEnSpec {}
1559 #[doc = "`write(|w| ..)` method takes [`gpio_int_en::W`](W) writer structure"]
1560 impl crate::Writable for GpioIntEnSpec {
1561 type Safety = crate::Unsafe;
1562 }
1563 #[doc = "`reset()` method sets GPIO_INT_EN to value 0"]
1564 impl crate::Resettable for GpioIntEnSpec {}
1565 }
1566 #[doc = "GPIO_INT_MASK (rw) register accessor: GPIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_mask`] module"]
1567 #[doc(alias = "GPIO_INT_MASK")]
1568 pub type GpioIntMask = crate::Reg<gpio_int_mask::GpioIntMaskSpec>;
1569 #[doc = "GPIO interrupt mask register"]
1570 pub mod gpio_int_mask {
1571 #[doc = "Register `GPIO_INT_MASK` reader"]
1572 pub type R = crate::R<GpioIntMaskSpec>;
1573 #[doc = "Register `GPIO_INT_MASK` writer"]
1574 pub type W = crate::W<GpioIntMaskSpec>;
1575 #[doc = "Field `gpio_int_mask` reader - Interrupt mask: 0=not masked; 1=masked"]
1576 pub type GpioIntMaskR = crate::FieldReader;
1577 #[doc = "Field `gpio_int_mask` writer - Interrupt mask: 0=not masked; 1=masked"]
1578 pub type GpioIntMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
1579 impl R {
1580 #[doc = "Bits 0:7 - Interrupt mask: 0=not masked; 1=masked"]
1581 #[inline(always)]
1582 pub fn gpio_int_mask(&self) -> GpioIntMaskR {
1583 GpioIntMaskR::new((self.bits & 0xff) as u8)
1584 }
1585 }
1586 impl W {
1587 #[doc = "Bits 0:7 - Interrupt mask: 0=not masked; 1=masked"]
1588 #[inline(always)]
1589 pub fn gpio_int_mask(&mut self) -> GpioIntMaskW<'_, GpioIntMaskSpec> {
1590 GpioIntMaskW::new(self, 0)
1591 }
1592 }
1593 #[doc = "GPIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1594 pub struct GpioIntMaskSpec;
1595 impl crate::RegisterSpec for GpioIntMaskSpec {
1596 type Ux = u32;
1597 }
1598 #[doc = "`read()` method returns [`gpio_int_mask::R`](R) reader structure"]
1599 impl crate::Readable for GpioIntMaskSpec {}
1600 #[doc = "`write(|w| ..)` method takes [`gpio_int_mask::W`](W) writer structure"]
1601 impl crate::Writable for GpioIntMaskSpec {
1602 type Safety = crate::Unsafe;
1603 }
1604 #[doc = "`reset()` method sets GPIO_INT_MASK to value 0"]
1605 impl crate::Resettable for GpioIntMaskSpec {}
1606 }
1607 #[doc = "GPIO_INT_TYPE (rw) register accessor: GPIO interrupt type register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_type`] module"]
1608 #[doc(alias = "GPIO_INT_TYPE")]
1609 pub type GpioIntType = crate::Reg<gpio_int_type::GpioIntTypeSpec>;
1610 #[doc = "GPIO interrupt type register"]
1611 pub mod gpio_int_type {
1612 #[doc = "Register `GPIO_INT_TYPE` reader"]
1613 pub type R = crate::R<GpioIntTypeSpec>;
1614 #[doc = "Register `GPIO_INT_TYPE` writer"]
1615 pub type W = crate::W<GpioIntTypeSpec>;
1616 #[doc = "Interrupt type: 0=level; 1=edge\n\nValue on reset: 0"]
1617 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1618 #[repr(u8)]
1619 pub enum GpioIntType {
1620 #[doc = "0: Level-sensitive"]
1621 Level = 0,
1622 #[doc = "1: Edge-triggered"]
1623 Edge = 1,
1624 }
1625 impl From<GpioIntType> for u8 {
1626 #[inline(always)]
1627 fn from(variant: GpioIntType) -> Self {
1628 variant as _
1629 }
1630 }
1631 impl crate::FieldSpec for GpioIntType {
1632 type Ux = u8;
1633 }
1634 impl crate::IsEnum for GpioIntType {}
1635 #[doc = "Field `gpio_int_type` reader - Interrupt type: 0=level; 1=edge"]
1636 pub type GpioIntTypeR = crate::FieldReader<GpioIntType>;
1637 impl GpioIntTypeR {
1638 #[doc = "Get enumerated values variant"]
1639 #[inline(always)]
1640 pub const fn variant(&self) -> Option<GpioIntType> {
1641 match self.bits {
1642 0 => Some(GpioIntType::Level),
1643 1 => Some(GpioIntType::Edge),
1644 _ => None,
1645 }
1646 }
1647 #[doc = "Level-sensitive"]
1648 #[inline(always)]
1649 pub fn is_level(&self) -> bool {
1650 *self == GpioIntType::Level
1651 }
1652 #[doc = "Edge-triggered"]
1653 #[inline(always)]
1654 pub fn is_edge(&self) -> bool {
1655 *self == GpioIntType::Edge
1656 }
1657 }
1658 #[doc = "Field `gpio_int_type` writer - Interrupt type: 0=level; 1=edge"]
1659 pub type GpioIntTypeW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioIntType>;
1660 impl<'a, REG> GpioIntTypeW<'a, REG>
1661 where
1662 REG: crate::Writable + crate::RegisterSpec,
1663 REG::Ux: From<u8>,
1664 {
1665 #[doc = "Level-sensitive"]
1666 #[inline(always)]
1667 pub fn level(self) -> &'a mut crate::W<REG> {
1668 self.variant(GpioIntType::Level)
1669 }
1670 #[doc = "Edge-triggered"]
1671 #[inline(always)]
1672 pub fn edge(self) -> &'a mut crate::W<REG> {
1673 self.variant(GpioIntType::Edge)
1674 }
1675 }
1676 impl R {
1677 #[doc = "Bits 0:7 - Interrupt type: 0=level; 1=edge"]
1678 #[inline(always)]
1679 pub fn gpio_int_type(&self) -> GpioIntTypeR {
1680 GpioIntTypeR::new((self.bits & 0xff) as u8)
1681 }
1682 }
1683 impl W {
1684 #[doc = "Bits 0:7 - Interrupt type: 0=level; 1=edge"]
1685 #[inline(always)]
1686 pub fn gpio_int_type(&mut self) -> GpioIntTypeW<'_, GpioIntTypeSpec> {
1687 GpioIntTypeW::new(self, 0)
1688 }
1689 }
1690 #[doc = "GPIO interrupt type register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1691 pub struct GpioIntTypeSpec;
1692 impl crate::RegisterSpec for GpioIntTypeSpec {
1693 type Ux = u32;
1694 }
1695 #[doc = "`read()` method returns [`gpio_int_type::R`](R) reader structure"]
1696 impl crate::Readable for GpioIntTypeSpec {}
1697 #[doc = "`write(|w| ..)` method takes [`gpio_int_type::W`](W) writer structure"]
1698 impl crate::Writable for GpioIntTypeSpec {
1699 type Safety = crate::Unsafe;
1700 }
1701 #[doc = "`reset()` method sets GPIO_INT_TYPE to value 0"]
1702 impl crate::Resettable for GpioIntTypeSpec {}
1703 }
1704 #[doc = "GPIO_INT_POLARITY (rw) register accessor: GPIO interrupt polarity register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_polarity::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_polarity::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_polarity`] module"]
1705 #[doc(alias = "GPIO_INT_POLARITY")]
1706 pub type GpioIntPolarity = crate::Reg<gpio_int_polarity::GpioIntPolaritySpec>;
1707 #[doc = "GPIO interrupt polarity register"]
1708 pub mod gpio_int_polarity {
1709 #[doc = "Register `GPIO_INT_POLARITY` reader"]
1710 pub type R = crate::R<GpioIntPolaritySpec>;
1711 #[doc = "Register `GPIO_INT_POLARITY` writer"]
1712 pub type W = crate::W<GpioIntPolaritySpec>;
1713 #[doc = "Interrupt polarity: 0=low/falling; 1=high/rising\n\nValue on reset: 0"]
1714 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1715 #[repr(u8)]
1716 pub enum GpioIntPolarity {
1717 #[doc = "0: Low level or falling edge"]
1718 LowFalling = 0,
1719 #[doc = "1: High level or rising edge"]
1720 HighRising = 1,
1721 }
1722 impl From<GpioIntPolarity> for u8 {
1723 #[inline(always)]
1724 fn from(variant: GpioIntPolarity) -> Self {
1725 variant as _
1726 }
1727 }
1728 impl crate::FieldSpec for GpioIntPolarity {
1729 type Ux = u8;
1730 }
1731 impl crate::IsEnum for GpioIntPolarity {}
1732 #[doc = "Field `gpio_int_polarity` reader - Interrupt polarity: 0=low/falling; 1=high/rising"]
1733 pub type GpioIntPolarityR = crate::FieldReader<GpioIntPolarity>;
1734 impl GpioIntPolarityR {
1735 #[doc = "Get enumerated values variant"]
1736 #[inline(always)]
1737 pub const fn variant(&self) -> Option<GpioIntPolarity> {
1738 match self.bits {
1739 0 => Some(GpioIntPolarity::LowFalling),
1740 1 => Some(GpioIntPolarity::HighRising),
1741 _ => None,
1742 }
1743 }
1744 #[doc = "Low level or falling edge"]
1745 #[inline(always)]
1746 pub fn is_low_falling(&self) -> bool {
1747 *self == GpioIntPolarity::LowFalling
1748 }
1749 #[doc = "High level or rising edge"]
1750 #[inline(always)]
1751 pub fn is_high_rising(&self) -> bool {
1752 *self == GpioIntPolarity::HighRising
1753 }
1754 }
1755 #[doc = "Field `gpio_int_polarity` writer - Interrupt polarity: 0=low/falling; 1=high/rising"]
1756 pub type GpioIntPolarityW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioIntPolarity>;
1757 impl<'a, REG> GpioIntPolarityW<'a, REG>
1758 where
1759 REG: crate::Writable + crate::RegisterSpec,
1760 REG::Ux: From<u8>,
1761 {
1762 #[doc = "Low level or falling edge"]
1763 #[inline(always)]
1764 pub fn low_falling(self) -> &'a mut crate::W<REG> {
1765 self.variant(GpioIntPolarity::LowFalling)
1766 }
1767 #[doc = "High level or rising edge"]
1768 #[inline(always)]
1769 pub fn high_rising(self) -> &'a mut crate::W<REG> {
1770 self.variant(GpioIntPolarity::HighRising)
1771 }
1772 }
1773 impl R {
1774 #[doc = "Bits 0:7 - Interrupt polarity: 0=low/falling; 1=high/rising"]
1775 #[inline(always)]
1776 pub fn gpio_int_polarity(&self) -> GpioIntPolarityR {
1777 GpioIntPolarityR::new((self.bits & 0xff) as u8)
1778 }
1779 }
1780 impl W {
1781 #[doc = "Bits 0:7 - Interrupt polarity: 0=low/falling; 1=high/rising"]
1782 #[inline(always)]
1783 pub fn gpio_int_polarity(&mut self) -> GpioIntPolarityW<'_, GpioIntPolaritySpec> {
1784 GpioIntPolarityW::new(self, 0)
1785 }
1786 }
1787 #[doc = "GPIO interrupt polarity register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_polarity::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_polarity::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1788 pub struct GpioIntPolaritySpec;
1789 impl crate::RegisterSpec for GpioIntPolaritySpec {
1790 type Ux = u32;
1791 }
1792 #[doc = "`read()` method returns [`gpio_int_polarity::R`](R) reader structure"]
1793 impl crate::Readable for GpioIntPolaritySpec {}
1794 #[doc = "`write(|w| ..)` method takes [`gpio_int_polarity::W`](W) writer structure"]
1795 impl crate::Writable for GpioIntPolaritySpec {
1796 type Safety = crate::Unsafe;
1797 }
1798 #[doc = "`reset()` method sets GPIO_INT_POLARITY to value 0"]
1799 impl crate::Resettable for GpioIntPolaritySpec {}
1800 }
1801 #[doc = "GPIO_INT_DEDGE (rw) register accessor: GPIO dual-edge interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_dedge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_dedge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_dedge`] module"]
1802 #[doc(alias = "GPIO_INT_DEDGE")]
1803 pub type GpioIntDedge = crate::Reg<gpio_int_dedge::GpioIntDedgeSpec>;
1804 #[doc = "GPIO dual-edge interrupt enable register"]
1805 pub mod gpio_int_dedge {
1806 #[doc = "Register `GPIO_INT_DEDGE` reader"]
1807 pub type R = crate::R<GpioIntDedgeSpec>;
1808 #[doc = "Register `GPIO_INT_DEDGE` writer"]
1809 pub type W = crate::W<GpioIntDedgeSpec>;
1810 #[doc = "Dual-edge interrupt enable: 0=disabled; 1=enabled\n\nValue on reset: 0"]
1811 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1812 #[repr(u8)]
1813 pub enum GpioIntDedge {
1814 #[doc = "0: Single-edge mode"]
1815 Disabled = 0,
1816 #[doc = "1: Dual-edge triggered"]
1817 Enabled = 1,
1818 }
1819 impl From<GpioIntDedge> for u8 {
1820 #[inline(always)]
1821 fn from(variant: GpioIntDedge) -> Self {
1822 variant as _
1823 }
1824 }
1825 impl crate::FieldSpec for GpioIntDedge {
1826 type Ux = u8;
1827 }
1828 impl crate::IsEnum for GpioIntDedge {}
1829 #[doc = "Field `gpio_int_dedge` reader - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
1830 pub type GpioIntDedgeR = crate::FieldReader<GpioIntDedge>;
1831 impl GpioIntDedgeR {
1832 #[doc = "Get enumerated values variant"]
1833 #[inline(always)]
1834 pub const fn variant(&self) -> Option<GpioIntDedge> {
1835 match self.bits {
1836 0 => Some(GpioIntDedge::Disabled),
1837 1 => Some(GpioIntDedge::Enabled),
1838 _ => None,
1839 }
1840 }
1841 #[doc = "Single-edge mode"]
1842 #[inline(always)]
1843 pub fn is_disabled(&self) -> bool {
1844 *self == GpioIntDedge::Disabled
1845 }
1846 #[doc = "Dual-edge triggered"]
1847 #[inline(always)]
1848 pub fn is_enabled(&self) -> bool {
1849 *self == GpioIntDedge::Enabled
1850 }
1851 }
1852 #[doc = "Field `gpio_int_dedge` writer - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
1853 pub type GpioIntDedgeW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioIntDedge>;
1854 impl<'a, REG> GpioIntDedgeW<'a, REG>
1855 where
1856 REG: crate::Writable + crate::RegisterSpec,
1857 REG::Ux: From<u8>,
1858 {
1859 #[doc = "Single-edge mode"]
1860 #[inline(always)]
1861 pub fn disabled(self) -> &'a mut crate::W<REG> {
1862 self.variant(GpioIntDedge::Disabled)
1863 }
1864 #[doc = "Dual-edge triggered"]
1865 #[inline(always)]
1866 pub fn enabled(self) -> &'a mut crate::W<REG> {
1867 self.variant(GpioIntDedge::Enabled)
1868 }
1869 }
1870 impl R {
1871 #[doc = "Bits 0:7 - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
1872 #[inline(always)]
1873 pub fn gpio_int_dedge(&self) -> GpioIntDedgeR {
1874 GpioIntDedgeR::new((self.bits & 0xff) as u8)
1875 }
1876 }
1877 impl W {
1878 #[doc = "Bits 0:7 - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
1879 #[inline(always)]
1880 pub fn gpio_int_dedge(&mut self) -> GpioIntDedgeW<'_, GpioIntDedgeSpec> {
1881 GpioIntDedgeW::new(self, 0)
1882 }
1883 }
1884 #[doc = "GPIO dual-edge interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_dedge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_dedge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1885 pub struct GpioIntDedgeSpec;
1886 impl crate::RegisterSpec for GpioIntDedgeSpec {
1887 type Ux = u32;
1888 }
1889 #[doc = "`read()` method returns [`gpio_int_dedge::R`](R) reader structure"]
1890 impl crate::Readable for GpioIntDedgeSpec {}
1891 #[doc = "`write(|w| ..)` method takes [`gpio_int_dedge::W`](W) writer structure"]
1892 impl crate::Writable for GpioIntDedgeSpec {
1893 type Safety = crate::Unsafe;
1894 }
1895 #[doc = "`reset()` method sets GPIO_INT_DEDGE to value 0"]
1896 impl crate::Resettable for GpioIntDedgeSpec {}
1897 }
1898 #[doc = "GPIO_INT_DEBOUNCE (rw) register accessor: GPIO interrupt debounce control register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_debounce::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_debounce::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_debounce`] module"]
1899 #[doc(alias = "GPIO_INT_DEBOUNCE")]
1900 pub type GpioIntDebounce = crate::Reg<gpio_int_debounce::GpioIntDebounceSpec>;
1901 #[doc = "GPIO interrupt debounce control register"]
1902 pub mod gpio_int_debounce {
1903 #[doc = "Register `GPIO_INT_DEBOUNCE` reader"]
1904 pub type R = crate::R<GpioIntDebounceSpec>;
1905 #[doc = "Register `GPIO_INT_DEBOUNCE` writer"]
1906 pub type W = crate::W<GpioIntDebounceSpec>;
1907 #[doc = "Field `gpio_int_debounce` reader - Debounce enable: 0=disabled; 1=enabled"]
1908 pub type GpioIntDebounceR = crate::FieldReader;
1909 #[doc = "Field `gpio_int_debounce` writer - Debounce enable: 0=disabled; 1=enabled"]
1910 pub type GpioIntDebounceW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
1911 impl R {
1912 #[doc = "Bits 0:7 - Debounce enable: 0=disabled; 1=enabled"]
1913 #[inline(always)]
1914 pub fn gpio_int_debounce(&self) -> GpioIntDebounceR {
1915 GpioIntDebounceR::new((self.bits & 0xff) as u8)
1916 }
1917 }
1918 impl W {
1919 #[doc = "Bits 0:7 - Debounce enable: 0=disabled; 1=enabled"]
1920 #[inline(always)]
1921 pub fn gpio_int_debounce(&mut self) -> GpioIntDebounceW<'_, GpioIntDebounceSpec> {
1922 GpioIntDebounceW::new(self, 0)
1923 }
1924 }
1925 #[doc = "GPIO interrupt debounce control register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_debounce::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_debounce::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1926 pub struct GpioIntDebounceSpec;
1927 impl crate::RegisterSpec for GpioIntDebounceSpec {
1928 type Ux = u32;
1929 }
1930 #[doc = "`read()` method returns [`gpio_int_debounce::R`](R) reader structure"]
1931 impl crate::Readable for GpioIntDebounceSpec {}
1932 #[doc = "`write(|w| ..)` method takes [`gpio_int_debounce::W`](W) writer structure"]
1933 impl crate::Writable for GpioIntDebounceSpec {
1934 type Safety = crate::Unsafe;
1935 }
1936 #[doc = "`reset()` method sets GPIO_INT_DEBOUNCE to value 0"]
1937 impl crate::Resettable for GpioIntDebounceSpec {}
1938 }
1939 #[doc = "GPIO_INT_RAW (rw) register accessor: GPIO raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_raw`] module"]
1940 #[doc(alias = "GPIO_INT_RAW")]
1941 pub type GpioIntRaw = crate::Reg<gpio_int_raw::GpioIntRawSpec>;
1942 #[doc = "GPIO raw interrupt status register"]
1943 pub mod gpio_int_raw {
1944 #[doc = "Register `GPIO_INT_RAW` reader"]
1945 pub type R = crate::R<GpioIntRawSpec>;
1946 #[doc = "Register `GPIO_INT_RAW` writer"]
1947 pub type W = crate::W<GpioIntRawSpec>;
1948 #[doc = "Field `gpio_int_raw` reader - Raw interrupt status (before mask): 0=no interrupt; 1=interrupt"]
1949 pub type GpioIntRawR = crate::FieldReader;
1950 impl R {
1951 #[doc = "Bits 0:7 - Raw interrupt status (before mask): 0=no interrupt; 1=interrupt"]
1952 #[inline(always)]
1953 pub fn gpio_int_raw(&self) -> GpioIntRawR {
1954 GpioIntRawR::new((self.bits & 0xff) as u8)
1955 }
1956 }
1957 impl W {}
1958 #[doc = "GPIO raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1959 pub struct GpioIntRawSpec;
1960 impl crate::RegisterSpec for GpioIntRawSpec {
1961 type Ux = u32;
1962 }
1963 #[doc = "`read()` method returns [`gpio_int_raw::R`](R) reader structure"]
1964 impl crate::Readable for GpioIntRawSpec {}
1965 #[doc = "`write(|w| ..)` method takes [`gpio_int_raw::W`](W) writer structure"]
1966 impl crate::Writable for GpioIntRawSpec {
1967 type Safety = crate::Unsafe;
1968 }
1969 #[doc = "`reset()` method sets GPIO_INT_RAW to value 0"]
1970 impl crate::Resettable for GpioIntRawSpec {}
1971 }
1972 #[doc = "GPIO_INTR (rw) register accessor: GPIO interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_intr`] module"]
1973 #[doc(alias = "GPIO_INTR")]
1974 pub type GpioIntr = crate::Reg<gpio_intr::GpioIntrSpec>;
1975 #[doc = "GPIO interrupt status register"]
1976 pub mod gpio_intr {
1977 #[doc = "Register `GPIO_INTR` reader"]
1978 pub type R = crate::R<GpioIntrSpec>;
1979 #[doc = "Register `GPIO_INTR` writer"]
1980 pub type W = crate::W<GpioIntrSpec>;
1981 #[doc = "Field `gpio_intr` reader - Interrupt status (after mask): 0=no interrupt; 1=interrupt"]
1982 pub type GpioIntrR = crate::FieldReader;
1983 impl R {
1984 #[doc = "Bits 0:7 - Interrupt status (after mask): 0=no interrupt; 1=interrupt"]
1985 #[inline(always)]
1986 pub fn gpio_intr(&self) -> GpioIntrR {
1987 GpioIntrR::new((self.bits & 0xff) as u8)
1988 }
1989 }
1990 impl W {}
1991 #[doc = "GPIO interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1992 pub struct GpioIntrSpec;
1993 impl crate::RegisterSpec for GpioIntrSpec {
1994 type Ux = u32;
1995 }
1996 #[doc = "`read()` method returns [`gpio_intr::R`](R) reader structure"]
1997 impl crate::Readable for GpioIntrSpec {}
1998 #[doc = "`write(|w| ..)` method takes [`gpio_intr::W`](W) writer structure"]
1999 impl crate::Writable for GpioIntrSpec {
2000 type Safety = crate::Unsafe;
2001 }
2002 #[doc = "`reset()` method sets GPIO_INTR to value 0"]
2003 impl crate::Resettable for GpioIntrSpec {}
2004 }
2005 #[doc = "GPIO_INT_EOI (rw) register accessor: GPIO interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_eoi`] module"]
2006 #[doc(alias = "GPIO_INT_EOI")]
2007 pub type GpioIntEoi = crate::Reg<gpio_int_eoi::GpioIntEoiSpec>;
2008 #[doc = "GPIO interrupt clear register"]
2009 pub mod gpio_int_eoi {
2010 #[doc = "Register `GPIO_INT_EOI` reader"]
2011 pub type R = crate::R<GpioIntEoiSpec>;
2012 #[doc = "Register `GPIO_INT_EOI` writer"]
2013 pub type W = crate::W<GpioIntEoiSpec>;
2014 #[doc = "Field `gpio_int_eoi` writer - Edge interrupt clear: 0=no clear; 1=clear interrupt"]
2015 pub type GpioIntEoiW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
2016 impl W {
2017 #[doc = "Bits 0:7 - Edge interrupt clear: 0=no clear; 1=clear interrupt"]
2018 #[inline(always)]
2019 pub fn gpio_int_eoi(&mut self) -> GpioIntEoiW<'_, GpioIntEoiSpec> {
2020 GpioIntEoiW::new(self, 0)
2021 }
2022 }
2023 #[doc = "GPIO interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2024 pub struct GpioIntEoiSpec;
2025 impl crate::RegisterSpec for GpioIntEoiSpec {
2026 type Ux = u32;
2027 }
2028 #[doc = "`read()` method returns [`gpio_int_eoi::R`](R) reader structure"]
2029 impl crate::Readable for GpioIntEoiSpec {}
2030 #[doc = "`write(|w| ..)` method takes [`gpio_int_eoi::W`](W) writer structure"]
2031 impl crate::Writable for GpioIntEoiSpec {
2032 type Safety = crate::Unsafe;
2033 }
2034 #[doc = "`reset()` method sets GPIO_INT_EOI to value 0"]
2035 impl crate::Resettable for GpioIntEoiSpec {}
2036 }
2037 #[doc = "GPIO_DATA_SET (rw) register accessor: GPIO data set register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_data_set`] module"]
2038 #[doc(alias = "GPIO_DATA_SET")]
2039 pub type GpioDataSet = crate::Reg<gpio_data_set::GpioDataSetSpec>;
2040 #[doc = "GPIO data set register"]
2041 pub mod gpio_data_set {
2042 #[doc = "Register `GPIO_DATA_SET` reader"]
2043 pub type R = crate::R<GpioDataSetSpec>;
2044 #[doc = "Register `GPIO_DATA_SET` writer"]
2045 pub type W = crate::W<GpioDataSetSpec>;
2046 #[doc = "Field `gpio_data_set` writer - Write 1 to set corresponding GPIO_SW_OUT bits"]
2047 pub type GpioDataSetW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
2048 impl W {
2049 #[doc = "Bits 0:7 - Write 1 to set corresponding GPIO_SW_OUT bits"]
2050 #[inline(always)]
2051 pub fn gpio_data_set(&mut self) -> GpioDataSetW<'_, GpioDataSetSpec> {
2052 GpioDataSetW::new(self, 0)
2053 }
2054 }
2055 #[doc = "GPIO data set register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2056 pub struct GpioDataSetSpec;
2057 impl crate::RegisterSpec for GpioDataSetSpec {
2058 type Ux = u32;
2059 }
2060 #[doc = "`read()` method returns [`gpio_data_set::R`](R) reader structure"]
2061 impl crate::Readable for GpioDataSetSpec {}
2062 #[doc = "`write(|w| ..)` method takes [`gpio_data_set::W`](W) writer structure"]
2063 impl crate::Writable for GpioDataSetSpec {
2064 type Safety = crate::Unsafe;
2065 }
2066 #[doc = "`reset()` method sets GPIO_DATA_SET to value 0"]
2067 impl crate::Resettable for GpioDataSetSpec {}
2068 }
2069 #[doc = "GPIO_DATA_CLR (rw) register accessor: GPIO data clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_data_clr`] module"]
2070 #[doc(alias = "GPIO_DATA_CLR")]
2071 pub type GpioDataClr = crate::Reg<gpio_data_clr::GpioDataClrSpec>;
2072 #[doc = "GPIO data clear register"]
2073 pub mod gpio_data_clr {
2074 #[doc = "Register `GPIO_DATA_CLR` reader"]
2075 pub type R = crate::R<GpioDataClrSpec>;
2076 #[doc = "Register `GPIO_DATA_CLR` writer"]
2077 pub type W = crate::W<GpioDataClrSpec>;
2078 #[doc = "Field `gpio_data_clr` writer - Write 1 to clear corresponding GPIO_SW_OUT bits"]
2079 pub type GpioDataClrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
2080 impl W {
2081 #[doc = "Bits 0:7 - Write 1 to clear corresponding GPIO_SW_OUT bits"]
2082 #[inline(always)]
2083 pub fn gpio_data_clr(&mut self) -> GpioDataClrW<'_, GpioDataClrSpec> {
2084 GpioDataClrW::new(self, 0)
2085 }
2086 }
2087 #[doc = "GPIO data clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2088 pub struct GpioDataClrSpec;
2089 impl crate::RegisterSpec for GpioDataClrSpec {
2090 type Ux = u32;
2091 }
2092 #[doc = "`read()` method returns [`gpio_data_clr::R`](R) reader structure"]
2093 impl crate::Readable for GpioDataClrSpec {}
2094 #[doc = "`write(|w| ..)` method takes [`gpio_data_clr::W`](W) writer structure"]
2095 impl crate::Writable for GpioDataClrSpec {
2096 type Safety = crate::Unsafe;
2097 }
2098 #[doc = "`reset()` method sets GPIO_DATA_CLR to value 0"]
2099 impl crate::Resettable for GpioDataClrSpec {}
2100 }
2101}
2102#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
2103pub type Uart0 = crate::Periph<uart0::RegisterBlock, 0x5208_1000>;
2104impl core::fmt::Debug for Uart0 {
2105 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
2106 f.debug_struct("Uart0").finish()
2107 }
2108}
2109#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
2110pub mod uart0 {
2111 #[repr(C)]
2112 #[doc = "Register block"]
2113 pub struct RegisterBlock {
2114 intr_id: IntrId,
2115 _reserved1: [u8; 0x02],
2116 data: Data,
2117 _reserved2: [u8; 0x02],
2118 uart_ctl: UartCtl,
2119 _reserved3: [u8; 0x02],
2120 div_h: DivH,
2121 _reserved4: [u8; 0x02],
2122 div_l: DivL,
2123 _reserved5: [u8; 0x02],
2124 div_fra: DivFra,
2125 _reserved6: [u8; 0x02],
2126 intr_en: IntrEn,
2127 _reserved7: [u8; 0x02],
2128 intr_status: IntrStatus,
2129 _reserved8: [u8; 0x06],
2130 fifo_ctl: FifoCtl,
2131 _reserved9: [u8; 0x02],
2132 far: Far,
2133 _reserved10: [u8; 0x02],
2134 modem_ctl: ModemCtl,
2135 _reserved11: [u8; 0x02],
2136 modem_status: ModemStatus,
2137 _reserved12: [u8; 0x02],
2138 line_status: LineStatus,
2139 _reserved13: [u8; 0x02],
2140 uart_gp_reg: UartGpReg,
2141 _reserved14: [u8; 0x02],
2142 tx_fifo_read: TxFifoRead,
2143 _reserved15: [u8; 0x02],
2144 rx_fifo_write: RxFifoWrite,
2145 _reserved16: [u8; 0x02],
2146 fifo_status: FifoStatus,
2147 _reserved17: [u8; 0x02],
2148 tx_fifo_cnt: TxFifoCnt,
2149 _reserved18: [u8; 0x02],
2150 rx_fifo_cnt: RxFifoCnt,
2151 _reserved19: [u8; 0x02],
2152 halt_tx: HaltTx,
2153 _reserved20: [u8; 0x02],
2154 dma_sw_ack: DmaSwAck,
2155 _reserved21: [u8; 0x02],
2156 baud_ctl: BaudCtl,
2157 _reserved22: [u8; 0x02],
2158 stp_ctl: StpCtl,
2159 _reserved23: [u8; 0x02],
2160 uart_parameter: UartParameter,
2161 }
2162 impl RegisterBlock {
2163 #[doc = "0x00 - Interrupt ID register"]
2164 #[inline(always)]
2165 pub const fn intr_id(&self) -> &IntrId {
2166 &self.intr_id
2167 }
2168 #[doc = "0x04 - Data register"]
2169 #[inline(always)]
2170 pub const fn data(&self) -> &Data {
2171 &self.data
2172 }
2173 #[doc = "0x08 - UART control register"]
2174 #[inline(always)]
2175 pub const fn uart_ctl(&self) -> &UartCtl {
2176 &self.uart_ctl
2177 }
2178 #[doc = "0x0c - Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
2179 #[inline(always)]
2180 pub const fn div_h(&self) -> &DivH {
2181 &self.div_h
2182 }
2183 #[doc = "0x10 - Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
2184 #[inline(always)]
2185 pub const fn div_l(&self) -> &DivL {
2186 &self.div_l
2187 }
2188 #[doc = "0x14 - Baud rate divider fractional part"]
2189 #[inline(always)]
2190 pub const fn div_fra(&self) -> &DivFra {
2191 &self.div_fra
2192 }
2193 #[doc = "0x18 - Interrupt enable register"]
2194 #[inline(always)]
2195 pub const fn intr_en(&self) -> &IntrEn {
2196 &self.intr_en
2197 }
2198 #[doc = "0x1c - Interrupt status register"]
2199 #[inline(always)]
2200 pub const fn intr_status(&self) -> &IntrStatus {
2201 &self.intr_status
2202 }
2203 #[doc = "0x24 - FIFO control register"]
2204 #[inline(always)]
2205 pub const fn fifo_ctl(&self) -> &FifoCtl {
2206 &self.fifo_ctl
2207 }
2208 #[doc = "0x28 - FIFO access mode enable register"]
2209 #[inline(always)]
2210 pub const fn far(&self) -> &Far {
2211 &self.far
2212 }
2213 #[doc = "0x2c - Modem control register"]
2214 #[inline(always)]
2215 pub const fn modem_ctl(&self) -> &ModemCtl {
2216 &self.modem_ctl
2217 }
2218 #[doc = "0x30 - Modem status register"]
2219 #[inline(always)]
2220 pub const fn modem_status(&self) -> &ModemStatus {
2221 &self.modem_status
2222 }
2223 #[doc = "0x34 - Line status register"]
2224 #[inline(always)]
2225 pub const fn line_status(&self) -> &LineStatus {
2226 &self.line_status
2227 }
2228 #[doc = "0x38 - UART general purpose register"]
2229 #[inline(always)]
2230 pub const fn uart_gp_reg(&self) -> &UartGpReg {
2231 &self.uart_gp_reg
2232 }
2233 #[doc = "0x3c - TX FIFO read register"]
2234 #[inline(always)]
2235 pub const fn tx_fifo_read(&self) -> &TxFifoRead {
2236 &self.tx_fifo_read
2237 }
2238 #[doc = "0x40 - RX FIFO write register"]
2239 #[inline(always)]
2240 pub const fn rx_fifo_write(&self) -> &RxFifoWrite {
2241 &self.rx_fifo_write
2242 }
2243 #[doc = "0x44 - FIFO status register"]
2244 #[inline(always)]
2245 pub const fn fifo_status(&self) -> &FifoStatus {
2246 &self.fifo_status
2247 }
2248 #[doc = "0x48 - TX FIFO data counter"]
2249 #[inline(always)]
2250 pub const fn tx_fifo_cnt(&self) -> &TxFifoCnt {
2251 &self.tx_fifo_cnt
2252 }
2253 #[doc = "0x4c - RX FIFO data counter"]
2254 #[inline(always)]
2255 pub const fn rx_fifo_cnt(&self) -> &RxFifoCnt {
2256 &self.rx_fifo_cnt
2257 }
2258 #[doc = "0x50 - TX halt register"]
2259 #[inline(always)]
2260 pub const fn halt_tx(&self) -> &HaltTx {
2261 &self.halt_tx
2262 }
2263 #[doc = "0x54 - DMA software acknowledge register"]
2264 #[inline(always)]
2265 pub const fn dma_sw_ack(&self) -> &DmaSwAck {
2266 &self.dma_sw_ack
2267 }
2268 #[doc = "0x58 - Baud rate control register"]
2269 #[inline(always)]
2270 pub const fn baud_ctl(&self) -> &BaudCtl {
2271 &self.baud_ctl
2272 }
2273 #[doc = "0x5c - Stop bit control register"]
2274 #[inline(always)]
2275 pub const fn stp_ctl(&self) -> &StpCtl {
2276 &self.stp_ctl
2277 }
2278 #[doc = "0x60 - UART parameter register"]
2279 #[inline(always)]
2280 pub const fn uart_parameter(&self) -> &UartParameter {
2281 &self.uart_parameter
2282 }
2283 }
2284 #[doc = "INTR_ID (rw) register accessor: Interrupt ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_id`] module"]
2285 #[doc(alias = "INTR_ID")]
2286 pub type IntrId = crate::Reg<intr_id::IntrIdSpec>;
2287 #[doc = "Interrupt ID register"]
2288 pub mod intr_id {
2289 #[doc = "Register `INTR_ID` reader"]
2290 pub type R = crate::R<IntrIdSpec>;
2291 #[doc = "Register `INTR_ID` writer"]
2292 pub type W = crate::W<IntrIdSpec>;
2293 #[doc = "Field `intr_id` reader - Interrupt ID: 0x0=modem status; 0x1=no interrupt; 0x2=THR empty; 0x4=rx data; 0x6=rx line status; 0x7=busy; 0xC=char timeout"]
2294 pub type IntrIdR = crate::FieldReader;
2295 #[doc = "Field `fifo_en_s` reader - FIFO enable status: 0=FIFO disabled; 1=FIFO enabled"]
2296 pub type FifoEnSR = crate::BitReader;
2297 impl R {
2298 #[doc = "Bits 0:3 - Interrupt ID: 0x0=modem status; 0x1=no interrupt; 0x2=THR empty; 0x4=rx data; 0x6=rx line status; 0x7=busy; 0xC=char timeout"]
2299 #[inline(always)]
2300 pub fn intr_id(&self) -> IntrIdR {
2301 IntrIdR::new((self.bits & 0x0f) as u8)
2302 }
2303 #[doc = "Bit 4 - FIFO enable status: 0=FIFO disabled; 1=FIFO enabled"]
2304 #[inline(always)]
2305 pub fn fifo_en_s(&self) -> FifoEnSR {
2306 FifoEnSR::new(((self.bits >> 4) & 1) != 0)
2307 }
2308 }
2309 impl W {}
2310 #[doc = "Interrupt ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2311 pub struct IntrIdSpec;
2312 impl crate::RegisterSpec for IntrIdSpec {
2313 type Ux = u16;
2314 }
2315 #[doc = "`read()` method returns [`intr_id::R`](R) reader structure"]
2316 impl crate::Readable for IntrIdSpec {}
2317 #[doc = "`write(|w| ..)` method takes [`intr_id::W`](W) writer structure"]
2318 impl crate::Writable for IntrIdSpec {
2319 type Safety = crate::Unsafe;
2320 }
2321 #[doc = "`reset()` method sets INTR_ID to value 0x01"]
2322 impl crate::Resettable for IntrIdSpec {
2323 const RESET_VALUE: u16 = 0x01;
2324 }
2325 }
2326 #[doc = "DATA (rw) register accessor: Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
2327 #[doc(alias = "DATA")]
2328 pub type Data = crate::Reg<data::DataSpec>;
2329 #[doc = "Data register"]
2330 pub mod data {
2331 #[doc = "Register `DATA` reader"]
2332 pub type R = crate::R<DataSpec>;
2333 #[doc = "Register `DATA` writer"]
2334 pub type W = crate::W<DataSpec>;
2335 #[doc = "Field `data` reader - Write: TX data; Read: RX data"]
2336 pub type DataR = crate::FieldReader;
2337 #[doc = "Field `data` writer - Write: TX data; Read: RX data"]
2338 pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
2339 impl R {
2340 #[doc = "Bits 0:7 - Write: TX data; Read: RX data"]
2341 #[inline(always)]
2342 pub fn data(&self) -> DataR {
2343 DataR::new((self.bits & 0xff) as u8)
2344 }
2345 }
2346 impl W {
2347 #[doc = "Bits 0:7 - Write: TX data; Read: RX data"]
2348 #[inline(always)]
2349 pub fn data(&mut self) -> DataW<'_, DataSpec> {
2350 DataW::new(self, 0)
2351 }
2352 }
2353 #[doc = "Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2354 pub struct DataSpec;
2355 impl crate::RegisterSpec for DataSpec {
2356 type Ux = u16;
2357 }
2358 #[doc = "`read()` method returns [`data::R`](R) reader structure"]
2359 impl crate::Readable for DataSpec {}
2360 #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
2361 impl crate::Writable for DataSpec {
2362 type Safety = crate::Unsafe;
2363 }
2364 #[doc = "`reset()` method sets DATA to value 0"]
2365 impl crate::Resettable for DataSpec {}
2366 }
2367 #[doc = "UART_CTL (rw) register accessor: UART control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_ctl`] module"]
2368 #[doc(alias = "UART_CTL")]
2369 pub type UartCtl = crate::Reg<uart_ctl::UartCtlSpec>;
2370 #[doc = "UART control register"]
2371 pub mod uart_ctl {
2372 #[doc = "Register `UART_CTL` reader"]
2373 pub type R = crate::R<UartCtlSpec>;
2374 #[doc = "Register `UART_CTL` writer"]
2375 pub type W = crate::W<UartCtlSpec>;
2376 #[doc = "Field `div_en` reader - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
2377 pub type DivEnR = crate::BitReader;
2378 #[doc = "Field `div_en` writer - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
2379 pub type DivEnW<'a, REG> = crate::BitWriter<'a, REG>;
2380 #[doc = "Field `xbreak` reader - Break control: 0=normal; 1=force TX to space"]
2381 pub type XbreakR = crate::BitReader;
2382 #[doc = "Field `xbreak` writer - Break control: 0=normal; 1=force TX to space"]
2383 pub type XbreakW<'a, REG> = crate::BitWriter<'a, REG>;
2384 #[doc = "Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit\n\nValue on reset: 0"]
2385 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2386 #[repr(u8)]
2387 pub enum Dlen {
2388 #[doc = "0: 5-bit data"]
2389 Bits5 = 0,
2390 #[doc = "1: 6-bit data"]
2391 Bits6 = 1,
2392 #[doc = "2: 7-bit data"]
2393 Bits7 = 2,
2394 #[doc = "3: 8-bit data"]
2395 Bits8 = 3,
2396 }
2397 impl From<Dlen> for u8 {
2398 #[inline(always)]
2399 fn from(variant: Dlen) -> Self {
2400 variant as _
2401 }
2402 }
2403 impl crate::FieldSpec for Dlen {
2404 type Ux = u8;
2405 }
2406 impl crate::IsEnum for Dlen {}
2407 #[doc = "Field `dlen` reader - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
2408 pub type DlenR = crate::FieldReader<Dlen>;
2409 impl DlenR {
2410 #[doc = "Get enumerated values variant"]
2411 #[inline(always)]
2412 pub const fn variant(&self) -> Dlen {
2413 match self.bits {
2414 0 => Dlen::Bits5,
2415 1 => Dlen::Bits6,
2416 2 => Dlen::Bits7,
2417 3 => Dlen::Bits8,
2418 _ => unreachable!(),
2419 }
2420 }
2421 #[doc = "5-bit data"]
2422 #[inline(always)]
2423 pub fn is_bits5(&self) -> bool {
2424 *self == Dlen::Bits5
2425 }
2426 #[doc = "6-bit data"]
2427 #[inline(always)]
2428 pub fn is_bits6(&self) -> bool {
2429 *self == Dlen::Bits6
2430 }
2431 #[doc = "7-bit data"]
2432 #[inline(always)]
2433 pub fn is_bits7(&self) -> bool {
2434 *self == Dlen::Bits7
2435 }
2436 #[doc = "8-bit data"]
2437 #[inline(always)]
2438 pub fn is_bits8(&self) -> bool {
2439 *self == Dlen::Bits8
2440 }
2441 }
2442 #[doc = "Field `dlen` writer - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
2443 pub type DlenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dlen, crate::Safe>;
2444 impl<'a, REG> DlenW<'a, REG>
2445 where
2446 REG: crate::Writable + crate::RegisterSpec,
2447 REG::Ux: From<u8>,
2448 {
2449 #[doc = "5-bit data"]
2450 #[inline(always)]
2451 pub fn bits5(self) -> &'a mut crate::W<REG> {
2452 self.variant(Dlen::Bits5)
2453 }
2454 #[doc = "6-bit data"]
2455 #[inline(always)]
2456 pub fn bits6(self) -> &'a mut crate::W<REG> {
2457 self.variant(Dlen::Bits6)
2458 }
2459 #[doc = "7-bit data"]
2460 #[inline(always)]
2461 pub fn bits7(self) -> &'a mut crate::W<REG> {
2462 self.variant(Dlen::Bits7)
2463 }
2464 #[doc = "8-bit data"]
2465 #[inline(always)]
2466 pub fn bits8(self) -> &'a mut crate::W<REG> {
2467 self.variant(Dlen::Bits8)
2468 }
2469 }
2470 #[doc = "Parity select: 0=odd; 1=even\n\nValue on reset: 0"]
2471 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2472 pub enum Eps {
2473 #[doc = "0: Odd parity"]
2474 Odd = 0,
2475 #[doc = "1: Even parity"]
2476 Even = 1,
2477 }
2478 impl From<Eps> for bool {
2479 #[inline(always)]
2480 fn from(variant: Eps) -> Self {
2481 variant as u8 != 0
2482 }
2483 }
2484 #[doc = "Field `eps` reader - Parity select: 0=odd; 1=even"]
2485 pub type EpsR = crate::BitReader<Eps>;
2486 impl EpsR {
2487 #[doc = "Get enumerated values variant"]
2488 #[inline(always)]
2489 pub const fn variant(&self) -> Eps {
2490 match self.bits {
2491 false => Eps::Odd,
2492 true => Eps::Even,
2493 }
2494 }
2495 #[doc = "Odd parity"]
2496 #[inline(always)]
2497 pub fn is_odd(&self) -> bool {
2498 *self == Eps::Odd
2499 }
2500 #[doc = "Even parity"]
2501 #[inline(always)]
2502 pub fn is_even(&self) -> bool {
2503 *self == Eps::Even
2504 }
2505 }
2506 #[doc = "Field `eps` writer - Parity select: 0=odd; 1=even"]
2507 pub type EpsW<'a, REG> = crate::BitWriter<'a, REG, Eps>;
2508 impl<'a, REG> EpsW<'a, REG>
2509 where
2510 REG: crate::Writable + crate::RegisterSpec,
2511 {
2512 #[doc = "Odd parity"]
2513 #[inline(always)]
2514 pub fn odd(self) -> &'a mut crate::W<REG> {
2515 self.variant(Eps::Odd)
2516 }
2517 #[doc = "Even parity"]
2518 #[inline(always)]
2519 pub fn even(self) -> &'a mut crate::W<REG> {
2520 self.variant(Eps::Even)
2521 }
2522 }
2523 #[doc = "Parity enable: 0=disabled; 1=enabled\n\nValue on reset: 0"]
2524 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2525 pub enum Pen {
2526 #[doc = "0: No parity"]
2527 Disabled = 0,
2528 #[doc = "1: Parity enabled"]
2529 Enabled = 1,
2530 }
2531 impl From<Pen> for bool {
2532 #[inline(always)]
2533 fn from(variant: Pen) -> Self {
2534 variant as u8 != 0
2535 }
2536 }
2537 #[doc = "Field `pen` reader - Parity enable: 0=disabled; 1=enabled"]
2538 pub type PenR = crate::BitReader<Pen>;
2539 impl PenR {
2540 #[doc = "Get enumerated values variant"]
2541 #[inline(always)]
2542 pub const fn variant(&self) -> Pen {
2543 match self.bits {
2544 false => Pen::Disabled,
2545 true => Pen::Enabled,
2546 }
2547 }
2548 #[doc = "No parity"]
2549 #[inline(always)]
2550 pub fn is_disabled(&self) -> bool {
2551 *self == Pen::Disabled
2552 }
2553 #[doc = "Parity enabled"]
2554 #[inline(always)]
2555 pub fn is_enabled(&self) -> bool {
2556 *self == Pen::Enabled
2557 }
2558 }
2559 #[doc = "Field `pen` writer - Parity enable: 0=disabled; 1=enabled"]
2560 pub type PenW<'a, REG> = crate::BitWriter<'a, REG, Pen>;
2561 impl<'a, REG> PenW<'a, REG>
2562 where
2563 REG: crate::Writable + crate::RegisterSpec,
2564 {
2565 #[doc = "No parity"]
2566 #[inline(always)]
2567 pub fn disabled(self) -> &'a mut crate::W<REG> {
2568 self.variant(Pen::Disabled)
2569 }
2570 #[doc = "Parity enabled"]
2571 #[inline(always)]
2572 pub fn enabled(self) -> &'a mut crate::W<REG> {
2573 self.variant(Pen::Enabled)
2574 }
2575 }
2576 #[doc = "Field `sps` reader - Sticky parity: 0=disabled; 1=enabled"]
2577 pub type SpsR = crate::BitReader;
2578 #[doc = "Field `sps` writer - Sticky parity: 0=disabled; 1=enabled"]
2579 pub type SpsW<'a, REG> = crate::BitWriter<'a, REG>;
2580 #[doc = "Stop bits: 0=1bit; 1=1.5/2bit\n\nValue on reset: 0"]
2581 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2582 pub enum Stp {
2583 #[doc = "0: 1 stop bit"]
2584 Stop1 = 0,
2585 #[doc = "1: 1.5 (5-bit data) or 2 stop bits"]
2586 Stop1_5Or2 = 1,
2587 }
2588 impl From<Stp> for bool {
2589 #[inline(always)]
2590 fn from(variant: Stp) -> Self {
2591 variant as u8 != 0
2592 }
2593 }
2594 #[doc = "Field `stp` reader - Stop bits: 0=1bit; 1=1.5/2bit"]
2595 pub type StpR = crate::BitReader<Stp>;
2596 impl StpR {
2597 #[doc = "Get enumerated values variant"]
2598 #[inline(always)]
2599 pub const fn variant(&self) -> Stp {
2600 match self.bits {
2601 false => Stp::Stop1,
2602 true => Stp::Stop1_5Or2,
2603 }
2604 }
2605 #[doc = "1 stop bit"]
2606 #[inline(always)]
2607 pub fn is_stop1(&self) -> bool {
2608 *self == Stp::Stop1
2609 }
2610 #[doc = "1.5 (5-bit data) or 2 stop bits"]
2611 #[inline(always)]
2612 pub fn is_stop1_5_or_2(&self) -> bool {
2613 *self == Stp::Stop1_5Or2
2614 }
2615 }
2616 #[doc = "Field `stp` writer - Stop bits: 0=1bit; 1=1.5/2bit"]
2617 pub type StpW<'a, REG> = crate::BitWriter<'a, REG, Stp>;
2618 impl<'a, REG> StpW<'a, REG>
2619 where
2620 REG: crate::Writable + crate::RegisterSpec,
2621 {
2622 #[doc = "1 stop bit"]
2623 #[inline(always)]
2624 pub fn stop1(self) -> &'a mut crate::W<REG> {
2625 self.variant(Stp::Stop1)
2626 }
2627 #[doc = "1.5 (5-bit data) or 2 stop bits"]
2628 #[inline(always)]
2629 pub fn stop1_5_or_2(self) -> &'a mut crate::W<REG> {
2630 self.variant(Stp::Stop1_5Or2)
2631 }
2632 }
2633 impl R {
2634 #[doc = "Bit 0 - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
2635 #[inline(always)]
2636 pub fn div_en(&self) -> DivEnR {
2637 DivEnR::new((self.bits & 1) != 0)
2638 }
2639 #[doc = "Bit 1 - Break control: 0=normal; 1=force TX to space"]
2640 #[inline(always)]
2641 pub fn xbreak(&self) -> XbreakR {
2642 XbreakR::new(((self.bits >> 1) & 1) != 0)
2643 }
2644 #[doc = "Bits 2:3 - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
2645 #[inline(always)]
2646 pub fn dlen(&self) -> DlenR {
2647 DlenR::new(((self.bits >> 2) & 3) as u8)
2648 }
2649 #[doc = "Bit 4 - Parity select: 0=odd; 1=even"]
2650 #[inline(always)]
2651 pub fn eps(&self) -> EpsR {
2652 EpsR::new(((self.bits >> 4) & 1) != 0)
2653 }
2654 #[doc = "Bit 5 - Parity enable: 0=disabled; 1=enabled"]
2655 #[inline(always)]
2656 pub fn pen(&self) -> PenR {
2657 PenR::new(((self.bits >> 5) & 1) != 0)
2658 }
2659 #[doc = "Bit 6 - Sticky parity: 0=disabled; 1=enabled"]
2660 #[inline(always)]
2661 pub fn sps(&self) -> SpsR {
2662 SpsR::new(((self.bits >> 6) & 1) != 0)
2663 }
2664 #[doc = "Bit 7 - Stop bits: 0=1bit; 1=1.5/2bit"]
2665 #[inline(always)]
2666 pub fn stp(&self) -> StpR {
2667 StpR::new(((self.bits >> 7) & 1) != 0)
2668 }
2669 }
2670 impl W {
2671 #[doc = "Bit 0 - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
2672 #[inline(always)]
2673 pub fn div_en(&mut self) -> DivEnW<'_, UartCtlSpec> {
2674 DivEnW::new(self, 0)
2675 }
2676 #[doc = "Bit 1 - Break control: 0=normal; 1=force TX to space"]
2677 #[inline(always)]
2678 pub fn xbreak(&mut self) -> XbreakW<'_, UartCtlSpec> {
2679 XbreakW::new(self, 1)
2680 }
2681 #[doc = "Bits 2:3 - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
2682 #[inline(always)]
2683 pub fn dlen(&mut self) -> DlenW<'_, UartCtlSpec> {
2684 DlenW::new(self, 2)
2685 }
2686 #[doc = "Bit 4 - Parity select: 0=odd; 1=even"]
2687 #[inline(always)]
2688 pub fn eps(&mut self) -> EpsW<'_, UartCtlSpec> {
2689 EpsW::new(self, 4)
2690 }
2691 #[doc = "Bit 5 - Parity enable: 0=disabled; 1=enabled"]
2692 #[inline(always)]
2693 pub fn pen(&mut self) -> PenW<'_, UartCtlSpec> {
2694 PenW::new(self, 5)
2695 }
2696 #[doc = "Bit 6 - Sticky parity: 0=disabled; 1=enabled"]
2697 #[inline(always)]
2698 pub fn sps(&mut self) -> SpsW<'_, UartCtlSpec> {
2699 SpsW::new(self, 6)
2700 }
2701 #[doc = "Bit 7 - Stop bits: 0=1bit; 1=1.5/2bit"]
2702 #[inline(always)]
2703 pub fn stp(&mut self) -> StpW<'_, UartCtlSpec> {
2704 StpW::new(self, 7)
2705 }
2706 }
2707 #[doc = "UART control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2708 pub struct UartCtlSpec;
2709 impl crate::RegisterSpec for UartCtlSpec {
2710 type Ux = u16;
2711 }
2712 #[doc = "`read()` method returns [`uart_ctl::R`](R) reader structure"]
2713 impl crate::Readable for UartCtlSpec {}
2714 #[doc = "`write(|w| ..)` method takes [`uart_ctl::W`](W) writer structure"]
2715 impl crate::Writable for UartCtlSpec {
2716 type Safety = crate::Unsafe;
2717 }
2718 #[doc = "`reset()` method sets UART_CTL to value 0"]
2719 impl crate::Resettable for UartCtlSpec {}
2720 }
2721 #[doc = "DIV_H (rw) register accessor: Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_h`] module"]
2722 #[doc(alias = "DIV_H")]
2723 pub type DivH = crate::Reg<div_h::DivHSpec>;
2724 #[doc = "Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
2725 pub mod div_h {
2726 #[doc = "Register `DIV_H` reader"]
2727 pub type R = crate::R<DivHSpec>;
2728 #[doc = "Register `DIV_H` writer"]
2729 pub type W = crate::W<DivHSpec>;
2730 #[doc = "Field `div_h` reader - Divider integer high 8 bits"]
2731 pub type DivHR = crate::FieldReader;
2732 #[doc = "Field `div_h` writer - Divider integer high 8 bits"]
2733 pub type DivHW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
2734 impl R {
2735 #[doc = "Bits 0:7 - Divider integer high 8 bits"]
2736 #[inline(always)]
2737 pub fn div_h(&self) -> DivHR {
2738 DivHR::new((self.bits & 0xff) as u8)
2739 }
2740 }
2741 impl W {
2742 #[doc = "Bits 0:7 - Divider integer high 8 bits"]
2743 #[inline(always)]
2744 pub fn div_h(&mut self) -> DivHW<'_, DivHSpec> {
2745 DivHW::new(self, 0)
2746 }
2747 }
2748 #[doc = "Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2749 pub struct DivHSpec;
2750 impl crate::RegisterSpec for DivHSpec {
2751 type Ux = u16;
2752 }
2753 #[doc = "`read()` method returns [`div_h::R`](R) reader structure"]
2754 impl crate::Readable for DivHSpec {}
2755 #[doc = "`write(|w| ..)` method takes [`div_h::W`](W) writer structure"]
2756 impl crate::Writable for DivHSpec {
2757 type Safety = crate::Unsafe;
2758 }
2759 #[doc = "`reset()` method sets DIV_H to value 0"]
2760 impl crate::Resettable for DivHSpec {}
2761 }
2762 #[doc = "DIV_L (rw) register accessor: Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_l`] module"]
2763 #[doc(alias = "DIV_L")]
2764 pub type DivL = crate::Reg<div_l::DivLSpec>;
2765 #[doc = "Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
2766 pub mod div_l {
2767 #[doc = "Register `DIV_L` reader"]
2768 pub type R = crate::R<DivLSpec>;
2769 #[doc = "Register `DIV_L` writer"]
2770 pub type W = crate::W<DivLSpec>;
2771 #[doc = "Field `div_l` reader - Divider integer low 8 bits"]
2772 pub type DivLR = crate::FieldReader;
2773 #[doc = "Field `div_l` writer - Divider integer low 8 bits"]
2774 pub type DivLW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
2775 impl R {
2776 #[doc = "Bits 0:7 - Divider integer low 8 bits"]
2777 #[inline(always)]
2778 pub fn div_l(&self) -> DivLR {
2779 DivLR::new((self.bits & 0xff) as u8)
2780 }
2781 }
2782 impl W {
2783 #[doc = "Bits 0:7 - Divider integer low 8 bits"]
2784 #[inline(always)]
2785 pub fn div_l(&mut self) -> DivLW<'_, DivLSpec> {
2786 DivLW::new(self, 0)
2787 }
2788 }
2789 #[doc = "Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2790 pub struct DivLSpec;
2791 impl crate::RegisterSpec for DivLSpec {
2792 type Ux = u16;
2793 }
2794 #[doc = "`read()` method returns [`div_l::R`](R) reader structure"]
2795 impl crate::Readable for DivLSpec {}
2796 #[doc = "`write(|w| ..)` method takes [`div_l::W`](W) writer structure"]
2797 impl crate::Writable for DivLSpec {
2798 type Safety = crate::Unsafe;
2799 }
2800 #[doc = "`reset()` method sets DIV_L to value 0"]
2801 impl crate::Resettable for DivLSpec {}
2802 }
2803 #[doc = "DIV_FRA (rw) register accessor: Baud rate divider fractional part\n\nYou can [`read`](crate::Reg::read) this register and get [`div_fra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_fra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_fra`] module"]
2804 #[doc(alias = "DIV_FRA")]
2805 pub type DivFra = crate::Reg<div_fra::DivFraSpec>;
2806 #[doc = "Baud rate divider fractional part"]
2807 pub mod div_fra {
2808 #[doc = "Register `DIV_FRA` reader"]
2809 pub type R = crate::R<DivFraSpec>;
2810 #[doc = "Register `DIV_FRA` writer"]
2811 pub type W = crate::W<DivFraSpec>;
2812 #[doc = "Field `div_fra` reader - Divider fractional part (divided by 2^6)"]
2813 pub type DivFraR = crate::FieldReader;
2814 #[doc = "Field `div_fra` writer - Divider fractional part (divided by 2^6)"]
2815 pub type DivFraW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
2816 impl R {
2817 #[doc = "Bits 0:5 - Divider fractional part (divided by 2^6)"]
2818 #[inline(always)]
2819 pub fn div_fra(&self) -> DivFraR {
2820 DivFraR::new((self.bits & 0x3f) as u8)
2821 }
2822 }
2823 impl W {
2824 #[doc = "Bits 0:5 - Divider fractional part (divided by 2^6)"]
2825 #[inline(always)]
2826 pub fn div_fra(&mut self) -> DivFraW<'_, DivFraSpec> {
2827 DivFraW::new(self, 0)
2828 }
2829 }
2830 #[doc = "Baud rate divider fractional part\n\nYou can [`read`](crate::Reg::read) this register and get [`div_fra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_fra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2831 pub struct DivFraSpec;
2832 impl crate::RegisterSpec for DivFraSpec {
2833 type Ux = u16;
2834 }
2835 #[doc = "`read()` method returns [`div_fra::R`](R) reader structure"]
2836 impl crate::Readable for DivFraSpec {}
2837 #[doc = "`write(|w| ..)` method takes [`div_fra::W`](W) writer structure"]
2838 impl crate::Writable for DivFraSpec {
2839 type Safety = crate::Unsafe;
2840 }
2841 #[doc = "`reset()` method sets DIV_FRA to value 0"]
2842 impl crate::Resettable for DivFraSpec {}
2843 }
2844 #[doc = "INTR_EN (rw) register accessor: Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_en`] module"]
2845 #[doc(alias = "INTR_EN")]
2846 pub type IntrEn = crate::Reg<intr_en::IntrEnSpec>;
2847 #[doc = "Interrupt enable register"]
2848 pub mod intr_en {
2849 #[doc = "Register `INTR_EN` reader"]
2850 pub type R = crate::R<IntrEnSpec>;
2851 #[doc = "Register `INTR_EN` writer"]
2852 pub type W = crate::W<IntrEnSpec>;
2853 #[doc = "Field `rece_line_stat_intr_en` reader - RX line status interrupt enable"]
2854 pub type ReceLineStatIntrEnR = crate::BitReader;
2855 #[doc = "Field `rece_line_stat_intr_en` writer - RX line status interrupt enable"]
2856 pub type ReceLineStatIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
2857 #[doc = "Field `modem_intr_en` reader - Modem status interrupt enable"]
2858 pub type ModemIntrEnR = crate::BitReader;
2859 #[doc = "Field `modem_intr_en` writer - Modem status interrupt enable"]
2860 pub type ModemIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
2861 #[doc = "Field `rece_data_intr_en` reader - RX data available interrupt enable"]
2862 pub type ReceDataIntrEnR = crate::BitReader;
2863 #[doc = "Field `rece_data_intr_en` writer - RX data available interrupt enable"]
2864 pub type ReceDataIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
2865 #[doc = "Field `tran_em_intr_en` reader - TX empty interrupt enable"]
2866 pub type TranEmIntrEnR = crate::BitReader;
2867 #[doc = "Field `tran_em_intr_en` writer - TX empty interrupt enable"]
2868 pub type TranEmIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
2869 #[doc = "Field `ptim_en` reader - Programmable THRE interrupt mode enable"]
2870 pub type PtimEnR = crate::BitReader;
2871 #[doc = "Field `ptim_en` writer - Programmable THRE interrupt mode enable"]
2872 pub type PtimEnW<'a, REG> = crate::BitWriter<'a, REG>;
2873 impl R {
2874 #[doc = "Bit 0 - RX line status interrupt enable"]
2875 #[inline(always)]
2876 pub fn rece_line_stat_intr_en(&self) -> ReceLineStatIntrEnR {
2877 ReceLineStatIntrEnR::new((self.bits & 1) != 0)
2878 }
2879 #[doc = "Bit 1 - Modem status interrupt enable"]
2880 #[inline(always)]
2881 pub fn modem_intr_en(&self) -> ModemIntrEnR {
2882 ModemIntrEnR::new(((self.bits >> 1) & 1) != 0)
2883 }
2884 #[doc = "Bit 2 - RX data available interrupt enable"]
2885 #[inline(always)]
2886 pub fn rece_data_intr_en(&self) -> ReceDataIntrEnR {
2887 ReceDataIntrEnR::new(((self.bits >> 2) & 1) != 0)
2888 }
2889 #[doc = "Bit 3 - TX empty interrupt enable"]
2890 #[inline(always)]
2891 pub fn tran_em_intr_en(&self) -> TranEmIntrEnR {
2892 TranEmIntrEnR::new(((self.bits >> 3) & 1) != 0)
2893 }
2894 #[doc = "Bit 4 - Programmable THRE interrupt mode enable"]
2895 #[inline(always)]
2896 pub fn ptim_en(&self) -> PtimEnR {
2897 PtimEnR::new(((self.bits >> 4) & 1) != 0)
2898 }
2899 }
2900 impl W {
2901 #[doc = "Bit 0 - RX line status interrupt enable"]
2902 #[inline(always)]
2903 pub fn rece_line_stat_intr_en(&mut self) -> ReceLineStatIntrEnW<'_, IntrEnSpec> {
2904 ReceLineStatIntrEnW::new(self, 0)
2905 }
2906 #[doc = "Bit 1 - Modem status interrupt enable"]
2907 #[inline(always)]
2908 pub fn modem_intr_en(&mut self) -> ModemIntrEnW<'_, IntrEnSpec> {
2909 ModemIntrEnW::new(self, 1)
2910 }
2911 #[doc = "Bit 2 - RX data available interrupt enable"]
2912 #[inline(always)]
2913 pub fn rece_data_intr_en(&mut self) -> ReceDataIntrEnW<'_, IntrEnSpec> {
2914 ReceDataIntrEnW::new(self, 2)
2915 }
2916 #[doc = "Bit 3 - TX empty interrupt enable"]
2917 #[inline(always)]
2918 pub fn tran_em_intr_en(&mut self) -> TranEmIntrEnW<'_, IntrEnSpec> {
2919 TranEmIntrEnW::new(self, 3)
2920 }
2921 #[doc = "Bit 4 - Programmable THRE interrupt mode enable"]
2922 #[inline(always)]
2923 pub fn ptim_en(&mut self) -> PtimEnW<'_, IntrEnSpec> {
2924 PtimEnW::new(self, 4)
2925 }
2926 }
2927 #[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2928 pub struct IntrEnSpec;
2929 impl crate::RegisterSpec for IntrEnSpec {
2930 type Ux = u16;
2931 }
2932 #[doc = "`read()` method returns [`intr_en::R`](R) reader structure"]
2933 impl crate::Readable for IntrEnSpec {}
2934 #[doc = "`write(|w| ..)` method takes [`intr_en::W`](W) writer structure"]
2935 impl crate::Writable for IntrEnSpec {
2936 type Safety = crate::Unsafe;
2937 }
2938 #[doc = "`reset()` method sets INTR_EN to value 0"]
2939 impl crate::Resettable for IntrEnSpec {}
2940 }
2941 #[doc = "INTR_STATUS (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status`] module"]
2942 #[doc(alias = "INTR_STATUS")]
2943 pub type IntrStatus = crate::Reg<intr_status::IntrStatusSpec>;
2944 #[doc = "Interrupt status register"]
2945 pub mod intr_status {
2946 #[doc = "Register `INTR_STATUS` reader"]
2947 pub type R = crate::R<IntrStatusSpec>;
2948 #[doc = "Register `INTR_STATUS` writer"]
2949 pub type W = crate::W<IntrStatusSpec>;
2950 #[doc = "Field `busy_det_intr` reader - Busy detect interrupt status"]
2951 pub type BusyDetIntrR = crate::BitReader;
2952 #[doc = "Field `modem_intr_status` reader - Modem interrupt status"]
2953 pub type ModemIntrStatusR = crate::BitReader;
2954 #[doc = "Field `thre_intr_status` reader - THR empty interrupt status"]
2955 pub type ThreIntrStatusR = crate::BitReader;
2956 #[doc = "Field `char_to_intr_status` reader - Character timeout interrupt status"]
2957 pub type CharToIntrStatusR = crate::BitReader;
2958 #[doc = "Field `data_avail_intr_status` reader - RX data available interrupt status"]
2959 pub type DataAvailIntrStatusR = crate::BitReader;
2960 #[doc = "Field `line_intr_status` reader - RX line interrupt status"]
2961 pub type LineIntrStatusR = crate::BitReader;
2962 impl R {
2963 #[doc = "Bit 0 - Busy detect interrupt status"]
2964 #[inline(always)]
2965 pub fn busy_det_intr(&self) -> BusyDetIntrR {
2966 BusyDetIntrR::new((self.bits & 1) != 0)
2967 }
2968 #[doc = "Bit 1 - Modem interrupt status"]
2969 #[inline(always)]
2970 pub fn modem_intr_status(&self) -> ModemIntrStatusR {
2971 ModemIntrStatusR::new(((self.bits >> 1) & 1) != 0)
2972 }
2973 #[doc = "Bit 2 - THR empty interrupt status"]
2974 #[inline(always)]
2975 pub fn thre_intr_status(&self) -> ThreIntrStatusR {
2976 ThreIntrStatusR::new(((self.bits >> 2) & 1) != 0)
2977 }
2978 #[doc = "Bit 3 - Character timeout interrupt status"]
2979 #[inline(always)]
2980 pub fn char_to_intr_status(&self) -> CharToIntrStatusR {
2981 CharToIntrStatusR::new(((self.bits >> 3) & 1) != 0)
2982 }
2983 #[doc = "Bit 4 - RX data available interrupt status"]
2984 #[inline(always)]
2985 pub fn data_avail_intr_status(&self) -> DataAvailIntrStatusR {
2986 DataAvailIntrStatusR::new(((self.bits >> 4) & 1) != 0)
2987 }
2988 #[doc = "Bit 5 - RX line interrupt status"]
2989 #[inline(always)]
2990 pub fn line_intr_status(&self) -> LineIntrStatusR {
2991 LineIntrStatusR::new(((self.bits >> 5) & 1) != 0)
2992 }
2993 }
2994 impl W {}
2995 #[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2996 pub struct IntrStatusSpec;
2997 impl crate::RegisterSpec for IntrStatusSpec {
2998 type Ux = u16;
2999 }
3000 #[doc = "`read()` method returns [`intr_status::R`](R) reader structure"]
3001 impl crate::Readable for IntrStatusSpec {}
3002 #[doc = "`write(|w| ..)` method takes [`intr_status::W`](W) writer structure"]
3003 impl crate::Writable for IntrStatusSpec {
3004 type Safety = crate::Unsafe;
3005 }
3006 #[doc = "`reset()` method sets INTR_STATUS to value 0"]
3007 impl crate::Resettable for IntrStatusSpec {}
3008 }
3009 #[doc = "FIFO_CTL (rw) register accessor: FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_ctl`] module"]
3010 #[doc(alias = "FIFO_CTL")]
3011 pub type FifoCtl = crate::Reg<fifo_ctl::FifoCtlSpec>;
3012 #[doc = "FIFO control register"]
3013 pub mod fifo_ctl {
3014 #[doc = "Register `FIFO_CTL` reader"]
3015 pub type R = crate::R<FifoCtlSpec>;
3016 #[doc = "Register `FIFO_CTL` writer"]
3017 pub type W = crate::W<FifoCtlSpec>;
3018 #[doc = "TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2\n\nValue on reset: 0"]
3019 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
3020 #[repr(u8)]
3021 pub enum TxEmptyTrig {
3022 #[doc = "0: FIFO empty"]
3023 Empty = 0,
3024 #[doc = "1: 2 characters remaining"]
3025 Chars2 = 1,
3026 #[doc = "2: FIFO 1/4 full"]
3027 Quarter = 2,
3028 #[doc = "3: FIFO 1/2 full"]
3029 Half = 3,
3030 }
3031 impl From<TxEmptyTrig> for u8 {
3032 #[inline(always)]
3033 fn from(variant: TxEmptyTrig) -> Self {
3034 variant as _
3035 }
3036 }
3037 impl crate::FieldSpec for TxEmptyTrig {
3038 type Ux = u8;
3039 }
3040 impl crate::IsEnum for TxEmptyTrig {}
3041 #[doc = "Field `tx_empty_trig` writer - TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2"]
3042 pub type TxEmptyTrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, TxEmptyTrig, crate::Safe>;
3043 impl<'a, REG> TxEmptyTrigW<'a, REG>
3044 where
3045 REG: crate::Writable + crate::RegisterSpec,
3046 REG::Ux: From<u8>,
3047 {
3048 #[doc = "FIFO empty"]
3049 #[inline(always)]
3050 pub fn empty(self) -> &'a mut crate::W<REG> {
3051 self.variant(TxEmptyTrig::Empty)
3052 }
3053 #[doc = "2 characters remaining"]
3054 #[inline(always)]
3055 pub fn chars2(self) -> &'a mut crate::W<REG> {
3056 self.variant(TxEmptyTrig::Chars2)
3057 }
3058 #[doc = "FIFO 1/4 full"]
3059 #[inline(always)]
3060 pub fn quarter(self) -> &'a mut crate::W<REG> {
3061 self.variant(TxEmptyTrig::Quarter)
3062 }
3063 #[doc = "FIFO 1/2 full"]
3064 #[inline(always)]
3065 pub fn half(self) -> &'a mut crate::W<REG> {
3066 self.variant(TxEmptyTrig::Half)
3067 }
3068 }
3069 #[doc = "RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full\n\nValue on reset: 0"]
3070 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
3071 #[repr(u8)]
3072 pub enum RxEmptyTrig {
3073 #[doc = "0: 1 character in FIFO"]
3074 Char1 = 0,
3075 #[doc = "1: FIFO 1/4 full"]
3076 Quarter = 1,
3077 #[doc = "2: FIFO 1/2 full"]
3078 Half = 2,
3079 #[doc = "3: 2 below full"]
3080 Less2 = 3,
3081 }
3082 impl From<RxEmptyTrig> for u8 {
3083 #[inline(always)]
3084 fn from(variant: RxEmptyTrig) -> Self {
3085 variant as _
3086 }
3087 }
3088 impl crate::FieldSpec for RxEmptyTrig {
3089 type Ux = u8;
3090 }
3091 impl crate::IsEnum for RxEmptyTrig {}
3092 #[doc = "Field `rx_empty_trig` writer - RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full"]
3093 pub type RxEmptyTrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, RxEmptyTrig, crate::Safe>;
3094 impl<'a, REG> RxEmptyTrigW<'a, REG>
3095 where
3096 REG: crate::Writable + crate::RegisterSpec,
3097 REG::Ux: From<u8>,
3098 {
3099 #[doc = "1 character in FIFO"]
3100 #[inline(always)]
3101 pub fn char1(self) -> &'a mut crate::W<REG> {
3102 self.variant(RxEmptyTrig::Char1)
3103 }
3104 #[doc = "FIFO 1/4 full"]
3105 #[inline(always)]
3106 pub fn quarter(self) -> &'a mut crate::W<REG> {
3107 self.variant(RxEmptyTrig::Quarter)
3108 }
3109 #[doc = "FIFO 1/2 full"]
3110 #[inline(always)]
3111 pub fn half(self) -> &'a mut crate::W<REG> {
3112 self.variant(RxEmptyTrig::Half)
3113 }
3114 #[doc = "2 below full"]
3115 #[inline(always)]
3116 pub fn less2(self) -> &'a mut crate::W<REG> {
3117 self.variant(RxEmptyTrig::Less2)
3118 }
3119 }
3120 #[doc = "Field `fifo_en` writer - FIFO enable"]
3121 pub type FifoEnW<'a, REG> = crate::BitWriter<'a, REG>;
3122 #[doc = "Field `tx_fifo_rst` writer - TX FIFO reset: 0=no reset; 1=reset"]
3123 pub type TxFifoRstW<'a, REG> = crate::BitWriter<'a, REG>;
3124 #[doc = "Field `rx_fifo_rst` writer - RX FIFO reset: 0=no reset; 1=reset"]
3125 pub type RxFifoRstW<'a, REG> = crate::BitWriter<'a, REG>;
3126 impl W {
3127 #[doc = "Bits 0:1 - TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2"]
3128 #[inline(always)]
3129 pub fn tx_empty_trig(&mut self) -> TxEmptyTrigW<'_, FifoCtlSpec> {
3130 TxEmptyTrigW::new(self, 0)
3131 }
3132 #[doc = "Bits 2:3 - RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full"]
3133 #[inline(always)]
3134 pub fn rx_empty_trig(&mut self) -> RxEmptyTrigW<'_, FifoCtlSpec> {
3135 RxEmptyTrigW::new(self, 2)
3136 }
3137 #[doc = "Bit 4 - FIFO enable"]
3138 #[inline(always)]
3139 pub fn fifo_en(&mut self) -> FifoEnW<'_, FifoCtlSpec> {
3140 FifoEnW::new(self, 4)
3141 }
3142 #[doc = "Bit 5 - TX FIFO reset: 0=no reset; 1=reset"]
3143 #[inline(always)]
3144 pub fn tx_fifo_rst(&mut self) -> TxFifoRstW<'_, FifoCtlSpec> {
3145 TxFifoRstW::new(self, 5)
3146 }
3147 #[doc = "Bit 6 - RX FIFO reset: 0=no reset; 1=reset"]
3148 #[inline(always)]
3149 pub fn rx_fifo_rst(&mut self) -> RxFifoRstW<'_, FifoCtlSpec> {
3150 RxFifoRstW::new(self, 6)
3151 }
3152 }
3153 #[doc = "FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3154 pub struct FifoCtlSpec;
3155 impl crate::RegisterSpec for FifoCtlSpec {
3156 type Ux = u16;
3157 }
3158 #[doc = "`read()` method returns [`fifo_ctl::R`](R) reader structure"]
3159 impl crate::Readable for FifoCtlSpec {}
3160 #[doc = "`write(|w| ..)` method takes [`fifo_ctl::W`](W) writer structure"]
3161 impl crate::Writable for FifoCtlSpec {
3162 type Safety = crate::Unsafe;
3163 }
3164 #[doc = "`reset()` method sets FIFO_CTL to value 0"]
3165 impl crate::Resettable for FifoCtlSpec {}
3166 }
3167 #[doc = "FAR (rw) register accessor: FIFO access mode enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"]
3168 #[doc(alias = "FAR")]
3169 pub type Far = crate::Reg<far::FarSpec>;
3170 #[doc = "FIFO access mode enable register"]
3171 pub mod far {
3172 #[doc = "Register `FAR` reader"]
3173 pub type R = crate::R<FarSpec>;
3174 #[doc = "Register `FAR` writer"]
3175 pub type W = crate::W<FarSpec>;
3176 #[doc = "Field `far` reader - FIFO access mode: 0=disabled; 1=enabled"]
3177 pub type FarR = crate::BitReader;
3178 #[doc = "Field `far` writer - FIFO access mode: 0=disabled; 1=enabled"]
3179 pub type FarW<'a, REG> = crate::BitWriter<'a, REG>;
3180 impl R {
3181 #[doc = "Bit 0 - FIFO access mode: 0=disabled; 1=enabled"]
3182 #[inline(always)]
3183 pub fn far(&self) -> FarR {
3184 FarR::new((self.bits & 1) != 0)
3185 }
3186 }
3187 impl W {
3188 #[doc = "Bit 0 - FIFO access mode: 0=disabled; 1=enabled"]
3189 #[inline(always)]
3190 pub fn far(&mut self) -> FarW<'_, FarSpec> {
3191 FarW::new(self, 0)
3192 }
3193 }
3194 #[doc = "FIFO access mode enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`far::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`far::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3195 pub struct FarSpec;
3196 impl crate::RegisterSpec for FarSpec {
3197 type Ux = u16;
3198 }
3199 #[doc = "`read()` method returns [`far::R`](R) reader structure"]
3200 impl crate::Readable for FarSpec {}
3201 #[doc = "`write(|w| ..)` method takes [`far::W`](W) writer structure"]
3202 impl crate::Writable for FarSpec {
3203 type Safety = crate::Unsafe;
3204 }
3205 #[doc = "`reset()` method sets FAR to value 0"]
3206 impl crate::Resettable for FarSpec {}
3207 }
3208 #[doc = "MODEM_CTL (rw) register accessor: Modem control register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modem_ctl`] module"]
3209 #[doc(alias = "MODEM_CTL")]
3210 pub type ModemCtl = crate::Reg<modem_ctl::ModemCtlSpec>;
3211 #[doc = "Modem control register"]
3212 pub mod modem_ctl {
3213 #[doc = "Register `MODEM_CTL` reader"]
3214 pub type R = crate::R<ModemCtlSpec>;
3215 #[doc = "Register `MODEM_CTL` writer"]
3216 pub type W = crate::W<ModemCtlSpec>;
3217 #[doc = "Field `afc_en` reader - Auto flow control enable"]
3218 pub type AfcEnR = crate::BitReader;
3219 #[doc = "Field `afc_en` writer - Auto flow control enable"]
3220 pub type AfcEnW<'a, REG> = crate::BitWriter<'a, REG>;
3221 #[doc = "Field `lb_mode` reader - Loopback mode: 0=disabled; 1=enabled"]
3222 pub type LbModeR = crate::BitReader;
3223 #[doc = "Field `lb_mode` writer - Loopback mode: 0=disabled; 1=enabled"]
3224 pub type LbModeW<'a, REG> = crate::BitWriter<'a, REG>;
3225 #[doc = "Field `rts` reader - RTS software control"]
3226 pub type RtsR = crate::BitReader;
3227 #[doc = "Field `rts` writer - RTS software control"]
3228 pub type RtsW<'a, REG> = crate::BitWriter<'a, REG>;
3229 impl R {
3230 #[doc = "Bit 0 - Auto flow control enable"]
3231 #[inline(always)]
3232 pub fn afc_en(&self) -> AfcEnR {
3233 AfcEnR::new((self.bits & 1) != 0)
3234 }
3235 #[doc = "Bit 1 - Loopback mode: 0=disabled; 1=enabled"]
3236 #[inline(always)]
3237 pub fn lb_mode(&self) -> LbModeR {
3238 LbModeR::new(((self.bits >> 1) & 1) != 0)
3239 }
3240 #[doc = "Bit 2 - RTS software control"]
3241 #[inline(always)]
3242 pub fn rts(&self) -> RtsR {
3243 RtsR::new(((self.bits >> 2) & 1) != 0)
3244 }
3245 }
3246 impl W {
3247 #[doc = "Bit 0 - Auto flow control enable"]
3248 #[inline(always)]
3249 pub fn afc_en(&mut self) -> AfcEnW<'_, ModemCtlSpec> {
3250 AfcEnW::new(self, 0)
3251 }
3252 #[doc = "Bit 1 - Loopback mode: 0=disabled; 1=enabled"]
3253 #[inline(always)]
3254 pub fn lb_mode(&mut self) -> LbModeW<'_, ModemCtlSpec> {
3255 LbModeW::new(self, 1)
3256 }
3257 #[doc = "Bit 2 - RTS software control"]
3258 #[inline(always)]
3259 pub fn rts(&mut self) -> RtsW<'_, ModemCtlSpec> {
3260 RtsW::new(self, 2)
3261 }
3262 }
3263 #[doc = "Modem control register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3264 pub struct ModemCtlSpec;
3265 impl crate::RegisterSpec for ModemCtlSpec {
3266 type Ux = u16;
3267 }
3268 #[doc = "`read()` method returns [`modem_ctl::R`](R) reader structure"]
3269 impl crate::Readable for ModemCtlSpec {}
3270 #[doc = "`write(|w| ..)` method takes [`modem_ctl::W`](W) writer structure"]
3271 impl crate::Writable for ModemCtlSpec {
3272 type Safety = crate::Unsafe;
3273 }
3274 #[doc = "`reset()` method sets MODEM_CTL to value 0"]
3275 impl crate::Resettable for ModemCtlSpec {}
3276 }
3277 #[doc = "MODEM_STATUS (rw) register accessor: Modem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modem_status`] module"]
3278 #[doc(alias = "MODEM_STATUS")]
3279 pub type ModemStatus = crate::Reg<modem_status::ModemStatusSpec>;
3280 #[doc = "Modem status register"]
3281 pub mod modem_status {
3282 #[doc = "Register `MODEM_STATUS` reader"]
3283 pub type R = crate::R<ModemStatusSpec>;
3284 #[doc = "Register `MODEM_STATUS` writer"]
3285 pub type W = crate::W<ModemStatusSpec>;
3286 #[doc = "Field `dcts` reader - CTS change indicator"]
3287 pub type DctsR = crate::BitReader;
3288 #[doc = "Field `cts` reader - CTS signal state"]
3289 pub type CtsR = crate::BitReader;
3290 impl R {
3291 #[doc = "Bit 0 - CTS change indicator"]
3292 #[inline(always)]
3293 pub fn dcts(&self) -> DctsR {
3294 DctsR::new((self.bits & 1) != 0)
3295 }
3296 #[doc = "Bit 1 - CTS signal state"]
3297 #[inline(always)]
3298 pub fn cts(&self) -> CtsR {
3299 CtsR::new(((self.bits >> 1) & 1) != 0)
3300 }
3301 }
3302 impl W {}
3303 #[doc = "Modem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3304 pub struct ModemStatusSpec;
3305 impl crate::RegisterSpec for ModemStatusSpec {
3306 type Ux = u16;
3307 }
3308 #[doc = "`read()` method returns [`modem_status::R`](R) reader structure"]
3309 impl crate::Readable for ModemStatusSpec {}
3310 #[doc = "`write(|w| ..)` method takes [`modem_status::W`](W) writer structure"]
3311 impl crate::Writable for ModemStatusSpec {
3312 type Safety = crate::Unsafe;
3313 }
3314 #[doc = "`reset()` method sets MODEM_STATUS to value 0"]
3315 impl crate::Resettable for ModemStatusSpec {}
3316 }
3317 #[doc = "LINE_STATUS (rw) register accessor: Line status register\n\nYou can [`read`](crate::Reg::read) this register and get [`line_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`line_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@line_status`] module"]
3318 #[doc(alias = "LINE_STATUS")]
3319 pub type LineStatus = crate::Reg<line_status::LineStatusSpec>;
3320 #[doc = "Line status register"]
3321 pub mod line_status {
3322 #[doc = "Register `LINE_STATUS` reader"]
3323 pub type R = crate::R<LineStatusSpec>;
3324 #[doc = "Register `LINE_STATUS` writer"]
3325 pub type W = crate::W<LineStatusSpec>;
3326 #[doc = "Field `rx_fifo_err` reader - RX FIFO error status"]
3327 pub type RxFifoErrR = crate::BitReader;
3328 #[doc = "Field `frame_err` reader - Framing error"]
3329 pub type FrameErrR = crate::BitReader;
3330 #[doc = "Field `parity_err` reader - Parity error"]
3331 pub type ParityErrR = crate::BitReader;
3332 #[doc = "Field `overrun_err` reader - Overrun error"]
3333 pub type OverrunErrR = crate::BitReader;
3334 #[doc = "Field `break_intr` reader - Break interrupt"]
3335 pub type BreakIntrR = crate::BitReader;
3336 #[doc = "Field `data_available` reader - Data available in RX FIFO/RBR"]
3337 pub type DataAvailableR = crate::BitReader;
3338 #[doc = "Field `thre_s` reader - THR empty flag"]
3339 pub type ThreSR = crate::BitReader;
3340 #[doc = "Field `tx_empty_s` reader - Transmitter empty flag"]
3341 pub type TxEmptySR = crate::BitReader;
3342 impl R {
3343 #[doc = "Bit 0 - RX FIFO error status"]
3344 #[inline(always)]
3345 pub fn rx_fifo_err(&self) -> RxFifoErrR {
3346 RxFifoErrR::new((self.bits & 1) != 0)
3347 }
3348 #[doc = "Bit 1 - Framing error"]
3349 #[inline(always)]
3350 pub fn frame_err(&self) -> FrameErrR {
3351 FrameErrR::new(((self.bits >> 1) & 1) != 0)
3352 }
3353 #[doc = "Bit 2 - Parity error"]
3354 #[inline(always)]
3355 pub fn parity_err(&self) -> ParityErrR {
3356 ParityErrR::new(((self.bits >> 2) & 1) != 0)
3357 }
3358 #[doc = "Bit 3 - Overrun error"]
3359 #[inline(always)]
3360 pub fn overrun_err(&self) -> OverrunErrR {
3361 OverrunErrR::new(((self.bits >> 3) & 1) != 0)
3362 }
3363 #[doc = "Bit 4 - Break interrupt"]
3364 #[inline(always)]
3365 pub fn break_intr(&self) -> BreakIntrR {
3366 BreakIntrR::new(((self.bits >> 4) & 1) != 0)
3367 }
3368 #[doc = "Bit 5 - Data available in RX FIFO/RBR"]
3369 #[inline(always)]
3370 pub fn data_available(&self) -> DataAvailableR {
3371 DataAvailableR::new(((self.bits >> 5) & 1) != 0)
3372 }
3373 #[doc = "Bit 6 - THR empty flag"]
3374 #[inline(always)]
3375 pub fn thre_s(&self) -> ThreSR {
3376 ThreSR::new(((self.bits >> 6) & 1) != 0)
3377 }
3378 #[doc = "Bit 7 - Transmitter empty flag"]
3379 #[inline(always)]
3380 pub fn tx_empty_s(&self) -> TxEmptySR {
3381 TxEmptySR::new(((self.bits >> 7) & 1) != 0)
3382 }
3383 }
3384 impl W {}
3385 #[doc = "Line status register\n\nYou can [`read`](crate::Reg::read) this register and get [`line_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`line_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3386 pub struct LineStatusSpec;
3387 impl crate::RegisterSpec for LineStatusSpec {
3388 type Ux = u16;
3389 }
3390 #[doc = "`read()` method returns [`line_status::R`](R) reader structure"]
3391 impl crate::Readable for LineStatusSpec {}
3392 #[doc = "`write(|w| ..)` method takes [`line_status::W`](W) writer structure"]
3393 impl crate::Writable for LineStatusSpec {
3394 type Safety = crate::Unsafe;
3395 }
3396 #[doc = "`reset()` method sets LINE_STATUS to value 0xc0"]
3397 impl crate::Resettable for LineStatusSpec {
3398 const RESET_VALUE: u16 = 0xc0;
3399 }
3400 }
3401 #[doc = "UART_GP_REG (rw) register accessor: UART general purpose register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_gp_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_gp_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_gp_reg`] module"]
3402 #[doc(alias = "UART_GP_REG")]
3403 pub type UartGpReg = crate::Reg<uart_gp_reg::UartGpRegSpec>;
3404 #[doc = "UART general purpose register"]
3405 pub mod uart_gp_reg {
3406 #[doc = "Register `UART_GP_REG` reader"]
3407 pub type R = crate::R<UartGpRegSpec>;
3408 #[doc = "Register `UART_GP_REG` writer"]
3409 pub type W = crate::W<UartGpRegSpec>;
3410 #[doc = "Field `uart_gp_reg` reader - General purpose storage"]
3411 pub type UartGpRegR = crate::FieldReader;
3412 #[doc = "Field `uart_gp_reg` writer - General purpose storage"]
3413 pub type UartGpRegW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
3414 impl R {
3415 #[doc = "Bits 0:7 - General purpose storage"]
3416 #[inline(always)]
3417 pub fn uart_gp_reg(&self) -> UartGpRegR {
3418 UartGpRegR::new((self.bits & 0xff) as u8)
3419 }
3420 }
3421 impl W {
3422 #[doc = "Bits 0:7 - General purpose storage"]
3423 #[inline(always)]
3424 pub fn uart_gp_reg(&mut self) -> UartGpRegW<'_, UartGpRegSpec> {
3425 UartGpRegW::new(self, 0)
3426 }
3427 }
3428 #[doc = "UART general purpose register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_gp_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_gp_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3429 pub struct UartGpRegSpec;
3430 impl crate::RegisterSpec for UartGpRegSpec {
3431 type Ux = u16;
3432 }
3433 #[doc = "`read()` method returns [`uart_gp_reg::R`](R) reader structure"]
3434 impl crate::Readable for UartGpRegSpec {}
3435 #[doc = "`write(|w| ..)` method takes [`uart_gp_reg::W`](W) writer structure"]
3436 impl crate::Writable for UartGpRegSpec {
3437 type Safety = crate::Unsafe;
3438 }
3439 #[doc = "`reset()` method sets UART_GP_REG to value 0"]
3440 impl crate::Resettable for UartGpRegSpec {}
3441 }
3442 #[doc = "TX_FIFO_READ (rw) register accessor: TX FIFO read register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_read::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_read::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_fifo_read`] module"]
3443 #[doc(alias = "TX_FIFO_READ")]
3444 pub type TxFifoRead = crate::Reg<tx_fifo_read::TxFifoReadSpec>;
3445 #[doc = "TX FIFO read register"]
3446 pub mod tx_fifo_read {
3447 #[doc = "Register `TX_FIFO_READ` reader"]
3448 pub type R = crate::R<TxFifoReadSpec>;
3449 #[doc = "Register `TX_FIFO_READ` writer"]
3450 pub type W = crate::W<TxFifoReadSpec>;
3451 #[doc = "Field `tx_fifo_read` reader - TX FIFO top data"]
3452 pub type TxFifoReadR = crate::FieldReader;
3453 impl R {
3454 #[doc = "Bits 0:7 - TX FIFO top data"]
3455 #[inline(always)]
3456 pub fn tx_fifo_read(&self) -> TxFifoReadR {
3457 TxFifoReadR::new((self.bits & 0xff) as u8)
3458 }
3459 }
3460 impl W {}
3461 #[doc = "TX FIFO read register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_read::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_read::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3462 pub struct TxFifoReadSpec;
3463 impl crate::RegisterSpec for TxFifoReadSpec {
3464 type Ux = u16;
3465 }
3466 #[doc = "`read()` method returns [`tx_fifo_read::R`](R) reader structure"]
3467 impl crate::Readable for TxFifoReadSpec {}
3468 #[doc = "`write(|w| ..)` method takes [`tx_fifo_read::W`](W) writer structure"]
3469 impl crate::Writable for TxFifoReadSpec {
3470 type Safety = crate::Unsafe;
3471 }
3472 #[doc = "`reset()` method sets TX_FIFO_READ to value 0"]
3473 impl crate::Resettable for TxFifoReadSpec {}
3474 }
3475 #[doc = "RX_FIFO_WRITE (rw) register accessor: RX FIFO write register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_write::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_write::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_fifo_write`] module"]
3476 #[doc(alias = "RX_FIFO_WRITE")]
3477 pub type RxFifoWrite = crate::Reg<rx_fifo_write::RxFifoWriteSpec>;
3478 #[doc = "RX FIFO write register"]
3479 pub mod rx_fifo_write {
3480 #[doc = "Register `RX_FIFO_WRITE` reader"]
3481 pub type R = crate::R<RxFifoWriteSpec>;
3482 #[doc = "Register `RX_FIFO_WRITE` writer"]
3483 pub type W = crate::W<RxFifoWriteSpec>;
3484 #[doc = "Field `rx_fifo_write` reader - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
3485 pub type RxFifoWriteR = crate::FieldReader;
3486 #[doc = "Field `rx_fifo_write` writer - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
3487 pub type RxFifoWriteW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
3488 #[doc = "Field `rx_fifo_pe` writer - RX FIFO parity error"]
3489 pub type RxFifoPeW<'a, REG> = crate::BitWriter<'a, REG>;
3490 #[doc = "Field `rx_fifo_fe` writer - RX FIFO framing error"]
3491 pub type RxFifoFeW<'a, REG> = crate::BitWriter<'a, REG>;
3492 impl R {
3493 #[doc = "Bits 0:7 - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
3494 #[inline(always)]
3495 pub fn rx_fifo_write(&self) -> RxFifoWriteR {
3496 RxFifoWriteR::new((self.bits & 0xff) as u8)
3497 }
3498 }
3499 impl W {
3500 #[doc = "Bits 0:7 - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
3501 #[inline(always)]
3502 pub fn rx_fifo_write(&mut self) -> RxFifoWriteW<'_, RxFifoWriteSpec> {
3503 RxFifoWriteW::new(self, 0)
3504 }
3505 #[doc = "Bit 8 - RX FIFO parity error"]
3506 #[inline(always)]
3507 pub fn rx_fifo_pe(&mut self) -> RxFifoPeW<'_, RxFifoWriteSpec> {
3508 RxFifoPeW::new(self, 8)
3509 }
3510 #[doc = "Bit 9 - RX FIFO framing error"]
3511 #[inline(always)]
3512 pub fn rx_fifo_fe(&mut self) -> RxFifoFeW<'_, RxFifoWriteSpec> {
3513 RxFifoFeW::new(self, 9)
3514 }
3515 }
3516 #[doc = "RX FIFO write register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_write::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_write::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3517 pub struct RxFifoWriteSpec;
3518 impl crate::RegisterSpec for RxFifoWriteSpec {
3519 type Ux = u16;
3520 }
3521 #[doc = "`read()` method returns [`rx_fifo_write::R`](R) reader structure"]
3522 impl crate::Readable for RxFifoWriteSpec {}
3523 #[doc = "`write(|w| ..)` method takes [`rx_fifo_write::W`](W) writer structure"]
3524 impl crate::Writable for RxFifoWriteSpec {
3525 type Safety = crate::Unsafe;
3526 }
3527 #[doc = "`reset()` method sets RX_FIFO_WRITE to value 0"]
3528 impl crate::Resettable for RxFifoWriteSpec {}
3529 }
3530 #[doc = "FIFO_STATUS (rw) register accessor: FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_status`] module"]
3531 #[doc(alias = "FIFO_STATUS")]
3532 pub type FifoStatus = crate::Reg<fifo_status::FifoStatusSpec>;
3533 #[doc = "FIFO status register"]
3534 pub mod fifo_status {
3535 #[doc = "Register `FIFO_STATUS` reader"]
3536 pub type R = crate::R<FifoStatusSpec>;
3537 #[doc = "Register `FIFO_STATUS` writer"]
3538 pub type W = crate::W<FifoStatusSpec>;
3539 #[doc = "Field `tx_fifo_full` reader - TX FIFO full flag"]
3540 pub type TxFifoFullR = crate::BitReader;
3541 #[doc = "Field `tx_fifo_empty` reader - TX FIFO empty flag"]
3542 pub type TxFifoEmptyR = crate::BitReader;
3543 #[doc = "Field `rx_fifo_full` reader - RX FIFO full flag"]
3544 pub type RxFifoFullR = crate::BitReader;
3545 #[doc = "Field `rx_fifo_empty` reader - RX FIFO empty flag"]
3546 pub type RxFifoEmptyR = crate::BitReader;
3547 impl R {
3548 #[doc = "Bit 0 - TX FIFO full flag"]
3549 #[inline(always)]
3550 pub fn tx_fifo_full(&self) -> TxFifoFullR {
3551 TxFifoFullR::new((self.bits & 1) != 0)
3552 }
3553 #[doc = "Bit 1 - TX FIFO empty flag"]
3554 #[inline(always)]
3555 pub fn tx_fifo_empty(&self) -> TxFifoEmptyR {
3556 TxFifoEmptyR::new(((self.bits >> 1) & 1) != 0)
3557 }
3558 #[doc = "Bit 2 - RX FIFO full flag"]
3559 #[inline(always)]
3560 pub fn rx_fifo_full(&self) -> RxFifoFullR {
3561 RxFifoFullR::new(((self.bits >> 2) & 1) != 0)
3562 }
3563 #[doc = "Bit 3 - RX FIFO empty flag"]
3564 #[inline(always)]
3565 pub fn rx_fifo_empty(&self) -> RxFifoEmptyR {
3566 RxFifoEmptyR::new(((self.bits >> 3) & 1) != 0)
3567 }
3568 }
3569 impl W {}
3570 #[doc = "FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3571 pub struct FifoStatusSpec;
3572 impl crate::RegisterSpec for FifoStatusSpec {
3573 type Ux = u16;
3574 }
3575 #[doc = "`read()` method returns [`fifo_status::R`](R) reader structure"]
3576 impl crate::Readable for FifoStatusSpec {}
3577 #[doc = "`write(|w| ..)` method takes [`fifo_status::W`](W) writer structure"]
3578 impl crate::Writable for FifoStatusSpec {
3579 type Safety = crate::Unsafe;
3580 }
3581 #[doc = "`reset()` method sets FIFO_STATUS to value 0x02"]
3582 impl crate::Resettable for FifoStatusSpec {
3583 const RESET_VALUE: u16 = 0x02;
3584 }
3585 }
3586 #[doc = "TX_FIFO_CNT (rw) register accessor: TX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_fifo_cnt`] module"]
3587 #[doc(alias = "TX_FIFO_CNT")]
3588 pub type TxFifoCnt = crate::Reg<tx_fifo_cnt::TxFifoCntSpec>;
3589 #[doc = "TX FIFO data counter"]
3590 pub mod tx_fifo_cnt {
3591 #[doc = "Register `TX_FIFO_CNT` reader"]
3592 pub type R = crate::R<TxFifoCntSpec>;
3593 #[doc = "Register `TX_FIFO_CNT` writer"]
3594 pub type W = crate::W<TxFifoCntSpec>;
3595 #[doc = "Field `tx_fifo_level` reader - TX FIFO data count"]
3596 pub type TxFifoLevelR = crate::FieldReader;
3597 impl R {
3598 #[doc = "Bits 0:6 - TX FIFO data count"]
3599 #[inline(always)]
3600 pub fn tx_fifo_level(&self) -> TxFifoLevelR {
3601 TxFifoLevelR::new((self.bits & 0x7f) as u8)
3602 }
3603 }
3604 impl W {}
3605 #[doc = "TX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3606 pub struct TxFifoCntSpec;
3607 impl crate::RegisterSpec for TxFifoCntSpec {
3608 type Ux = u16;
3609 }
3610 #[doc = "`read()` method returns [`tx_fifo_cnt::R`](R) reader structure"]
3611 impl crate::Readable for TxFifoCntSpec {}
3612 #[doc = "`write(|w| ..)` method takes [`tx_fifo_cnt::W`](W) writer structure"]
3613 impl crate::Writable for TxFifoCntSpec {
3614 type Safety = crate::Unsafe;
3615 }
3616 #[doc = "`reset()` method sets TX_FIFO_CNT to value 0"]
3617 impl crate::Resettable for TxFifoCntSpec {}
3618 }
3619 #[doc = "RX_FIFO_CNT (rw) register accessor: RX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_fifo_cnt`] module"]
3620 #[doc(alias = "RX_FIFO_CNT")]
3621 pub type RxFifoCnt = crate::Reg<rx_fifo_cnt::RxFifoCntSpec>;
3622 #[doc = "RX FIFO data counter"]
3623 pub mod rx_fifo_cnt {
3624 #[doc = "Register `RX_FIFO_CNT` reader"]
3625 pub type R = crate::R<RxFifoCntSpec>;
3626 #[doc = "Register `RX_FIFO_CNT` writer"]
3627 pub type W = crate::W<RxFifoCntSpec>;
3628 impl W {}
3629 #[doc = "RX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3630 pub struct RxFifoCntSpec;
3631 impl crate::RegisterSpec for RxFifoCntSpec {
3632 type Ux = u16;
3633 }
3634 #[doc = "`read()` method returns [`rx_fifo_cnt::R`](R) reader structure"]
3635 impl crate::Readable for RxFifoCntSpec {}
3636 #[doc = "`write(|w| ..)` method takes [`rx_fifo_cnt::W`](W) writer structure"]
3637 impl crate::Writable for RxFifoCntSpec {
3638 type Safety = crate::Unsafe;
3639 }
3640 #[doc = "`reset()` method sets RX_FIFO_CNT to value 0"]
3641 impl crate::Resettable for RxFifoCntSpec {}
3642 }
3643 #[doc = "HALT_TX (rw) register accessor: TX halt register\n\nYou can [`read`](crate::Reg::read) this register and get [`halt_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halt_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@halt_tx`] module"]
3644 #[doc(alias = "HALT_TX")]
3645 pub type HaltTx = crate::Reg<halt_tx::HaltTxSpec>;
3646 #[doc = "TX halt register"]
3647 pub mod halt_tx {
3648 #[doc = "Register `HALT_TX` reader"]
3649 pub type R = crate::R<HaltTxSpec>;
3650 #[doc = "Register `HALT_TX` writer"]
3651 pub type W = crate::W<HaltTxSpec>;
3652 #[doc = "Field `halt_tx` reader - TX halt: 0=disabled; 1=enabled"]
3653 pub type HaltTxR = crate::BitReader;
3654 #[doc = "Field `halt_tx` writer - TX halt: 0=disabled; 1=enabled"]
3655 pub type HaltTxW<'a, REG> = crate::BitWriter<'a, REG>;
3656 impl R {
3657 #[doc = "Bit 0 - TX halt: 0=disabled; 1=enabled"]
3658 #[inline(always)]
3659 pub fn halt_tx(&self) -> HaltTxR {
3660 HaltTxR::new((self.bits & 1) != 0)
3661 }
3662 }
3663 impl W {
3664 #[doc = "Bit 0 - TX halt: 0=disabled; 1=enabled"]
3665 #[inline(always)]
3666 pub fn halt_tx(&mut self) -> HaltTxW<'_, HaltTxSpec> {
3667 HaltTxW::new(self, 0)
3668 }
3669 }
3670 #[doc = "TX halt register\n\nYou can [`read`](crate::Reg::read) this register and get [`halt_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halt_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3671 pub struct HaltTxSpec;
3672 impl crate::RegisterSpec for HaltTxSpec {
3673 type Ux = u16;
3674 }
3675 #[doc = "`read()` method returns [`halt_tx::R`](R) reader structure"]
3676 impl crate::Readable for HaltTxSpec {}
3677 #[doc = "`write(|w| ..)` method takes [`halt_tx::W`](W) writer structure"]
3678 impl crate::Writable for HaltTxSpec {
3679 type Safety = crate::Unsafe;
3680 }
3681 #[doc = "`reset()` method sets HALT_TX to value 0"]
3682 impl crate::Resettable for HaltTxSpec {}
3683 }
3684 #[doc = "DMA_SW_ACK (rw) register accessor: DMA software acknowledge register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sw_ack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sw_ack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_sw_ack`] module"]
3685 #[doc(alias = "DMA_SW_ACK")]
3686 pub type DmaSwAck = crate::Reg<dma_sw_ack::DmaSwAckSpec>;
3687 #[doc = "DMA software acknowledge register"]
3688 pub mod dma_sw_ack {
3689 #[doc = "Register `DMA_SW_ACK` reader"]
3690 pub type R = crate::R<DmaSwAckSpec>;
3691 #[doc = "Register `DMA_SW_ACK` writer"]
3692 pub type W = crate::W<DmaSwAckSpec>;
3693 #[doc = "Field `dma_sw_ack` writer - DMA software acknowledge (write-clear)"]
3694 pub type DmaSwAckW<'a, REG> = crate::BitWriter<'a, REG>;
3695 impl W {
3696 #[doc = "Bit 0 - DMA software acknowledge (write-clear)"]
3697 #[inline(always)]
3698 pub fn dma_sw_ack(&mut self) -> DmaSwAckW<'_, DmaSwAckSpec> {
3699 DmaSwAckW::new(self, 0)
3700 }
3701 }
3702 #[doc = "DMA software acknowledge register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sw_ack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sw_ack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3703 pub struct DmaSwAckSpec;
3704 impl crate::RegisterSpec for DmaSwAckSpec {
3705 type Ux = u16;
3706 }
3707 #[doc = "`read()` method returns [`dma_sw_ack::R`](R) reader structure"]
3708 impl crate::Readable for DmaSwAckSpec {}
3709 #[doc = "`write(|w| ..)` method takes [`dma_sw_ack::W`](W) writer structure"]
3710 impl crate::Writable for DmaSwAckSpec {
3711 type Safety = crate::Unsafe;
3712 }
3713 #[doc = "`reset()` method sets DMA_SW_ACK to value 0"]
3714 impl crate::Resettable for DmaSwAckSpec {}
3715 }
3716 #[doc = "BAUD_CTL (rw) register accessor: Baud rate control register\n\nYou can [`read`](crate::Reg::read) this register and get [`baud_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud_ctl`] module"]
3717 #[doc(alias = "BAUD_CTL")]
3718 pub type BaudCtl = crate::Reg<baud_ctl::BaudCtlSpec>;
3719 #[doc = "Baud rate control register"]
3720 pub mod baud_ctl {
3721 #[doc = "Register `BAUD_CTL` reader"]
3722 pub type R = crate::R<BaudCtlSpec>;
3723 #[doc = "Register `BAUD_CTL` writer"]
3724 pub type W = crate::W<BaudCtlSpec>;
3725 #[doc = "Baud rate oversampling: 0x7=8x; 0xF=16x\n\nValue on reset: 15"]
3726 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
3727 #[repr(u8)]
3728 pub enum BaudDiv {
3729 #[doc = "7: 8x oversampling"]
3730 Div8 = 7,
3731 #[doc = "15: 16x oversampling"]
3732 Div16 = 15,
3733 }
3734 impl From<BaudDiv> for u8 {
3735 #[inline(always)]
3736 fn from(variant: BaudDiv) -> Self {
3737 variant as _
3738 }
3739 }
3740 impl crate::FieldSpec for BaudDiv {
3741 type Ux = u8;
3742 }
3743 impl crate::IsEnum for BaudDiv {}
3744 #[doc = "Field `baud_div` reader - Baud rate oversampling: 0x7=8x; 0xF=16x"]
3745 pub type BaudDivR = crate::FieldReader<BaudDiv>;
3746 impl BaudDivR {
3747 #[doc = "Get enumerated values variant"]
3748 #[inline(always)]
3749 pub const fn variant(&self) -> Option<BaudDiv> {
3750 match self.bits {
3751 7 => Some(BaudDiv::Div8),
3752 15 => Some(BaudDiv::Div16),
3753 _ => None,
3754 }
3755 }
3756 #[doc = "8x oversampling"]
3757 #[inline(always)]
3758 pub fn is_div8(&self) -> bool {
3759 *self == BaudDiv::Div8
3760 }
3761 #[doc = "16x oversampling"]
3762 #[inline(always)]
3763 pub fn is_div16(&self) -> bool {
3764 *self == BaudDiv::Div16
3765 }
3766 }
3767 #[doc = "Field `baud_div` writer - Baud rate oversampling: 0x7=8x; 0xF=16x"]
3768 pub type BaudDivW<'a, REG> = crate::FieldWriter<'a, REG, 4, BaudDiv>;
3769 impl<'a, REG> BaudDivW<'a, REG>
3770 where
3771 REG: crate::Writable + crate::RegisterSpec,
3772 REG::Ux: From<u8>,
3773 {
3774 #[doc = "8x oversampling"]
3775 #[inline(always)]
3776 pub fn div8(self) -> &'a mut crate::W<REG> {
3777 self.variant(BaudDiv::Div8)
3778 }
3779 #[doc = "16x oversampling"]
3780 #[inline(always)]
3781 pub fn div16(self) -> &'a mut crate::W<REG> {
3782 self.variant(BaudDiv::Div16)
3783 }
3784 }
3785 #[doc = "Field `sample_phase` reader - RX sample phase"]
3786 pub type SamplePhaseR = crate::FieldReader;
3787 #[doc = "Field `sample_phase` writer - RX sample phase"]
3788 pub type SamplePhaseW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
3789 impl R {
3790 #[doc = "Bits 0:3 - Baud rate oversampling: 0x7=8x; 0xF=16x"]
3791 #[inline(always)]
3792 pub fn baud_div(&self) -> BaudDivR {
3793 BaudDivR::new((self.bits & 0x0f) as u8)
3794 }
3795 #[doc = "Bits 4:7 - RX sample phase"]
3796 #[inline(always)]
3797 pub fn sample_phase(&self) -> SamplePhaseR {
3798 SamplePhaseR::new(((self.bits >> 4) & 0x0f) as u8)
3799 }
3800 }
3801 impl W {
3802 #[doc = "Bits 0:3 - Baud rate oversampling: 0x7=8x; 0xF=16x"]
3803 #[inline(always)]
3804 pub fn baud_div(&mut self) -> BaudDivW<'_, BaudCtlSpec> {
3805 BaudDivW::new(self, 0)
3806 }
3807 #[doc = "Bits 4:7 - RX sample phase"]
3808 #[inline(always)]
3809 pub fn sample_phase(&mut self) -> SamplePhaseW<'_, BaudCtlSpec> {
3810 SamplePhaseW::new(self, 4)
3811 }
3812 }
3813 #[doc = "Baud rate control register\n\nYou can [`read`](crate::Reg::read) this register and get [`baud_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3814 pub struct BaudCtlSpec;
3815 impl crate::RegisterSpec for BaudCtlSpec {
3816 type Ux = u16;
3817 }
3818 #[doc = "`read()` method returns [`baud_ctl::R`](R) reader structure"]
3819 impl crate::Readable for BaudCtlSpec {}
3820 #[doc = "`write(|w| ..)` method takes [`baud_ctl::W`](W) writer structure"]
3821 impl crate::Writable for BaudCtlSpec {
3822 type Safety = crate::Unsafe;
3823 }
3824 #[doc = "`reset()` method sets BAUD_CTL to value 0x7f"]
3825 impl crate::Resettable for BaudCtlSpec {
3826 const RESET_VALUE: u16 = 0x7f;
3827 }
3828 }
3829 #[doc = "STP_CTL (rw) register accessor: Stop bit control register\n\nYou can [`read`](crate::Reg::read) this register and get [`stp_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stp_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stp_ctl`] module"]
3830 #[doc(alias = "STP_CTL")]
3831 pub type StpCtl = crate::Reg<stp_ctl::StpCtlSpec>;
3832 #[doc = "Stop bit control register"]
3833 pub mod stp_ctl {
3834 #[doc = "Register `STP_CTL` reader"]
3835 pub type R = crate::R<StpCtlSpec>;
3836 #[doc = "Register `STP_CTL` writer"]
3837 pub type W = crate::W<StpCtlSpec>;
3838 #[doc = "Field `rx_sp` reader - RX stop bits when stp_mode=1"]
3839 pub type RxSpR = crate::BitReader;
3840 #[doc = "Field `rx_sp` writer - RX stop bits when stp_mode=1"]
3841 pub type RxSpW<'a, REG> = crate::BitWriter<'a, REG>;
3842 #[doc = "Field `tx_sp` reader - TX stop bits when stp_mode=1"]
3843 pub type TxSpR = crate::BitReader;
3844 #[doc = "Field `tx_sp` writer - TX stop bits when stp_mode=1"]
3845 pub type TxSpW<'a, REG> = crate::BitWriter<'a, REG>;
3846 #[doc = "Field `stp_mode` reader - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
3847 pub type StpModeR = crate::BitReader;
3848 #[doc = "Field `stp_mode` writer - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
3849 pub type StpModeW<'a, REG> = crate::BitWriter<'a, REG>;
3850 impl R {
3851 #[doc = "Bit 0 - RX stop bits when stp_mode=1"]
3852 #[inline(always)]
3853 pub fn rx_sp(&self) -> RxSpR {
3854 RxSpR::new((self.bits & 1) != 0)
3855 }
3856 #[doc = "Bit 1 - TX stop bits when stp_mode=1"]
3857 #[inline(always)]
3858 pub fn tx_sp(&self) -> TxSpR {
3859 TxSpR::new(((self.bits >> 1) & 1) != 0)
3860 }
3861 #[doc = "Bit 2 - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
3862 #[inline(always)]
3863 pub fn stp_mode(&self) -> StpModeR {
3864 StpModeR::new(((self.bits >> 2) & 1) != 0)
3865 }
3866 }
3867 impl W {
3868 #[doc = "Bit 0 - RX stop bits when stp_mode=1"]
3869 #[inline(always)]
3870 pub fn rx_sp(&mut self) -> RxSpW<'_, StpCtlSpec> {
3871 RxSpW::new(self, 0)
3872 }
3873 #[doc = "Bit 1 - TX stop bits when stp_mode=1"]
3874 #[inline(always)]
3875 pub fn tx_sp(&mut self) -> TxSpW<'_, StpCtlSpec> {
3876 TxSpW::new(self, 1)
3877 }
3878 #[doc = "Bit 2 - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
3879 #[inline(always)]
3880 pub fn stp_mode(&mut self) -> StpModeW<'_, StpCtlSpec> {
3881 StpModeW::new(self, 2)
3882 }
3883 }
3884 #[doc = "Stop bit control register\n\nYou can [`read`](crate::Reg::read) this register and get [`stp_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stp_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3885 pub struct StpCtlSpec;
3886 impl crate::RegisterSpec for StpCtlSpec {
3887 type Ux = u16;
3888 }
3889 #[doc = "`read()` method returns [`stp_ctl::R`](R) reader structure"]
3890 impl crate::Readable for StpCtlSpec {}
3891 #[doc = "`write(|w| ..)` method takes [`stp_ctl::W`](W) writer structure"]
3892 impl crate::Writable for StpCtlSpec {
3893 type Safety = crate::Unsafe;
3894 }
3895 #[doc = "`reset()` method sets STP_CTL to value 0"]
3896 impl crate::Resettable for StpCtlSpec {}
3897 }
3898 #[doc = "UART_PARAMETER (rw) register accessor: UART parameter register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_parameter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_parameter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_parameter`] module"]
3899 #[doc(alias = "UART_PARAMETER")]
3900 pub type UartParameter = crate::Reg<uart_parameter::UartParameterSpec>;
3901 #[doc = "UART parameter register"]
3902 pub mod uart_parameter {
3903 #[doc = "Register `UART_PARAMETER` reader"]
3904 pub type R = crate::R<UartParameterSpec>;
3905 #[doc = "Register `UART_PARAMETER` writer"]
3906 pub type W = crate::W<UartParameterSpec>;
3907 #[doc = "Field `fifo_depth` reader - FIFO depth: 0x4=64"]
3908 pub type FifoDepthR = crate::FieldReader;
3909 #[doc = "Field `apb_data_width` reader - APB data width: 0x1=16bit"]
3910 pub type ApbDataWidthR = crate::FieldReader;
3911 #[doc = "Field `afce_mode` reader - AFCE mode: 0=disabled; 1=enabled"]
3912 pub type AfceModeR = crate::BitReader;
3913 #[doc = "Field `dma_mode` reader - DMA mode: 0=DMA_EXTRA disabled; 1=enabled"]
3914 pub type DmaModeR = crate::BitReader;
3915 #[doc = "Field `shadow` reader - Shadow feature enable"]
3916 pub type ShadowR = crate::BitReader;
3917 impl R {
3918 #[doc = "Bits 0:7 - FIFO depth: 0x4=64"]
3919 #[inline(always)]
3920 pub fn fifo_depth(&self) -> FifoDepthR {
3921 FifoDepthR::new((self.bits & 0xff) as u8)
3922 }
3923 #[doc = "Bits 8:9 - APB data width: 0x1=16bit"]
3924 #[inline(always)]
3925 pub fn apb_data_width(&self) -> ApbDataWidthR {
3926 ApbDataWidthR::new(((self.bits >> 8) & 3) as u8)
3927 }
3928 #[doc = "Bit 10 - AFCE mode: 0=disabled; 1=enabled"]
3929 #[inline(always)]
3930 pub fn afce_mode(&self) -> AfceModeR {
3931 AfceModeR::new(((self.bits >> 10) & 1) != 0)
3932 }
3933 #[doc = "Bit 11 - DMA mode: 0=DMA_EXTRA disabled; 1=enabled"]
3934 #[inline(always)]
3935 pub fn dma_mode(&self) -> DmaModeR {
3936 DmaModeR::new(((self.bits >> 11) & 1) != 0)
3937 }
3938 #[doc = "Bit 12 - Shadow feature enable"]
3939 #[inline(always)]
3940 pub fn shadow(&self) -> ShadowR {
3941 ShadowR::new(((self.bits >> 12) & 1) != 0)
3942 }
3943 }
3944 impl W {}
3945 #[doc = "UART parameter register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_parameter::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_parameter::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
3946 pub struct UartParameterSpec;
3947 impl crate::RegisterSpec for UartParameterSpec {
3948 type Ux = u16;
3949 }
3950 #[doc = "`read()` method returns [`uart_parameter::R`](R) reader structure"]
3951 impl crate::Readable for UartParameterSpec {}
3952 #[doc = "`write(|w| ..)` method takes [`uart_parameter::W`](W) writer structure"]
3953 impl crate::Writable for UartParameterSpec {
3954 type Safety = crate::Unsafe;
3955 }
3956 #[doc = "`reset()` method sets UART_PARAMETER to value 0x0d04"]
3957 impl crate::Resettable for UartParameterSpec {
3958 const RESET_VALUE: u16 = 0x0d04;
3959 }
3960 }
3961}
3962#[doc = "Timer module with 3 independent 32-bit timers (v150)"]
3963pub type Timer = crate::Periph<timer::RegisterBlock, 0x5200_2000>;
3964impl core::fmt::Debug for Timer {
3965 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
3966 f.debug_struct("Timer").finish()
3967 }
3968}
3969#[doc = "Timer module with 3 independent 32-bit timers (v150)"]
3970pub mod timer {
3971 #[repr(C)]
3972 #[doc = "Register block"]
3973 pub struct RegisterBlock {
3974 _reserved0: [u8; 0x60],
3975 abnor_intr_raw: AbnorIntrRaw,
3976 abnor_imsk: AbnorImsk,
3977 abnor_intr_stat: AbnorIntrStat,
3978 _reserved3: [u8; 0x0c],
3979 eoi_ren: EoiRen,
3980 raw_intr_stat: RawIntrStat,
3981 intr_stat: IntrStat,
3982 _reserved6: [u8; 0x7c],
3983 timer0_load_count: (),
3984 _reserved7: [u8; 0x08],
3985 timer0_current_value: (),
3986 _reserved8: [u8; 0x08],
3987 timer0_control: (),
3988 _reserved9: [u8; 0x04],
3989 timer0_eoi: (),
3990 _reserved10: [u8; 0x04],
3991 timer0_raw_intr: (),
3992 }
3993 impl RegisterBlock {
3994 #[doc = "0x60 - Abnormal interrupt raw status"]
3995 #[inline(always)]
3996 pub const fn abnor_intr_raw(&self) -> &AbnorIntrRaw {
3997 &self.abnor_intr_raw
3998 }
3999 #[doc = "0x64 - Abnormal interrupt mask"]
4000 #[inline(always)]
4001 pub const fn abnor_imsk(&self) -> &AbnorImsk {
4002 &self.abnor_imsk
4003 }
4004 #[doc = "0x68 - Abnormal interrupt status"]
4005 #[inline(always)]
4006 pub const fn abnor_intr_stat(&self) -> &AbnorIntrStat {
4007 &self.abnor_intr_stat
4008 }
4009 #[doc = "0x78 - End-of-interrupt register"]
4010 #[inline(always)]
4011 pub const fn eoi_ren(&self) -> &EoiRen {
4012 &self.eoi_ren
4013 }
4014 #[doc = "0x7c - Raw interrupt status"]
4015 #[inline(always)]
4016 pub const fn raw_intr_stat(&self) -> &RawIntrStat {
4017 &self.raw_intr_stat
4018 }
4019 #[doc = "0x80 - Interrupt status (masked)"]
4020 #[inline(always)]
4021 pub const fn intr_stat(&self) -> &IntrStat {
4022 &self.intr_stat
4023 }
4024 #[doc = "0x100..0x10c - Timer %s \\[dim=3\\] load count"]
4025 #[inline(always)]
4026 pub const fn timer0_load_count(&self, n: usize) -> &TimerLoadCount {
4027 #[allow(clippy::no_effect)]
4028 [(); 3][n];
4029 unsafe {
4030 &*core::ptr::from_ref(self)
4031 .cast::<u8>()
4032 .add(256)
4033 .add(256 * n)
4034 .cast()
4035 }
4036 }
4037 #[doc = "Iterator for array of:"]
4038 #[doc = "0x100..0x10c - Timer %s \\[dim=3\\] load count"]
4039 #[inline(always)]
4040 pub fn timer0_load_count_iter(&self) -> impl Iterator<Item = &TimerLoadCount> {
4041 (0..3).map(move |n| unsafe {
4042 &*core::ptr::from_ref(self)
4043 .cast::<u8>()
4044 .add(256)
4045 .add(256 * n)
4046 .cast()
4047 })
4048 }
4049 #[doc = "0x200 - Timer 1 \\[dim=3\\] load count"]
4050 #[inline(always)]
4051 pub const fn timer1_load_count(&self) -> &TimerLoadCount {
4052 self.timer0_load_count(1)
4053 }
4054 #[doc = "0x300 - Timer 2 \\[dim=3\\] load count"]
4055 #[inline(always)]
4056 pub const fn timer2_load_count(&self) -> &TimerLoadCount {
4057 self.timer0_load_count(2)
4058 }
4059 #[doc = "0x108..0x114 - Timer %s \\[dim=3\\] current value"]
4060 #[inline(always)]
4061 pub const fn timer0_current_value(&self, n: usize) -> &TimerCurrentValue {
4062 #[allow(clippy::no_effect)]
4063 [(); 3][n];
4064 unsafe {
4065 &*core::ptr::from_ref(self)
4066 .cast::<u8>()
4067 .add(264)
4068 .add(256 * n)
4069 .cast()
4070 }
4071 }
4072 #[doc = "Iterator for array of:"]
4073 #[doc = "0x108..0x114 - Timer %s \\[dim=3\\] current value"]
4074 #[inline(always)]
4075 pub fn timer0_current_value_iter(&self) -> impl Iterator<Item = &TimerCurrentValue> {
4076 (0..3).map(move |n| unsafe {
4077 &*core::ptr::from_ref(self)
4078 .cast::<u8>()
4079 .add(264)
4080 .add(256 * n)
4081 .cast()
4082 })
4083 }
4084 #[doc = "0x208 - Timer 1 \\[dim=3\\] current value"]
4085 #[inline(always)]
4086 pub const fn timer1_current_value(&self) -> &TimerCurrentValue {
4087 self.timer0_current_value(1)
4088 }
4089 #[doc = "0x308 - Timer 2 \\[dim=3\\] current value"]
4090 #[inline(always)]
4091 pub const fn timer2_current_value(&self) -> &TimerCurrentValue {
4092 self.timer0_current_value(2)
4093 }
4094 #[doc = "0x110..0x11c - Timer %s \\[dim=3\\] control register"]
4095 #[inline(always)]
4096 pub const fn timer0_control(&self, n: usize) -> &TimerControl {
4097 #[allow(clippy::no_effect)]
4098 [(); 3][n];
4099 unsafe {
4100 &*core::ptr::from_ref(self)
4101 .cast::<u8>()
4102 .add(272)
4103 .add(256 * n)
4104 .cast()
4105 }
4106 }
4107 #[doc = "Iterator for array of:"]
4108 #[doc = "0x110..0x11c - Timer %s \\[dim=3\\] control register"]
4109 #[inline(always)]
4110 pub fn timer0_control_iter(&self) -> impl Iterator<Item = &TimerControl> {
4111 (0..3).map(move |n| unsafe {
4112 &*core::ptr::from_ref(self)
4113 .cast::<u8>()
4114 .add(272)
4115 .add(256 * n)
4116 .cast()
4117 })
4118 }
4119 #[doc = "0x210 - Timer 1 \\[dim=3\\] control register"]
4120 #[inline(always)]
4121 pub const fn timer1_control(&self) -> &TimerControl {
4122 self.timer0_control(1)
4123 }
4124 #[doc = "0x310 - Timer 2 \\[dim=3\\] control register"]
4125 #[inline(always)]
4126 pub const fn timer2_control(&self) -> &TimerControl {
4127 self.timer0_control(2)
4128 }
4129 #[doc = "0x114..0x120 - Timer %s \\[dim=3\\] end-of-interrupt"]
4130 #[inline(always)]
4131 pub const fn timer0_eoi(&self, n: usize) -> &TimerEoi {
4132 #[allow(clippy::no_effect)]
4133 [(); 3][n];
4134 unsafe {
4135 &*core::ptr::from_ref(self)
4136 .cast::<u8>()
4137 .add(276)
4138 .add(256 * n)
4139 .cast()
4140 }
4141 }
4142 #[doc = "Iterator for array of:"]
4143 #[doc = "0x114..0x120 - Timer %s \\[dim=3\\] end-of-interrupt"]
4144 #[inline(always)]
4145 pub fn timer0_eoi_iter(&self) -> impl Iterator<Item = &TimerEoi> {
4146 (0..3).map(move |n| unsafe {
4147 &*core::ptr::from_ref(self)
4148 .cast::<u8>()
4149 .add(276)
4150 .add(256 * n)
4151 .cast()
4152 })
4153 }
4154 #[doc = "0x214 - Timer 1 \\[dim=3\\] end-of-interrupt"]
4155 #[inline(always)]
4156 pub const fn timer1_eoi(&self) -> &TimerEoi {
4157 self.timer0_eoi(1)
4158 }
4159 #[doc = "0x314 - Timer 2 \\[dim=3\\] end-of-interrupt"]
4160 #[inline(always)]
4161 pub const fn timer2_eoi(&self) -> &TimerEoi {
4162 self.timer0_eoi(2)
4163 }
4164 #[doc = "0x118..0x124 - Timer %s \\[dim=3\\] raw interrupt status"]
4165 #[inline(always)]
4166 pub const fn timer0_raw_intr(&self, n: usize) -> &TimerRawIntr {
4167 #[allow(clippy::no_effect)]
4168 [(); 3][n];
4169 unsafe {
4170 &*core::ptr::from_ref(self)
4171 .cast::<u8>()
4172 .add(280)
4173 .add(256 * n)
4174 .cast()
4175 }
4176 }
4177 #[doc = "Iterator for array of:"]
4178 #[doc = "0x118..0x124 - Timer %s \\[dim=3\\] raw interrupt status"]
4179 #[inline(always)]
4180 pub fn timer0_raw_intr_iter(&self) -> impl Iterator<Item = &TimerRawIntr> {
4181 (0..3).map(move |n| unsafe {
4182 &*core::ptr::from_ref(self)
4183 .cast::<u8>()
4184 .add(280)
4185 .add(256 * n)
4186 .cast()
4187 })
4188 }
4189 #[doc = "0x218 - Timer 1 \\[dim=3\\] raw interrupt status"]
4190 #[inline(always)]
4191 pub const fn timer1_raw_intr(&self) -> &TimerRawIntr {
4192 self.timer0_raw_intr(1)
4193 }
4194 #[doc = "0x318 - Timer 2 \\[dim=3\\] raw interrupt status"]
4195 #[inline(always)]
4196 pub const fn timer2_raw_intr(&self) -> &TimerRawIntr {
4197 self.timer0_raw_intr(2)
4198 }
4199 }
4200 #[doc = "ABNOR_INTR_RAW (rw) register accessor: Abnormal interrupt raw status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_intr_raw`] module"]
4201 #[doc(alias = "ABNOR_INTR_RAW")]
4202 pub type AbnorIntrRaw = crate::Reg<abnor_intr_raw::AbnorIntrRawSpec>;
4203 #[doc = "Abnormal interrupt raw status"]
4204 pub mod abnor_intr_raw {
4205 #[doc = "Register `ABNOR_INTR_RAW` reader"]
4206 pub type R = crate::R<AbnorIntrRawSpec>;
4207 #[doc = "Register `ABNOR_INTR_RAW` writer"]
4208 pub type W = crate::W<AbnorIntrRawSpec>;
4209 #[doc = "Field `abnor_intr_raw` reader - Abnormal interrupt raw status for all timers"]
4210 pub type AbnorIntrRawR = crate::FieldReader;
4211 impl R {
4212 #[doc = "Bits 0:2 - Abnormal interrupt raw status for all timers"]
4213 #[inline(always)]
4214 pub fn abnor_intr_raw(&self) -> AbnorIntrRawR {
4215 AbnorIntrRawR::new((self.bits & 7) as u8)
4216 }
4217 }
4218 impl W {}
4219 #[doc = "Abnormal interrupt raw status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4220 pub struct AbnorIntrRawSpec;
4221 impl crate::RegisterSpec for AbnorIntrRawSpec {
4222 type Ux = u32;
4223 }
4224 #[doc = "`read()` method returns [`abnor_intr_raw::R`](R) reader structure"]
4225 impl crate::Readable for AbnorIntrRawSpec {}
4226 #[doc = "`write(|w| ..)` method takes [`abnor_intr_raw::W`](W) writer structure"]
4227 impl crate::Writable for AbnorIntrRawSpec {
4228 type Safety = crate::Unsafe;
4229 }
4230 #[doc = "`reset()` method sets ABNOR_INTR_RAW to value 0"]
4231 impl crate::Resettable for AbnorIntrRawSpec {}
4232 }
4233 #[doc = "ABNOR_IMSK (rw) register accessor: Abnormal interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_imsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_imsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_imsk`] module"]
4234 #[doc(alias = "ABNOR_IMSK")]
4235 pub type AbnorImsk = crate::Reg<abnor_imsk::AbnorImskSpec>;
4236 #[doc = "Abnormal interrupt mask"]
4237 pub mod abnor_imsk {
4238 #[doc = "Register `ABNOR_IMSK` reader"]
4239 pub type R = crate::R<AbnorImskSpec>;
4240 #[doc = "Register `ABNOR_IMSK` writer"]
4241 pub type W = crate::W<AbnorImskSpec>;
4242 #[doc = "Field `abnor_imsk` reader - Abnormal interrupt mask for all timers"]
4243 pub type AbnorImskR = crate::FieldReader;
4244 #[doc = "Field `abnor_imsk` writer - Abnormal interrupt mask for all timers"]
4245 pub type AbnorImskW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
4246 impl R {
4247 #[doc = "Bits 0:2 - Abnormal interrupt mask for all timers"]
4248 #[inline(always)]
4249 pub fn abnor_imsk(&self) -> AbnorImskR {
4250 AbnorImskR::new((self.bits & 7) as u8)
4251 }
4252 }
4253 impl W {
4254 #[doc = "Bits 0:2 - Abnormal interrupt mask for all timers"]
4255 #[inline(always)]
4256 pub fn abnor_imsk(&mut self) -> AbnorImskW<'_, AbnorImskSpec> {
4257 AbnorImskW::new(self, 0)
4258 }
4259 }
4260 #[doc = "Abnormal interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_imsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_imsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4261 pub struct AbnorImskSpec;
4262 impl crate::RegisterSpec for AbnorImskSpec {
4263 type Ux = u32;
4264 }
4265 #[doc = "`read()` method returns [`abnor_imsk::R`](R) reader structure"]
4266 impl crate::Readable for AbnorImskSpec {}
4267 #[doc = "`write(|w| ..)` method takes [`abnor_imsk::W`](W) writer structure"]
4268 impl crate::Writable for AbnorImskSpec {
4269 type Safety = crate::Unsafe;
4270 }
4271 #[doc = "`reset()` method sets ABNOR_IMSK to value 0"]
4272 impl crate::Resettable for AbnorImskSpec {}
4273 }
4274 #[doc = "ABNOR_INTR_STAT (rw) register accessor: Abnormal interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_intr_stat`] module"]
4275 #[doc(alias = "ABNOR_INTR_STAT")]
4276 pub type AbnorIntrStat = crate::Reg<abnor_intr_stat::AbnorIntrStatSpec>;
4277 #[doc = "Abnormal interrupt status"]
4278 pub mod abnor_intr_stat {
4279 #[doc = "Register `ABNOR_INTR_STAT` reader"]
4280 pub type R = crate::R<AbnorIntrStatSpec>;
4281 #[doc = "Register `ABNOR_INTR_STAT` writer"]
4282 pub type W = crate::W<AbnorIntrStatSpec>;
4283 #[doc = "Field `abnor_intr_stat` reader - Abnormal interrupt status for all timers"]
4284 pub type AbnorIntrStatR = crate::FieldReader;
4285 impl R {
4286 #[doc = "Bits 0:2 - Abnormal interrupt status for all timers"]
4287 #[inline(always)]
4288 pub fn abnor_intr_stat(&self) -> AbnorIntrStatR {
4289 AbnorIntrStatR::new((self.bits & 7) as u8)
4290 }
4291 }
4292 impl W {}
4293 #[doc = "Abnormal interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4294 pub struct AbnorIntrStatSpec;
4295 impl crate::RegisterSpec for AbnorIntrStatSpec {
4296 type Ux = u32;
4297 }
4298 #[doc = "`read()` method returns [`abnor_intr_stat::R`](R) reader structure"]
4299 impl crate::Readable for AbnorIntrStatSpec {}
4300 #[doc = "`write(|w| ..)` method takes [`abnor_intr_stat::W`](W) writer structure"]
4301 impl crate::Writable for AbnorIntrStatSpec {
4302 type Safety = crate::Unsafe;
4303 }
4304 #[doc = "`reset()` method sets ABNOR_INTR_STAT to value 0"]
4305 impl crate::Resettable for AbnorIntrStatSpec {}
4306 }
4307 #[doc = "EOI_REN (rw) register accessor: End-of-interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi_ren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi_ren`] module"]
4308 #[doc(alias = "EOI_REN")]
4309 pub type EoiRen = crate::Reg<eoi_ren::EoiRenSpec>;
4310 #[doc = "End-of-interrupt register"]
4311 pub mod eoi_ren {
4312 #[doc = "Register `EOI_REN` reader"]
4313 pub type R = crate::R<EoiRenSpec>;
4314 #[doc = "Register `EOI_REN` writer"]
4315 pub type W = crate::W<EoiRenSpec>;
4316 #[doc = "Field `eoi` reader - Clear interrupts for all timers (read to clear)"]
4317 pub type EoiR = crate::FieldReader;
4318 impl R {
4319 #[doc = "Bits 0:2 - Clear interrupts for all timers (read to clear)"]
4320 #[inline(always)]
4321 pub fn eoi(&self) -> EoiR {
4322 EoiR::new((self.bits & 7) as u8)
4323 }
4324 }
4325 impl W {}
4326 #[doc = "End-of-interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi_ren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4327 pub struct EoiRenSpec;
4328 impl crate::RegisterSpec for EoiRenSpec {
4329 type Ux = u32;
4330 }
4331 #[doc = "`read()` method returns [`eoi_ren::R`](R) reader structure"]
4332 impl crate::Readable for EoiRenSpec {}
4333 #[doc = "`write(|w| ..)` method takes [`eoi_ren::W`](W) writer structure"]
4334 impl crate::Writable for EoiRenSpec {
4335 type Safety = crate::Unsafe;
4336 }
4337 #[doc = "`reset()` method sets EOI_REN to value 0"]
4338 impl crate::Resettable for EoiRenSpec {}
4339 }
4340 #[doc = "RAW_INTR_STAT (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"]
4341 #[doc(alias = "RAW_INTR_STAT")]
4342 pub type RawIntrStat = crate::Reg<raw_intr_stat::RawIntrStatSpec>;
4343 #[doc = "Raw interrupt status"]
4344 pub mod raw_intr_stat {
4345 #[doc = "Register `RAW_INTR_STAT` reader"]
4346 pub type R = crate::R<RawIntrStatSpec>;
4347 #[doc = "Register `RAW_INTR_STAT` writer"]
4348 pub type W = crate::W<RawIntrStatSpec>;
4349 #[doc = "Field `raw_intr` reader - Raw interrupt status for all timers"]
4350 pub type RawIntrR = crate::FieldReader;
4351 impl R {
4352 #[doc = "Bits 0:2 - Raw interrupt status for all timers"]
4353 #[inline(always)]
4354 pub fn raw_intr(&self) -> RawIntrR {
4355 RawIntrR::new((self.bits & 7) as u8)
4356 }
4357 }
4358 impl W {}
4359 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4360 pub struct RawIntrStatSpec;
4361 impl crate::RegisterSpec for RawIntrStatSpec {
4362 type Ux = u32;
4363 }
4364 #[doc = "`read()` method returns [`raw_intr_stat::R`](R) reader structure"]
4365 impl crate::Readable for RawIntrStatSpec {}
4366 #[doc = "`write(|w| ..)` method takes [`raw_intr_stat::W`](W) writer structure"]
4367 impl crate::Writable for RawIntrStatSpec {
4368 type Safety = crate::Unsafe;
4369 }
4370 #[doc = "`reset()` method sets RAW_INTR_STAT to value 0"]
4371 impl crate::Resettable for RawIntrStatSpec {}
4372 }
4373 #[doc = "INTR_STAT (rw) register accessor: Interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"]
4374 #[doc(alias = "INTR_STAT")]
4375 pub type IntrStat = crate::Reg<intr_stat::IntrStatSpec>;
4376 #[doc = "Interrupt status (masked)"]
4377 pub mod intr_stat {
4378 #[doc = "Register `INTR_STAT` reader"]
4379 pub type R = crate::R<IntrStatSpec>;
4380 #[doc = "Register `INTR_STAT` writer"]
4381 pub type W = crate::W<IntrStatSpec>;
4382 #[doc = "Field `intr_stat` reader - Interrupt status for all timers (after mask)"]
4383 pub type IntrStatR = crate::FieldReader;
4384 impl R {
4385 #[doc = "Bits 0:2 - Interrupt status for all timers (after mask)"]
4386 #[inline(always)]
4387 pub fn intr_stat(&self) -> IntrStatR {
4388 IntrStatR::new((self.bits & 7) as u8)
4389 }
4390 }
4391 impl W {}
4392 #[doc = "Interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4393 pub struct IntrStatSpec;
4394 impl crate::RegisterSpec for IntrStatSpec {
4395 type Ux = u32;
4396 }
4397 #[doc = "`read()` method returns [`intr_stat::R`](R) reader structure"]
4398 impl crate::Readable for IntrStatSpec {}
4399 #[doc = "`write(|w| ..)` method takes [`intr_stat::W`](W) writer structure"]
4400 impl crate::Writable for IntrStatSpec {
4401 type Safety = crate::Unsafe;
4402 }
4403 #[doc = "`reset()` method sets INTR_STAT to value 0"]
4404 impl crate::Resettable for IntrStatSpec {}
4405 }
4406 #[doc = "TIMER_LOAD_COUNT (rw) register accessor: Timer %s \\[dim=3\\] load count\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_load_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_load_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_load_count`] module"]
4407 #[doc(alias = "TIMER_LOAD_COUNT")]
4408 pub type TimerLoadCount = crate::Reg<timer_load_count::TimerLoadCountSpec>;
4409 #[doc = "Timer %s \\[dim=3\\] load count"]
4410 pub mod timer_load_count {
4411 #[doc = "Register `TIMER%s_LOAD_COUNT` reader"]
4412 pub type R = crate::R<TimerLoadCountSpec>;
4413 #[doc = "Register `TIMER%s_LOAD_COUNT` writer"]
4414 pub type W = crate::W<TimerLoadCountSpec>;
4415 #[doc = "Field `load_count` reader - Timer 0 load count value"]
4416 pub type LoadCountR = crate::FieldReader<u32>;
4417 #[doc = "Field `load_count` writer - Timer 0 load count value"]
4418 pub type LoadCountW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
4419 impl R {
4420 #[doc = "Bits 0:31 - Timer 0 load count value"]
4421 #[inline(always)]
4422 pub fn load_count(&self) -> LoadCountR {
4423 LoadCountR::new(self.bits)
4424 }
4425 }
4426 impl W {
4427 #[doc = "Bits 0:31 - Timer 0 load count value"]
4428 #[inline(always)]
4429 pub fn load_count(&mut self) -> LoadCountW<'_, TimerLoadCountSpec> {
4430 LoadCountW::new(self, 0)
4431 }
4432 }
4433 #[doc = "Timer %s \\[dim=3\\] load count\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_load_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_load_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4434 pub struct TimerLoadCountSpec;
4435 impl crate::RegisterSpec for TimerLoadCountSpec {
4436 type Ux = u32;
4437 }
4438 #[doc = "`read()` method returns [`timer_load_count::R`](R) reader structure"]
4439 impl crate::Readable for TimerLoadCountSpec {}
4440 #[doc = "`write(|w| ..)` method takes [`timer_load_count::W`](W) writer structure"]
4441 impl crate::Writable for TimerLoadCountSpec {
4442 type Safety = crate::Unsafe;
4443 }
4444 #[doc = "`reset()` method sets TIMER%s_LOAD_COUNT to value 0"]
4445 impl crate::Resettable for TimerLoadCountSpec {}
4446 }
4447 #[doc = "TIMER_CURRENT_VALUE (rw) register accessor: Timer %s \\[dim=3\\] current value\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_current_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_current_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_current_value`] module"]
4448 #[doc(alias = "TIMER_CURRENT_VALUE")]
4449 pub type TimerCurrentValue = crate::Reg<timer_current_value::TimerCurrentValueSpec>;
4450 #[doc = "Timer %s \\[dim=3\\] current value"]
4451 pub mod timer_current_value {
4452 #[doc = "Register `TIMER%s_CURRENT_VALUE` reader"]
4453 pub type R = crate::R<TimerCurrentValueSpec>;
4454 #[doc = "Register `TIMER%s_CURRENT_VALUE` writer"]
4455 pub type W = crate::W<TimerCurrentValueSpec>;
4456 #[doc = "Field `current_value` reader - Timer 0 current count value"]
4457 pub type CurrentValueR = crate::FieldReader<u32>;
4458 impl R {
4459 #[doc = "Bits 0:31 - Timer 0 current count value"]
4460 #[inline(always)]
4461 pub fn current_value(&self) -> CurrentValueR {
4462 CurrentValueR::new(self.bits)
4463 }
4464 }
4465 impl W {}
4466 #[doc = "Timer %s \\[dim=3\\] current value\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_current_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_current_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4467 pub struct TimerCurrentValueSpec;
4468 impl crate::RegisterSpec for TimerCurrentValueSpec {
4469 type Ux = u32;
4470 }
4471 #[doc = "`read()` method returns [`timer_current_value::R`](R) reader structure"]
4472 impl crate::Readable for TimerCurrentValueSpec {}
4473 #[doc = "`write(|w| ..)` method takes [`timer_current_value::W`](W) writer structure"]
4474 impl crate::Writable for TimerCurrentValueSpec {
4475 type Safety = crate::Unsafe;
4476 }
4477 #[doc = "`reset()` method sets TIMER%s_CURRENT_VALUE to value 0"]
4478 impl crate::Resettable for TimerCurrentValueSpec {}
4479 }
4480 #[doc = "TIMER_CONTROL (rw) register accessor: Timer %s \\[dim=3\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_control`] module"]
4481 #[doc(alias = "TIMER_CONTROL")]
4482 pub type TimerControl = crate::Reg<timer_control::TimerControlSpec>;
4483 #[doc = "Timer %s \\[dim=3\\] control register"]
4484 pub mod timer_control {
4485 #[doc = "Register `TIMER%s_CONTROL` reader"]
4486 pub type R = crate::R<TimerControlSpec>;
4487 #[doc = "Register `TIMER%s_CONTROL` writer"]
4488 pub type W = crate::W<TimerControlSpec>;
4489 #[doc = "Field `enable` reader - Timer enable: 0=disabled; 1=enabled"]
4490 pub type EnableR = crate::BitReader;
4491 #[doc = "Field `enable` writer - Timer enable: 0=disabled; 1=enabled"]
4492 pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
4493 #[doc = "Timer mode: 00=free running; 01=one-shot; 10=periodic\n\nValue on reset: 0"]
4494 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
4495 #[repr(u8)]
4496 pub enum Mode {
4497 #[doc = "0: Free-running mode"]
4498 FreeRunning = 0,
4499 #[doc = "1: One-shot mode"]
4500 OneShot = 1,
4501 #[doc = "2: Periodic mode"]
4502 Periodic = 2,
4503 }
4504 impl From<Mode> for u8 {
4505 #[inline(always)]
4506 fn from(variant: Mode) -> Self {
4507 variant as _
4508 }
4509 }
4510 impl crate::FieldSpec for Mode {
4511 type Ux = u8;
4512 }
4513 impl crate::IsEnum for Mode {}
4514 #[doc = "Field `mode` reader - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
4515 pub type ModeR = crate::FieldReader<Mode>;
4516 impl ModeR {
4517 #[doc = "Get enumerated values variant"]
4518 #[inline(always)]
4519 pub const fn variant(&self) -> Option<Mode> {
4520 match self.bits {
4521 0 => Some(Mode::FreeRunning),
4522 1 => Some(Mode::OneShot),
4523 2 => Some(Mode::Periodic),
4524 _ => None,
4525 }
4526 }
4527 #[doc = "Free-running mode"]
4528 #[inline(always)]
4529 pub fn is_free_running(&self) -> bool {
4530 *self == Mode::FreeRunning
4531 }
4532 #[doc = "One-shot mode"]
4533 #[inline(always)]
4534 pub fn is_one_shot(&self) -> bool {
4535 *self == Mode::OneShot
4536 }
4537 #[doc = "Periodic mode"]
4538 #[inline(always)]
4539 pub fn is_periodic(&self) -> bool {
4540 *self == Mode::Periodic
4541 }
4542 }
4543 #[doc = "Field `mode` writer - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
4544 pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mode>;
4545 impl<'a, REG> ModeW<'a, REG>
4546 where
4547 REG: crate::Writable + crate::RegisterSpec,
4548 REG::Ux: From<u8>,
4549 {
4550 #[doc = "Free-running mode"]
4551 #[inline(always)]
4552 pub fn free_running(self) -> &'a mut crate::W<REG> {
4553 self.variant(Mode::FreeRunning)
4554 }
4555 #[doc = "One-shot mode"]
4556 #[inline(always)]
4557 pub fn one_shot(self) -> &'a mut crate::W<REG> {
4558 self.variant(Mode::OneShot)
4559 }
4560 #[doc = "Periodic mode"]
4561 #[inline(always)]
4562 pub fn periodic(self) -> &'a mut crate::W<REG> {
4563 self.variant(Mode::Periodic)
4564 }
4565 }
4566 #[doc = "Field `int_mask` reader - Interrupt mask: 0=unmasked; 1=masked"]
4567 pub type IntMaskR = crate::BitReader;
4568 #[doc = "Field `int_mask` writer - Interrupt mask: 0=unmasked; 1=masked"]
4569 pub type IntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
4570 #[doc = "Field `rstfsm` writer - Reset FSM: 1=reset timer FSM"]
4571 pub type RstfsmW<'a, REG> = crate::BitWriter<'a, REG>;
4572 impl R {
4573 #[doc = "Bit 0 - Timer enable: 0=disabled; 1=enabled"]
4574 #[inline(always)]
4575 pub fn enable(&self) -> EnableR {
4576 EnableR::new((self.bits & 1) != 0)
4577 }
4578 #[doc = "Bits 1:2 - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
4579 #[inline(always)]
4580 pub fn mode(&self) -> ModeR {
4581 ModeR::new(((self.bits >> 1) & 3) as u8)
4582 }
4583 #[doc = "Bit 3 - Interrupt mask: 0=unmasked; 1=masked"]
4584 #[inline(always)]
4585 pub fn int_mask(&self) -> IntMaskR {
4586 IntMaskR::new(((self.bits >> 3) & 1) != 0)
4587 }
4588 }
4589 impl W {
4590 #[doc = "Bit 0 - Timer enable: 0=disabled; 1=enabled"]
4591 #[inline(always)]
4592 pub fn enable(&mut self) -> EnableW<'_, TimerControlSpec> {
4593 EnableW::new(self, 0)
4594 }
4595 #[doc = "Bits 1:2 - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
4596 #[inline(always)]
4597 pub fn mode(&mut self) -> ModeW<'_, TimerControlSpec> {
4598 ModeW::new(self, 1)
4599 }
4600 #[doc = "Bit 3 - Interrupt mask: 0=unmasked; 1=masked"]
4601 #[inline(always)]
4602 pub fn int_mask(&mut self) -> IntMaskW<'_, TimerControlSpec> {
4603 IntMaskW::new(self, 3)
4604 }
4605 #[doc = "Bit 4 - Reset FSM: 1=reset timer FSM"]
4606 #[inline(always)]
4607 pub fn rstfsm(&mut self) -> RstfsmW<'_, TimerControlSpec> {
4608 RstfsmW::new(self, 4)
4609 }
4610 }
4611 #[doc = "Timer %s \\[dim=3\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4612 pub struct TimerControlSpec;
4613 impl crate::RegisterSpec for TimerControlSpec {
4614 type Ux = u32;
4615 }
4616 #[doc = "`read()` method returns [`timer_control::R`](R) reader structure"]
4617 impl crate::Readable for TimerControlSpec {}
4618 #[doc = "`write(|w| ..)` method takes [`timer_control::W`](W) writer structure"]
4619 impl crate::Writable for TimerControlSpec {
4620 type Safety = crate::Unsafe;
4621 }
4622 #[doc = "`reset()` method sets TIMER%s_CONTROL to value 0"]
4623 impl crate::Resettable for TimerControlSpec {}
4624 }
4625 #[doc = "TIMER_EOI (rw) register accessor: Timer %s \\[dim=3\\] end-of-interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_eoi`] module"]
4626 #[doc(alias = "TIMER_EOI")]
4627 pub type TimerEoi = crate::Reg<timer_eoi::TimerEoiSpec>;
4628 #[doc = "Timer %s \\[dim=3\\] end-of-interrupt"]
4629 pub mod timer_eoi {
4630 #[doc = "Register `TIMER%s_EOI` reader"]
4631 pub type R = crate::R<TimerEoiSpec>;
4632 #[doc = "Register `TIMER%s_EOI` writer"]
4633 pub type W = crate::W<TimerEoiSpec>;
4634 #[doc = "Field `eoi` reader - Read to clear timer 0 interrupt"]
4635 pub type EoiR = crate::BitReader;
4636 impl R {
4637 #[doc = "Bit 0 - Read to clear timer 0 interrupt"]
4638 #[inline(always)]
4639 pub fn eoi(&self) -> EoiR {
4640 EoiR::new((self.bits & 1) != 0)
4641 }
4642 }
4643 impl W {}
4644 #[doc = "Timer %s \\[dim=3\\] end-of-interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4645 pub struct TimerEoiSpec;
4646 impl crate::RegisterSpec for TimerEoiSpec {
4647 type Ux = u32;
4648 }
4649 #[doc = "`read()` method returns [`timer_eoi::R`](R) reader structure"]
4650 impl crate::Readable for TimerEoiSpec {}
4651 #[doc = "`write(|w| ..)` method takes [`timer_eoi::W`](W) writer structure"]
4652 impl crate::Writable for TimerEoiSpec {
4653 type Safety = crate::Unsafe;
4654 }
4655 #[doc = "`reset()` method sets TIMER%s_EOI to value 0"]
4656 impl crate::Resettable for TimerEoiSpec {}
4657 }
4658 #[doc = "TIMER_RAW_INTR (rw) register accessor: Timer %s \\[dim=3\\] raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_raw_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_raw_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_raw_intr`] module"]
4659 #[doc(alias = "TIMER_RAW_INTR")]
4660 pub type TimerRawIntr = crate::Reg<timer_raw_intr::TimerRawIntrSpec>;
4661 #[doc = "Timer %s \\[dim=3\\] raw interrupt status"]
4662 pub mod timer_raw_intr {
4663 #[doc = "Register `TIMER%s_RAW_INTR` reader"]
4664 pub type R = crate::R<TimerRawIntrSpec>;
4665 #[doc = "Register `TIMER%s_RAW_INTR` writer"]
4666 pub type W = crate::W<TimerRawIntrSpec>;
4667 #[doc = "Field `raw_intr` reader - Raw interrupt status"]
4668 pub type RawIntrR = crate::BitReader;
4669 impl R {
4670 #[doc = "Bit 0 - Raw interrupt status"]
4671 #[inline(always)]
4672 pub fn raw_intr(&self) -> RawIntrR {
4673 RawIntrR::new((self.bits & 1) != 0)
4674 }
4675 }
4676 impl W {}
4677 #[doc = "Timer %s \\[dim=3\\] raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_raw_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_raw_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4678 pub struct TimerRawIntrSpec;
4679 impl crate::RegisterSpec for TimerRawIntrSpec {
4680 type Ux = u32;
4681 }
4682 #[doc = "`read()` method returns [`timer_raw_intr::R`](R) reader structure"]
4683 impl crate::Readable for TimerRawIntrSpec {}
4684 #[doc = "`write(|w| ..)` method takes [`timer_raw_intr::W`](W) writer structure"]
4685 impl crate::Writable for TimerRawIntrSpec {
4686 type Safety = crate::Unsafe;
4687 }
4688 #[doc = "`reset()` method sets TIMER%s_RAW_INTR to value 0"]
4689 impl crate::Resettable for TimerRawIntrSpec {}
4690 }
4691}
4692#[doc = "Watchdog timer (v151)"]
4693pub type Wdt = crate::Periph<wdt::RegisterBlock, 0x5200_3000>;
4694impl core::fmt::Debug for Wdt {
4695 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
4696 f.debug_struct("Wdt").finish()
4697 }
4698}
4699#[doc = "Watchdog timer (v151)"]
4700pub mod wdt {
4701 #[repr(C)]
4702 #[doc = "Register block"]
4703 pub struct RegisterBlock {
4704 wdt_lock: WdtLock,
4705 wdt_load: WdtLoad,
4706 wdt_restart: WdtRestart,
4707 wdt_eoi: WdtEoi,
4708 wdt_cr: WdtCr,
4709 wdt_cnt: WdtCnt,
4710 wdt_raw_intr: WdtRawIntr,
4711 wdt_intr: WdtIntr,
4712 wdt_lpif_state: WdtLpifState,
4713 wdt_status: WdtStatus,
4714 wdt_ccvr_en: WdtCcvrEn,
4715 }
4716 impl RegisterBlock {
4717 #[doc = "0x00 - Watchdog lock register"]
4718 #[inline(always)]
4719 pub const fn wdt_lock(&self) -> &WdtLock {
4720 &self.wdt_lock
4721 }
4722 #[doc = "0x04 - Watchdog load value"]
4723 #[inline(always)]
4724 pub const fn wdt_load(&self) -> &WdtLoad {
4725 &self.wdt_load
4726 }
4727 #[doc = "0x08 - Watchdog restart register"]
4728 #[inline(always)]
4729 pub const fn wdt_restart(&self) -> &WdtRestart {
4730 &self.wdt_restart
4731 }
4732 #[doc = "0x0c - Watchdog interrupt clear (read to clear)"]
4733 #[inline(always)]
4734 pub const fn wdt_eoi(&self) -> &WdtEoi {
4735 &self.wdt_eoi
4736 }
4737 #[doc = "0x10 - Watchdog control register"]
4738 #[inline(always)]
4739 pub const fn wdt_cr(&self) -> &WdtCr {
4740 &self.wdt_cr
4741 }
4742 #[doc = "0x14 - Watchdog current counter value"]
4743 #[inline(always)]
4744 pub const fn wdt_cnt(&self) -> &WdtCnt {
4745 &self.wdt_cnt
4746 }
4747 #[doc = "0x18 - Watchdog raw interrupt status"]
4748 #[inline(always)]
4749 pub const fn wdt_raw_intr(&self) -> &WdtRawIntr {
4750 &self.wdt_raw_intr
4751 }
4752 #[doc = "0x1c - Watchdog interrupt status (masked)"]
4753 #[inline(always)]
4754 pub const fn wdt_intr(&self) -> &WdtIntr {
4755 &self.wdt_intr
4756 }
4757 #[doc = "0x20 - Watchdog low power state"]
4758 #[inline(always)]
4759 pub const fn wdt_lpif_state(&self) -> &WdtLpifState {
4760 &self.wdt_lpif_state
4761 }
4762 #[doc = "0x24 - Watchdog status"]
4763 #[inline(always)]
4764 pub const fn wdt_status(&self) -> &WdtStatus {
4765 &self.wdt_status
4766 }
4767 #[doc = "0x28 - Watchdog counter value request"]
4768 #[inline(always)]
4769 pub const fn wdt_ccvr_en(&self) -> &WdtCcvrEn {
4770 &self.wdt_ccvr_en
4771 }
4772 }
4773 #[doc = "WDT_LOCK (rw) register accessor: Watchdog lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_lock`] module"]
4774 #[doc(alias = "WDT_LOCK")]
4775 pub type WdtLock = crate::Reg<wdt_lock::WdtLockSpec>;
4776 #[doc = "Watchdog lock register"]
4777 pub mod wdt_lock {
4778 #[doc = "Register `WDT_LOCK` reader"]
4779 pub type R = crate::R<WdtLockSpec>;
4780 #[doc = "Register `WDT_LOCK` writer"]
4781 pub type W = crate::W<WdtLockSpec>;
4782 #[doc = "Field `wdt_lock` writer - Write 0x5A5A5A5A to unlock, other values lock"]
4783 pub type WdtLockW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
4784 impl W {
4785 #[doc = "Bits 0:31 - Write 0x5A5A5A5A to unlock, other values lock"]
4786 #[inline(always)]
4787 pub fn wdt_lock(&mut self) -> WdtLockW<'_, WdtLockSpec> {
4788 WdtLockW::new(self, 0)
4789 }
4790 }
4791 #[doc = "Watchdog lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4792 pub struct WdtLockSpec;
4793 impl crate::RegisterSpec for WdtLockSpec {
4794 type Ux = u32;
4795 }
4796 #[doc = "`read()` method returns [`wdt_lock::R`](R) reader structure"]
4797 impl crate::Readable for WdtLockSpec {}
4798 #[doc = "`write(|w| ..)` method takes [`wdt_lock::W`](W) writer structure"]
4799 impl crate::Writable for WdtLockSpec {
4800 type Safety = crate::Unsafe;
4801 }
4802 #[doc = "`reset()` method sets WDT_LOCK to value 0"]
4803 impl crate::Resettable for WdtLockSpec {}
4804 }
4805 #[doc = "WDT_LOAD (rw) register accessor: Watchdog load value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_load::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_load::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_load`] module"]
4806 #[doc(alias = "WDT_LOAD")]
4807 pub type WdtLoad = crate::Reg<wdt_load::WdtLoadSpec>;
4808 #[doc = "Watchdog load value"]
4809 pub mod wdt_load {
4810 #[doc = "Register `WDT_LOAD` reader"]
4811 pub type R = crate::R<WdtLoadSpec>;
4812 #[doc = "Register `WDT_LOAD` writer"]
4813 pub type W = crate::W<WdtLoadSpec>;
4814 #[doc = "Field `wdt_load` reader - Load count value (24-bit, low 8 bits reserved)"]
4815 pub type WdtLoadR = crate::FieldReader<u32>;
4816 #[doc = "Field `wdt_load` writer - Load count value (24-bit, low 8 bits reserved)"]
4817 pub type WdtLoadW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
4818 impl R {
4819 #[doc = "Bits 8:31 - Load count value (24-bit, low 8 bits reserved)"]
4820 #[inline(always)]
4821 pub fn wdt_load(&self) -> WdtLoadR {
4822 WdtLoadR::new((self.bits >> 8) & 0x00ff_ffff)
4823 }
4824 }
4825 impl W {
4826 #[doc = "Bits 8:31 - Load count value (24-bit, low 8 bits reserved)"]
4827 #[inline(always)]
4828 pub fn wdt_load(&mut self) -> WdtLoadW<'_, WdtLoadSpec> {
4829 WdtLoadW::new(self, 8)
4830 }
4831 }
4832 #[doc = "Watchdog load value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_load::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_load::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4833 pub struct WdtLoadSpec;
4834 impl crate::RegisterSpec for WdtLoadSpec {
4835 type Ux = u32;
4836 }
4837 #[doc = "`read()` method returns [`wdt_load::R`](R) reader structure"]
4838 impl crate::Readable for WdtLoadSpec {}
4839 #[doc = "`write(|w| ..)` method takes [`wdt_load::W`](W) writer structure"]
4840 impl crate::Writable for WdtLoadSpec {
4841 type Safety = crate::Unsafe;
4842 }
4843 #[doc = "`reset()` method sets WDT_LOAD to value 0"]
4844 impl crate::Resettable for WdtLoadSpec {}
4845 }
4846 #[doc = "WDT_RESTART (rw) register accessor: Watchdog restart register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_restart::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_restart::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_restart`] module"]
4847 #[doc(alias = "WDT_RESTART")]
4848 pub type WdtRestart = crate::Reg<wdt_restart::WdtRestartSpec>;
4849 #[doc = "Watchdog restart register"]
4850 pub mod wdt_restart {
4851 #[doc = "Register `WDT_RESTART` reader"]
4852 pub type R = crate::R<WdtRestartSpec>;
4853 #[doc = "Register `WDT_RESTART` writer"]
4854 pub type W = crate::W<WdtRestartSpec>;
4855 #[doc = "Field `wdt_restart` writer - Write anything except 0x5A5A5A5A to restart counter"]
4856 pub type WdtRestartW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
4857 impl W {
4858 #[doc = "Bits 0:31 - Write anything except 0x5A5A5A5A to restart counter"]
4859 #[inline(always)]
4860 pub fn wdt_restart(&mut self) -> WdtRestartW<'_, WdtRestartSpec> {
4861 WdtRestartW::new(self, 0)
4862 }
4863 }
4864 #[doc = "Watchdog restart register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_restart::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_restart::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4865 pub struct WdtRestartSpec;
4866 impl crate::RegisterSpec for WdtRestartSpec {
4867 type Ux = u32;
4868 }
4869 #[doc = "`read()` method returns [`wdt_restart::R`](R) reader structure"]
4870 impl crate::Readable for WdtRestartSpec {}
4871 #[doc = "`write(|w| ..)` method takes [`wdt_restart::W`](W) writer structure"]
4872 impl crate::Writable for WdtRestartSpec {
4873 type Safety = crate::Unsafe;
4874 }
4875 #[doc = "`reset()` method sets WDT_RESTART to value 0"]
4876 impl crate::Resettable for WdtRestartSpec {}
4877 }
4878 #[doc = "WDT_EOI (rw) register accessor: Watchdog interrupt clear (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_eoi`] module"]
4879 #[doc(alias = "WDT_EOI")]
4880 pub type WdtEoi = crate::Reg<wdt_eoi::WdtEoiSpec>;
4881 #[doc = "Watchdog interrupt clear (read to clear)"]
4882 pub mod wdt_eoi {
4883 #[doc = "Register `WDT_EOI` reader"]
4884 pub type R = crate::R<WdtEoiSpec>;
4885 #[doc = "Register `WDT_EOI` writer"]
4886 pub type W = crate::W<WdtEoiSpec>;
4887 #[doc = "Field `wdt_eoi` reader - Read to clear watchdog interrupt"]
4888 pub type WdtEoiR = crate::BitReader;
4889 impl R {
4890 #[doc = "Bit 0 - Read to clear watchdog interrupt"]
4891 #[inline(always)]
4892 pub fn wdt_eoi(&self) -> WdtEoiR {
4893 WdtEoiR::new((self.bits & 1) != 0)
4894 }
4895 }
4896 impl W {}
4897 #[doc = "Watchdog interrupt clear (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
4898 pub struct WdtEoiSpec;
4899 impl crate::RegisterSpec for WdtEoiSpec {
4900 type Ux = u32;
4901 }
4902 #[doc = "`read()` method returns [`wdt_eoi::R`](R) reader structure"]
4903 impl crate::Readable for WdtEoiSpec {}
4904 #[doc = "`write(|w| ..)` method takes [`wdt_eoi::W`](W) writer structure"]
4905 impl crate::Writable for WdtEoiSpec {
4906 type Safety = crate::Unsafe;
4907 }
4908 #[doc = "`reset()` method sets WDT_EOI to value 0"]
4909 impl crate::Resettable for WdtEoiSpec {}
4910 }
4911 #[doc = "WDT_CR (rw) register accessor: Watchdog control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cr`] module"]
4912 #[doc(alias = "WDT_CR")]
4913 pub type WdtCr = crate::Reg<wdt_cr::WdtCrSpec>;
4914 #[doc = "Watchdog control register"]
4915 pub mod wdt_cr {
4916 #[doc = "Register `WDT_CR` reader"]
4917 pub type R = crate::R<WdtCrSpec>;
4918 #[doc = "Register `WDT_CR` writer"]
4919 pub type W = crate::W<WdtCrSpec>;
4920 #[doc = "Field `wdt_en` reader - Watchdog enable: 0=disabled; 1=enabled"]
4921 pub type WdtEnR = crate::BitReader;
4922 #[doc = "Field `wdt_en` writer - Watchdog enable: 0=disabled; 1=enabled"]
4923 pub type WdtEnW<'a, REG> = crate::BitWriter<'a, REG>;
4924 #[doc = "Field `rst_en` reader - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
4925 pub type RstEnR = crate::BitReader;
4926 #[doc = "Field `rst_en` writer - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
4927 pub type RstEnW<'a, REG> = crate::BitWriter<'a, REG>;
4928 #[doc = "Field `rst_pl` reader - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
4929 pub type RstPlR = crate::FieldReader;
4930 #[doc = "Field `rst_pl` writer - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
4931 pub type RstPlW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
4932 #[doc = "Field `wdt_imsk` reader - Interrupt mask: 0=unmasked; 1=masked"]
4933 pub type WdtImskR = crate::BitReader;
4934 #[doc = "Field `wdt_imsk` writer - Interrupt mask: 0=unmasked; 1=masked"]
4935 pub type WdtImskW<'a, REG> = crate::BitWriter<'a, REG>;
4936 #[doc = "Mode: 0=one interrupt then reset; 1=two interrupts then reset\n\nValue on reset: 0"]
4937 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
4938 pub enum WdtMode {
4939 #[doc = "0: Single interrupt then reset"]
4940 Mode1 = 0,
4941 #[doc = "1: Two interrupts then reset"]
4942 Mode2 = 1,
4943 }
4944 impl From<WdtMode> for bool {
4945 #[inline(always)]
4946 fn from(variant: WdtMode) -> Self {
4947 variant as u8 != 0
4948 }
4949 }
4950 #[doc = "Field `wdt_mode` reader - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
4951 pub type WdtModeR = crate::BitReader<WdtMode>;
4952 impl WdtModeR {
4953 #[doc = "Get enumerated values variant"]
4954 #[inline(always)]
4955 pub const fn variant(&self) -> WdtMode {
4956 match self.bits {
4957 false => WdtMode::Mode1,
4958 true => WdtMode::Mode2,
4959 }
4960 }
4961 #[doc = "Single interrupt then reset"]
4962 #[inline(always)]
4963 pub fn is_mode1(&self) -> bool {
4964 *self == WdtMode::Mode1
4965 }
4966 #[doc = "Two interrupts then reset"]
4967 #[inline(always)]
4968 pub fn is_mode2(&self) -> bool {
4969 *self == WdtMode::Mode2
4970 }
4971 }
4972 #[doc = "Field `wdt_mode` writer - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
4973 pub type WdtModeW<'a, REG> = crate::BitWriter<'a, REG, WdtMode>;
4974 impl<'a, REG> WdtModeW<'a, REG>
4975 where
4976 REG: crate::Writable + crate::RegisterSpec,
4977 {
4978 #[doc = "Single interrupt then reset"]
4979 #[inline(always)]
4980 pub fn mode1(self) -> &'a mut crate::W<REG> {
4981 self.variant(WdtMode::Mode1)
4982 }
4983 #[doc = "Two interrupts then reset"]
4984 #[inline(always)]
4985 pub fn mode2(self) -> &'a mut crate::W<REG> {
4986 self.variant(WdtMode::Mode2)
4987 }
4988 }
4989 impl R {
4990 #[doc = "Bit 0 - Watchdog enable: 0=disabled; 1=enabled"]
4991 #[inline(always)]
4992 pub fn wdt_en(&self) -> WdtEnR {
4993 WdtEnR::new((self.bits & 1) != 0)
4994 }
4995 #[doc = "Bit 2 - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
4996 #[inline(always)]
4997 pub fn rst_en(&self) -> RstEnR {
4998 RstEnR::new(((self.bits >> 2) & 1) != 0)
4999 }
5000 #[doc = "Bits 3:5 - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
5001 #[inline(always)]
5002 pub fn rst_pl(&self) -> RstPlR {
5003 RstPlR::new(((self.bits >> 3) & 7) as u8)
5004 }
5005 #[doc = "Bit 6 - Interrupt mask: 0=unmasked; 1=masked"]
5006 #[inline(always)]
5007 pub fn wdt_imsk(&self) -> WdtImskR {
5008 WdtImskR::new(((self.bits >> 6) & 1) != 0)
5009 }
5010 #[doc = "Bit 7 - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
5011 #[inline(always)]
5012 pub fn wdt_mode(&self) -> WdtModeR {
5013 WdtModeR::new(((self.bits >> 7) & 1) != 0)
5014 }
5015 }
5016 impl W {
5017 #[doc = "Bit 0 - Watchdog enable: 0=disabled; 1=enabled"]
5018 #[inline(always)]
5019 pub fn wdt_en(&mut self) -> WdtEnW<'_, WdtCrSpec> {
5020 WdtEnW::new(self, 0)
5021 }
5022 #[doc = "Bit 2 - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
5023 #[inline(always)]
5024 pub fn rst_en(&mut self) -> RstEnW<'_, WdtCrSpec> {
5025 RstEnW::new(self, 2)
5026 }
5027 #[doc = "Bits 3:5 - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
5028 #[inline(always)]
5029 pub fn rst_pl(&mut self) -> RstPlW<'_, WdtCrSpec> {
5030 RstPlW::new(self, 3)
5031 }
5032 #[doc = "Bit 6 - Interrupt mask: 0=unmasked; 1=masked"]
5033 #[inline(always)]
5034 pub fn wdt_imsk(&mut self) -> WdtImskW<'_, WdtCrSpec> {
5035 WdtImskW::new(self, 6)
5036 }
5037 #[doc = "Bit 7 - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
5038 #[inline(always)]
5039 pub fn wdt_mode(&mut self) -> WdtModeW<'_, WdtCrSpec> {
5040 WdtModeW::new(self, 7)
5041 }
5042 }
5043 #[doc = "Watchdog control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5044 pub struct WdtCrSpec;
5045 impl crate::RegisterSpec for WdtCrSpec {
5046 type Ux = u32;
5047 }
5048 #[doc = "`read()` method returns [`wdt_cr::R`](R) reader structure"]
5049 impl crate::Readable for WdtCrSpec {}
5050 #[doc = "`write(|w| ..)` method takes [`wdt_cr::W`](W) writer structure"]
5051 impl crate::Writable for WdtCrSpec {
5052 type Safety = crate::Unsafe;
5053 }
5054 #[doc = "`reset()` method sets WDT_CR to value 0"]
5055 impl crate::Resettable for WdtCrSpec {}
5056 }
5057 #[doc = "WDT_CNT (rw) register accessor: Watchdog current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cnt`] module"]
5058 #[doc(alias = "WDT_CNT")]
5059 pub type WdtCnt = crate::Reg<wdt_cnt::WdtCntSpec>;
5060 #[doc = "Watchdog current counter value"]
5061 pub mod wdt_cnt {
5062 #[doc = "Register `WDT_CNT` reader"]
5063 pub type R = crate::R<WdtCntSpec>;
5064 #[doc = "Register `WDT_CNT` writer"]
5065 pub type W = crate::W<WdtCntSpec>;
5066 #[doc = "Field `wdt_cnt` reader - Current counter value"]
5067 pub type WdtCntR = crate::FieldReader<u32>;
5068 impl R {
5069 #[doc = "Bits 0:31 - Current counter value"]
5070 #[inline(always)]
5071 pub fn wdt_cnt(&self) -> WdtCntR {
5072 WdtCntR::new(self.bits)
5073 }
5074 }
5075 impl W {}
5076 #[doc = "Watchdog current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5077 pub struct WdtCntSpec;
5078 impl crate::RegisterSpec for WdtCntSpec {
5079 type Ux = u32;
5080 }
5081 #[doc = "`read()` method returns [`wdt_cnt::R`](R) reader structure"]
5082 impl crate::Readable for WdtCntSpec {}
5083 #[doc = "`write(|w| ..)` method takes [`wdt_cnt::W`](W) writer structure"]
5084 impl crate::Writable for WdtCntSpec {
5085 type Safety = crate::Unsafe;
5086 }
5087 #[doc = "`reset()` method sets WDT_CNT to value 0"]
5088 impl crate::Resettable for WdtCntSpec {}
5089 }
5090 #[doc = "WDT_RAW_INTR (rw) register accessor: Watchdog raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_raw_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_raw_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_raw_intr`] module"]
5091 #[doc(alias = "WDT_RAW_INTR")]
5092 pub type WdtRawIntr = crate::Reg<wdt_raw_intr::WdtRawIntrSpec>;
5093 #[doc = "Watchdog raw interrupt status"]
5094 pub mod wdt_raw_intr {
5095 #[doc = "Register `WDT_RAW_INTR` reader"]
5096 pub type R = crate::R<WdtRawIntrSpec>;
5097 #[doc = "Register `WDT_RAW_INTR` writer"]
5098 pub type W = crate::W<WdtRawIntrSpec>;
5099 #[doc = "Field `wdt_raw_intr` reader - Raw interrupt status"]
5100 pub type WdtRawIntrR = crate::BitReader;
5101 impl R {
5102 #[doc = "Bit 0 - Raw interrupt status"]
5103 #[inline(always)]
5104 pub fn wdt_raw_intr(&self) -> WdtRawIntrR {
5105 WdtRawIntrR::new((self.bits & 1) != 0)
5106 }
5107 }
5108 impl W {}
5109 #[doc = "Watchdog raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_raw_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_raw_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5110 pub struct WdtRawIntrSpec;
5111 impl crate::RegisterSpec for WdtRawIntrSpec {
5112 type Ux = u32;
5113 }
5114 #[doc = "`read()` method returns [`wdt_raw_intr::R`](R) reader structure"]
5115 impl crate::Readable for WdtRawIntrSpec {}
5116 #[doc = "`write(|w| ..)` method takes [`wdt_raw_intr::W`](W) writer structure"]
5117 impl crate::Writable for WdtRawIntrSpec {
5118 type Safety = crate::Unsafe;
5119 }
5120 #[doc = "`reset()` method sets WDT_RAW_INTR to value 0"]
5121 impl crate::Resettable for WdtRawIntrSpec {}
5122 }
5123 #[doc = "WDT_INTR (rw) register accessor: Watchdog interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_intr`] module"]
5124 #[doc(alias = "WDT_INTR")]
5125 pub type WdtIntr = crate::Reg<wdt_intr::WdtIntrSpec>;
5126 #[doc = "Watchdog interrupt status (masked)"]
5127 pub mod wdt_intr {
5128 #[doc = "Register `WDT_INTR` reader"]
5129 pub type R = crate::R<WdtIntrSpec>;
5130 #[doc = "Register `WDT_INTR` writer"]
5131 pub type W = crate::W<WdtIntrSpec>;
5132 #[doc = "Field `wdt_intr` reader - Interrupt status after mask"]
5133 pub type WdtIntrR = crate::BitReader;
5134 impl R {
5135 #[doc = "Bit 0 - Interrupt status after mask"]
5136 #[inline(always)]
5137 pub fn wdt_intr(&self) -> WdtIntrR {
5138 WdtIntrR::new((self.bits & 1) != 0)
5139 }
5140 }
5141 impl W {}
5142 #[doc = "Watchdog interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5143 pub struct WdtIntrSpec;
5144 impl crate::RegisterSpec for WdtIntrSpec {
5145 type Ux = u32;
5146 }
5147 #[doc = "`read()` method returns [`wdt_intr::R`](R) reader structure"]
5148 impl crate::Readable for WdtIntrSpec {}
5149 #[doc = "`write(|w| ..)` method takes [`wdt_intr::W`](W) writer structure"]
5150 impl crate::Writable for WdtIntrSpec {
5151 type Safety = crate::Unsafe;
5152 }
5153 #[doc = "`reset()` method sets WDT_INTR to value 0"]
5154 impl crate::Resettable for WdtIntrSpec {}
5155 }
5156 #[doc = "WDT_LPIF_STATE (rw) register accessor: Watchdog low power state\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lpif_state::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lpif_state::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_lpif_state`] module"]
5157 #[doc(alias = "WDT_LPIF_STATE")]
5158 pub type WdtLpifState = crate::Reg<wdt_lpif_state::WdtLpifStateSpec>;
5159 #[doc = "Watchdog low power state"]
5160 pub mod wdt_lpif_state {
5161 #[doc = "Register `WDT_LPIF_STATE` reader"]
5162 pub type R = crate::R<WdtLpifStateSpec>;
5163 #[doc = "Register `WDT_LPIF_STATE` writer"]
5164 pub type W = crate::W<WdtLpifStateSpec>;
5165 #[doc = "Field `wdt_lpif_state` reader - Low power interface state"]
5166 pub type WdtLpifStateR = crate::FieldReader;
5167 impl R {
5168 #[doc = "Bits 0:2 - Low power interface state"]
5169 #[inline(always)]
5170 pub fn wdt_lpif_state(&self) -> WdtLpifStateR {
5171 WdtLpifStateR::new((self.bits & 7) as u8)
5172 }
5173 }
5174 impl W {}
5175 #[doc = "Watchdog low power state\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lpif_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lpif_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5176 pub struct WdtLpifStateSpec;
5177 impl crate::RegisterSpec for WdtLpifStateSpec {
5178 type Ux = u32;
5179 }
5180 #[doc = "`read()` method returns [`wdt_lpif_state::R`](R) reader structure"]
5181 impl crate::Readable for WdtLpifStateSpec {}
5182 #[doc = "`write(|w| ..)` method takes [`wdt_lpif_state::W`](W) writer structure"]
5183 impl crate::Writable for WdtLpifStateSpec {
5184 type Safety = crate::Unsafe;
5185 }
5186 #[doc = "`reset()` method sets WDT_LPIF_STATE to value 0"]
5187 impl crate::Resettable for WdtLpifStateSpec {}
5188 }
5189 #[doc = "WDT_STATUS (rw) register accessor: Watchdog status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_status`] module"]
5190 #[doc(alias = "WDT_STATUS")]
5191 pub type WdtStatus = crate::Reg<wdt_status::WdtStatusSpec>;
5192 #[doc = "Watchdog status"]
5193 pub mod wdt_status {
5194 #[doc = "Register `WDT_STATUS` reader"]
5195 pub type R = crate::R<WdtStatusSpec>;
5196 #[doc = "Register `WDT_STATUS` writer"]
5197 pub type W = crate::W<WdtStatusSpec>;
5198 #[doc = "Field `wdt_status` reader - Status: 0=busy; 1=free"]
5199 pub type WdtStatusR = crate::BitReader;
5200 impl R {
5201 #[doc = "Bit 0 - Status: 0=busy; 1=free"]
5202 #[inline(always)]
5203 pub fn wdt_status(&self) -> WdtStatusR {
5204 WdtStatusR::new((self.bits & 1) != 0)
5205 }
5206 }
5207 impl W {}
5208 #[doc = "Watchdog status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5209 pub struct WdtStatusSpec;
5210 impl crate::RegisterSpec for WdtStatusSpec {
5211 type Ux = u32;
5212 }
5213 #[doc = "`read()` method returns [`wdt_status::R`](R) reader structure"]
5214 impl crate::Readable for WdtStatusSpec {}
5215 #[doc = "`write(|w| ..)` method takes [`wdt_status::W`](W) writer structure"]
5216 impl crate::Writable for WdtStatusSpec {
5217 type Safety = crate::Unsafe;
5218 }
5219 #[doc = "`reset()` method sets WDT_STATUS to value 0"]
5220 impl crate::Resettable for WdtStatusSpec {}
5221 }
5222 #[doc = "WDT_CCVR_EN (rw) register accessor: Watchdog counter value request\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_ccvr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_ccvr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_ccvr_en`] module"]
5223 #[doc(alias = "WDT_CCVR_EN")]
5224 pub type WdtCcvrEn = crate::Reg<wdt_ccvr_en::WdtCcvrEnSpec>;
5225 #[doc = "Watchdog counter value request"]
5226 pub mod wdt_ccvr_en {
5227 #[doc = "Register `WDT_CCVR_EN` reader"]
5228 pub type R = crate::R<WdtCcvrEnSpec>;
5229 #[doc = "Register `WDT_CCVR_EN` writer"]
5230 pub type W = crate::W<WdtCcvrEnSpec>;
5231 #[doc = "Field `ccvr_req` writer - Write 1 to request current counter value"]
5232 pub type CcvrReqW<'a, REG> = crate::BitWriter<'a, REG>;
5233 #[doc = "Field `ccvr_ack` reader - Acknowledge: 1=counter value valid"]
5234 pub type CcvrAckR = crate::BitReader;
5235 impl R {
5236 #[doc = "Bit 1 - Acknowledge: 1=counter value valid"]
5237 #[inline(always)]
5238 pub fn ccvr_ack(&self) -> CcvrAckR {
5239 CcvrAckR::new(((self.bits >> 1) & 1) != 0)
5240 }
5241 }
5242 impl W {
5243 #[doc = "Bit 0 - Write 1 to request current counter value"]
5244 #[inline(always)]
5245 pub fn ccvr_req(&mut self) -> CcvrReqW<'_, WdtCcvrEnSpec> {
5246 CcvrReqW::new(self, 0)
5247 }
5248 }
5249 #[doc = "Watchdog counter value request\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_ccvr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_ccvr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5250 pub struct WdtCcvrEnSpec;
5251 impl crate::RegisterSpec for WdtCcvrEnSpec {
5252 type Ux = u32;
5253 }
5254 #[doc = "`read()` method returns [`wdt_ccvr_en::R`](R) reader structure"]
5255 impl crate::Readable for WdtCcvrEnSpec {}
5256 #[doc = "`write(|w| ..)` method takes [`wdt_ccvr_en::W`](W) writer structure"]
5257 impl crate::Writable for WdtCcvrEnSpec {
5258 type Safety = crate::Unsafe;
5259 }
5260 #[doc = "`reset()` method sets WDT_CCVR_EN to value 0"]
5261 impl crate::Resettable for WdtCcvrEnSpec {}
5262 }
5263}
5264#[doc = "TCXO 64-bit free-running counter (v150)"]
5265pub type Tcxo = crate::Periph<tcxo::RegisterBlock, 0x5700_0200>;
5266impl core::fmt::Debug for Tcxo {
5267 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5268 f.debug_struct("Tcxo").finish()
5269 }
5270}
5271#[doc = "TCXO 64-bit free-running counter (v150)"]
5272pub mod tcxo {
5273 #[repr(C)]
5274 #[doc = "Register block"]
5275 pub struct RegisterBlock {
5276 tcxo_status: TcxoStatus,
5277 tcxo_count0: TcxoCount0,
5278 tcxo_count1: TcxoCount1,
5279 tcxo_count2: TcxoCount2,
5280 tcxo_count3: TcxoCount3,
5281 }
5282 impl RegisterBlock {
5283 #[doc = "0x00 - TCXO status and control register"]
5284 #[inline(always)]
5285 pub const fn tcxo_status(&self) -> &TcxoStatus {
5286 &self.tcxo_status
5287 }
5288 #[doc = "0x04 - TCXO count bits \\[15:0\\]"]
5289 #[inline(always)]
5290 pub const fn tcxo_count0(&self) -> &TcxoCount0 {
5291 &self.tcxo_count0
5292 }
5293 #[doc = "0x08 - TCXO count bits \\[31:16\\]"]
5294 #[inline(always)]
5295 pub const fn tcxo_count1(&self) -> &TcxoCount1 {
5296 &self.tcxo_count1
5297 }
5298 #[doc = "0x0c - TCXO count bits \\[47:32\\]"]
5299 #[inline(always)]
5300 pub const fn tcxo_count2(&self) -> &TcxoCount2 {
5301 &self.tcxo_count2
5302 }
5303 #[doc = "0x10 - TCXO count bits \\[63:48\\]"]
5304 #[inline(always)]
5305 pub const fn tcxo_count3(&self) -> &TcxoCount3 {
5306 &self.tcxo_count3
5307 }
5308 }
5309 #[doc = "TCXO_STATUS (rw) register accessor: TCXO status and control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_status`] module"]
5310 #[doc(alias = "TCXO_STATUS")]
5311 pub type TcxoStatus = crate::Reg<tcxo_status::TcxoStatusSpec>;
5312 #[doc = "TCXO status and control register"]
5313 pub mod tcxo_status {
5314 #[doc = "Register `TCXO_STATUS` reader"]
5315 pub type R = crate::R<TcxoStatusSpec>;
5316 #[doc = "Register `TCXO_STATUS` writer"]
5317 pub type W = crate::W<TcxoStatusSpec>;
5318 #[doc = "Field `refresh` reader - TCXO count refresh: 1=trigger count latch"]
5319 pub type RefreshR = crate::BitReader;
5320 #[doc = "Field `refresh` writer - TCXO count refresh: 1=trigger count latch"]
5321 pub type RefreshW<'a, REG> = crate::BitWriter<'a, REG>;
5322 #[doc = "Field `clear` reader - TCXO count clear: 1=clear counter"]
5323 pub type ClearR = crate::BitReader;
5324 #[doc = "Field `clear` writer - TCXO count clear: 1=clear counter"]
5325 pub type ClearW<'a, REG> = crate::BitWriter<'a, REG>;
5326 #[doc = "Field `enable` reader - TCXO count enable: 1=enable counting"]
5327 pub type EnableR = crate::BitReader;
5328 #[doc = "Field `enable` writer - TCXO count enable: 1=enable counting"]
5329 pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
5330 #[doc = "Field `valid` reader - TCXO count value valid flag"]
5331 pub type ValidR = crate::BitReader;
5332 impl R {
5333 #[doc = "Bit 0 - TCXO count refresh: 1=trigger count latch"]
5334 #[inline(always)]
5335 pub fn refresh(&self) -> RefreshR {
5336 RefreshR::new((self.bits & 1) != 0)
5337 }
5338 #[doc = "Bit 1 - TCXO count clear: 1=clear counter"]
5339 #[inline(always)]
5340 pub fn clear(&self) -> ClearR {
5341 ClearR::new(((self.bits >> 1) & 1) != 0)
5342 }
5343 #[doc = "Bit 2 - TCXO count enable: 1=enable counting"]
5344 #[inline(always)]
5345 pub fn enable(&self) -> EnableR {
5346 EnableR::new(((self.bits >> 2) & 1) != 0)
5347 }
5348 #[doc = "Bit 4 - TCXO count value valid flag"]
5349 #[inline(always)]
5350 pub fn valid(&self) -> ValidR {
5351 ValidR::new(((self.bits >> 4) & 1) != 0)
5352 }
5353 }
5354 impl W {
5355 #[doc = "Bit 0 - TCXO count refresh: 1=trigger count latch"]
5356 #[inline(always)]
5357 pub fn refresh(&mut self) -> RefreshW<'_, TcxoStatusSpec> {
5358 RefreshW::new(self, 0)
5359 }
5360 #[doc = "Bit 1 - TCXO count clear: 1=clear counter"]
5361 #[inline(always)]
5362 pub fn clear(&mut self) -> ClearW<'_, TcxoStatusSpec> {
5363 ClearW::new(self, 1)
5364 }
5365 #[doc = "Bit 2 - TCXO count enable: 1=enable counting"]
5366 #[inline(always)]
5367 pub fn enable(&mut self) -> EnableW<'_, TcxoStatusSpec> {
5368 EnableW::new(self, 2)
5369 }
5370 }
5371 #[doc = "TCXO status and control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5372 pub struct TcxoStatusSpec;
5373 impl crate::RegisterSpec for TcxoStatusSpec {
5374 type Ux = u32;
5375 }
5376 #[doc = "`read()` method returns [`tcxo_status::R`](R) reader structure"]
5377 impl crate::Readable for TcxoStatusSpec {}
5378 #[doc = "`write(|w| ..)` method takes [`tcxo_status::W`](W) writer structure"]
5379 impl crate::Writable for TcxoStatusSpec {
5380 type Safety = crate::Unsafe;
5381 }
5382 #[doc = "`reset()` method sets TCXO_STATUS to value 0"]
5383 impl crate::Resettable for TcxoStatusSpec {}
5384 }
5385 #[doc = "TCXO_COUNT0 (rw) register accessor: TCXO count bits \\[15:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count0`] module"]
5386 #[doc(alias = "TCXO_COUNT0")]
5387 pub type TcxoCount0 = crate::Reg<tcxo_count0::TcxoCount0Spec>;
5388 #[doc = "TCXO count bits \\[15:0\\]"]
5389 pub mod tcxo_count0 {
5390 #[doc = "Register `TCXO_COUNT0` reader"]
5391 pub type R = crate::R<TcxoCount0Spec>;
5392 #[doc = "Register `TCXO_COUNT0` writer"]
5393 pub type W = crate::W<TcxoCount0Spec>;
5394 #[doc = "Field `count0` reader - Counter value bits \\[15:0\\]"]
5395 pub type Count0R = crate::FieldReader<u16>;
5396 impl R {
5397 #[doc = "Bits 0:15 - Counter value bits \\[15:0\\]"]
5398 #[inline(always)]
5399 pub fn count0(&self) -> Count0R {
5400 Count0R::new((self.bits & 0xffff) as u16)
5401 }
5402 }
5403 impl W {}
5404 #[doc = "TCXO count bits \\[15:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5405 pub struct TcxoCount0Spec;
5406 impl crate::RegisterSpec for TcxoCount0Spec {
5407 type Ux = u32;
5408 }
5409 #[doc = "`read()` method returns [`tcxo_count0::R`](R) reader structure"]
5410 impl crate::Readable for TcxoCount0Spec {}
5411 #[doc = "`write(|w| ..)` method takes [`tcxo_count0::W`](W) writer structure"]
5412 impl crate::Writable for TcxoCount0Spec {
5413 type Safety = crate::Unsafe;
5414 }
5415 #[doc = "`reset()` method sets TCXO_COUNT0 to value 0"]
5416 impl crate::Resettable for TcxoCount0Spec {}
5417 }
5418 #[doc = "TCXO_COUNT1 (rw) register accessor: TCXO count bits \\[31:16\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count1`] module"]
5419 #[doc(alias = "TCXO_COUNT1")]
5420 pub type TcxoCount1 = crate::Reg<tcxo_count1::TcxoCount1Spec>;
5421 #[doc = "TCXO count bits \\[31:16\\]"]
5422 pub mod tcxo_count1 {
5423 #[doc = "Register `TCXO_COUNT1` reader"]
5424 pub type R = crate::R<TcxoCount1Spec>;
5425 #[doc = "Register `TCXO_COUNT1` writer"]
5426 pub type W = crate::W<TcxoCount1Spec>;
5427 #[doc = "Field `count1` reader - Counter value bits \\[31:16\\]"]
5428 pub type Count1R = crate::FieldReader<u16>;
5429 impl R {
5430 #[doc = "Bits 0:15 - Counter value bits \\[31:16\\]"]
5431 #[inline(always)]
5432 pub fn count1(&self) -> Count1R {
5433 Count1R::new((self.bits & 0xffff) as u16)
5434 }
5435 }
5436 impl W {}
5437 #[doc = "TCXO count bits \\[31:16\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5438 pub struct TcxoCount1Spec;
5439 impl crate::RegisterSpec for TcxoCount1Spec {
5440 type Ux = u32;
5441 }
5442 #[doc = "`read()` method returns [`tcxo_count1::R`](R) reader structure"]
5443 impl crate::Readable for TcxoCount1Spec {}
5444 #[doc = "`write(|w| ..)` method takes [`tcxo_count1::W`](W) writer structure"]
5445 impl crate::Writable for TcxoCount1Spec {
5446 type Safety = crate::Unsafe;
5447 }
5448 #[doc = "`reset()` method sets TCXO_COUNT1 to value 0"]
5449 impl crate::Resettable for TcxoCount1Spec {}
5450 }
5451 #[doc = "TCXO_COUNT2 (rw) register accessor: TCXO count bits \\[47:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count2`] module"]
5452 #[doc(alias = "TCXO_COUNT2")]
5453 pub type TcxoCount2 = crate::Reg<tcxo_count2::TcxoCount2Spec>;
5454 #[doc = "TCXO count bits \\[47:32\\]"]
5455 pub mod tcxo_count2 {
5456 #[doc = "Register `TCXO_COUNT2` reader"]
5457 pub type R = crate::R<TcxoCount2Spec>;
5458 #[doc = "Register `TCXO_COUNT2` writer"]
5459 pub type W = crate::W<TcxoCount2Spec>;
5460 #[doc = "Field `count2` reader - Counter value bits \\[47:32\\]"]
5461 pub type Count2R = crate::FieldReader<u16>;
5462 impl R {
5463 #[doc = "Bits 0:15 - Counter value bits \\[47:32\\]"]
5464 #[inline(always)]
5465 pub fn count2(&self) -> Count2R {
5466 Count2R::new((self.bits & 0xffff) as u16)
5467 }
5468 }
5469 impl W {}
5470 #[doc = "TCXO count bits \\[47:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5471 pub struct TcxoCount2Spec;
5472 impl crate::RegisterSpec for TcxoCount2Spec {
5473 type Ux = u32;
5474 }
5475 #[doc = "`read()` method returns [`tcxo_count2::R`](R) reader structure"]
5476 impl crate::Readable for TcxoCount2Spec {}
5477 #[doc = "`write(|w| ..)` method takes [`tcxo_count2::W`](W) writer structure"]
5478 impl crate::Writable for TcxoCount2Spec {
5479 type Safety = crate::Unsafe;
5480 }
5481 #[doc = "`reset()` method sets TCXO_COUNT2 to value 0"]
5482 impl crate::Resettable for TcxoCount2Spec {}
5483 }
5484 #[doc = "TCXO_COUNT3 (rw) register accessor: TCXO count bits \\[63:48\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count3`] module"]
5485 #[doc(alias = "TCXO_COUNT3")]
5486 pub type TcxoCount3 = crate::Reg<tcxo_count3::TcxoCount3Spec>;
5487 #[doc = "TCXO count bits \\[63:48\\]"]
5488 pub mod tcxo_count3 {
5489 #[doc = "Register `TCXO_COUNT3` reader"]
5490 pub type R = crate::R<TcxoCount3Spec>;
5491 #[doc = "Register `TCXO_COUNT3` writer"]
5492 pub type W = crate::W<TcxoCount3Spec>;
5493 #[doc = "Field `count3` reader - Counter value bits \\[63:48\\]"]
5494 pub type Count3R = crate::FieldReader<u16>;
5495 impl R {
5496 #[doc = "Bits 0:15 - Counter value bits \\[63:48\\]"]
5497 #[inline(always)]
5498 pub fn count3(&self) -> Count3R {
5499 Count3R::new((self.bits & 0xffff) as u16)
5500 }
5501 }
5502 impl W {}
5503 #[doc = "TCXO count bits \\[63:48\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5504 pub struct TcxoCount3Spec;
5505 impl crate::RegisterSpec for TcxoCount3Spec {
5506 type Ux = u32;
5507 }
5508 #[doc = "`read()` method returns [`tcxo_count3::R`](R) reader structure"]
5509 impl crate::Readable for TcxoCount3Spec {}
5510 #[doc = "`write(|w| ..)` method takes [`tcxo_count3::W`](W) writer structure"]
5511 impl crate::Writable for TcxoCount3Spec {
5512 type Safety = crate::Unsafe;
5513 }
5514 #[doc = "`reset()` method sets TCXO_COUNT3 to value 0"]
5515 impl crate::Resettable for TcxoCount3Spec {}
5516 }
5517}
5518#[doc = "I2C0 master controller (DesignWare SSI, IP v151)"]
5519pub type I2c0 = crate::Periph<i2c0::RegisterBlock, 0x5208_3000>;
5520impl core::fmt::Debug for I2c0 {
5521 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
5522 f.debug_struct("I2c0").finish()
5523 }
5524}
5525#[doc = "I2C0 master controller (DesignWare SSI, IP v151)"]
5526pub mod i2c0 {
5527 #[repr(C)]
5528 #[doc = "Register block"]
5529 pub struct RegisterBlock {
5530 ic_con: IcCon,
5531 ic_enable: IcEnable,
5532 _reserved2: [u8; 0x08],
5533 ic_tar: IcTar,
5534 ic_sar: IcSar,
5535 ic_hs_maddr: IcHsMaddr,
5536 ic_data_cmd: IcDataCmd,
5537 _reserved6: [u8; 0x10],
5538 ic_ss_scl_hcnt: IcSsSclHcnt,
5539 ic_ss_scl_lcnt: IcSsSclLcnt,
5540 _reserved8: [u8; 0x04],
5541 ic_fs_scl_hcnt: IcFsSclHcnt,
5542 ic_fs_scl_lcnt: IcFsSclLcnt,
5543 ic_hs_scl_hcnt: IcHsSclHcnt,
5544 ic_hs_scl_lcnt: IcHsSclLcnt,
5545 _reserved12: [u8; 0x04],
5546 ic_rx_tl: IcRxTl,
5547 ic_tx_tl: IcTxTl,
5548 ic_slv_data_nack_only: IcSlvDataNackOnly,
5549 _reserved15: [u8; 0x04],
5550 ic_status: IcStatus,
5551 ic_txflr: IcTxflr,
5552 ic_rxflr: IcRxflr,
5553 ic_sda_hold: IcSdaHold,
5554 ic_sda_hold_tx: IcSdaHoldTx,
5555 ic_tx_flush_cnt: IcTxFlushCnt,
5556 ic_tx_abrt_source: IcTxAbrtSource,
5557 ic_tx_abrt_slv_intx: IcTxAbrtSlvIntx,
5558 ic_ack_general_call: IcAckGeneralCall,
5559 ic_enable_status: IcEnableStatus,
5560 _reserved25: [u8; 0x18],
5561 ic_dma_cr: IcDmaCr,
5562 ic_dma_tdlr: IcDmaTdlr,
5563 ic_dma_rdlr: IcDmaRdlr,
5564 ic_sda_setup: IcSdaSetup,
5565 ic_intr_mask: IcIntrMask,
5566 ic_intr_stat: IcIntrStat,
5567 ic_raw_intr_stat: IcRawIntrStat,
5568 ic_intr_stat_all: IcIntrStatAll,
5569 ic_clr_intr: IcClrIntr,
5570 ic_clr_int: IcClrInt,
5571 }
5572 impl RegisterBlock {
5573 #[doc = "0x00 - IC_CON"]
5574 #[inline(always)]
5575 pub const fn ic_con(&self) -> &IcCon {
5576 &self.ic_con
5577 }
5578 #[doc = "0x04 - IC_ENABLE"]
5579 #[inline(always)]
5580 pub const fn ic_enable(&self) -> &IcEnable {
5581 &self.ic_enable
5582 }
5583 #[doc = "0x10 - IC_TAR"]
5584 #[inline(always)]
5585 pub const fn ic_tar(&self) -> &IcTar {
5586 &self.ic_tar
5587 }
5588 #[doc = "0x14 - IC_SAR"]
5589 #[inline(always)]
5590 pub const fn ic_sar(&self) -> &IcSar {
5591 &self.ic_sar
5592 }
5593 #[doc = "0x18 - IC_HS_MADDR"]
5594 #[inline(always)]
5595 pub const fn ic_hs_maddr(&self) -> &IcHsMaddr {
5596 &self.ic_hs_maddr
5597 }
5598 #[doc = "0x1c - IC_DATA_CMD"]
5599 #[inline(always)]
5600 pub const fn ic_data_cmd(&self) -> &IcDataCmd {
5601 &self.ic_data_cmd
5602 }
5603 #[doc = "0x30 - IC_SS_SCL_HCNT"]
5604 #[inline(always)]
5605 pub const fn ic_ss_scl_hcnt(&self) -> &IcSsSclHcnt {
5606 &self.ic_ss_scl_hcnt
5607 }
5608 #[doc = "0x34 - IC_SS_SCL_LCNT"]
5609 #[inline(always)]
5610 pub const fn ic_ss_scl_lcnt(&self) -> &IcSsSclLcnt {
5611 &self.ic_ss_scl_lcnt
5612 }
5613 #[doc = "0x3c - IC_FS_SCL_HCNT"]
5614 #[inline(always)]
5615 pub const fn ic_fs_scl_hcnt(&self) -> &IcFsSclHcnt {
5616 &self.ic_fs_scl_hcnt
5617 }
5618 #[doc = "0x40 - IC_FS_SCL_LCNT"]
5619 #[inline(always)]
5620 pub const fn ic_fs_scl_lcnt(&self) -> &IcFsSclLcnt {
5621 &self.ic_fs_scl_lcnt
5622 }
5623 #[doc = "0x44 - IC_HS_SCL_HCNT"]
5624 #[inline(always)]
5625 pub const fn ic_hs_scl_hcnt(&self) -> &IcHsSclHcnt {
5626 &self.ic_hs_scl_hcnt
5627 }
5628 #[doc = "0x48 - IC_HS_SCL_LCNT"]
5629 #[inline(always)]
5630 pub const fn ic_hs_scl_lcnt(&self) -> &IcHsSclLcnt {
5631 &self.ic_hs_scl_lcnt
5632 }
5633 #[doc = "0x50 - IC_RX_TL"]
5634 #[inline(always)]
5635 pub const fn ic_rx_tl(&self) -> &IcRxTl {
5636 &self.ic_rx_tl
5637 }
5638 #[doc = "0x54 - IC_TX_TL"]
5639 #[inline(always)]
5640 pub const fn ic_tx_tl(&self) -> &IcTxTl {
5641 &self.ic_tx_tl
5642 }
5643 #[doc = "0x58 - IC_SLV_DATA_NACK_ONLY"]
5644 #[inline(always)]
5645 pub const fn ic_slv_data_nack_only(&self) -> &IcSlvDataNackOnly {
5646 &self.ic_slv_data_nack_only
5647 }
5648 #[doc = "0x60 - IC_STATUS"]
5649 #[inline(always)]
5650 pub const fn ic_status(&self) -> &IcStatus {
5651 &self.ic_status
5652 }
5653 #[doc = "0x64 - IC_TXFLR"]
5654 #[inline(always)]
5655 pub const fn ic_txflr(&self) -> &IcTxflr {
5656 &self.ic_txflr
5657 }
5658 #[doc = "0x68 - IC_RXFLR"]
5659 #[inline(always)]
5660 pub const fn ic_rxflr(&self) -> &IcRxflr {
5661 &self.ic_rxflr
5662 }
5663 #[doc = "0x6c - IC_SDA_HOLD"]
5664 #[inline(always)]
5665 pub const fn ic_sda_hold(&self) -> &IcSdaHold {
5666 &self.ic_sda_hold
5667 }
5668 #[doc = "0x70 - IC_SDA_HOLD_TX"]
5669 #[inline(always)]
5670 pub const fn ic_sda_hold_tx(&self) -> &IcSdaHoldTx {
5671 &self.ic_sda_hold_tx
5672 }
5673 #[doc = "0x74 - IC_TX_FLUSH_CNT"]
5674 #[inline(always)]
5675 pub const fn ic_tx_flush_cnt(&self) -> &IcTxFlushCnt {
5676 &self.ic_tx_flush_cnt
5677 }
5678 #[doc = "0x78 - IC_TX_ABRT_SOURCE"]
5679 #[inline(always)]
5680 pub const fn ic_tx_abrt_source(&self) -> &IcTxAbrtSource {
5681 &self.ic_tx_abrt_source
5682 }
5683 #[doc = "0x7c - IC_TX_ABRT_SLV_INTX"]
5684 #[inline(always)]
5685 pub const fn ic_tx_abrt_slv_intx(&self) -> &IcTxAbrtSlvIntx {
5686 &self.ic_tx_abrt_slv_intx
5687 }
5688 #[doc = "0x80 - IC_ACK_GENERAL_CALL"]
5689 #[inline(always)]
5690 pub const fn ic_ack_general_call(&self) -> &IcAckGeneralCall {
5691 &self.ic_ack_general_call
5692 }
5693 #[doc = "0x84 - IC_ENABLE_STATUS"]
5694 #[inline(always)]
5695 pub const fn ic_enable_status(&self) -> &IcEnableStatus {
5696 &self.ic_enable_status
5697 }
5698 #[doc = "0xa0 - IC_DMA_CR"]
5699 #[inline(always)]
5700 pub const fn ic_dma_cr(&self) -> &IcDmaCr {
5701 &self.ic_dma_cr
5702 }
5703 #[doc = "0xa4 - IC_DMA_TDLR"]
5704 #[inline(always)]
5705 pub const fn ic_dma_tdlr(&self) -> &IcDmaTdlr {
5706 &self.ic_dma_tdlr
5707 }
5708 #[doc = "0xa8 - IC_DMA_RDLR"]
5709 #[inline(always)]
5710 pub const fn ic_dma_rdlr(&self) -> &IcDmaRdlr {
5711 &self.ic_dma_rdlr
5712 }
5713 #[doc = "0xac - IC_SDA_SETUP"]
5714 #[inline(always)]
5715 pub const fn ic_sda_setup(&self) -> &IcSdaSetup {
5716 &self.ic_sda_setup
5717 }
5718 #[doc = "0xb0 - IC_INTR_MASK"]
5719 #[inline(always)]
5720 pub const fn ic_intr_mask(&self) -> &IcIntrMask {
5721 &self.ic_intr_mask
5722 }
5723 #[doc = "0xb4 - IC_INTR_STAT"]
5724 #[inline(always)]
5725 pub const fn ic_intr_stat(&self) -> &IcIntrStat {
5726 &self.ic_intr_stat
5727 }
5728 #[doc = "0xb8 - IC_RAW_INTR_STAT"]
5729 #[inline(always)]
5730 pub const fn ic_raw_intr_stat(&self) -> &IcRawIntrStat {
5731 &self.ic_raw_intr_stat
5732 }
5733 #[doc = "0xbc - IC_INTR_STAT_ALL"]
5734 #[inline(always)]
5735 pub const fn ic_intr_stat_all(&self) -> &IcIntrStatAll {
5736 &self.ic_intr_stat_all
5737 }
5738 #[doc = "0xc0 - IC_CLR_INTR"]
5739 #[inline(always)]
5740 pub const fn ic_clr_intr(&self) -> &IcClrIntr {
5741 &self.ic_clr_intr
5742 }
5743 #[doc = "0xc4 - IC_CLR_INT"]
5744 #[inline(always)]
5745 pub const fn ic_clr_int(&self) -> &IcClrInt {
5746 &self.ic_clr_int
5747 }
5748 }
5749 #[doc = "IC_CON (rw) register accessor: IC_CON\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_con::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_con::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_con`] module"]
5750 #[doc(alias = "IC_CON")]
5751 pub type IcCon = crate::Reg<ic_con::IcConSpec>;
5752 #[doc = "IC_CON"]
5753 pub mod ic_con {
5754 #[doc = "Register `IC_CON` reader"]
5755 pub type R = crate::R<IcConSpec>;
5756 #[doc = "Register `IC_CON` writer"]
5757 pub type W = crate::W<IcConSpec>;
5758 #[doc = "Field `master_mode` reader - 1=master"]
5759 pub type MasterModeR = crate::BitReader;
5760 #[doc = "Field `master_mode` writer - 1=master"]
5761 pub type MasterModeW<'a, REG> = crate::BitWriter<'a, REG>;
5762 #[doc = "Field `speed` reader - 1=SS 2=FS 3=HS"]
5763 pub type SpeedR = crate::FieldReader;
5764 #[doc = "Field `speed` writer - 1=SS 2=FS 3=HS"]
5765 pub type SpeedW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
5766 #[doc = "Field `ic_10bitaddr_slave` reader - "]
5767 pub type Ic10bitaddrSlaveR = crate::BitReader;
5768 #[doc = "Field `ic_10bitaddr_slave` writer - "]
5769 pub type Ic10bitaddrSlaveW<'a, REG> = crate::BitWriter<'a, REG>;
5770 #[doc = "Field `ic_10bitaddr_master` reader - "]
5771 pub type Ic10bitaddrMasterR = crate::BitReader;
5772 #[doc = "Field `ic_10bitaddr_master` writer - "]
5773 pub type Ic10bitaddrMasterW<'a, REG> = crate::BitWriter<'a, REG>;
5774 #[doc = "Field `ic_restart_en` reader - "]
5775 pub type IcRestartEnR = crate::BitReader;
5776 #[doc = "Field `ic_restart_en` writer - "]
5777 pub type IcRestartEnW<'a, REG> = crate::BitWriter<'a, REG>;
5778 #[doc = "Field `ic_slave_disable` reader - "]
5779 pub type IcSlaveDisableR = crate::BitReader;
5780 #[doc = "Field `ic_slave_disable` writer - "]
5781 pub type IcSlaveDisableW<'a, REG> = crate::BitWriter<'a, REG>;
5782 #[doc = "Field `stop_det_ifaddressed` reader - "]
5783 pub type StopDetIfaddressedR = crate::BitReader;
5784 #[doc = "Field `stop_det_ifaddressed` writer - "]
5785 pub type StopDetIfaddressedW<'a, REG> = crate::BitWriter<'a, REG>;
5786 #[doc = "Field `tx_empty_ctrl` reader - "]
5787 pub type TxEmptyCtrlR = crate::BitReader;
5788 #[doc = "Field `tx_empty_ctrl` writer - "]
5789 pub type TxEmptyCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
5790 #[doc = "Field `rx_fifo_full_hld_ctrl` reader - "]
5791 pub type RxFifoFullHldCtrlR = crate::BitReader;
5792 #[doc = "Field `rx_fifo_full_hld_ctrl` writer - "]
5793 pub type RxFifoFullHldCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
5794 #[doc = "Field `stop_det_if_master_active` reader - "]
5795 pub type StopDetIfMasterActiveR = crate::BitReader;
5796 #[doc = "Field `stop_det_if_master_active` writer - "]
5797 pub type StopDetIfMasterActiveW<'a, REG> = crate::BitWriter<'a, REG>;
5798 #[doc = "Field `bus_clear_feature_ctrl` reader - "]
5799 pub type BusClearFeatureCtrlR = crate::BitReader;
5800 #[doc = "Field `bus_clear_feature_ctrl` writer - "]
5801 pub type BusClearFeatureCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
5802 impl R {
5803 #[doc = "Bit 0 - 1=master"]
5804 #[inline(always)]
5805 pub fn master_mode(&self) -> MasterModeR {
5806 MasterModeR::new((self.bits & 1) != 0)
5807 }
5808 #[doc = "Bits 1:2 - 1=SS 2=FS 3=HS"]
5809 #[inline(always)]
5810 pub fn speed(&self) -> SpeedR {
5811 SpeedR::new(((self.bits >> 1) & 3) as u8)
5812 }
5813 #[doc = "Bit 3"]
5814 #[inline(always)]
5815 pub fn ic_10bitaddr_slave(&self) -> Ic10bitaddrSlaveR {
5816 Ic10bitaddrSlaveR::new(((self.bits >> 3) & 1) != 0)
5817 }
5818 #[doc = "Bit 4"]
5819 #[inline(always)]
5820 pub fn ic_10bitaddr_master(&self) -> Ic10bitaddrMasterR {
5821 Ic10bitaddrMasterR::new(((self.bits >> 4) & 1) != 0)
5822 }
5823 #[doc = "Bit 5"]
5824 #[inline(always)]
5825 pub fn ic_restart_en(&self) -> IcRestartEnR {
5826 IcRestartEnR::new(((self.bits >> 5) & 1) != 0)
5827 }
5828 #[doc = "Bit 6"]
5829 #[inline(always)]
5830 pub fn ic_slave_disable(&self) -> IcSlaveDisableR {
5831 IcSlaveDisableR::new(((self.bits >> 6) & 1) != 0)
5832 }
5833 #[doc = "Bit 7"]
5834 #[inline(always)]
5835 pub fn stop_det_ifaddressed(&self) -> StopDetIfaddressedR {
5836 StopDetIfaddressedR::new(((self.bits >> 7) & 1) != 0)
5837 }
5838 #[doc = "Bit 8"]
5839 #[inline(always)]
5840 pub fn tx_empty_ctrl(&self) -> TxEmptyCtrlR {
5841 TxEmptyCtrlR::new(((self.bits >> 8) & 1) != 0)
5842 }
5843 #[doc = "Bit 9"]
5844 #[inline(always)]
5845 pub fn rx_fifo_full_hld_ctrl(&self) -> RxFifoFullHldCtrlR {
5846 RxFifoFullHldCtrlR::new(((self.bits >> 9) & 1) != 0)
5847 }
5848 #[doc = "Bit 10"]
5849 #[inline(always)]
5850 pub fn stop_det_if_master_active(&self) -> StopDetIfMasterActiveR {
5851 StopDetIfMasterActiveR::new(((self.bits >> 10) & 1) != 0)
5852 }
5853 #[doc = "Bit 11"]
5854 #[inline(always)]
5855 pub fn bus_clear_feature_ctrl(&self) -> BusClearFeatureCtrlR {
5856 BusClearFeatureCtrlR::new(((self.bits >> 11) & 1) != 0)
5857 }
5858 }
5859 impl W {
5860 #[doc = "Bit 0 - 1=master"]
5861 #[inline(always)]
5862 pub fn master_mode(&mut self) -> MasterModeW<'_, IcConSpec> {
5863 MasterModeW::new(self, 0)
5864 }
5865 #[doc = "Bits 1:2 - 1=SS 2=FS 3=HS"]
5866 #[inline(always)]
5867 pub fn speed(&mut self) -> SpeedW<'_, IcConSpec> {
5868 SpeedW::new(self, 1)
5869 }
5870 #[doc = "Bit 3"]
5871 #[inline(always)]
5872 pub fn ic_10bitaddr_slave(&mut self) -> Ic10bitaddrSlaveW<'_, IcConSpec> {
5873 Ic10bitaddrSlaveW::new(self, 3)
5874 }
5875 #[doc = "Bit 4"]
5876 #[inline(always)]
5877 pub fn ic_10bitaddr_master(&mut self) -> Ic10bitaddrMasterW<'_, IcConSpec> {
5878 Ic10bitaddrMasterW::new(self, 4)
5879 }
5880 #[doc = "Bit 5"]
5881 #[inline(always)]
5882 pub fn ic_restart_en(&mut self) -> IcRestartEnW<'_, IcConSpec> {
5883 IcRestartEnW::new(self, 5)
5884 }
5885 #[doc = "Bit 6"]
5886 #[inline(always)]
5887 pub fn ic_slave_disable(&mut self) -> IcSlaveDisableW<'_, IcConSpec> {
5888 IcSlaveDisableW::new(self, 6)
5889 }
5890 #[doc = "Bit 7"]
5891 #[inline(always)]
5892 pub fn stop_det_ifaddressed(&mut self) -> StopDetIfaddressedW<'_, IcConSpec> {
5893 StopDetIfaddressedW::new(self, 7)
5894 }
5895 #[doc = "Bit 8"]
5896 #[inline(always)]
5897 pub fn tx_empty_ctrl(&mut self) -> TxEmptyCtrlW<'_, IcConSpec> {
5898 TxEmptyCtrlW::new(self, 8)
5899 }
5900 #[doc = "Bit 9"]
5901 #[inline(always)]
5902 pub fn rx_fifo_full_hld_ctrl(&mut self) -> RxFifoFullHldCtrlW<'_, IcConSpec> {
5903 RxFifoFullHldCtrlW::new(self, 9)
5904 }
5905 #[doc = "Bit 10"]
5906 #[inline(always)]
5907 pub fn stop_det_if_master_active(&mut self) -> StopDetIfMasterActiveW<'_, IcConSpec> {
5908 StopDetIfMasterActiveW::new(self, 10)
5909 }
5910 #[doc = "Bit 11"]
5911 #[inline(always)]
5912 pub fn bus_clear_feature_ctrl(&mut self) -> BusClearFeatureCtrlW<'_, IcConSpec> {
5913 BusClearFeatureCtrlW::new(self, 11)
5914 }
5915 }
5916 #[doc = "IC_CON\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_con::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_con::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
5917 pub struct IcConSpec;
5918 impl crate::RegisterSpec for IcConSpec {
5919 type Ux = u32;
5920 }
5921 #[doc = "`read()` method returns [`ic_con::R`](R) reader structure"]
5922 impl crate::Readable for IcConSpec {}
5923 #[doc = "`write(|w| ..)` method takes [`ic_con::W`](W) writer structure"]
5924 impl crate::Writable for IcConSpec {
5925 type Safety = crate::Unsafe;
5926 }
5927 #[doc = "`reset()` method sets IC_CON to value 0"]
5928 impl crate::Resettable for IcConSpec {}
5929 }
5930 #[doc = "IC_ENABLE (rw) register accessor: IC_ENABLE\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_enable`] module"]
5931 #[doc(alias = "IC_ENABLE")]
5932 pub type IcEnable = crate::Reg<ic_enable::IcEnableSpec>;
5933 #[doc = "IC_ENABLE"]
5934 pub mod ic_enable {
5935 #[doc = "Register `IC_ENABLE` reader"]
5936 pub type R = crate::R<IcEnableSpec>;
5937 #[doc = "Register `IC_ENABLE` writer"]
5938 pub type W = crate::W<IcEnableSpec>;
5939 #[doc = "Field `enable` reader - "]
5940 pub type EnableR = crate::BitReader;
5941 #[doc = "Field `enable` writer - "]
5942 pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
5943 #[doc = "Field `abort` reader - "]
5944 pub type AbortR = crate::BitReader;
5945 #[doc = "Field `abort` writer - "]
5946 pub type AbortW<'a, REG> = crate::BitWriter<'a, REG>;
5947 #[doc = "Field `tx_cmd_block` reader - "]
5948 pub type TxCmdBlockR = crate::BitReader;
5949 #[doc = "Field `tx_cmd_block` writer - "]
5950 pub type TxCmdBlockW<'a, REG> = crate::BitWriter<'a, REG>;
5951 #[doc = "Field `sda_stuck_recovery_enable` reader - "]
5952 pub type SdaStuckRecoveryEnableR = crate::BitReader;
5953 #[doc = "Field `sda_stuck_recovery_enable` writer - "]
5954 pub type SdaStuckRecoveryEnableW<'a, REG> = crate::BitWriter<'a, REG>;
5955 impl R {
5956 #[doc = "Bit 0"]
5957 #[inline(always)]
5958 pub fn enable(&self) -> EnableR {
5959 EnableR::new((self.bits & 1) != 0)
5960 }
5961 #[doc = "Bit 1"]
5962 #[inline(always)]
5963 pub fn abort(&self) -> AbortR {
5964 AbortR::new(((self.bits >> 1) & 1) != 0)
5965 }
5966 #[doc = "Bit 2"]
5967 #[inline(always)]
5968 pub fn tx_cmd_block(&self) -> TxCmdBlockR {
5969 TxCmdBlockR::new(((self.bits >> 2) & 1) != 0)
5970 }
5971 #[doc = "Bit 3"]
5972 #[inline(always)]
5973 pub fn sda_stuck_recovery_enable(&self) -> SdaStuckRecoveryEnableR {
5974 SdaStuckRecoveryEnableR::new(((self.bits >> 3) & 1) != 0)
5975 }
5976 }
5977 impl W {
5978 #[doc = "Bit 0"]
5979 #[inline(always)]
5980 pub fn enable(&mut self) -> EnableW<'_, IcEnableSpec> {
5981 EnableW::new(self, 0)
5982 }
5983 #[doc = "Bit 1"]
5984 #[inline(always)]
5985 pub fn abort(&mut self) -> AbortW<'_, IcEnableSpec> {
5986 AbortW::new(self, 1)
5987 }
5988 #[doc = "Bit 2"]
5989 #[inline(always)]
5990 pub fn tx_cmd_block(&mut self) -> TxCmdBlockW<'_, IcEnableSpec> {
5991 TxCmdBlockW::new(self, 2)
5992 }
5993 #[doc = "Bit 3"]
5994 #[inline(always)]
5995 pub fn sda_stuck_recovery_enable(
5996 &mut self,
5997 ) -> SdaStuckRecoveryEnableW<'_, IcEnableSpec> {
5998 SdaStuckRecoveryEnableW::new(self, 3)
5999 }
6000 }
6001 #[doc = "IC_ENABLE\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6002 pub struct IcEnableSpec;
6003 impl crate::RegisterSpec for IcEnableSpec {
6004 type Ux = u32;
6005 }
6006 #[doc = "`read()` method returns [`ic_enable::R`](R) reader structure"]
6007 impl crate::Readable for IcEnableSpec {}
6008 #[doc = "`write(|w| ..)` method takes [`ic_enable::W`](W) writer structure"]
6009 impl crate::Writable for IcEnableSpec {
6010 type Safety = crate::Unsafe;
6011 }
6012 #[doc = "`reset()` method sets IC_ENABLE to value 0"]
6013 impl crate::Resettable for IcEnableSpec {}
6014 }
6015 #[doc = "IC_TAR (rw) register accessor: IC_TAR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tar`] module"]
6016 #[doc(alias = "IC_TAR")]
6017 pub type IcTar = crate::Reg<ic_tar::IcTarSpec>;
6018 #[doc = "IC_TAR"]
6019 pub mod ic_tar {
6020 #[doc = "Register `IC_TAR` reader"]
6021 pub type R = crate::R<IcTarSpec>;
6022 #[doc = "Register `IC_TAR` writer"]
6023 pub type W = crate::W<IcTarSpec>;
6024 #[doc = "Field `ic_tar` reader - target address"]
6025 pub type IcTarR = crate::FieldReader<u16>;
6026 #[doc = "Field `ic_tar` writer - target address"]
6027 pub type IcTarW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
6028 #[doc = "Field `gc_or_start` reader - "]
6029 pub type GcOrStartR = crate::BitReader;
6030 #[doc = "Field `gc_or_start` writer - "]
6031 pub type GcOrStartW<'a, REG> = crate::BitWriter<'a, REG>;
6032 #[doc = "Field `special` reader - "]
6033 pub type SpecialR = crate::BitReader;
6034 #[doc = "Field `special` writer - "]
6035 pub type SpecialW<'a, REG> = crate::BitWriter<'a, REG>;
6036 #[doc = "Field `master_10bitaddr` reader - "]
6037 pub type Master10bitaddrR = crate::BitReader;
6038 #[doc = "Field `master_10bitaddr` writer - "]
6039 pub type Master10bitaddrW<'a, REG> = crate::BitWriter<'a, REG>;
6040 #[doc = "Field `device_id` reader - "]
6041 pub type DeviceIdR = crate::BitReader;
6042 #[doc = "Field `device_id` writer - "]
6043 pub type DeviceIdW<'a, REG> = crate::BitWriter<'a, REG>;
6044 impl R {
6045 #[doc = "Bits 0:9 - target address"]
6046 #[inline(always)]
6047 pub fn ic_tar(&self) -> IcTarR {
6048 IcTarR::new((self.bits & 0x03ff) as u16)
6049 }
6050 #[doc = "Bit 10"]
6051 #[inline(always)]
6052 pub fn gc_or_start(&self) -> GcOrStartR {
6053 GcOrStartR::new(((self.bits >> 10) & 1) != 0)
6054 }
6055 #[doc = "Bit 11"]
6056 #[inline(always)]
6057 pub fn special(&self) -> SpecialR {
6058 SpecialR::new(((self.bits >> 11) & 1) != 0)
6059 }
6060 #[doc = "Bit 12"]
6061 #[inline(always)]
6062 pub fn master_10bitaddr(&self) -> Master10bitaddrR {
6063 Master10bitaddrR::new(((self.bits >> 12) & 1) != 0)
6064 }
6065 #[doc = "Bit 13"]
6066 #[inline(always)]
6067 pub fn device_id(&self) -> DeviceIdR {
6068 DeviceIdR::new(((self.bits >> 13) & 1) != 0)
6069 }
6070 }
6071 impl W {
6072 #[doc = "Bits 0:9 - target address"]
6073 #[inline(always)]
6074 pub fn ic_tar(&mut self) -> IcTarW<'_, IcTarSpec> {
6075 IcTarW::new(self, 0)
6076 }
6077 #[doc = "Bit 10"]
6078 #[inline(always)]
6079 pub fn gc_or_start(&mut self) -> GcOrStartW<'_, IcTarSpec> {
6080 GcOrStartW::new(self, 10)
6081 }
6082 #[doc = "Bit 11"]
6083 #[inline(always)]
6084 pub fn special(&mut self) -> SpecialW<'_, IcTarSpec> {
6085 SpecialW::new(self, 11)
6086 }
6087 #[doc = "Bit 12"]
6088 #[inline(always)]
6089 pub fn master_10bitaddr(&mut self) -> Master10bitaddrW<'_, IcTarSpec> {
6090 Master10bitaddrW::new(self, 12)
6091 }
6092 #[doc = "Bit 13"]
6093 #[inline(always)]
6094 pub fn device_id(&mut self) -> DeviceIdW<'_, IcTarSpec> {
6095 DeviceIdW::new(self, 13)
6096 }
6097 }
6098 #[doc = "IC_TAR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6099 pub struct IcTarSpec;
6100 impl crate::RegisterSpec for IcTarSpec {
6101 type Ux = u32;
6102 }
6103 #[doc = "`read()` method returns [`ic_tar::R`](R) reader structure"]
6104 impl crate::Readable for IcTarSpec {}
6105 #[doc = "`write(|w| ..)` method takes [`ic_tar::W`](W) writer structure"]
6106 impl crate::Writable for IcTarSpec {
6107 type Safety = crate::Unsafe;
6108 }
6109 #[doc = "`reset()` method sets IC_TAR to value 0"]
6110 impl crate::Resettable for IcTarSpec {}
6111 }
6112 #[doc = "IC_SAR (rw) register accessor: IC_SAR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_sar`] module"]
6113 #[doc(alias = "IC_SAR")]
6114 pub type IcSar = crate::Reg<ic_sar::IcSarSpec>;
6115 #[doc = "IC_SAR"]
6116 pub mod ic_sar {
6117 #[doc = "Register `IC_SAR` reader"]
6118 pub type R = crate::R<IcSarSpec>;
6119 #[doc = "Register `IC_SAR` writer"]
6120 pub type W = crate::W<IcSarSpec>;
6121 #[doc = "Field `ic_sar` reader - slave address"]
6122 pub type IcSarR = crate::FieldReader<u16>;
6123 #[doc = "Field `ic_sar` writer - slave address"]
6124 pub type IcSarW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
6125 impl R {
6126 #[doc = "Bits 0:9 - slave address"]
6127 #[inline(always)]
6128 pub fn ic_sar(&self) -> IcSarR {
6129 IcSarR::new((self.bits & 0x03ff) as u16)
6130 }
6131 }
6132 impl W {
6133 #[doc = "Bits 0:9 - slave address"]
6134 #[inline(always)]
6135 pub fn ic_sar(&mut self) -> IcSarW<'_, IcSarSpec> {
6136 IcSarW::new(self, 0)
6137 }
6138 }
6139 #[doc = "IC_SAR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6140 pub struct IcSarSpec;
6141 impl crate::RegisterSpec for IcSarSpec {
6142 type Ux = u32;
6143 }
6144 #[doc = "`read()` method returns [`ic_sar::R`](R) reader structure"]
6145 impl crate::Readable for IcSarSpec {}
6146 #[doc = "`write(|w| ..)` method takes [`ic_sar::W`](W) writer structure"]
6147 impl crate::Writable for IcSarSpec {
6148 type Safety = crate::Unsafe;
6149 }
6150 #[doc = "`reset()` method sets IC_SAR to value 0"]
6151 impl crate::Resettable for IcSarSpec {}
6152 }
6153 #[doc = "IC_HS_MADDR (rw) register accessor: IC_HS_MADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_maddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_maddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_hs_maddr`] module"]
6154 #[doc(alias = "IC_HS_MADDR")]
6155 pub type IcHsMaddr = crate::Reg<ic_hs_maddr::IcHsMaddrSpec>;
6156 #[doc = "IC_HS_MADDR"]
6157 pub mod ic_hs_maddr {
6158 #[doc = "Register `IC_HS_MADDR` reader"]
6159 pub type R = crate::R<IcHsMaddrSpec>;
6160 #[doc = "Register `IC_HS_MADDR` writer"]
6161 pub type W = crate::W<IcHsMaddrSpec>;
6162 #[doc = "Field `ic_hs_mar` reader - "]
6163 pub type IcHsMarR = crate::FieldReader;
6164 #[doc = "Field `ic_hs_mar` writer - "]
6165 pub type IcHsMarW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
6166 impl R {
6167 #[doc = "Bits 0:2"]
6168 #[inline(always)]
6169 pub fn ic_hs_mar(&self) -> IcHsMarR {
6170 IcHsMarR::new((self.bits & 7) as u8)
6171 }
6172 }
6173 impl W {
6174 #[doc = "Bits 0:2"]
6175 #[inline(always)]
6176 pub fn ic_hs_mar(&mut self) -> IcHsMarW<'_, IcHsMaddrSpec> {
6177 IcHsMarW::new(self, 0)
6178 }
6179 }
6180 #[doc = "IC_HS_MADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_maddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_maddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6181 pub struct IcHsMaddrSpec;
6182 impl crate::RegisterSpec for IcHsMaddrSpec {
6183 type Ux = u32;
6184 }
6185 #[doc = "`read()` method returns [`ic_hs_maddr::R`](R) reader structure"]
6186 impl crate::Readable for IcHsMaddrSpec {}
6187 #[doc = "`write(|w| ..)` method takes [`ic_hs_maddr::W`](W) writer structure"]
6188 impl crate::Writable for IcHsMaddrSpec {
6189 type Safety = crate::Unsafe;
6190 }
6191 #[doc = "`reset()` method sets IC_HS_MADDR to value 0"]
6192 impl crate::Resettable for IcHsMaddrSpec {}
6193 }
6194 #[doc = "IC_DATA_CMD (rw) register accessor: IC_DATA_CMD\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_data_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_data_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_data_cmd`] module"]
6195 #[doc(alias = "IC_DATA_CMD")]
6196 pub type IcDataCmd = crate::Reg<ic_data_cmd::IcDataCmdSpec>;
6197 #[doc = "IC_DATA_CMD"]
6198 pub mod ic_data_cmd {
6199 #[doc = "Register `IC_DATA_CMD` reader"]
6200 pub type R = crate::R<IcDataCmdSpec>;
6201 #[doc = "Register `IC_DATA_CMD` writer"]
6202 pub type W = crate::W<IcDataCmdSpec>;
6203 #[doc = "Field `dat` reader - data byte"]
6204 pub type DatR = crate::FieldReader;
6205 #[doc = "Field `dat` writer - data byte"]
6206 pub type DatW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6207 #[doc = "Field `cmd` reader - 1=read 0=write"]
6208 pub type CmdR = crate::BitReader;
6209 #[doc = "Field `cmd` writer - 1=read 0=write"]
6210 pub type CmdW<'a, REG> = crate::BitWriter<'a, REG>;
6211 #[doc = "Field `stop` reader - "]
6212 pub type StopR = crate::BitReader;
6213 #[doc = "Field `stop` writer - "]
6214 pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
6215 #[doc = "Field `restart` reader - "]
6216 pub type RestartR = crate::BitReader;
6217 #[doc = "Field `restart` writer - "]
6218 pub type RestartW<'a, REG> = crate::BitWriter<'a, REG>;
6219 #[doc = "Field `first_data_byte` reader - "]
6220 pub type FirstDataByteR = crate::BitReader;
6221 impl R {
6222 #[doc = "Bits 0:7 - data byte"]
6223 #[inline(always)]
6224 pub fn dat(&self) -> DatR {
6225 DatR::new((self.bits & 0xff) as u8)
6226 }
6227 #[doc = "Bit 8 - 1=read 0=write"]
6228 #[inline(always)]
6229 pub fn cmd(&self) -> CmdR {
6230 CmdR::new(((self.bits >> 8) & 1) != 0)
6231 }
6232 #[doc = "Bit 9"]
6233 #[inline(always)]
6234 pub fn stop(&self) -> StopR {
6235 StopR::new(((self.bits >> 9) & 1) != 0)
6236 }
6237 #[doc = "Bit 10"]
6238 #[inline(always)]
6239 pub fn restart(&self) -> RestartR {
6240 RestartR::new(((self.bits >> 10) & 1) != 0)
6241 }
6242 #[doc = "Bit 11"]
6243 #[inline(always)]
6244 pub fn first_data_byte(&self) -> FirstDataByteR {
6245 FirstDataByteR::new(((self.bits >> 11) & 1) != 0)
6246 }
6247 }
6248 impl W {
6249 #[doc = "Bits 0:7 - data byte"]
6250 #[inline(always)]
6251 pub fn dat(&mut self) -> DatW<'_, IcDataCmdSpec> {
6252 DatW::new(self, 0)
6253 }
6254 #[doc = "Bit 8 - 1=read 0=write"]
6255 #[inline(always)]
6256 pub fn cmd(&mut self) -> CmdW<'_, IcDataCmdSpec> {
6257 CmdW::new(self, 8)
6258 }
6259 #[doc = "Bit 9"]
6260 #[inline(always)]
6261 pub fn stop(&mut self) -> StopW<'_, IcDataCmdSpec> {
6262 StopW::new(self, 9)
6263 }
6264 #[doc = "Bit 10"]
6265 #[inline(always)]
6266 pub fn restart(&mut self) -> RestartW<'_, IcDataCmdSpec> {
6267 RestartW::new(self, 10)
6268 }
6269 }
6270 #[doc = "IC_DATA_CMD\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_data_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_data_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6271 pub struct IcDataCmdSpec;
6272 impl crate::RegisterSpec for IcDataCmdSpec {
6273 type Ux = u32;
6274 }
6275 #[doc = "`read()` method returns [`ic_data_cmd::R`](R) reader structure"]
6276 impl crate::Readable for IcDataCmdSpec {}
6277 #[doc = "`write(|w| ..)` method takes [`ic_data_cmd::W`](W) writer structure"]
6278 impl crate::Writable for IcDataCmdSpec {
6279 type Safety = crate::Unsafe;
6280 }
6281 #[doc = "`reset()` method sets IC_DATA_CMD to value 0"]
6282 impl crate::Resettable for IcDataCmdSpec {}
6283 }
6284 #[doc = "IC_SS_SCL_HCNT (rw) register accessor: IC_SS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_ss_scl_hcnt`] module"]
6285 #[doc(alias = "IC_SS_SCL_HCNT")]
6286 pub type IcSsSclHcnt = crate::Reg<ic_ss_scl_hcnt::IcSsSclHcntSpec>;
6287 #[doc = "IC_SS_SCL_HCNT"]
6288 pub mod ic_ss_scl_hcnt {
6289 #[doc = "Register `IC_SS_SCL_HCNT` reader"]
6290 pub type R = crate::R<IcSsSclHcntSpec>;
6291 #[doc = "Register `IC_SS_SCL_HCNT` writer"]
6292 pub type W = crate::W<IcSsSclHcntSpec>;
6293 #[doc = "Field `cnt` reader - "]
6294 pub type CntR = crate::FieldReader<u16>;
6295 #[doc = "Field `cnt` writer - "]
6296 pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
6297 impl R {
6298 #[doc = "Bits 0:15"]
6299 #[inline(always)]
6300 pub fn cnt(&self) -> CntR {
6301 CntR::new((self.bits & 0xffff) as u16)
6302 }
6303 }
6304 impl W {
6305 #[doc = "Bits 0:15"]
6306 #[inline(always)]
6307 pub fn cnt(&mut self) -> CntW<'_, IcSsSclHcntSpec> {
6308 CntW::new(self, 0)
6309 }
6310 }
6311 #[doc = "IC_SS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6312 pub struct IcSsSclHcntSpec;
6313 impl crate::RegisterSpec for IcSsSclHcntSpec {
6314 type Ux = u32;
6315 }
6316 #[doc = "`read()` method returns [`ic_ss_scl_hcnt::R`](R) reader structure"]
6317 impl crate::Readable for IcSsSclHcntSpec {}
6318 #[doc = "`write(|w| ..)` method takes [`ic_ss_scl_hcnt::W`](W) writer structure"]
6319 impl crate::Writable for IcSsSclHcntSpec {
6320 type Safety = crate::Unsafe;
6321 }
6322 #[doc = "`reset()` method sets IC_SS_SCL_HCNT to value 0"]
6323 impl crate::Resettable for IcSsSclHcntSpec {}
6324 }
6325 #[doc = "IC_SS_SCL_LCNT (rw) register accessor: IC_SS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_ss_scl_lcnt`] module"]
6326 #[doc(alias = "IC_SS_SCL_LCNT")]
6327 pub type IcSsSclLcnt = crate::Reg<ic_ss_scl_lcnt::IcSsSclLcntSpec>;
6328 #[doc = "IC_SS_SCL_LCNT"]
6329 pub mod ic_ss_scl_lcnt {
6330 #[doc = "Register `IC_SS_SCL_LCNT` reader"]
6331 pub type R = crate::R<IcSsSclLcntSpec>;
6332 #[doc = "Register `IC_SS_SCL_LCNT` writer"]
6333 pub type W = crate::W<IcSsSclLcntSpec>;
6334 #[doc = "Field `cnt` reader - "]
6335 pub type CntR = crate::FieldReader<u16>;
6336 #[doc = "Field `cnt` writer - "]
6337 pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
6338 impl R {
6339 #[doc = "Bits 0:15"]
6340 #[inline(always)]
6341 pub fn cnt(&self) -> CntR {
6342 CntR::new((self.bits & 0xffff) as u16)
6343 }
6344 }
6345 impl W {
6346 #[doc = "Bits 0:15"]
6347 #[inline(always)]
6348 pub fn cnt(&mut self) -> CntW<'_, IcSsSclLcntSpec> {
6349 CntW::new(self, 0)
6350 }
6351 }
6352 #[doc = "IC_SS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6353 pub struct IcSsSclLcntSpec;
6354 impl crate::RegisterSpec for IcSsSclLcntSpec {
6355 type Ux = u32;
6356 }
6357 #[doc = "`read()` method returns [`ic_ss_scl_lcnt::R`](R) reader structure"]
6358 impl crate::Readable for IcSsSclLcntSpec {}
6359 #[doc = "`write(|w| ..)` method takes [`ic_ss_scl_lcnt::W`](W) writer structure"]
6360 impl crate::Writable for IcSsSclLcntSpec {
6361 type Safety = crate::Unsafe;
6362 }
6363 #[doc = "`reset()` method sets IC_SS_SCL_LCNT to value 0"]
6364 impl crate::Resettable for IcSsSclLcntSpec {}
6365 }
6366 #[doc = "IC_FS_SCL_HCNT (rw) register accessor: IC_FS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_fs_scl_hcnt`] module"]
6367 #[doc(alias = "IC_FS_SCL_HCNT")]
6368 pub type IcFsSclHcnt = crate::Reg<ic_fs_scl_hcnt::IcFsSclHcntSpec>;
6369 #[doc = "IC_FS_SCL_HCNT"]
6370 pub mod ic_fs_scl_hcnt {
6371 #[doc = "Register `IC_FS_SCL_HCNT` reader"]
6372 pub type R = crate::R<IcFsSclHcntSpec>;
6373 #[doc = "Register `IC_FS_SCL_HCNT` writer"]
6374 pub type W = crate::W<IcFsSclHcntSpec>;
6375 #[doc = "Field `cnt` reader - "]
6376 pub type CntR = crate::FieldReader<u16>;
6377 #[doc = "Field `cnt` writer - "]
6378 pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
6379 impl R {
6380 #[doc = "Bits 0:15"]
6381 #[inline(always)]
6382 pub fn cnt(&self) -> CntR {
6383 CntR::new((self.bits & 0xffff) as u16)
6384 }
6385 }
6386 impl W {
6387 #[doc = "Bits 0:15"]
6388 #[inline(always)]
6389 pub fn cnt(&mut self) -> CntW<'_, IcFsSclHcntSpec> {
6390 CntW::new(self, 0)
6391 }
6392 }
6393 #[doc = "IC_FS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6394 pub struct IcFsSclHcntSpec;
6395 impl crate::RegisterSpec for IcFsSclHcntSpec {
6396 type Ux = u32;
6397 }
6398 #[doc = "`read()` method returns [`ic_fs_scl_hcnt::R`](R) reader structure"]
6399 impl crate::Readable for IcFsSclHcntSpec {}
6400 #[doc = "`write(|w| ..)` method takes [`ic_fs_scl_hcnt::W`](W) writer structure"]
6401 impl crate::Writable for IcFsSclHcntSpec {
6402 type Safety = crate::Unsafe;
6403 }
6404 #[doc = "`reset()` method sets IC_FS_SCL_HCNT to value 0"]
6405 impl crate::Resettable for IcFsSclHcntSpec {}
6406 }
6407 #[doc = "IC_FS_SCL_LCNT (rw) register accessor: IC_FS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_fs_scl_lcnt`] module"]
6408 #[doc(alias = "IC_FS_SCL_LCNT")]
6409 pub type IcFsSclLcnt = crate::Reg<ic_fs_scl_lcnt::IcFsSclLcntSpec>;
6410 #[doc = "IC_FS_SCL_LCNT"]
6411 pub mod ic_fs_scl_lcnt {
6412 #[doc = "Register `IC_FS_SCL_LCNT` reader"]
6413 pub type R = crate::R<IcFsSclLcntSpec>;
6414 #[doc = "Register `IC_FS_SCL_LCNT` writer"]
6415 pub type W = crate::W<IcFsSclLcntSpec>;
6416 #[doc = "Field `cnt` reader - "]
6417 pub type CntR = crate::FieldReader<u16>;
6418 #[doc = "Field `cnt` writer - "]
6419 pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
6420 impl R {
6421 #[doc = "Bits 0:15"]
6422 #[inline(always)]
6423 pub fn cnt(&self) -> CntR {
6424 CntR::new((self.bits & 0xffff) as u16)
6425 }
6426 }
6427 impl W {
6428 #[doc = "Bits 0:15"]
6429 #[inline(always)]
6430 pub fn cnt(&mut self) -> CntW<'_, IcFsSclLcntSpec> {
6431 CntW::new(self, 0)
6432 }
6433 }
6434 #[doc = "IC_FS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6435 pub struct IcFsSclLcntSpec;
6436 impl crate::RegisterSpec for IcFsSclLcntSpec {
6437 type Ux = u32;
6438 }
6439 #[doc = "`read()` method returns [`ic_fs_scl_lcnt::R`](R) reader structure"]
6440 impl crate::Readable for IcFsSclLcntSpec {}
6441 #[doc = "`write(|w| ..)` method takes [`ic_fs_scl_lcnt::W`](W) writer structure"]
6442 impl crate::Writable for IcFsSclLcntSpec {
6443 type Safety = crate::Unsafe;
6444 }
6445 #[doc = "`reset()` method sets IC_FS_SCL_LCNT to value 0"]
6446 impl crate::Resettable for IcFsSclLcntSpec {}
6447 }
6448 #[doc = "IC_HS_SCL_HCNT (rw) register accessor: IC_HS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_hs_scl_hcnt`] module"]
6449 #[doc(alias = "IC_HS_SCL_HCNT")]
6450 pub type IcHsSclHcnt = crate::Reg<ic_hs_scl_hcnt::IcHsSclHcntSpec>;
6451 #[doc = "IC_HS_SCL_HCNT"]
6452 pub mod ic_hs_scl_hcnt {
6453 #[doc = "Register `IC_HS_SCL_HCNT` reader"]
6454 pub type R = crate::R<IcHsSclHcntSpec>;
6455 #[doc = "Register `IC_HS_SCL_HCNT` writer"]
6456 pub type W = crate::W<IcHsSclHcntSpec>;
6457 #[doc = "Field `cnt` reader - "]
6458 pub type CntR = crate::FieldReader<u16>;
6459 #[doc = "Field `cnt` writer - "]
6460 pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
6461 impl R {
6462 #[doc = "Bits 0:15"]
6463 #[inline(always)]
6464 pub fn cnt(&self) -> CntR {
6465 CntR::new((self.bits & 0xffff) as u16)
6466 }
6467 }
6468 impl W {
6469 #[doc = "Bits 0:15"]
6470 #[inline(always)]
6471 pub fn cnt(&mut self) -> CntW<'_, IcHsSclHcntSpec> {
6472 CntW::new(self, 0)
6473 }
6474 }
6475 #[doc = "IC_HS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6476 pub struct IcHsSclHcntSpec;
6477 impl crate::RegisterSpec for IcHsSclHcntSpec {
6478 type Ux = u32;
6479 }
6480 #[doc = "`read()` method returns [`ic_hs_scl_hcnt::R`](R) reader structure"]
6481 impl crate::Readable for IcHsSclHcntSpec {}
6482 #[doc = "`write(|w| ..)` method takes [`ic_hs_scl_hcnt::W`](W) writer structure"]
6483 impl crate::Writable for IcHsSclHcntSpec {
6484 type Safety = crate::Unsafe;
6485 }
6486 #[doc = "`reset()` method sets IC_HS_SCL_HCNT to value 0"]
6487 impl crate::Resettable for IcHsSclHcntSpec {}
6488 }
6489 #[doc = "IC_HS_SCL_LCNT (rw) register accessor: IC_HS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_hs_scl_lcnt`] module"]
6490 #[doc(alias = "IC_HS_SCL_LCNT")]
6491 pub type IcHsSclLcnt = crate::Reg<ic_hs_scl_lcnt::IcHsSclLcntSpec>;
6492 #[doc = "IC_HS_SCL_LCNT"]
6493 pub mod ic_hs_scl_lcnt {
6494 #[doc = "Register `IC_HS_SCL_LCNT` reader"]
6495 pub type R = crate::R<IcHsSclLcntSpec>;
6496 #[doc = "Register `IC_HS_SCL_LCNT` writer"]
6497 pub type W = crate::W<IcHsSclLcntSpec>;
6498 #[doc = "Field `cnt` reader - "]
6499 pub type CntR = crate::FieldReader<u16>;
6500 #[doc = "Field `cnt` writer - "]
6501 pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
6502 impl R {
6503 #[doc = "Bits 0:15"]
6504 #[inline(always)]
6505 pub fn cnt(&self) -> CntR {
6506 CntR::new((self.bits & 0xffff) as u16)
6507 }
6508 }
6509 impl W {
6510 #[doc = "Bits 0:15"]
6511 #[inline(always)]
6512 pub fn cnt(&mut self) -> CntW<'_, IcHsSclLcntSpec> {
6513 CntW::new(self, 0)
6514 }
6515 }
6516 #[doc = "IC_HS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6517 pub struct IcHsSclLcntSpec;
6518 impl crate::RegisterSpec for IcHsSclLcntSpec {
6519 type Ux = u32;
6520 }
6521 #[doc = "`read()` method returns [`ic_hs_scl_lcnt::R`](R) reader structure"]
6522 impl crate::Readable for IcHsSclLcntSpec {}
6523 #[doc = "`write(|w| ..)` method takes [`ic_hs_scl_lcnt::W`](W) writer structure"]
6524 impl crate::Writable for IcHsSclLcntSpec {
6525 type Safety = crate::Unsafe;
6526 }
6527 #[doc = "`reset()` method sets IC_HS_SCL_LCNT to value 0"]
6528 impl crate::Resettable for IcHsSclLcntSpec {}
6529 }
6530 #[doc = "IC_RX_TL (rw) register accessor: IC_RX_TL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_rx_tl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rx_tl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_rx_tl`] module"]
6531 #[doc(alias = "IC_RX_TL")]
6532 pub type IcRxTl = crate::Reg<ic_rx_tl::IcRxTlSpec>;
6533 #[doc = "IC_RX_TL"]
6534 pub mod ic_rx_tl {
6535 #[doc = "Register `IC_RX_TL` reader"]
6536 pub type R = crate::R<IcRxTlSpec>;
6537 #[doc = "Register `IC_RX_TL` writer"]
6538 pub type W = crate::W<IcRxTlSpec>;
6539 #[doc = "Field `rx_tl` reader - "]
6540 pub type RxTlR = crate::FieldReader;
6541 #[doc = "Field `rx_tl` writer - "]
6542 pub type RxTlW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6543 impl R {
6544 #[doc = "Bits 0:7"]
6545 #[inline(always)]
6546 pub fn rx_tl(&self) -> RxTlR {
6547 RxTlR::new((self.bits & 0xff) as u8)
6548 }
6549 }
6550 impl W {
6551 #[doc = "Bits 0:7"]
6552 #[inline(always)]
6553 pub fn rx_tl(&mut self) -> RxTlW<'_, IcRxTlSpec> {
6554 RxTlW::new(self, 0)
6555 }
6556 }
6557 #[doc = "IC_RX_TL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_rx_tl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rx_tl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6558 pub struct IcRxTlSpec;
6559 impl crate::RegisterSpec for IcRxTlSpec {
6560 type Ux = u32;
6561 }
6562 #[doc = "`read()` method returns [`ic_rx_tl::R`](R) reader structure"]
6563 impl crate::Readable for IcRxTlSpec {}
6564 #[doc = "`write(|w| ..)` method takes [`ic_rx_tl::W`](W) writer structure"]
6565 impl crate::Writable for IcRxTlSpec {
6566 type Safety = crate::Unsafe;
6567 }
6568 #[doc = "`reset()` method sets IC_RX_TL to value 0"]
6569 impl crate::Resettable for IcRxTlSpec {}
6570 }
6571 #[doc = "IC_TX_TL (rw) register accessor: IC_TX_TL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_tl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_tl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tx_tl`] module"]
6572 #[doc(alias = "IC_TX_TL")]
6573 pub type IcTxTl = crate::Reg<ic_tx_tl::IcTxTlSpec>;
6574 #[doc = "IC_TX_TL"]
6575 pub mod ic_tx_tl {
6576 #[doc = "Register `IC_TX_TL` reader"]
6577 pub type R = crate::R<IcTxTlSpec>;
6578 #[doc = "Register `IC_TX_TL` writer"]
6579 pub type W = crate::W<IcTxTlSpec>;
6580 #[doc = "Field `tx_tl` reader - "]
6581 pub type TxTlR = crate::FieldReader;
6582 #[doc = "Field `tx_tl` writer - "]
6583 pub type TxTlW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6584 impl R {
6585 #[doc = "Bits 0:7"]
6586 #[inline(always)]
6587 pub fn tx_tl(&self) -> TxTlR {
6588 TxTlR::new((self.bits & 0xff) as u8)
6589 }
6590 }
6591 impl W {
6592 #[doc = "Bits 0:7"]
6593 #[inline(always)]
6594 pub fn tx_tl(&mut self) -> TxTlW<'_, IcTxTlSpec> {
6595 TxTlW::new(self, 0)
6596 }
6597 }
6598 #[doc = "IC_TX_TL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_tl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_tl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6599 pub struct IcTxTlSpec;
6600 impl crate::RegisterSpec for IcTxTlSpec {
6601 type Ux = u32;
6602 }
6603 #[doc = "`read()` method returns [`ic_tx_tl::R`](R) reader structure"]
6604 impl crate::Readable for IcTxTlSpec {}
6605 #[doc = "`write(|w| ..)` method takes [`ic_tx_tl::W`](W) writer structure"]
6606 impl crate::Writable for IcTxTlSpec {
6607 type Safety = crate::Unsafe;
6608 }
6609 #[doc = "`reset()` method sets IC_TX_TL to value 0"]
6610 impl crate::Resettable for IcTxTlSpec {}
6611 }
6612 #[doc = "IC_SLV_DATA_NACK_ONLY (rw) register accessor: IC_SLV_DATA_NACK_ONLY\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_slv_data_nack_only::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_slv_data_nack_only`] module"]
6613 #[doc(alias = "IC_SLV_DATA_NACK_ONLY")]
6614 pub type IcSlvDataNackOnly = crate::Reg<ic_slv_data_nack_only::IcSlvDataNackOnlySpec>;
6615 #[doc = "IC_SLV_DATA_NACK_ONLY"]
6616 pub mod ic_slv_data_nack_only {
6617 #[doc = "Register `IC_SLV_DATA_NACK_ONLY` reader"]
6618 pub type R = crate::R<IcSlvDataNackOnlySpec>;
6619 #[doc = "Register `IC_SLV_DATA_NACK_ONLY` writer"]
6620 pub type W = crate::W<IcSlvDataNackOnlySpec>;
6621 #[doc = "Field `nack` reader - "]
6622 pub type NackR = crate::BitReader;
6623 #[doc = "Field `nack` writer - "]
6624 pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
6625 impl R {
6626 #[doc = "Bit 0"]
6627 #[inline(always)]
6628 pub fn nack(&self) -> NackR {
6629 NackR::new((self.bits & 1) != 0)
6630 }
6631 }
6632 impl W {
6633 #[doc = "Bit 0"]
6634 #[inline(always)]
6635 pub fn nack(&mut self) -> NackW<'_, IcSlvDataNackOnlySpec> {
6636 NackW::new(self, 0)
6637 }
6638 }
6639 #[doc = "IC_SLV_DATA_NACK_ONLY\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_slv_data_nack_only::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6640 pub struct IcSlvDataNackOnlySpec;
6641 impl crate::RegisterSpec for IcSlvDataNackOnlySpec {
6642 type Ux = u32;
6643 }
6644 #[doc = "`read()` method returns [`ic_slv_data_nack_only::R`](R) reader structure"]
6645 impl crate::Readable for IcSlvDataNackOnlySpec {}
6646 #[doc = "`write(|w| ..)` method takes [`ic_slv_data_nack_only::W`](W) writer structure"]
6647 impl crate::Writable for IcSlvDataNackOnlySpec {
6648 type Safety = crate::Unsafe;
6649 }
6650 #[doc = "`reset()` method sets IC_SLV_DATA_NACK_ONLY to value 0"]
6651 impl crate::Resettable for IcSlvDataNackOnlySpec {}
6652 }
6653 #[doc = "IC_STATUS (r) register accessor: IC_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_status`] module"]
6654 #[doc(alias = "IC_STATUS")]
6655 pub type IcStatus = crate::Reg<ic_status::IcStatusSpec>;
6656 #[doc = "IC_STATUS"]
6657 pub mod ic_status {
6658 #[doc = "Register `IC_STATUS` reader"]
6659 pub type R = crate::R<IcStatusSpec>;
6660 #[doc = "Field `activity` reader - "]
6661 pub type ActivityR = crate::BitReader;
6662 #[doc = "Field `tfnf` reader - TX not full"]
6663 pub type TfnfR = crate::BitReader;
6664 #[doc = "Field `tfe` reader - TX empty"]
6665 pub type TfeR = crate::BitReader;
6666 #[doc = "Field `rfne` reader - RX not empty"]
6667 pub type RfneR = crate::BitReader;
6668 #[doc = "Field `rff` reader - RX full"]
6669 pub type RffR = crate::BitReader;
6670 #[doc = "Field `mst_activity` reader - "]
6671 pub type MstActivityR = crate::BitReader;
6672 #[doc = "Field `slv_activity` reader - "]
6673 pub type SlvActivityR = crate::BitReader;
6674 impl R {
6675 #[doc = "Bit 0"]
6676 #[inline(always)]
6677 pub fn activity(&self) -> ActivityR {
6678 ActivityR::new((self.bits & 1) != 0)
6679 }
6680 #[doc = "Bit 1 - TX not full"]
6681 #[inline(always)]
6682 pub fn tfnf(&self) -> TfnfR {
6683 TfnfR::new(((self.bits >> 1) & 1) != 0)
6684 }
6685 #[doc = "Bit 2 - TX empty"]
6686 #[inline(always)]
6687 pub fn tfe(&self) -> TfeR {
6688 TfeR::new(((self.bits >> 2) & 1) != 0)
6689 }
6690 #[doc = "Bit 3 - RX not empty"]
6691 #[inline(always)]
6692 pub fn rfne(&self) -> RfneR {
6693 RfneR::new(((self.bits >> 3) & 1) != 0)
6694 }
6695 #[doc = "Bit 4 - RX full"]
6696 #[inline(always)]
6697 pub fn rff(&self) -> RffR {
6698 RffR::new(((self.bits >> 4) & 1) != 0)
6699 }
6700 #[doc = "Bit 5"]
6701 #[inline(always)]
6702 pub fn mst_activity(&self) -> MstActivityR {
6703 MstActivityR::new(((self.bits >> 5) & 1) != 0)
6704 }
6705 #[doc = "Bit 6"]
6706 #[inline(always)]
6707 pub fn slv_activity(&self) -> SlvActivityR {
6708 SlvActivityR::new(((self.bits >> 6) & 1) != 0)
6709 }
6710 }
6711 #[doc = "IC_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6712 pub struct IcStatusSpec;
6713 impl crate::RegisterSpec for IcStatusSpec {
6714 type Ux = u32;
6715 }
6716 #[doc = "`read()` method returns [`ic_status::R`](R) reader structure"]
6717 impl crate::Readable for IcStatusSpec {}
6718 #[doc = "`reset()` method sets IC_STATUS to value 0"]
6719 impl crate::Resettable for IcStatusSpec {}
6720 }
6721 #[doc = "IC_TXFLR (r) register accessor: IC_TXFLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_txflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_txflr`] module"]
6722 #[doc(alias = "IC_TXFLR")]
6723 pub type IcTxflr = crate::Reg<ic_txflr::IcTxflrSpec>;
6724 #[doc = "IC_TXFLR"]
6725 pub mod ic_txflr {
6726 #[doc = "Register `IC_TXFLR` reader"]
6727 pub type R = crate::R<IcTxflrSpec>;
6728 #[doc = "Field `txflr` reader - "]
6729 pub type TxflrR = crate::FieldReader;
6730 impl R {
6731 #[doc = "Bits 0:5"]
6732 #[inline(always)]
6733 pub fn txflr(&self) -> TxflrR {
6734 TxflrR::new((self.bits & 0x3f) as u8)
6735 }
6736 }
6737 #[doc = "IC_TXFLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_txflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6738 pub struct IcTxflrSpec;
6739 impl crate::RegisterSpec for IcTxflrSpec {
6740 type Ux = u32;
6741 }
6742 #[doc = "`read()` method returns [`ic_txflr::R`](R) reader structure"]
6743 impl crate::Readable for IcTxflrSpec {}
6744 #[doc = "`reset()` method sets IC_TXFLR to value 0"]
6745 impl crate::Resettable for IcTxflrSpec {}
6746 }
6747 #[doc = "IC_RXFLR (r) register accessor: IC_RXFLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_rxflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_rxflr`] module"]
6748 #[doc(alias = "IC_RXFLR")]
6749 pub type IcRxflr = crate::Reg<ic_rxflr::IcRxflrSpec>;
6750 #[doc = "IC_RXFLR"]
6751 pub mod ic_rxflr {
6752 #[doc = "Register `IC_RXFLR` reader"]
6753 pub type R = crate::R<IcRxflrSpec>;
6754 #[doc = "Field `rxflr` reader - "]
6755 pub type RxflrR = crate::FieldReader;
6756 impl R {
6757 #[doc = "Bits 0:5"]
6758 #[inline(always)]
6759 pub fn rxflr(&self) -> RxflrR {
6760 RxflrR::new((self.bits & 0x3f) as u8)
6761 }
6762 }
6763 #[doc = "IC_RXFLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_rxflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6764 pub struct IcRxflrSpec;
6765 impl crate::RegisterSpec for IcRxflrSpec {
6766 type Ux = u32;
6767 }
6768 #[doc = "`read()` method returns [`ic_rxflr::R`](R) reader structure"]
6769 impl crate::Readable for IcRxflrSpec {}
6770 #[doc = "`reset()` method sets IC_RXFLR to value 0"]
6771 impl crate::Resettable for IcRxflrSpec {}
6772 }
6773 #[doc = "IC_SDA_HOLD (rw) register accessor: IC_SDA_HOLD\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_sda_hold`] module"]
6774 #[doc(alias = "IC_SDA_HOLD")]
6775 pub type IcSdaHold = crate::Reg<ic_sda_hold::IcSdaHoldSpec>;
6776 #[doc = "IC_SDA_HOLD"]
6777 pub mod ic_sda_hold {
6778 #[doc = "Register `IC_SDA_HOLD` reader"]
6779 pub type R = crate::R<IcSdaHoldSpec>;
6780 #[doc = "Register `IC_SDA_HOLD` writer"]
6781 pub type W = crate::W<IcSdaHoldSpec>;
6782 #[doc = "Field `sda_rx_hold` reader - "]
6783 pub type SdaRxHoldR = crate::FieldReader;
6784 #[doc = "Field `sda_rx_hold` writer - "]
6785 pub type SdaRxHoldW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
6786 impl R {
6787 #[doc = "Bits 0:7"]
6788 #[inline(always)]
6789 pub fn sda_rx_hold(&self) -> SdaRxHoldR {
6790 SdaRxHoldR::new((self.bits & 0xff) as u8)
6791 }
6792 }
6793 impl W {
6794 #[doc = "Bits 0:7"]
6795 #[inline(always)]
6796 pub fn sda_rx_hold(&mut self) -> SdaRxHoldW<'_, IcSdaHoldSpec> {
6797 SdaRxHoldW::new(self, 0)
6798 }
6799 }
6800 #[doc = "IC_SDA_HOLD\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6801 pub struct IcSdaHoldSpec;
6802 impl crate::RegisterSpec for IcSdaHoldSpec {
6803 type Ux = u32;
6804 }
6805 #[doc = "`read()` method returns [`ic_sda_hold::R`](R) reader structure"]
6806 impl crate::Readable for IcSdaHoldSpec {}
6807 #[doc = "`write(|w| ..)` method takes [`ic_sda_hold::W`](W) writer structure"]
6808 impl crate::Writable for IcSdaHoldSpec {
6809 type Safety = crate::Unsafe;
6810 }
6811 #[doc = "`reset()` method sets IC_SDA_HOLD to value 0"]
6812 impl crate::Resettable for IcSdaHoldSpec {}
6813 }
6814 #[doc = "IC_SDA_HOLD_TX (rw) register accessor: IC_SDA_HOLD_TX\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_hold_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_sda_hold_tx`] module"]
6815 #[doc(alias = "IC_SDA_HOLD_TX")]
6816 pub type IcSdaHoldTx = crate::Reg<ic_sda_hold_tx::IcSdaHoldTxSpec>;
6817 #[doc = "IC_SDA_HOLD_TX"]
6818 pub mod ic_sda_hold_tx {
6819 #[doc = "Register `IC_SDA_HOLD_TX` reader"]
6820 pub type R = crate::R<IcSdaHoldTxSpec>;
6821 #[doc = "Register `IC_SDA_HOLD_TX` writer"]
6822 pub type W = crate::W<IcSdaHoldTxSpec>;
6823 #[doc = "Field `sda_tx_hold` reader - "]
6824 pub type SdaTxHoldR = crate::FieldReader<u16>;
6825 #[doc = "Field `sda_tx_hold` writer - "]
6826 pub type SdaTxHoldW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
6827 impl R {
6828 #[doc = "Bits 0:15"]
6829 #[inline(always)]
6830 pub fn sda_tx_hold(&self) -> SdaTxHoldR {
6831 SdaTxHoldR::new((self.bits & 0xffff) as u16)
6832 }
6833 }
6834 impl W {
6835 #[doc = "Bits 0:15"]
6836 #[inline(always)]
6837 pub fn sda_tx_hold(&mut self) -> SdaTxHoldW<'_, IcSdaHoldTxSpec> {
6838 SdaTxHoldW::new(self, 0)
6839 }
6840 }
6841 #[doc = "IC_SDA_HOLD_TX\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_hold_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6842 pub struct IcSdaHoldTxSpec;
6843 impl crate::RegisterSpec for IcSdaHoldTxSpec {
6844 type Ux = u32;
6845 }
6846 #[doc = "`read()` method returns [`ic_sda_hold_tx::R`](R) reader structure"]
6847 impl crate::Readable for IcSdaHoldTxSpec {}
6848 #[doc = "`write(|w| ..)` method takes [`ic_sda_hold_tx::W`](W) writer structure"]
6849 impl crate::Writable for IcSdaHoldTxSpec {
6850 type Safety = crate::Unsafe;
6851 }
6852 #[doc = "`reset()` method sets IC_SDA_HOLD_TX to value 0"]
6853 impl crate::Resettable for IcSdaHoldTxSpec {}
6854 }
6855 #[doc = "IC_TX_FLUSH_CNT (r) register accessor: IC_TX_FLUSH_CNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_flush_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tx_flush_cnt`] module"]
6856 #[doc(alias = "IC_TX_FLUSH_CNT")]
6857 pub type IcTxFlushCnt = crate::Reg<ic_tx_flush_cnt::IcTxFlushCntSpec>;
6858 #[doc = "IC_TX_FLUSH_CNT"]
6859 pub mod ic_tx_flush_cnt {
6860 #[doc = "Register `IC_TX_FLUSH_CNT` reader"]
6861 pub type R = crate::R<IcTxFlushCntSpec>;
6862 #[doc = "Field `cnt` reader - "]
6863 pub type CntR = crate::FieldReader<u16>;
6864 impl R {
6865 #[doc = "Bits 0:15"]
6866 #[inline(always)]
6867 pub fn cnt(&self) -> CntR {
6868 CntR::new((self.bits & 0xffff) as u16)
6869 }
6870 }
6871 #[doc = "IC_TX_FLUSH_CNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_flush_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6872 pub struct IcTxFlushCntSpec;
6873 impl crate::RegisterSpec for IcTxFlushCntSpec {
6874 type Ux = u32;
6875 }
6876 #[doc = "`read()` method returns [`ic_tx_flush_cnt::R`](R) reader structure"]
6877 impl crate::Readable for IcTxFlushCntSpec {}
6878 #[doc = "`reset()` method sets IC_TX_FLUSH_CNT to value 0"]
6879 impl crate::Resettable for IcTxFlushCntSpec {}
6880 }
6881 #[doc = "IC_TX_ABRT_SOURCE (r) register accessor: IC_TX_ABRT_SOURCE\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_source::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tx_abrt_source`] module"]
6882 #[doc(alias = "IC_TX_ABRT_SOURCE")]
6883 pub type IcTxAbrtSource = crate::Reg<ic_tx_abrt_source::IcTxAbrtSourceSpec>;
6884 #[doc = "IC_TX_ABRT_SOURCE"]
6885 pub mod ic_tx_abrt_source {
6886 #[doc = "Register `IC_TX_ABRT_SOURCE` reader"]
6887 pub type R = crate::R<IcTxAbrtSourceSpec>;
6888 #[doc = "Field `user_abrt` reader - "]
6889 pub type UserAbrtR = crate::BitReader;
6890 #[doc = "Field `sda_stuck_at_low` reader - "]
6891 pub type SdaStuckAtLowR = crate::BitReader;
6892 #[doc = "Field `device_noack` reader - "]
6893 pub type DeviceNoackR = crate::BitReader;
6894 #[doc = "Field `device_slvaddr_noack` reader - "]
6895 pub type DeviceSlvaddrNoackR = crate::BitReader;
6896 #[doc = "Field `abrt_device_write` reader - "]
6897 pub type AbrtDeviceWriteR = crate::BitReader;
6898 impl R {
6899 #[doc = "Bit 0"]
6900 #[inline(always)]
6901 pub fn user_abrt(&self) -> UserAbrtR {
6902 UserAbrtR::new((self.bits & 1) != 0)
6903 }
6904 #[doc = "Bit 1"]
6905 #[inline(always)]
6906 pub fn sda_stuck_at_low(&self) -> SdaStuckAtLowR {
6907 SdaStuckAtLowR::new(((self.bits >> 1) & 1) != 0)
6908 }
6909 #[doc = "Bit 2"]
6910 #[inline(always)]
6911 pub fn device_noack(&self) -> DeviceNoackR {
6912 DeviceNoackR::new(((self.bits >> 2) & 1) != 0)
6913 }
6914 #[doc = "Bit 3"]
6915 #[inline(always)]
6916 pub fn device_slvaddr_noack(&self) -> DeviceSlvaddrNoackR {
6917 DeviceSlvaddrNoackR::new(((self.bits >> 3) & 1) != 0)
6918 }
6919 #[doc = "Bit 4"]
6920 #[inline(always)]
6921 pub fn abrt_device_write(&self) -> AbrtDeviceWriteR {
6922 AbrtDeviceWriteR::new(((self.bits >> 4) & 1) != 0)
6923 }
6924 }
6925 #[doc = "IC_TX_ABRT_SOURCE\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_source::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6926 pub struct IcTxAbrtSourceSpec;
6927 impl crate::RegisterSpec for IcTxAbrtSourceSpec {
6928 type Ux = u32;
6929 }
6930 #[doc = "`read()` method returns [`ic_tx_abrt_source::R`](R) reader structure"]
6931 impl crate::Readable for IcTxAbrtSourceSpec {}
6932 #[doc = "`reset()` method sets IC_TX_ABRT_SOURCE to value 0"]
6933 impl crate::Resettable for IcTxAbrtSourceSpec {}
6934 }
6935 #[doc = "IC_TX_ABRT_SLV_INTX (r) register accessor: IC_TX_ABRT_SLV_INTX\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_slv_intx::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tx_abrt_slv_intx`] module"]
6936 #[doc(alias = "IC_TX_ABRT_SLV_INTX")]
6937 pub type IcTxAbrtSlvIntx = crate::Reg<ic_tx_abrt_slv_intx::IcTxAbrtSlvIntxSpec>;
6938 #[doc = "IC_TX_ABRT_SLV_INTX"]
6939 pub mod ic_tx_abrt_slv_intx {
6940 #[doc = "Register `IC_TX_ABRT_SLV_INTX` reader"]
6941 pub type R = crate::R<IcTxAbrtSlvIntxSpec>;
6942 #[doc = "Field `addr_7b_noack` reader - 7-bit address NACK (bus scan)"]
6943 pub type Addr7bNoackR = crate::BitReader;
6944 #[doc = "Field `addr1_10b_noack` reader - "]
6945 pub type Addr1_10bNoackR = crate::BitReader;
6946 #[doc = "Field `addr2_10b_noack` reader - "]
6947 pub type Addr2_10bNoackR = crate::BitReader;
6948 #[doc = "Field `txdata_noack` reader - "]
6949 pub type TxdataNoackR = crate::BitReader;
6950 #[doc = "Field `gcall_noack` reader - "]
6951 pub type GcallNoackR = crate::BitReader;
6952 #[doc = "Field `lost` reader - arbitration lost"]
6953 pub type LostR = crate::BitReader;
6954 impl R {
6955 #[doc = "Bit 0 - 7-bit address NACK (bus scan)"]
6956 #[inline(always)]
6957 pub fn addr_7b_noack(&self) -> Addr7bNoackR {
6958 Addr7bNoackR::new((self.bits & 1) != 0)
6959 }
6960 #[doc = "Bit 1"]
6961 #[inline(always)]
6962 pub fn addr1_10b_noack(&self) -> Addr1_10bNoackR {
6963 Addr1_10bNoackR::new(((self.bits >> 1) & 1) != 0)
6964 }
6965 #[doc = "Bit 2"]
6966 #[inline(always)]
6967 pub fn addr2_10b_noack(&self) -> Addr2_10bNoackR {
6968 Addr2_10bNoackR::new(((self.bits >> 2) & 1) != 0)
6969 }
6970 #[doc = "Bit 3"]
6971 #[inline(always)]
6972 pub fn txdata_noack(&self) -> TxdataNoackR {
6973 TxdataNoackR::new(((self.bits >> 3) & 1) != 0)
6974 }
6975 #[doc = "Bit 4"]
6976 #[inline(always)]
6977 pub fn gcall_noack(&self) -> GcallNoackR {
6978 GcallNoackR::new(((self.bits >> 4) & 1) != 0)
6979 }
6980 #[doc = "Bit 12 - arbitration lost"]
6981 #[inline(always)]
6982 pub fn lost(&self) -> LostR {
6983 LostR::new(((self.bits >> 12) & 1) != 0)
6984 }
6985 }
6986 #[doc = "IC_TX_ABRT_SLV_INTX\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_slv_intx::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
6987 pub struct IcTxAbrtSlvIntxSpec;
6988 impl crate::RegisterSpec for IcTxAbrtSlvIntxSpec {
6989 type Ux = u32;
6990 }
6991 #[doc = "`read()` method returns [`ic_tx_abrt_slv_intx::R`](R) reader structure"]
6992 impl crate::Readable for IcTxAbrtSlvIntxSpec {}
6993 #[doc = "`reset()` method sets IC_TX_ABRT_SLV_INTX to value 0"]
6994 impl crate::Resettable for IcTxAbrtSlvIntxSpec {}
6995 }
6996 #[doc = "IC_ACK_GENERAL_CALL (rw) register accessor: IC_ACK_GENERAL_CALL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ack_general_call::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ack_general_call::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_ack_general_call`] module"]
6997 #[doc(alias = "IC_ACK_GENERAL_CALL")]
6998 pub type IcAckGeneralCall = crate::Reg<ic_ack_general_call::IcAckGeneralCallSpec>;
6999 #[doc = "IC_ACK_GENERAL_CALL"]
7000 pub mod ic_ack_general_call {
7001 #[doc = "Register `IC_ACK_GENERAL_CALL` reader"]
7002 pub type R = crate::R<IcAckGeneralCallSpec>;
7003 #[doc = "Register `IC_ACK_GENERAL_CALL` writer"]
7004 pub type W = crate::W<IcAckGeneralCallSpec>;
7005 #[doc = "Field `ack_gen_call` reader - "]
7006 pub type AckGenCallR = crate::BitReader;
7007 #[doc = "Field `ack_gen_call` writer - "]
7008 pub type AckGenCallW<'a, REG> = crate::BitWriter<'a, REG>;
7009 impl R {
7010 #[doc = "Bit 0"]
7011 #[inline(always)]
7012 pub fn ack_gen_call(&self) -> AckGenCallR {
7013 AckGenCallR::new((self.bits & 1) != 0)
7014 }
7015 }
7016 impl W {
7017 #[doc = "Bit 0"]
7018 #[inline(always)]
7019 pub fn ack_gen_call(&mut self) -> AckGenCallW<'_, IcAckGeneralCallSpec> {
7020 AckGenCallW::new(self, 0)
7021 }
7022 }
7023 #[doc = "IC_ACK_GENERAL_CALL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ack_general_call::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ack_general_call::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7024 pub struct IcAckGeneralCallSpec;
7025 impl crate::RegisterSpec for IcAckGeneralCallSpec {
7026 type Ux = u32;
7027 }
7028 #[doc = "`read()` method returns [`ic_ack_general_call::R`](R) reader structure"]
7029 impl crate::Readable for IcAckGeneralCallSpec {}
7030 #[doc = "`write(|w| ..)` method takes [`ic_ack_general_call::W`](W) writer structure"]
7031 impl crate::Writable for IcAckGeneralCallSpec {
7032 type Safety = crate::Unsafe;
7033 }
7034 #[doc = "`reset()` method sets IC_ACK_GENERAL_CALL to value 0"]
7035 impl crate::Resettable for IcAckGeneralCallSpec {}
7036 }
7037 #[doc = "IC_ENABLE_STATUS (r) register accessor: IC_ENABLE_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_enable_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_enable_status`] module"]
7038 #[doc(alias = "IC_ENABLE_STATUS")]
7039 pub type IcEnableStatus = crate::Reg<ic_enable_status::IcEnableStatusSpec>;
7040 #[doc = "IC_ENABLE_STATUS"]
7041 pub mod ic_enable_status {
7042 #[doc = "Register `IC_ENABLE_STATUS` reader"]
7043 pub type R = crate::R<IcEnableStatusSpec>;
7044 #[doc = "Field `ic_en` reader - "]
7045 pub type IcEnR = crate::BitReader;
7046 #[doc = "Field `slv_disable_while_busy` reader - "]
7047 pub type SlvDisableWhileBusyR = crate::BitReader;
7048 #[doc = "Field `slv_rx_data_lost` reader - "]
7049 pub type SlvRxDataLostR = crate::BitReader;
7050 impl R {
7051 #[doc = "Bit 0"]
7052 #[inline(always)]
7053 pub fn ic_en(&self) -> IcEnR {
7054 IcEnR::new((self.bits & 1) != 0)
7055 }
7056 #[doc = "Bit 1"]
7057 #[inline(always)]
7058 pub fn slv_disable_while_busy(&self) -> SlvDisableWhileBusyR {
7059 SlvDisableWhileBusyR::new(((self.bits >> 1) & 1) != 0)
7060 }
7061 #[doc = "Bit 2"]
7062 #[inline(always)]
7063 pub fn slv_rx_data_lost(&self) -> SlvRxDataLostR {
7064 SlvRxDataLostR::new(((self.bits >> 2) & 1) != 0)
7065 }
7066 }
7067 #[doc = "IC_ENABLE_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_enable_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7068 pub struct IcEnableStatusSpec;
7069 impl crate::RegisterSpec for IcEnableStatusSpec {
7070 type Ux = u32;
7071 }
7072 #[doc = "`read()` method returns [`ic_enable_status::R`](R) reader structure"]
7073 impl crate::Readable for IcEnableStatusSpec {}
7074 #[doc = "`reset()` method sets IC_ENABLE_STATUS to value 0"]
7075 impl crate::Resettable for IcEnableStatusSpec {}
7076 }
7077 #[doc = "IC_DMA_CR (rw) register accessor: IC_DMA_CR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_dma_cr`] module"]
7078 #[doc(alias = "IC_DMA_CR")]
7079 pub type IcDmaCr = crate::Reg<ic_dma_cr::IcDmaCrSpec>;
7080 #[doc = "IC_DMA_CR"]
7081 pub mod ic_dma_cr {
7082 #[doc = "Register `IC_DMA_CR` reader"]
7083 pub type R = crate::R<IcDmaCrSpec>;
7084 #[doc = "Register `IC_DMA_CR` writer"]
7085 pub type W = crate::W<IcDmaCrSpec>;
7086 #[doc = "Field `rdmae` reader - "]
7087 pub type RdmaeR = crate::BitReader;
7088 #[doc = "Field `rdmae` writer - "]
7089 pub type RdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
7090 #[doc = "Field `tdmae` reader - "]
7091 pub type TdmaeR = crate::BitReader;
7092 #[doc = "Field `tdmae` writer - "]
7093 pub type TdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
7094 impl R {
7095 #[doc = "Bit 0"]
7096 #[inline(always)]
7097 pub fn rdmae(&self) -> RdmaeR {
7098 RdmaeR::new((self.bits & 1) != 0)
7099 }
7100 #[doc = "Bit 1"]
7101 #[inline(always)]
7102 pub fn tdmae(&self) -> TdmaeR {
7103 TdmaeR::new(((self.bits >> 1) & 1) != 0)
7104 }
7105 }
7106 impl W {
7107 #[doc = "Bit 0"]
7108 #[inline(always)]
7109 pub fn rdmae(&mut self) -> RdmaeW<'_, IcDmaCrSpec> {
7110 RdmaeW::new(self, 0)
7111 }
7112 #[doc = "Bit 1"]
7113 #[inline(always)]
7114 pub fn tdmae(&mut self) -> TdmaeW<'_, IcDmaCrSpec> {
7115 TdmaeW::new(self, 1)
7116 }
7117 }
7118 #[doc = "IC_DMA_CR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7119 pub struct IcDmaCrSpec;
7120 impl crate::RegisterSpec for IcDmaCrSpec {
7121 type Ux = u32;
7122 }
7123 #[doc = "`read()` method returns [`ic_dma_cr::R`](R) reader structure"]
7124 impl crate::Readable for IcDmaCrSpec {}
7125 #[doc = "`write(|w| ..)` method takes [`ic_dma_cr::W`](W) writer structure"]
7126 impl crate::Writable for IcDmaCrSpec {
7127 type Safety = crate::Unsafe;
7128 }
7129 #[doc = "`reset()` method sets IC_DMA_CR to value 0"]
7130 impl crate::Resettable for IcDmaCrSpec {}
7131 }
7132 #[doc = "IC_DMA_TDLR (rw) register accessor: IC_DMA_TDLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_tdlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_dma_tdlr`] module"]
7133 #[doc(alias = "IC_DMA_TDLR")]
7134 pub type IcDmaTdlr = crate::Reg<ic_dma_tdlr::IcDmaTdlrSpec>;
7135 #[doc = "IC_DMA_TDLR"]
7136 pub mod ic_dma_tdlr {
7137 #[doc = "Register `IC_DMA_TDLR` reader"]
7138 pub type R = crate::R<IcDmaTdlrSpec>;
7139 #[doc = "Register `IC_DMA_TDLR` writer"]
7140 pub type W = crate::W<IcDmaTdlrSpec>;
7141 #[doc = "Field `dmatdl` reader - "]
7142 pub type DmatdlR = crate::FieldReader;
7143 #[doc = "Field `dmatdl` writer - "]
7144 pub type DmatdlW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
7145 impl R {
7146 #[doc = "Bits 0:5"]
7147 #[inline(always)]
7148 pub fn dmatdl(&self) -> DmatdlR {
7149 DmatdlR::new((self.bits & 0x3f) as u8)
7150 }
7151 }
7152 impl W {
7153 #[doc = "Bits 0:5"]
7154 #[inline(always)]
7155 pub fn dmatdl(&mut self) -> DmatdlW<'_, IcDmaTdlrSpec> {
7156 DmatdlW::new(self, 0)
7157 }
7158 }
7159 #[doc = "IC_DMA_TDLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_tdlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7160 pub struct IcDmaTdlrSpec;
7161 impl crate::RegisterSpec for IcDmaTdlrSpec {
7162 type Ux = u32;
7163 }
7164 #[doc = "`read()` method returns [`ic_dma_tdlr::R`](R) reader structure"]
7165 impl crate::Readable for IcDmaTdlrSpec {}
7166 #[doc = "`write(|w| ..)` method takes [`ic_dma_tdlr::W`](W) writer structure"]
7167 impl crate::Writable for IcDmaTdlrSpec {
7168 type Safety = crate::Unsafe;
7169 }
7170 #[doc = "`reset()` method sets IC_DMA_TDLR to value 0"]
7171 impl crate::Resettable for IcDmaTdlrSpec {}
7172 }
7173 #[doc = "IC_DMA_RDLR (rw) register accessor: IC_DMA_RDLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_rdlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_dma_rdlr`] module"]
7174 #[doc(alias = "IC_DMA_RDLR")]
7175 pub type IcDmaRdlr = crate::Reg<ic_dma_rdlr::IcDmaRdlrSpec>;
7176 #[doc = "IC_DMA_RDLR"]
7177 pub mod ic_dma_rdlr {
7178 #[doc = "Register `IC_DMA_RDLR` reader"]
7179 pub type R = crate::R<IcDmaRdlrSpec>;
7180 #[doc = "Register `IC_DMA_RDLR` writer"]
7181 pub type W = crate::W<IcDmaRdlrSpec>;
7182 #[doc = "Field `dmardl` reader - "]
7183 pub type DmardlR = crate::FieldReader;
7184 #[doc = "Field `dmardl` writer - "]
7185 pub type DmardlW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
7186 impl R {
7187 #[doc = "Bits 0:5"]
7188 #[inline(always)]
7189 pub fn dmardl(&self) -> DmardlR {
7190 DmardlR::new((self.bits & 0x3f) as u8)
7191 }
7192 }
7193 impl W {
7194 #[doc = "Bits 0:5"]
7195 #[inline(always)]
7196 pub fn dmardl(&mut self) -> DmardlW<'_, IcDmaRdlrSpec> {
7197 DmardlW::new(self, 0)
7198 }
7199 }
7200 #[doc = "IC_DMA_RDLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_rdlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7201 pub struct IcDmaRdlrSpec;
7202 impl crate::RegisterSpec for IcDmaRdlrSpec {
7203 type Ux = u32;
7204 }
7205 #[doc = "`read()` method returns [`ic_dma_rdlr::R`](R) reader structure"]
7206 impl crate::Readable for IcDmaRdlrSpec {}
7207 #[doc = "`write(|w| ..)` method takes [`ic_dma_rdlr::W`](W) writer structure"]
7208 impl crate::Writable for IcDmaRdlrSpec {
7209 type Safety = crate::Unsafe;
7210 }
7211 #[doc = "`reset()` method sets IC_DMA_RDLR to value 0"]
7212 impl crate::Resettable for IcDmaRdlrSpec {}
7213 }
7214 #[doc = "IC_SDA_SETUP (rw) register accessor: IC_SDA_SETUP\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_sda_setup`] module"]
7215 #[doc(alias = "IC_SDA_SETUP")]
7216 pub type IcSdaSetup = crate::Reg<ic_sda_setup::IcSdaSetupSpec>;
7217 #[doc = "IC_SDA_SETUP"]
7218 pub mod ic_sda_setup {
7219 #[doc = "Register `IC_SDA_SETUP` reader"]
7220 pub type R = crate::R<IcSdaSetupSpec>;
7221 #[doc = "Register `IC_SDA_SETUP` writer"]
7222 pub type W = crate::W<IcSdaSetupSpec>;
7223 #[doc = "Field `sda_setup` reader - "]
7224 pub type SdaSetupR = crate::FieldReader;
7225 #[doc = "Field `sda_setup` writer - "]
7226 pub type SdaSetupW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
7227 impl R {
7228 #[doc = "Bits 0:7"]
7229 #[inline(always)]
7230 pub fn sda_setup(&self) -> SdaSetupR {
7231 SdaSetupR::new((self.bits & 0xff) as u8)
7232 }
7233 }
7234 impl W {
7235 #[doc = "Bits 0:7"]
7236 #[inline(always)]
7237 pub fn sda_setup(&mut self) -> SdaSetupW<'_, IcSdaSetupSpec> {
7238 SdaSetupW::new(self, 0)
7239 }
7240 }
7241 #[doc = "IC_SDA_SETUP\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7242 pub struct IcSdaSetupSpec;
7243 impl crate::RegisterSpec for IcSdaSetupSpec {
7244 type Ux = u32;
7245 }
7246 #[doc = "`read()` method returns [`ic_sda_setup::R`](R) reader structure"]
7247 impl crate::Readable for IcSdaSetupSpec {}
7248 #[doc = "`write(|w| ..)` method takes [`ic_sda_setup::W`](W) writer structure"]
7249 impl crate::Writable for IcSdaSetupSpec {
7250 type Safety = crate::Unsafe;
7251 }
7252 #[doc = "`reset()` method sets IC_SDA_SETUP to value 0"]
7253 impl crate::Resettable for IcSdaSetupSpec {}
7254 }
7255 #[doc = "IC_INTR_MASK (rw) register accessor: IC_INTR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_intr_mask`] module"]
7256 #[doc(alias = "IC_INTR_MASK")]
7257 pub type IcIntrMask = crate::Reg<ic_intr_mask::IcIntrMaskSpec>;
7258 #[doc = "IC_INTR_MASK"]
7259 pub mod ic_intr_mask {
7260 #[doc = "Register `IC_INTR_MASK` reader"]
7261 pub type R = crate::R<IcIntrMaskSpec>;
7262 #[doc = "Register `IC_INTR_MASK` writer"]
7263 pub type W = crate::W<IcIntrMaskSpec>;
7264 #[doc = "Field `rx_under` reader - "]
7265 pub type RxUnderR = crate::BitReader;
7266 #[doc = "Field `rx_under` writer - "]
7267 pub type RxUnderW<'a, REG> = crate::BitWriter<'a, REG>;
7268 #[doc = "Field `rx_over` reader - "]
7269 pub type RxOverR = crate::BitReader;
7270 #[doc = "Field `rx_over` writer - "]
7271 pub type RxOverW<'a, REG> = crate::BitWriter<'a, REG>;
7272 #[doc = "Field `rx_full` reader - "]
7273 pub type RxFullR = crate::BitReader;
7274 #[doc = "Field `rx_full` writer - "]
7275 pub type RxFullW<'a, REG> = crate::BitWriter<'a, REG>;
7276 #[doc = "Field `tx_over` reader - "]
7277 pub type TxOverR = crate::BitReader;
7278 #[doc = "Field `tx_over` writer - "]
7279 pub type TxOverW<'a, REG> = crate::BitWriter<'a, REG>;
7280 #[doc = "Field `tx_empty` reader - "]
7281 pub type TxEmptyR = crate::BitReader;
7282 #[doc = "Field `tx_empty` writer - "]
7283 pub type TxEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
7284 #[doc = "Field `rd_req` reader - "]
7285 pub type RdReqR = crate::BitReader;
7286 #[doc = "Field `rd_req` writer - "]
7287 pub type RdReqW<'a, REG> = crate::BitWriter<'a, REG>;
7288 #[doc = "Field `tx_abrt` reader - "]
7289 pub type TxAbrtR = crate::BitReader;
7290 #[doc = "Field `tx_abrt` writer - "]
7291 pub type TxAbrtW<'a, REG> = crate::BitWriter<'a, REG>;
7292 #[doc = "Field `rx_done` reader - "]
7293 pub type RxDoneR = crate::BitReader;
7294 #[doc = "Field `rx_done` writer - "]
7295 pub type RxDoneW<'a, REG> = crate::BitWriter<'a, REG>;
7296 #[doc = "Field `activity` reader - "]
7297 pub type ActivityR = crate::BitReader;
7298 #[doc = "Field `activity` writer - "]
7299 pub type ActivityW<'a, REG> = crate::BitWriter<'a, REG>;
7300 #[doc = "Field `stop_det` reader - "]
7301 pub type StopDetR = crate::BitReader;
7302 #[doc = "Field `stop_det` writer - "]
7303 pub type StopDetW<'a, REG> = crate::BitWriter<'a, REG>;
7304 #[doc = "Field `start_det` reader - "]
7305 pub type StartDetR = crate::BitReader;
7306 #[doc = "Field `start_det` writer - "]
7307 pub type StartDetW<'a, REG> = crate::BitWriter<'a, REG>;
7308 #[doc = "Field `gen_call` reader - "]
7309 pub type GenCallR = crate::BitReader;
7310 #[doc = "Field `gen_call` writer - "]
7311 pub type GenCallW<'a, REG> = crate::BitWriter<'a, REG>;
7312 #[doc = "Field `restart_det` reader - "]
7313 pub type RestartDetR = crate::BitReader;
7314 #[doc = "Field `restart_det` writer - "]
7315 pub type RestartDetW<'a, REG> = crate::BitWriter<'a, REG>;
7316 impl R {
7317 #[doc = "Bit 0"]
7318 #[inline(always)]
7319 pub fn rx_under(&self) -> RxUnderR {
7320 RxUnderR::new((self.bits & 1) != 0)
7321 }
7322 #[doc = "Bit 1"]
7323 #[inline(always)]
7324 pub fn rx_over(&self) -> RxOverR {
7325 RxOverR::new(((self.bits >> 1) & 1) != 0)
7326 }
7327 #[doc = "Bit 2"]
7328 #[inline(always)]
7329 pub fn rx_full(&self) -> RxFullR {
7330 RxFullR::new(((self.bits >> 2) & 1) != 0)
7331 }
7332 #[doc = "Bit 3"]
7333 #[inline(always)]
7334 pub fn tx_over(&self) -> TxOverR {
7335 TxOverR::new(((self.bits >> 3) & 1) != 0)
7336 }
7337 #[doc = "Bit 4"]
7338 #[inline(always)]
7339 pub fn tx_empty(&self) -> TxEmptyR {
7340 TxEmptyR::new(((self.bits >> 4) & 1) != 0)
7341 }
7342 #[doc = "Bit 5"]
7343 #[inline(always)]
7344 pub fn rd_req(&self) -> RdReqR {
7345 RdReqR::new(((self.bits >> 5) & 1) != 0)
7346 }
7347 #[doc = "Bit 6"]
7348 #[inline(always)]
7349 pub fn tx_abrt(&self) -> TxAbrtR {
7350 TxAbrtR::new(((self.bits >> 6) & 1) != 0)
7351 }
7352 #[doc = "Bit 7"]
7353 #[inline(always)]
7354 pub fn rx_done(&self) -> RxDoneR {
7355 RxDoneR::new(((self.bits >> 7) & 1) != 0)
7356 }
7357 #[doc = "Bit 8"]
7358 #[inline(always)]
7359 pub fn activity(&self) -> ActivityR {
7360 ActivityR::new(((self.bits >> 8) & 1) != 0)
7361 }
7362 #[doc = "Bit 9"]
7363 #[inline(always)]
7364 pub fn stop_det(&self) -> StopDetR {
7365 StopDetR::new(((self.bits >> 9) & 1) != 0)
7366 }
7367 #[doc = "Bit 10"]
7368 #[inline(always)]
7369 pub fn start_det(&self) -> StartDetR {
7370 StartDetR::new(((self.bits >> 10) & 1) != 0)
7371 }
7372 #[doc = "Bit 11"]
7373 #[inline(always)]
7374 pub fn gen_call(&self) -> GenCallR {
7375 GenCallR::new(((self.bits >> 11) & 1) != 0)
7376 }
7377 #[doc = "Bit 12"]
7378 #[inline(always)]
7379 pub fn restart_det(&self) -> RestartDetR {
7380 RestartDetR::new(((self.bits >> 12) & 1) != 0)
7381 }
7382 }
7383 impl W {
7384 #[doc = "Bit 0"]
7385 #[inline(always)]
7386 pub fn rx_under(&mut self) -> RxUnderW<'_, IcIntrMaskSpec> {
7387 RxUnderW::new(self, 0)
7388 }
7389 #[doc = "Bit 1"]
7390 #[inline(always)]
7391 pub fn rx_over(&mut self) -> RxOverW<'_, IcIntrMaskSpec> {
7392 RxOverW::new(self, 1)
7393 }
7394 #[doc = "Bit 2"]
7395 #[inline(always)]
7396 pub fn rx_full(&mut self) -> RxFullW<'_, IcIntrMaskSpec> {
7397 RxFullW::new(self, 2)
7398 }
7399 #[doc = "Bit 3"]
7400 #[inline(always)]
7401 pub fn tx_over(&mut self) -> TxOverW<'_, IcIntrMaskSpec> {
7402 TxOverW::new(self, 3)
7403 }
7404 #[doc = "Bit 4"]
7405 #[inline(always)]
7406 pub fn tx_empty(&mut self) -> TxEmptyW<'_, IcIntrMaskSpec> {
7407 TxEmptyW::new(self, 4)
7408 }
7409 #[doc = "Bit 5"]
7410 #[inline(always)]
7411 pub fn rd_req(&mut self) -> RdReqW<'_, IcIntrMaskSpec> {
7412 RdReqW::new(self, 5)
7413 }
7414 #[doc = "Bit 6"]
7415 #[inline(always)]
7416 pub fn tx_abrt(&mut self) -> TxAbrtW<'_, IcIntrMaskSpec> {
7417 TxAbrtW::new(self, 6)
7418 }
7419 #[doc = "Bit 7"]
7420 #[inline(always)]
7421 pub fn rx_done(&mut self) -> RxDoneW<'_, IcIntrMaskSpec> {
7422 RxDoneW::new(self, 7)
7423 }
7424 #[doc = "Bit 8"]
7425 #[inline(always)]
7426 pub fn activity(&mut self) -> ActivityW<'_, IcIntrMaskSpec> {
7427 ActivityW::new(self, 8)
7428 }
7429 #[doc = "Bit 9"]
7430 #[inline(always)]
7431 pub fn stop_det(&mut self) -> StopDetW<'_, IcIntrMaskSpec> {
7432 StopDetW::new(self, 9)
7433 }
7434 #[doc = "Bit 10"]
7435 #[inline(always)]
7436 pub fn start_det(&mut self) -> StartDetW<'_, IcIntrMaskSpec> {
7437 StartDetW::new(self, 10)
7438 }
7439 #[doc = "Bit 11"]
7440 #[inline(always)]
7441 pub fn gen_call(&mut self) -> GenCallW<'_, IcIntrMaskSpec> {
7442 GenCallW::new(self, 11)
7443 }
7444 #[doc = "Bit 12"]
7445 #[inline(always)]
7446 pub fn restart_det(&mut self) -> RestartDetW<'_, IcIntrMaskSpec> {
7447 RestartDetW::new(self, 12)
7448 }
7449 }
7450 #[doc = "IC_INTR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7451 pub struct IcIntrMaskSpec;
7452 impl crate::RegisterSpec for IcIntrMaskSpec {
7453 type Ux = u32;
7454 }
7455 #[doc = "`read()` method returns [`ic_intr_mask::R`](R) reader structure"]
7456 impl crate::Readable for IcIntrMaskSpec {}
7457 #[doc = "`write(|w| ..)` method takes [`ic_intr_mask::W`](W) writer structure"]
7458 impl crate::Writable for IcIntrMaskSpec {
7459 type Safety = crate::Unsafe;
7460 }
7461 #[doc = "`reset()` method sets IC_INTR_MASK to value 0"]
7462 impl crate::Resettable for IcIntrMaskSpec {}
7463 }
7464 #[doc = "IC_INTR_STAT (r) register accessor: IC_INTR_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_intr_stat`] module"]
7465 #[doc(alias = "IC_INTR_STAT")]
7466 pub type IcIntrStat = crate::Reg<ic_intr_stat::IcIntrStatSpec>;
7467 #[doc = "IC_INTR_STAT"]
7468 pub mod ic_intr_stat {
7469 #[doc = "Register `IC_INTR_STAT` reader"]
7470 pub type R = crate::R<IcIntrStatSpec>;
7471 #[doc = "Field `rx_under` reader - "]
7472 pub type RxUnderR = crate::BitReader;
7473 #[doc = "Field `rx_over` reader - "]
7474 pub type RxOverR = crate::BitReader;
7475 #[doc = "Field `rx_full` reader - "]
7476 pub type RxFullR = crate::BitReader;
7477 #[doc = "Field `tx_over` reader - "]
7478 pub type TxOverR = crate::BitReader;
7479 #[doc = "Field `tx_empty` reader - "]
7480 pub type TxEmptyR = crate::BitReader;
7481 #[doc = "Field `rd_req` reader - "]
7482 pub type RdReqR = crate::BitReader;
7483 #[doc = "Field `tx_abrt` reader - "]
7484 pub type TxAbrtR = crate::BitReader;
7485 #[doc = "Field `rx_done` reader - "]
7486 pub type RxDoneR = crate::BitReader;
7487 #[doc = "Field `activity` reader - "]
7488 pub type ActivityR = crate::BitReader;
7489 #[doc = "Field `stop_det` reader - "]
7490 pub type StopDetR = crate::BitReader;
7491 #[doc = "Field `start_det` reader - "]
7492 pub type StartDetR = crate::BitReader;
7493 #[doc = "Field `gen_call` reader - "]
7494 pub type GenCallR = crate::BitReader;
7495 #[doc = "Field `restart_det` reader - "]
7496 pub type RestartDetR = crate::BitReader;
7497 impl R {
7498 #[doc = "Bit 0"]
7499 #[inline(always)]
7500 pub fn rx_under(&self) -> RxUnderR {
7501 RxUnderR::new((self.bits & 1) != 0)
7502 }
7503 #[doc = "Bit 1"]
7504 #[inline(always)]
7505 pub fn rx_over(&self) -> RxOverR {
7506 RxOverR::new(((self.bits >> 1) & 1) != 0)
7507 }
7508 #[doc = "Bit 2"]
7509 #[inline(always)]
7510 pub fn rx_full(&self) -> RxFullR {
7511 RxFullR::new(((self.bits >> 2) & 1) != 0)
7512 }
7513 #[doc = "Bit 3"]
7514 #[inline(always)]
7515 pub fn tx_over(&self) -> TxOverR {
7516 TxOverR::new(((self.bits >> 3) & 1) != 0)
7517 }
7518 #[doc = "Bit 4"]
7519 #[inline(always)]
7520 pub fn tx_empty(&self) -> TxEmptyR {
7521 TxEmptyR::new(((self.bits >> 4) & 1) != 0)
7522 }
7523 #[doc = "Bit 5"]
7524 #[inline(always)]
7525 pub fn rd_req(&self) -> RdReqR {
7526 RdReqR::new(((self.bits >> 5) & 1) != 0)
7527 }
7528 #[doc = "Bit 6"]
7529 #[inline(always)]
7530 pub fn tx_abrt(&self) -> TxAbrtR {
7531 TxAbrtR::new(((self.bits >> 6) & 1) != 0)
7532 }
7533 #[doc = "Bit 7"]
7534 #[inline(always)]
7535 pub fn rx_done(&self) -> RxDoneR {
7536 RxDoneR::new(((self.bits >> 7) & 1) != 0)
7537 }
7538 #[doc = "Bit 8"]
7539 #[inline(always)]
7540 pub fn activity(&self) -> ActivityR {
7541 ActivityR::new(((self.bits >> 8) & 1) != 0)
7542 }
7543 #[doc = "Bit 9"]
7544 #[inline(always)]
7545 pub fn stop_det(&self) -> StopDetR {
7546 StopDetR::new(((self.bits >> 9) & 1) != 0)
7547 }
7548 #[doc = "Bit 10"]
7549 #[inline(always)]
7550 pub fn start_det(&self) -> StartDetR {
7551 StartDetR::new(((self.bits >> 10) & 1) != 0)
7552 }
7553 #[doc = "Bit 11"]
7554 #[inline(always)]
7555 pub fn gen_call(&self) -> GenCallR {
7556 GenCallR::new(((self.bits >> 11) & 1) != 0)
7557 }
7558 #[doc = "Bit 12"]
7559 #[inline(always)]
7560 pub fn restart_det(&self) -> RestartDetR {
7561 RestartDetR::new(((self.bits >> 12) & 1) != 0)
7562 }
7563 }
7564 #[doc = "IC_INTR_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7565 pub struct IcIntrStatSpec;
7566 impl crate::RegisterSpec for IcIntrStatSpec {
7567 type Ux = u32;
7568 }
7569 #[doc = "`read()` method returns [`ic_intr_stat::R`](R) reader structure"]
7570 impl crate::Readable for IcIntrStatSpec {}
7571 #[doc = "`reset()` method sets IC_INTR_STAT to value 0"]
7572 impl crate::Resettable for IcIntrStatSpec {}
7573 }
7574 #[doc = "IC_RAW_INTR_STAT (r) register accessor: IC_RAW_INTR_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_raw_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_raw_intr_stat`] module"]
7575 #[doc(alias = "IC_RAW_INTR_STAT")]
7576 pub type IcRawIntrStat = crate::Reg<ic_raw_intr_stat::IcRawIntrStatSpec>;
7577 #[doc = "IC_RAW_INTR_STAT"]
7578 pub mod ic_raw_intr_stat {
7579 #[doc = "Register `IC_RAW_INTR_STAT` reader"]
7580 pub type R = crate::R<IcRawIntrStatSpec>;
7581 #[doc = "Field `rx_under` reader - "]
7582 pub type RxUnderR = crate::BitReader;
7583 #[doc = "Field `rx_over` reader - "]
7584 pub type RxOverR = crate::BitReader;
7585 #[doc = "Field `rx_full` reader - "]
7586 pub type RxFullR = crate::BitReader;
7587 #[doc = "Field `tx_over` reader - "]
7588 pub type TxOverR = crate::BitReader;
7589 #[doc = "Field `tx_empty` reader - "]
7590 pub type TxEmptyR = crate::BitReader;
7591 #[doc = "Field `rd_req` reader - "]
7592 pub type RdReqR = crate::BitReader;
7593 #[doc = "Field `tx_abrt` reader - "]
7594 pub type TxAbrtR = crate::BitReader;
7595 #[doc = "Field `rx_done` reader - "]
7596 pub type RxDoneR = crate::BitReader;
7597 #[doc = "Field `activity` reader - "]
7598 pub type ActivityR = crate::BitReader;
7599 #[doc = "Field `stop_det` reader - "]
7600 pub type StopDetR = crate::BitReader;
7601 #[doc = "Field `start_det` reader - "]
7602 pub type StartDetR = crate::BitReader;
7603 #[doc = "Field `gen_call` reader - "]
7604 pub type GenCallR = crate::BitReader;
7605 #[doc = "Field `restart_det` reader - "]
7606 pub type RestartDetR = crate::BitReader;
7607 impl R {
7608 #[doc = "Bit 0"]
7609 #[inline(always)]
7610 pub fn rx_under(&self) -> RxUnderR {
7611 RxUnderR::new((self.bits & 1) != 0)
7612 }
7613 #[doc = "Bit 1"]
7614 #[inline(always)]
7615 pub fn rx_over(&self) -> RxOverR {
7616 RxOverR::new(((self.bits >> 1) & 1) != 0)
7617 }
7618 #[doc = "Bit 2"]
7619 #[inline(always)]
7620 pub fn rx_full(&self) -> RxFullR {
7621 RxFullR::new(((self.bits >> 2) & 1) != 0)
7622 }
7623 #[doc = "Bit 3"]
7624 #[inline(always)]
7625 pub fn tx_over(&self) -> TxOverR {
7626 TxOverR::new(((self.bits >> 3) & 1) != 0)
7627 }
7628 #[doc = "Bit 4"]
7629 #[inline(always)]
7630 pub fn tx_empty(&self) -> TxEmptyR {
7631 TxEmptyR::new(((self.bits >> 4) & 1) != 0)
7632 }
7633 #[doc = "Bit 5"]
7634 #[inline(always)]
7635 pub fn rd_req(&self) -> RdReqR {
7636 RdReqR::new(((self.bits >> 5) & 1) != 0)
7637 }
7638 #[doc = "Bit 6"]
7639 #[inline(always)]
7640 pub fn tx_abrt(&self) -> TxAbrtR {
7641 TxAbrtR::new(((self.bits >> 6) & 1) != 0)
7642 }
7643 #[doc = "Bit 7"]
7644 #[inline(always)]
7645 pub fn rx_done(&self) -> RxDoneR {
7646 RxDoneR::new(((self.bits >> 7) & 1) != 0)
7647 }
7648 #[doc = "Bit 8"]
7649 #[inline(always)]
7650 pub fn activity(&self) -> ActivityR {
7651 ActivityR::new(((self.bits >> 8) & 1) != 0)
7652 }
7653 #[doc = "Bit 9"]
7654 #[inline(always)]
7655 pub fn stop_det(&self) -> StopDetR {
7656 StopDetR::new(((self.bits >> 9) & 1) != 0)
7657 }
7658 #[doc = "Bit 10"]
7659 #[inline(always)]
7660 pub fn start_det(&self) -> StartDetR {
7661 StartDetR::new(((self.bits >> 10) & 1) != 0)
7662 }
7663 #[doc = "Bit 11"]
7664 #[inline(always)]
7665 pub fn gen_call(&self) -> GenCallR {
7666 GenCallR::new(((self.bits >> 11) & 1) != 0)
7667 }
7668 #[doc = "Bit 12"]
7669 #[inline(always)]
7670 pub fn restart_det(&self) -> RestartDetR {
7671 RestartDetR::new(((self.bits >> 12) & 1) != 0)
7672 }
7673 }
7674 #[doc = "IC_RAW_INTR_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_raw_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7675 pub struct IcRawIntrStatSpec;
7676 impl crate::RegisterSpec for IcRawIntrStatSpec {
7677 type Ux = u32;
7678 }
7679 #[doc = "`read()` method returns [`ic_raw_intr_stat::R`](R) reader structure"]
7680 impl crate::Readable for IcRawIntrStatSpec {}
7681 #[doc = "`reset()` method sets IC_RAW_INTR_STAT to value 0"]
7682 impl crate::Resettable for IcRawIntrStatSpec {}
7683 }
7684 #[doc = "IC_INTR_STAT_ALL (r) register accessor: IC_INTR_STAT_ALL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_stat_all::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_intr_stat_all`] module"]
7685 #[doc(alias = "IC_INTR_STAT_ALL")]
7686 pub type IcIntrStatAll = crate::Reg<ic_intr_stat_all::IcIntrStatAllSpec>;
7687 #[doc = "IC_INTR_STAT_ALL"]
7688 pub mod ic_intr_stat_all {
7689 #[doc = "Register `IC_INTR_STAT_ALL` reader"]
7690 pub type R = crate::R<IcIntrStatAllSpec>;
7691 #[doc = "Field `stat` reader - "]
7692 pub type StatR = crate::FieldReader<u16>;
7693 impl R {
7694 #[doc = "Bits 0:12"]
7695 #[inline(always)]
7696 pub fn stat(&self) -> StatR {
7697 StatR::new((self.bits & 0x1fff) as u16)
7698 }
7699 }
7700 #[doc = "IC_INTR_STAT_ALL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_stat_all::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7701 pub struct IcIntrStatAllSpec;
7702 impl crate::RegisterSpec for IcIntrStatAllSpec {
7703 type Ux = u32;
7704 }
7705 #[doc = "`read()` method returns [`ic_intr_stat_all::R`](R) reader structure"]
7706 impl crate::Readable for IcIntrStatAllSpec {}
7707 #[doc = "`reset()` method sets IC_INTR_STAT_ALL to value 0"]
7708 impl crate::Resettable for IcIntrStatAllSpec {}
7709 }
7710 #[doc = "IC_CLR_INTR (r) register accessor: IC_CLR_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_clr_intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_clr_intr`] module"]
7711 #[doc(alias = "IC_CLR_INTR")]
7712 pub type IcClrIntr = crate::Reg<ic_clr_intr::IcClrIntrSpec>;
7713 #[doc = "IC_CLR_INTR"]
7714 pub mod ic_clr_intr {
7715 #[doc = "Register `IC_CLR_INTR` reader"]
7716 pub type R = crate::R<IcClrIntrSpec>;
7717 #[doc = "Field `clr` reader - read-to-clear all"]
7718 pub type ClrR = crate::BitReader;
7719 impl R {
7720 #[doc = "Bit 0 - read-to-clear all"]
7721 #[inline(always)]
7722 pub fn clr(&self) -> ClrR {
7723 ClrR::new((self.bits & 1) != 0)
7724 }
7725 }
7726 #[doc = "IC_CLR_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_clr_intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7727 pub struct IcClrIntrSpec;
7728 impl crate::RegisterSpec for IcClrIntrSpec {
7729 type Ux = u32;
7730 }
7731 #[doc = "`read()` method returns [`ic_clr_intr::R`](R) reader structure"]
7732 impl crate::Readable for IcClrIntrSpec {}
7733 #[doc = "`reset()` method sets IC_CLR_INTR to value 0"]
7734 impl crate::Resettable for IcClrIntrSpec {}
7735 }
7736 #[doc = "IC_CLR_INT (r) register accessor: IC_CLR_INT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_clr_int::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_clr_int`] module"]
7737 #[doc(alias = "IC_CLR_INT")]
7738 pub type IcClrInt = crate::Reg<ic_clr_int::IcClrIntSpec>;
7739 #[doc = "IC_CLR_INT"]
7740 pub mod ic_clr_int {
7741 #[doc = "Register `IC_CLR_INT` reader"]
7742 pub type R = crate::R<IcClrIntSpec>;
7743 #[doc = "Field `clr` reader - read-to-clear combined"]
7744 pub type ClrR = crate::BitReader;
7745 impl R {
7746 #[doc = "Bit 0 - read-to-clear combined"]
7747 #[inline(always)]
7748 pub fn clr(&self) -> ClrR {
7749 ClrR::new((self.bits & 1) != 0)
7750 }
7751 }
7752 #[doc = "IC_CLR_INT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_clr_int::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7753 pub struct IcClrIntSpec;
7754 impl crate::RegisterSpec for IcClrIntSpec {
7755 type Ux = u32;
7756 }
7757 #[doc = "`read()` method returns [`ic_clr_int::R`](R) reader structure"]
7758 impl crate::Readable for IcClrIntSpec {}
7759 #[doc = "`reset()` method sets IC_CLR_INT to value 0"]
7760 impl crate::Resettable for IcClrIntSpec {}
7761 }
7762}
7763#[doc = "SPI0 master/slave controller (SSI v151)"]
7764pub type Spi0 = crate::Periph<spi0::RegisterBlock, 0x5208_7000>;
7765impl core::fmt::Debug for Spi0 {
7766 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
7767 f.debug_struct("Spi0").finish()
7768 }
7769}
7770#[doc = "SPI0 master/slave controller (SSI v151)"]
7771pub mod spi0 {
7772 #[repr(C)]
7773 #[doc = "Register block"]
7774 pub struct RegisterBlock {
7775 spi_er: SpiEr,
7776 spi_ctra: SpiCtra,
7777 spi_ctrb: SpiCtrb,
7778 spi_enhctl: SpiEnhctl,
7779 _reserved4: [u8; 0x04],
7780 spi_brs: SpiBrs,
7781 spi_dcr: SpiDcr,
7782 spi_drdl: SpiDrdl,
7783 spi_dtdl: SpiDtdl,
7784 _reserved8: [u8; 0x3c],
7785 spi_dr: SpiDr,
7786 _reserved9: [u8; 0x58],
7787 spi_rainsr: SpiRainsr,
7788 spi_insr: SpiInsr,
7789 spi_inmar: SpiInmar,
7790 spi_slenr: SpiSlenr,
7791 spi_twlr: SpiTwlr,
7792 spi_tlr: SpiTlr,
7793 _reserved15: [u8; 0x04],
7794 spi_rwlr: SpiRwlr,
7795 spi_rlr: SpiRlr,
7796 _reserved17: [u8; 0x04],
7797 spi_wsr: SpiWsr,
7798 _reserved18: [u8; 0x10],
7799 spi_icr: SpiIcr,
7800 }
7801 impl RegisterBlock {
7802 #[doc = "0x00 - SPI enable register"]
7803 #[inline(always)]
7804 pub const fn spi_er(&self) -> &SpiEr {
7805 &self.spi_er
7806 }
7807 #[doc = "0x04 - SPI control register 0"]
7808 #[inline(always)]
7809 pub const fn spi_ctra(&self) -> &SpiCtra {
7810 &self.spi_ctra
7811 }
7812 #[doc = "0x08 - SPI control register 1 (master only)"]
7813 #[inline(always)]
7814 pub const fn spi_ctrb(&self) -> &SpiCtrb {
7815 &self.spi_ctrb
7816 }
7817 #[doc = "0x0c - Enhanced control register (Dual/Quad/Octal)"]
7818 #[inline(always)]
7819 pub const fn spi_enhctl(&self) -> &SpiEnhctl {
7820 &self.spi_enhctl
7821 }
7822 #[doc = "0x14 - Baud rate select register"]
7823 #[inline(always)]
7824 pub const fn spi_brs(&self) -> &SpiBrs {
7825 &self.spi_brs
7826 }
7827 #[doc = "0x18 - DMA control register"]
7828 #[inline(always)]
7829 pub const fn spi_dcr(&self) -> &SpiDcr {
7830 &self.spi_dcr
7831 }
7832 #[doc = "0x1c - DMA RX data level"]
7833 #[inline(always)]
7834 pub const fn spi_drdl(&self) -> &SpiDrdl {
7835 &self.spi_drdl
7836 }
7837 #[doc = "0x20 - DMA TX data level"]
7838 #[inline(always)]
7839 pub const fn spi_dtdl(&self) -> &SpiDtdl {
7840 &self.spi_dtdl
7841 }
7842 #[doc = "0x60 - Data register (FIFO read/write)"]
7843 #[inline(always)]
7844 pub const fn spi_dr(&self) -> &SpiDr {
7845 &self.spi_dr
7846 }
7847 #[doc = "0xbc - Raw interrupt status register"]
7848 #[inline(always)]
7849 pub const fn spi_rainsr(&self) -> &SpiRainsr {
7850 &self.spi_rainsr
7851 }
7852 #[doc = "0xc0 - Interrupt status register (masked)"]
7853 #[inline(always)]
7854 pub const fn spi_insr(&self) -> &SpiInsr {
7855 &self.spi_insr
7856 }
7857 #[doc = "0xc4 - Interrupt mask register"]
7858 #[inline(always)]
7859 pub const fn spi_inmar(&self) -> &SpiInmar {
7860 &self.spi_inmar
7861 }
7862 #[doc = "0xc8 - Slave enable register (master only)"]
7863 #[inline(always)]
7864 pub const fn spi_slenr(&self) -> &SpiSlenr {
7865 &self.spi_slenr
7866 }
7867 #[doc = "0xcc - TX FIFO threshold level"]
7868 #[inline(always)]
7869 pub const fn spi_twlr(&self) -> &SpiTwlr {
7870 &self.spi_twlr
7871 }
7872 #[doc = "0xd0 - TX FIFO level register"]
7873 #[inline(always)]
7874 pub const fn spi_tlr(&self) -> &SpiTlr {
7875 &self.spi_tlr
7876 }
7877 #[doc = "0xd8 - RX FIFO threshold level"]
7878 #[inline(always)]
7879 pub const fn spi_rwlr(&self) -> &SpiRwlr {
7880 &self.spi_rwlr
7881 }
7882 #[doc = "0xdc - RX FIFO level register"]
7883 #[inline(always)]
7884 pub const fn spi_rlr(&self) -> &SpiRlr {
7885 &self.spi_rlr
7886 }
7887 #[doc = "0xe4 - Status register"]
7888 #[inline(always)]
7889 pub const fn spi_wsr(&self) -> &SpiWsr {
7890 &self.spi_wsr
7891 }
7892 #[doc = "0xf8 - Interrupt clear register"]
7893 #[inline(always)]
7894 pub const fn spi_icr(&self) -> &SpiIcr {
7895 &self.spi_icr
7896 }
7897 }
7898 #[doc = "SPI_ER (rw) register accessor: SPI enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_er::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_er::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_er`] module"]
7899 #[doc(alias = "SPI_ER")]
7900 pub type SpiEr = crate::Reg<spi_er::SpiErSpec>;
7901 #[doc = "SPI enable register"]
7902 pub mod spi_er {
7903 #[doc = "Register `SPI_ER` reader"]
7904 pub type R = crate::R<SpiErSpec>;
7905 #[doc = "Register `SPI_ER` writer"]
7906 pub type W = crate::W<SpiErSpec>;
7907 #[doc = "Field `spi_en` reader - SPI enable: 0=disabled; 1=enabled"]
7908 pub type SpiEnR = crate::BitReader;
7909 #[doc = "Field `spi_en` writer - SPI enable: 0=disabled; 1=enabled"]
7910 pub type SpiEnW<'a, REG> = crate::BitWriter<'a, REG>;
7911 impl R {
7912 #[doc = "Bit 0 - SPI enable: 0=disabled; 1=enabled"]
7913 #[inline(always)]
7914 pub fn spi_en(&self) -> SpiEnR {
7915 SpiEnR::new((self.bits & 1) != 0)
7916 }
7917 }
7918 impl W {
7919 #[doc = "Bit 0 - SPI enable: 0=disabled; 1=enabled"]
7920 #[inline(always)]
7921 pub fn spi_en(&mut self) -> SpiEnW<'_, SpiErSpec> {
7922 SpiEnW::new(self, 0)
7923 }
7924 }
7925 #[doc = "SPI enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_er::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_er::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
7926 pub struct SpiErSpec;
7927 impl crate::RegisterSpec for SpiErSpec {
7928 type Ux = u32;
7929 }
7930 #[doc = "`read()` method returns [`spi_er::R`](R) reader structure"]
7931 impl crate::Readable for SpiErSpec {}
7932 #[doc = "`write(|w| ..)` method takes [`spi_er::W`](W) writer structure"]
7933 impl crate::Writable for SpiErSpec {
7934 type Safety = crate::Unsafe;
7935 }
7936 #[doc = "`reset()` method sets SPI_ER to value 0"]
7937 impl crate::Resettable for SpiErSpec {}
7938 }
7939 #[doc = "SPI_CTRA (rw) register accessor: SPI control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctra`] module"]
7940 #[doc(alias = "SPI_CTRA")]
7941 pub type SpiCtra = crate::Reg<spi_ctra::SpiCtraSpec>;
7942 #[doc = "SPI control register 0"]
7943 pub mod spi_ctra {
7944 #[doc = "Register `SPI_CTRA` reader"]
7945 pub type R = crate::R<SpiCtraSpec>;
7946 #[doc = "Register `SPI_CTRA` writer"]
7947 pub type W = crate::W<SpiCtraSpec>;
7948 #[doc = "Field `soe` reader - Shift register loop test: 0=normal; 1=loopback"]
7949 pub type SoeR = crate::BitReader;
7950 #[doc = "Field `soe` writer - Shift register loop test: 0=normal; 1=loopback"]
7951 pub type SoeW<'a, REG> = crate::BitWriter<'a, REG>;
7952 #[doc = "Clock phase: 0=first edge sample; 1=second edge sample\n\nValue on reset: 0"]
7953 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
7954 pub enum Scph {
7955 #[doc = "0: Sample on first clock edge"]
7956 FirstEdge = 0,
7957 #[doc = "1: Sample on second clock edge"]
7958 SecondEdge = 1,
7959 }
7960 impl From<Scph> for bool {
7961 #[inline(always)]
7962 fn from(variant: Scph) -> Self {
7963 variant as u8 != 0
7964 }
7965 }
7966 #[doc = "Field `scph` reader - Clock phase: 0=first edge sample; 1=second edge sample"]
7967 pub type ScphR = crate::BitReader<Scph>;
7968 impl ScphR {
7969 #[doc = "Get enumerated values variant"]
7970 #[inline(always)]
7971 pub const fn variant(&self) -> Scph {
7972 match self.bits {
7973 false => Scph::FirstEdge,
7974 true => Scph::SecondEdge,
7975 }
7976 }
7977 #[doc = "Sample on first clock edge"]
7978 #[inline(always)]
7979 pub fn is_first_edge(&self) -> bool {
7980 *self == Scph::FirstEdge
7981 }
7982 #[doc = "Sample on second clock edge"]
7983 #[inline(always)]
7984 pub fn is_second_edge(&self) -> bool {
7985 *self == Scph::SecondEdge
7986 }
7987 }
7988 #[doc = "Field `scph` writer - Clock phase: 0=first edge sample; 1=second edge sample"]
7989 pub type ScphW<'a, REG> = crate::BitWriter<'a, REG, Scph>;
7990 impl<'a, REG> ScphW<'a, REG>
7991 where
7992 REG: crate::Writable + crate::RegisterSpec,
7993 {
7994 #[doc = "Sample on first clock edge"]
7995 #[inline(always)]
7996 pub fn first_edge(self) -> &'a mut crate::W<REG> {
7997 self.variant(Scph::FirstEdge)
7998 }
7999 #[doc = "Sample on second clock edge"]
8000 #[inline(always)]
8001 pub fn second_edge(self) -> &'a mut crate::W<REG> {
8002 self.variant(Scph::SecondEdge)
8003 }
8004 }
8005 #[doc = "Clock polarity: 0=low idle; 1=high idle\n\nValue on reset: 0"]
8006 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
8007 pub enum Scpol {
8008 #[doc = "0: SCK idle low"]
8009 LowIdle = 0,
8010 #[doc = "1: SCK idle high"]
8011 HighIdle = 1,
8012 }
8013 impl From<Scpol> for bool {
8014 #[inline(always)]
8015 fn from(variant: Scpol) -> Self {
8016 variant as u8 != 0
8017 }
8018 }
8019 #[doc = "Field `scpol` reader - Clock polarity: 0=low idle; 1=high idle"]
8020 pub type ScpolR = crate::BitReader<Scpol>;
8021 impl ScpolR {
8022 #[doc = "Get enumerated values variant"]
8023 #[inline(always)]
8024 pub const fn variant(&self) -> Scpol {
8025 match self.bits {
8026 false => Scpol::LowIdle,
8027 true => Scpol::HighIdle,
8028 }
8029 }
8030 #[doc = "SCK idle low"]
8031 #[inline(always)]
8032 pub fn is_low_idle(&self) -> bool {
8033 *self == Scpol::LowIdle
8034 }
8035 #[doc = "SCK idle high"]
8036 #[inline(always)]
8037 pub fn is_high_idle(&self) -> bool {
8038 *self == Scpol::HighIdle
8039 }
8040 }
8041 #[doc = "Field `scpol` writer - Clock polarity: 0=low idle; 1=high idle"]
8042 pub type ScpolW<'a, REG> = crate::BitWriter<'a, REG, Scpol>;
8043 impl<'a, REG> ScpolW<'a, REG>
8044 where
8045 REG: crate::Writable + crate::RegisterSpec,
8046 {
8047 #[doc = "SCK idle low"]
8048 #[inline(always)]
8049 pub fn low_idle(self) -> &'a mut crate::W<REG> {
8050 self.variant(Scpol::LowIdle)
8051 }
8052 #[doc = "SCK idle high"]
8053 #[inline(always)]
8054 pub fn high_idle(self) -> &'a mut crate::W<REG> {
8055 self.variant(Scpol::HighIdle)
8056 }
8057 }
8058 #[doc = "Field `dfs32` reader - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
8059 pub type Dfs32R = crate::FieldReader;
8060 #[doc = "Field `dfs32` writer - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
8061 pub type Dfs32W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
8062 #[doc = "Transfer mode: 00=TX/RX; 01=TX only; 10=RX only\n\nValue on reset: 0"]
8063 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
8064 #[repr(u8)]
8065 pub enum Trsm {
8066 #[doc = "0: Transmit and Receive"]
8067 TxRx = 0,
8068 #[doc = "1: Transmit Only"]
8069 TxOnly = 1,
8070 #[doc = "2: Receive Only"]
8071 RxOnly = 2,
8072 }
8073 impl From<Trsm> for u8 {
8074 #[inline(always)]
8075 fn from(variant: Trsm) -> Self {
8076 variant as _
8077 }
8078 }
8079 impl crate::FieldSpec for Trsm {
8080 type Ux = u8;
8081 }
8082 impl crate::IsEnum for Trsm {}
8083 #[doc = "Field `trsm` reader - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
8084 pub type TrsmR = crate::FieldReader<Trsm>;
8085 impl TrsmR {
8086 #[doc = "Get enumerated values variant"]
8087 #[inline(always)]
8088 pub const fn variant(&self) -> Option<Trsm> {
8089 match self.bits {
8090 0 => Some(Trsm::TxRx),
8091 1 => Some(Trsm::TxOnly),
8092 2 => Some(Trsm::RxOnly),
8093 _ => None,
8094 }
8095 }
8096 #[doc = "Transmit and Receive"]
8097 #[inline(always)]
8098 pub fn is_tx_rx(&self) -> bool {
8099 *self == Trsm::TxRx
8100 }
8101 #[doc = "Transmit Only"]
8102 #[inline(always)]
8103 pub fn is_tx_only(&self) -> bool {
8104 *self == Trsm::TxOnly
8105 }
8106 #[doc = "Receive Only"]
8107 #[inline(always)]
8108 pub fn is_rx_only(&self) -> bool {
8109 *self == Trsm::RxOnly
8110 }
8111 }
8112 #[doc = "Field `trsm` writer - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
8113 pub type TrsmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trsm>;
8114 impl<'a, REG> TrsmW<'a, REG>
8115 where
8116 REG: crate::Writable + crate::RegisterSpec,
8117 REG::Ux: From<u8>,
8118 {
8119 #[doc = "Transmit and Receive"]
8120 #[inline(always)]
8121 pub fn tx_rx(self) -> &'a mut crate::W<REG> {
8122 self.variant(Trsm::TxRx)
8123 }
8124 #[doc = "Transmit Only"]
8125 #[inline(always)]
8126 pub fn tx_only(self) -> &'a mut crate::W<REG> {
8127 self.variant(Trsm::TxOnly)
8128 }
8129 #[doc = "Receive Only"]
8130 #[inline(always)]
8131 pub fn rx_only(self) -> &'a mut crate::W<REG> {
8132 self.variant(Trsm::RxOnly)
8133 }
8134 }
8135 impl R {
8136 #[doc = "Bit 0 - Shift register loop test: 0=normal; 1=loopback"]
8137 #[inline(always)]
8138 pub fn soe(&self) -> SoeR {
8139 SoeR::new((self.bits & 1) != 0)
8140 }
8141 #[doc = "Bit 3 - Clock phase: 0=first edge sample; 1=second edge sample"]
8142 #[inline(always)]
8143 pub fn scph(&self) -> ScphR {
8144 ScphR::new(((self.bits >> 3) & 1) != 0)
8145 }
8146 #[doc = "Bit 4 - Clock polarity: 0=low idle; 1=high idle"]
8147 #[inline(always)]
8148 pub fn scpol(&self) -> ScpolR {
8149 ScpolR::new(((self.bits >> 4) & 1) != 0)
8150 }
8151 #[doc = "Bits 13:17 - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
8152 #[inline(always)]
8153 pub fn dfs32(&self) -> Dfs32R {
8154 Dfs32R::new(((self.bits >> 13) & 0x1f) as u8)
8155 }
8156 #[doc = "Bits 18:19 - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
8157 #[inline(always)]
8158 pub fn trsm(&self) -> TrsmR {
8159 TrsmR::new(((self.bits >> 18) & 3) as u8)
8160 }
8161 }
8162 impl W {
8163 #[doc = "Bit 0 - Shift register loop test: 0=normal; 1=loopback"]
8164 #[inline(always)]
8165 pub fn soe(&mut self) -> SoeW<'_, SpiCtraSpec> {
8166 SoeW::new(self, 0)
8167 }
8168 #[doc = "Bit 3 - Clock phase: 0=first edge sample; 1=second edge sample"]
8169 #[inline(always)]
8170 pub fn scph(&mut self) -> ScphW<'_, SpiCtraSpec> {
8171 ScphW::new(self, 3)
8172 }
8173 #[doc = "Bit 4 - Clock polarity: 0=low idle; 1=high idle"]
8174 #[inline(always)]
8175 pub fn scpol(&mut self) -> ScpolW<'_, SpiCtraSpec> {
8176 ScpolW::new(self, 4)
8177 }
8178 #[doc = "Bits 13:17 - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
8179 #[inline(always)]
8180 pub fn dfs32(&mut self) -> Dfs32W<'_, SpiCtraSpec> {
8181 Dfs32W::new(self, 13)
8182 }
8183 #[doc = "Bits 18:19 - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
8184 #[inline(always)]
8185 pub fn trsm(&mut self) -> TrsmW<'_, SpiCtraSpec> {
8186 TrsmW::new(self, 18)
8187 }
8188 }
8189 #[doc = "SPI control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8190 pub struct SpiCtraSpec;
8191 impl crate::RegisterSpec for SpiCtraSpec {
8192 type Ux = u32;
8193 }
8194 #[doc = "`read()` method returns [`spi_ctra::R`](R) reader structure"]
8195 impl crate::Readable for SpiCtraSpec {}
8196 #[doc = "`write(|w| ..)` method takes [`spi_ctra::W`](W) writer structure"]
8197 impl crate::Writable for SpiCtraSpec {
8198 type Safety = crate::Unsafe;
8199 }
8200 #[doc = "`reset()` method sets SPI_CTRA to value 0"]
8201 impl crate::Resettable for SpiCtraSpec {}
8202 }
8203 #[doc = "SPI_CTRB (rw) register accessor: SPI control register 1 (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrb`] module"]
8204 #[doc(alias = "SPI_CTRB")]
8205 pub type SpiCtrb = crate::Reg<spi_ctrb::SpiCtrbSpec>;
8206 #[doc = "SPI control register 1 (master only)"]
8207 pub mod spi_ctrb {
8208 #[doc = "Register `SPI_CTRB` reader"]
8209 pub type R = crate::R<SpiCtrbSpec>;
8210 #[doc = "Register `SPI_CTRB` writer"]
8211 pub type W = crate::W<SpiCtrbSpec>;
8212 #[doc = "Field `ndf` reader - Number of data frames (master TX only mode)"]
8213 pub type NdfR = crate::FieldReader<u16>;
8214 #[doc = "Field `ndf` writer - Number of data frames (master TX only mode)"]
8215 pub type NdfW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
8216 #[doc = "Field `ssi_clk_stretch_en` reader - Clock stretch enable"]
8217 pub type SsiClkStretchEnR = crate::BitReader;
8218 #[doc = "Field `ssi_clk_stretch_en` writer - Clock stretch enable"]
8219 pub type SsiClkStretchEnW<'a, REG> = crate::BitWriter<'a, REG>;
8220 impl R {
8221 #[doc = "Bits 0:15 - Number of data frames (master TX only mode)"]
8222 #[inline(always)]
8223 pub fn ndf(&self) -> NdfR {
8224 NdfR::new((self.bits & 0xffff) as u16)
8225 }
8226 #[doc = "Bit 27 - Clock stretch enable"]
8227 #[inline(always)]
8228 pub fn ssi_clk_stretch_en(&self) -> SsiClkStretchEnR {
8229 SsiClkStretchEnR::new(((self.bits >> 27) & 1) != 0)
8230 }
8231 }
8232 impl W {
8233 #[doc = "Bits 0:15 - Number of data frames (master TX only mode)"]
8234 #[inline(always)]
8235 pub fn ndf(&mut self) -> NdfW<'_, SpiCtrbSpec> {
8236 NdfW::new(self, 0)
8237 }
8238 #[doc = "Bit 27 - Clock stretch enable"]
8239 #[inline(always)]
8240 pub fn ssi_clk_stretch_en(&mut self) -> SsiClkStretchEnW<'_, SpiCtrbSpec> {
8241 SsiClkStretchEnW::new(self, 27)
8242 }
8243 }
8244 #[doc = "SPI control register 1 (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8245 pub struct SpiCtrbSpec;
8246 impl crate::RegisterSpec for SpiCtrbSpec {
8247 type Ux = u32;
8248 }
8249 #[doc = "`read()` method returns [`spi_ctrb::R`](R) reader structure"]
8250 impl crate::Readable for SpiCtrbSpec {}
8251 #[doc = "`write(|w| ..)` method takes [`spi_ctrb::W`](W) writer structure"]
8252 impl crate::Writable for SpiCtrbSpec {
8253 type Safety = crate::Unsafe;
8254 }
8255 #[doc = "`reset()` method sets SPI_CTRB to value 0"]
8256 impl crate::Resettable for SpiCtrbSpec {}
8257 }
8258 #[doc = "SPI_ENHCTL (rw) register accessor: Enhanced control register (Dual/Quad/Octal)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_enhctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_enhctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_enhctl`] module"]
8259 #[doc(alias = "SPI_ENHCTL")]
8260 pub type SpiEnhctl = crate::Reg<spi_enhctl::SpiEnhctlSpec>;
8261 #[doc = "Enhanced control register (Dual/Quad/Octal)"]
8262 pub mod spi_enhctl {
8263 #[doc = "Register `SPI_ENHCTL` reader"]
8264 pub type R = crate::R<SpiEnhctlSpec>;
8265 #[doc = "Register `SPI_ENHCTL` writer"]
8266 pub type W = crate::W<SpiEnhctlSpec>;
8267 #[doc = "Field `spi_dual_en` reader - Dual SPI mode enable"]
8268 pub type SpiDualEnR = crate::BitReader;
8269 #[doc = "Field `spi_dual_en` writer - Dual SPI mode enable"]
8270 pub type SpiDualEnW<'a, REG> = crate::BitWriter<'a, REG>;
8271 #[doc = "Field `spi_quad_en` reader - Quad SPI mode enable"]
8272 pub type SpiQuadEnR = crate::BitReader;
8273 #[doc = "Field `spi_quad_en` writer - Quad SPI mode enable"]
8274 pub type SpiQuadEnW<'a, REG> = crate::BitWriter<'a, REG>;
8275 #[doc = "Field `spi_oct_en` reader - Octal SPI mode enable"]
8276 pub type SpiOctEnR = crate::BitReader;
8277 #[doc = "Field `spi_oct_en` writer - Octal SPI mode enable"]
8278 pub type SpiOctEnW<'a, REG> = crate::BitWriter<'a, REG>;
8279 impl R {
8280 #[doc = "Bit 0 - Dual SPI mode enable"]
8281 #[inline(always)]
8282 pub fn spi_dual_en(&self) -> SpiDualEnR {
8283 SpiDualEnR::new((self.bits & 1) != 0)
8284 }
8285 #[doc = "Bit 1 - Quad SPI mode enable"]
8286 #[inline(always)]
8287 pub fn spi_quad_en(&self) -> SpiQuadEnR {
8288 SpiQuadEnR::new(((self.bits >> 1) & 1) != 0)
8289 }
8290 #[doc = "Bit 2 - Octal SPI mode enable"]
8291 #[inline(always)]
8292 pub fn spi_oct_en(&self) -> SpiOctEnR {
8293 SpiOctEnR::new(((self.bits >> 2) & 1) != 0)
8294 }
8295 }
8296 impl W {
8297 #[doc = "Bit 0 - Dual SPI mode enable"]
8298 #[inline(always)]
8299 pub fn spi_dual_en(&mut self) -> SpiDualEnW<'_, SpiEnhctlSpec> {
8300 SpiDualEnW::new(self, 0)
8301 }
8302 #[doc = "Bit 1 - Quad SPI mode enable"]
8303 #[inline(always)]
8304 pub fn spi_quad_en(&mut self) -> SpiQuadEnW<'_, SpiEnhctlSpec> {
8305 SpiQuadEnW::new(self, 1)
8306 }
8307 #[doc = "Bit 2 - Octal SPI mode enable"]
8308 #[inline(always)]
8309 pub fn spi_oct_en(&mut self) -> SpiOctEnW<'_, SpiEnhctlSpec> {
8310 SpiOctEnW::new(self, 2)
8311 }
8312 }
8313 #[doc = "Enhanced control register (Dual/Quad/Octal)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_enhctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_enhctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8314 pub struct SpiEnhctlSpec;
8315 impl crate::RegisterSpec for SpiEnhctlSpec {
8316 type Ux = u32;
8317 }
8318 #[doc = "`read()` method returns [`spi_enhctl::R`](R) reader structure"]
8319 impl crate::Readable for SpiEnhctlSpec {}
8320 #[doc = "`write(|w| ..)` method takes [`spi_enhctl::W`](W) writer structure"]
8321 impl crate::Writable for SpiEnhctlSpec {
8322 type Safety = crate::Unsafe;
8323 }
8324 #[doc = "`reset()` method sets SPI_ENHCTL to value 0"]
8325 impl crate::Resettable for SpiEnhctlSpec {}
8326 }
8327 #[doc = "SPI_BRS (rw) register accessor: Baud rate select register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_brs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_brs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_brs`] module"]
8328 #[doc(alias = "SPI_BRS")]
8329 pub type SpiBrs = crate::Reg<spi_brs::SpiBrsSpec>;
8330 #[doc = "Baud rate select register"]
8331 pub mod spi_brs {
8332 #[doc = "Register `SPI_BRS` reader"]
8333 pub type R = crate::R<SpiBrsSpec>;
8334 #[doc = "Register `SPI_BRS` writer"]
8335 pub type W = crate::W<SpiBrsSpec>;
8336 #[doc = "Field `clk_div` reader - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
8337 pub type ClkDivR = crate::FieldReader<u16>;
8338 #[doc = "Field `clk_div` writer - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
8339 pub type ClkDivW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
8340 impl R {
8341 #[doc = "Bits 0:15 - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
8342 #[inline(always)]
8343 pub fn clk_div(&self) -> ClkDivR {
8344 ClkDivR::new((self.bits & 0xffff) as u16)
8345 }
8346 }
8347 impl W {
8348 #[doc = "Bits 0:15 - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
8349 #[inline(always)]
8350 pub fn clk_div(&mut self) -> ClkDivW<'_, SpiBrsSpec> {
8351 ClkDivW::new(self, 0)
8352 }
8353 }
8354 #[doc = "Baud rate select register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_brs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_brs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8355 pub struct SpiBrsSpec;
8356 impl crate::RegisterSpec for SpiBrsSpec {
8357 type Ux = u32;
8358 }
8359 #[doc = "`read()` method returns [`spi_brs::R`](R) reader structure"]
8360 impl crate::Readable for SpiBrsSpec {}
8361 #[doc = "`write(|w| ..)` method takes [`spi_brs::W`](W) writer structure"]
8362 impl crate::Writable for SpiBrsSpec {
8363 type Safety = crate::Unsafe;
8364 }
8365 #[doc = "`reset()` method sets SPI_BRS to value 0"]
8366 impl crate::Resettable for SpiBrsSpec {}
8367 }
8368 #[doc = "SPI_DCR (rw) register accessor: DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dcr`] module"]
8369 #[doc(alias = "SPI_DCR")]
8370 pub type SpiDcr = crate::Reg<spi_dcr::SpiDcrSpec>;
8371 #[doc = "DMA control register"]
8372 pub mod spi_dcr {
8373 #[doc = "Register `SPI_DCR` reader"]
8374 pub type R = crate::R<SpiDcrSpec>;
8375 #[doc = "Register `SPI_DCR` writer"]
8376 pub type W = crate::W<SpiDcrSpec>;
8377 #[doc = "Field `tdmae` reader - TX DMA enable"]
8378 pub type TdmaeR = crate::BitReader;
8379 #[doc = "Field `tdmae` writer - TX DMA enable"]
8380 pub type TdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
8381 #[doc = "Field `rdmae` reader - RX DMA enable"]
8382 pub type RdmaeR = crate::BitReader;
8383 #[doc = "Field `rdmae` writer - RX DMA enable"]
8384 pub type RdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
8385 impl R {
8386 #[doc = "Bit 0 - TX DMA enable"]
8387 #[inline(always)]
8388 pub fn tdmae(&self) -> TdmaeR {
8389 TdmaeR::new((self.bits & 1) != 0)
8390 }
8391 #[doc = "Bit 1 - RX DMA enable"]
8392 #[inline(always)]
8393 pub fn rdmae(&self) -> RdmaeR {
8394 RdmaeR::new(((self.bits >> 1) & 1) != 0)
8395 }
8396 }
8397 impl W {
8398 #[doc = "Bit 0 - TX DMA enable"]
8399 #[inline(always)]
8400 pub fn tdmae(&mut self) -> TdmaeW<'_, SpiDcrSpec> {
8401 TdmaeW::new(self, 0)
8402 }
8403 #[doc = "Bit 1 - RX DMA enable"]
8404 #[inline(always)]
8405 pub fn rdmae(&mut self) -> RdmaeW<'_, SpiDcrSpec> {
8406 RdmaeW::new(self, 1)
8407 }
8408 }
8409 #[doc = "DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8410 pub struct SpiDcrSpec;
8411 impl crate::RegisterSpec for SpiDcrSpec {
8412 type Ux = u32;
8413 }
8414 #[doc = "`read()` method returns [`spi_dcr::R`](R) reader structure"]
8415 impl crate::Readable for SpiDcrSpec {}
8416 #[doc = "`write(|w| ..)` method takes [`spi_dcr::W`](W) writer structure"]
8417 impl crate::Writable for SpiDcrSpec {
8418 type Safety = crate::Unsafe;
8419 }
8420 #[doc = "`reset()` method sets SPI_DCR to value 0"]
8421 impl crate::Resettable for SpiDcrSpec {}
8422 }
8423 #[doc = "SPI_DRDL (rw) register accessor: DMA RX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_drdl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_drdl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_drdl`] module"]
8424 #[doc(alias = "SPI_DRDL")]
8425 pub type SpiDrdl = crate::Reg<spi_drdl::SpiDrdlSpec>;
8426 #[doc = "DMA RX data level"]
8427 pub mod spi_drdl {
8428 #[doc = "Register `SPI_DRDL` reader"]
8429 pub type R = crate::R<SpiDrdlSpec>;
8430 #[doc = "Register `SPI_DRDL` writer"]
8431 pub type W = crate::W<SpiDrdlSpec>;
8432 #[doc = "Field `dma_rx_data_level` reader - DMA RX FIFO threshold"]
8433 pub type DmaRxDataLevelR = crate::FieldReader;
8434 #[doc = "Field `dma_rx_data_level` writer - DMA RX FIFO threshold"]
8435 pub type DmaRxDataLevelW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
8436 impl R {
8437 #[doc = "Bits 0:7 - DMA RX FIFO threshold"]
8438 #[inline(always)]
8439 pub fn dma_rx_data_level(&self) -> DmaRxDataLevelR {
8440 DmaRxDataLevelR::new((self.bits & 0xff) as u8)
8441 }
8442 }
8443 impl W {
8444 #[doc = "Bits 0:7 - DMA RX FIFO threshold"]
8445 #[inline(always)]
8446 pub fn dma_rx_data_level(&mut self) -> DmaRxDataLevelW<'_, SpiDrdlSpec> {
8447 DmaRxDataLevelW::new(self, 0)
8448 }
8449 }
8450 #[doc = "DMA RX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_drdl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_drdl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8451 pub struct SpiDrdlSpec;
8452 impl crate::RegisterSpec for SpiDrdlSpec {
8453 type Ux = u32;
8454 }
8455 #[doc = "`read()` method returns [`spi_drdl::R`](R) reader structure"]
8456 impl crate::Readable for SpiDrdlSpec {}
8457 #[doc = "`write(|w| ..)` method takes [`spi_drdl::W`](W) writer structure"]
8458 impl crate::Writable for SpiDrdlSpec {
8459 type Safety = crate::Unsafe;
8460 }
8461 #[doc = "`reset()` method sets SPI_DRDL to value 0"]
8462 impl crate::Resettable for SpiDrdlSpec {}
8463 }
8464 #[doc = "SPI_DTDL (rw) register accessor: DMA TX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dtdl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dtdl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dtdl`] module"]
8465 #[doc(alias = "SPI_DTDL")]
8466 pub type SpiDtdl = crate::Reg<spi_dtdl::SpiDtdlSpec>;
8467 #[doc = "DMA TX data level"]
8468 pub mod spi_dtdl {
8469 #[doc = "Register `SPI_DTDL` reader"]
8470 pub type R = crate::R<SpiDtdlSpec>;
8471 #[doc = "Register `SPI_DTDL` writer"]
8472 pub type W = crate::W<SpiDtdlSpec>;
8473 #[doc = "Field `dma_tx_data_level` reader - DMA TX FIFO threshold"]
8474 pub type DmaTxDataLevelR = crate::FieldReader;
8475 #[doc = "Field `dma_tx_data_level` writer - DMA TX FIFO threshold"]
8476 pub type DmaTxDataLevelW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
8477 impl R {
8478 #[doc = "Bits 0:7 - DMA TX FIFO threshold"]
8479 #[inline(always)]
8480 pub fn dma_tx_data_level(&self) -> DmaTxDataLevelR {
8481 DmaTxDataLevelR::new((self.bits & 0xff) as u8)
8482 }
8483 }
8484 impl W {
8485 #[doc = "Bits 0:7 - DMA TX FIFO threshold"]
8486 #[inline(always)]
8487 pub fn dma_tx_data_level(&mut self) -> DmaTxDataLevelW<'_, SpiDtdlSpec> {
8488 DmaTxDataLevelW::new(self, 0)
8489 }
8490 }
8491 #[doc = "DMA TX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dtdl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dtdl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8492 pub struct SpiDtdlSpec;
8493 impl crate::RegisterSpec for SpiDtdlSpec {
8494 type Ux = u32;
8495 }
8496 #[doc = "`read()` method returns [`spi_dtdl::R`](R) reader structure"]
8497 impl crate::Readable for SpiDtdlSpec {}
8498 #[doc = "`write(|w| ..)` method takes [`spi_dtdl::W`](W) writer structure"]
8499 impl crate::Writable for SpiDtdlSpec {
8500 type Safety = crate::Unsafe;
8501 }
8502 #[doc = "`reset()` method sets SPI_DTDL to value 0"]
8503 impl crate::Resettable for SpiDtdlSpec {}
8504 }
8505 #[doc = "SPI_DR (rw) register accessor: Data register (FIFO read/write)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dr`] module"]
8506 #[doc(alias = "SPI_DR")]
8507 pub type SpiDr = crate::Reg<spi_dr::SpiDrSpec>;
8508 #[doc = "Data register (FIFO read/write)"]
8509 pub mod spi_dr {
8510 #[doc = "Register `SPI_DR` reader"]
8511 pub type R = crate::R<SpiDrSpec>;
8512 #[doc = "Register `SPI_DR` writer"]
8513 pub type W = crate::W<SpiDrSpec>;
8514 #[doc = "Field `dr` reader - Write: push to TX FIFO; Read: pop from RX FIFO"]
8515 pub type DrR = crate::FieldReader<u32>;
8516 #[doc = "Field `dr` writer - Write: push to TX FIFO; Read: pop from RX FIFO"]
8517 pub type DrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
8518 impl R {
8519 #[doc = "Bits 0:31 - Write: push to TX FIFO; Read: pop from RX FIFO"]
8520 #[inline(always)]
8521 pub fn dr(&self) -> DrR {
8522 DrR::new(self.bits)
8523 }
8524 }
8525 impl W {
8526 #[doc = "Bits 0:31 - Write: push to TX FIFO; Read: pop from RX FIFO"]
8527 #[inline(always)]
8528 pub fn dr(&mut self) -> DrW<'_, SpiDrSpec> {
8529 DrW::new(self, 0)
8530 }
8531 }
8532 #[doc = "Data register (FIFO read/write)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8533 pub struct SpiDrSpec;
8534 impl crate::RegisterSpec for SpiDrSpec {
8535 type Ux = u32;
8536 }
8537 #[doc = "`read()` method returns [`spi_dr::R`](R) reader structure"]
8538 impl crate::Readable for SpiDrSpec {}
8539 #[doc = "`write(|w| ..)` method takes [`spi_dr::W`](W) writer structure"]
8540 impl crate::Writable for SpiDrSpec {
8541 type Safety = crate::Unsafe;
8542 }
8543 #[doc = "`reset()` method sets SPI_DR to value 0"]
8544 impl crate::Resettable for SpiDrSpec {}
8545 }
8546 #[doc = "SPI_RAINSR (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rainsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rainsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rainsr`] module"]
8547 #[doc(alias = "SPI_RAINSR")]
8548 pub type SpiRainsr = crate::Reg<spi_rainsr::SpiRainsrSpec>;
8549 #[doc = "Raw interrupt status register"]
8550 pub mod spi_rainsr {
8551 #[doc = "Register `SPI_RAINSR` reader"]
8552 pub type R = crate::R<SpiRainsrSpec>;
8553 #[doc = "Register `SPI_RAINSR` writer"]
8554 pub type W = crate::W<SpiRainsrSpec>;
8555 #[doc = "Field `txe_irq` reader - TX FIFO empty raw status"]
8556 pub type TxeIrqR = crate::BitReader;
8557 #[doc = "Field `txo_irq` reader - TX FIFO overflow raw status"]
8558 pub type TxoIrqR = crate::BitReader;
8559 #[doc = "Field `rxu_irq` reader - RX FIFO underflow raw status"]
8560 pub type RxuIrqR = crate::BitReader;
8561 #[doc = "Field `rxo_irq` reader - RX FIFO overflow raw status"]
8562 pub type RxoIrqR = crate::BitReader;
8563 #[doc = "Field `rxf_irq` reader - RX FIFO full raw status"]
8564 pub type RxfIrqR = crate::BitReader;
8565 #[doc = "Field `mst_irq` reader - Multi-master contention raw status"]
8566 pub type MstIrqR = crate::BitReader;
8567 impl R {
8568 #[doc = "Bit 0 - TX FIFO empty raw status"]
8569 #[inline(always)]
8570 pub fn txe_irq(&self) -> TxeIrqR {
8571 TxeIrqR::new((self.bits & 1) != 0)
8572 }
8573 #[doc = "Bit 1 - TX FIFO overflow raw status"]
8574 #[inline(always)]
8575 pub fn txo_irq(&self) -> TxoIrqR {
8576 TxoIrqR::new(((self.bits >> 1) & 1) != 0)
8577 }
8578 #[doc = "Bit 2 - RX FIFO underflow raw status"]
8579 #[inline(always)]
8580 pub fn rxu_irq(&self) -> RxuIrqR {
8581 RxuIrqR::new(((self.bits >> 2) & 1) != 0)
8582 }
8583 #[doc = "Bit 3 - RX FIFO overflow raw status"]
8584 #[inline(always)]
8585 pub fn rxo_irq(&self) -> RxoIrqR {
8586 RxoIrqR::new(((self.bits >> 3) & 1) != 0)
8587 }
8588 #[doc = "Bit 4 - RX FIFO full raw status"]
8589 #[inline(always)]
8590 pub fn rxf_irq(&self) -> RxfIrqR {
8591 RxfIrqR::new(((self.bits >> 4) & 1) != 0)
8592 }
8593 #[doc = "Bit 5 - Multi-master contention raw status"]
8594 #[inline(always)]
8595 pub fn mst_irq(&self) -> MstIrqR {
8596 MstIrqR::new(((self.bits >> 5) & 1) != 0)
8597 }
8598 }
8599 impl W {}
8600 #[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rainsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rainsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8601 pub struct SpiRainsrSpec;
8602 impl crate::RegisterSpec for SpiRainsrSpec {
8603 type Ux = u32;
8604 }
8605 #[doc = "`read()` method returns [`spi_rainsr::R`](R) reader structure"]
8606 impl crate::Readable for SpiRainsrSpec {}
8607 #[doc = "`write(|w| ..)` method takes [`spi_rainsr::W`](W) writer structure"]
8608 impl crate::Writable for SpiRainsrSpec {
8609 type Safety = crate::Unsafe;
8610 }
8611 #[doc = "`reset()` method sets SPI_RAINSR to value 0"]
8612 impl crate::Resettable for SpiRainsrSpec {}
8613 }
8614 #[doc = "SPI_INSR (rw) register accessor: Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_insr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_insr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_insr`] module"]
8615 #[doc(alias = "SPI_INSR")]
8616 pub type SpiInsr = crate::Reg<spi_insr::SpiInsrSpec>;
8617 #[doc = "Interrupt status register (masked)"]
8618 pub mod spi_insr {
8619 #[doc = "Register `SPI_INSR` reader"]
8620 pub type R = crate::R<SpiInsrSpec>;
8621 #[doc = "Register `SPI_INSR` writer"]
8622 pub type W = crate::W<SpiInsrSpec>;
8623 #[doc = "Field `txe_is` reader - TX empty interrupt status"]
8624 pub type TxeIsR = crate::BitReader;
8625 #[doc = "Field `txo_is` reader - TX overflow interrupt status"]
8626 pub type TxoIsR = crate::BitReader;
8627 #[doc = "Field `rxu_is` reader - RX underflow interrupt status"]
8628 pub type RxuIsR = crate::BitReader;
8629 #[doc = "Field `rxo_is` reader - RX overflow interrupt status"]
8630 pub type RxoIsR = crate::BitReader;
8631 #[doc = "Field `rxf_is` reader - RX full interrupt status"]
8632 pub type RxfIsR = crate::BitReader;
8633 #[doc = "Field `mst_is` reader - Multi-master interrupt status"]
8634 pub type MstIsR = crate::BitReader;
8635 impl R {
8636 #[doc = "Bit 0 - TX empty interrupt status"]
8637 #[inline(always)]
8638 pub fn txe_is(&self) -> TxeIsR {
8639 TxeIsR::new((self.bits & 1) != 0)
8640 }
8641 #[doc = "Bit 1 - TX overflow interrupt status"]
8642 #[inline(always)]
8643 pub fn txo_is(&self) -> TxoIsR {
8644 TxoIsR::new(((self.bits >> 1) & 1) != 0)
8645 }
8646 #[doc = "Bit 2 - RX underflow interrupt status"]
8647 #[inline(always)]
8648 pub fn rxu_is(&self) -> RxuIsR {
8649 RxuIsR::new(((self.bits >> 2) & 1) != 0)
8650 }
8651 #[doc = "Bit 3 - RX overflow interrupt status"]
8652 #[inline(always)]
8653 pub fn rxo_is(&self) -> RxoIsR {
8654 RxoIsR::new(((self.bits >> 3) & 1) != 0)
8655 }
8656 #[doc = "Bit 4 - RX full interrupt status"]
8657 #[inline(always)]
8658 pub fn rxf_is(&self) -> RxfIsR {
8659 RxfIsR::new(((self.bits >> 4) & 1) != 0)
8660 }
8661 #[doc = "Bit 5 - Multi-master interrupt status"]
8662 #[inline(always)]
8663 pub fn mst_is(&self) -> MstIsR {
8664 MstIsR::new(((self.bits >> 5) & 1) != 0)
8665 }
8666 }
8667 impl W {}
8668 #[doc = "Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_insr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_insr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8669 pub struct SpiInsrSpec;
8670 impl crate::RegisterSpec for SpiInsrSpec {
8671 type Ux = u32;
8672 }
8673 #[doc = "`read()` method returns [`spi_insr::R`](R) reader structure"]
8674 impl crate::Readable for SpiInsrSpec {}
8675 #[doc = "`write(|w| ..)` method takes [`spi_insr::W`](W) writer structure"]
8676 impl crate::Writable for SpiInsrSpec {
8677 type Safety = crate::Unsafe;
8678 }
8679 #[doc = "`reset()` method sets SPI_INSR to value 0"]
8680 impl crate::Resettable for SpiInsrSpec {}
8681 }
8682 #[doc = "SPI_INMAR (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_inmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_inmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_inmar`] module"]
8683 #[doc(alias = "SPI_INMAR")]
8684 pub type SpiInmar = crate::Reg<spi_inmar::SpiInmarSpec>;
8685 #[doc = "Interrupt mask register"]
8686 pub mod spi_inmar {
8687 #[doc = "Register `SPI_INMAR` reader"]
8688 pub type R = crate::R<SpiInmarSpec>;
8689 #[doc = "Register `SPI_INMAR` writer"]
8690 pub type W = crate::W<SpiInmarSpec>;
8691 #[doc = "Field `txe_im` reader - TX empty interrupt mask"]
8692 pub type TxeImR = crate::BitReader;
8693 #[doc = "Field `txe_im` writer - TX empty interrupt mask"]
8694 pub type TxeImW<'a, REG> = crate::BitWriter<'a, REG>;
8695 #[doc = "Field `txo_im` reader - TX overflow interrupt mask"]
8696 pub type TxoImR = crate::BitReader;
8697 #[doc = "Field `txo_im` writer - TX overflow interrupt mask"]
8698 pub type TxoImW<'a, REG> = crate::BitWriter<'a, REG>;
8699 #[doc = "Field `rxu_im` reader - RX underflow interrupt mask"]
8700 pub type RxuImR = crate::BitReader;
8701 #[doc = "Field `rxu_im` writer - RX underflow interrupt mask"]
8702 pub type RxuImW<'a, REG> = crate::BitWriter<'a, REG>;
8703 #[doc = "Field `rxo_im` reader - RX overflow interrupt mask"]
8704 pub type RxoImR = crate::BitReader;
8705 #[doc = "Field `rxo_im` writer - RX overflow interrupt mask"]
8706 pub type RxoImW<'a, REG> = crate::BitWriter<'a, REG>;
8707 #[doc = "Field `rxf_im` reader - RX full interrupt mask"]
8708 pub type RxfImR = crate::BitReader;
8709 #[doc = "Field `rxf_im` writer - RX full interrupt mask"]
8710 pub type RxfImW<'a, REG> = crate::BitWriter<'a, REG>;
8711 #[doc = "Field `mst_im` reader - Multi-master interrupt mask"]
8712 pub type MstImR = crate::BitReader;
8713 #[doc = "Field `mst_im` writer - Multi-master interrupt mask"]
8714 pub type MstImW<'a, REG> = crate::BitWriter<'a, REG>;
8715 impl R {
8716 #[doc = "Bit 0 - TX empty interrupt mask"]
8717 #[inline(always)]
8718 pub fn txe_im(&self) -> TxeImR {
8719 TxeImR::new((self.bits & 1) != 0)
8720 }
8721 #[doc = "Bit 1 - TX overflow interrupt mask"]
8722 #[inline(always)]
8723 pub fn txo_im(&self) -> TxoImR {
8724 TxoImR::new(((self.bits >> 1) & 1) != 0)
8725 }
8726 #[doc = "Bit 2 - RX underflow interrupt mask"]
8727 #[inline(always)]
8728 pub fn rxu_im(&self) -> RxuImR {
8729 RxuImR::new(((self.bits >> 2) & 1) != 0)
8730 }
8731 #[doc = "Bit 3 - RX overflow interrupt mask"]
8732 #[inline(always)]
8733 pub fn rxo_im(&self) -> RxoImR {
8734 RxoImR::new(((self.bits >> 3) & 1) != 0)
8735 }
8736 #[doc = "Bit 4 - RX full interrupt mask"]
8737 #[inline(always)]
8738 pub fn rxf_im(&self) -> RxfImR {
8739 RxfImR::new(((self.bits >> 4) & 1) != 0)
8740 }
8741 #[doc = "Bit 5 - Multi-master interrupt mask"]
8742 #[inline(always)]
8743 pub fn mst_im(&self) -> MstImR {
8744 MstImR::new(((self.bits >> 5) & 1) != 0)
8745 }
8746 }
8747 impl W {
8748 #[doc = "Bit 0 - TX empty interrupt mask"]
8749 #[inline(always)]
8750 pub fn txe_im(&mut self) -> TxeImW<'_, SpiInmarSpec> {
8751 TxeImW::new(self, 0)
8752 }
8753 #[doc = "Bit 1 - TX overflow interrupt mask"]
8754 #[inline(always)]
8755 pub fn txo_im(&mut self) -> TxoImW<'_, SpiInmarSpec> {
8756 TxoImW::new(self, 1)
8757 }
8758 #[doc = "Bit 2 - RX underflow interrupt mask"]
8759 #[inline(always)]
8760 pub fn rxu_im(&mut self) -> RxuImW<'_, SpiInmarSpec> {
8761 RxuImW::new(self, 2)
8762 }
8763 #[doc = "Bit 3 - RX overflow interrupt mask"]
8764 #[inline(always)]
8765 pub fn rxo_im(&mut self) -> RxoImW<'_, SpiInmarSpec> {
8766 RxoImW::new(self, 3)
8767 }
8768 #[doc = "Bit 4 - RX full interrupt mask"]
8769 #[inline(always)]
8770 pub fn rxf_im(&mut self) -> RxfImW<'_, SpiInmarSpec> {
8771 RxfImW::new(self, 4)
8772 }
8773 #[doc = "Bit 5 - Multi-master interrupt mask"]
8774 #[inline(always)]
8775 pub fn mst_im(&mut self) -> MstImW<'_, SpiInmarSpec> {
8776 MstImW::new(self, 5)
8777 }
8778 }
8779 #[doc = "Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_inmar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_inmar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8780 pub struct SpiInmarSpec;
8781 impl crate::RegisterSpec for SpiInmarSpec {
8782 type Ux = u32;
8783 }
8784 #[doc = "`read()` method returns [`spi_inmar::R`](R) reader structure"]
8785 impl crate::Readable for SpiInmarSpec {}
8786 #[doc = "`write(|w| ..)` method takes [`spi_inmar::W`](W) writer structure"]
8787 impl crate::Writable for SpiInmarSpec {
8788 type Safety = crate::Unsafe;
8789 }
8790 #[doc = "`reset()` method sets SPI_INMAR to value 0"]
8791 impl crate::Resettable for SpiInmarSpec {}
8792 }
8793 #[doc = "SPI_SLENR (rw) register accessor: Slave enable register (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_slenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_slenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slenr`] module"]
8794 #[doc(alias = "SPI_SLENR")]
8795 pub type SpiSlenr = crate::Reg<spi_slenr::SpiSlenrSpec>;
8796 #[doc = "Slave enable register (master only)"]
8797 pub mod spi_slenr {
8798 #[doc = "Register `SPI_SLENR` reader"]
8799 pub type R = crate::R<SpiSlenrSpec>;
8800 #[doc = "Register `SPI_SLENR` writer"]
8801 pub type W = crate::W<SpiSlenrSpec>;
8802 #[doc = "Field `slave_enable` reader - Slave select enable"]
8803 pub type SlaveEnableR = crate::BitReader;
8804 #[doc = "Field `slave_enable` writer - Slave select enable"]
8805 pub type SlaveEnableW<'a, REG> = crate::BitWriter<'a, REG>;
8806 impl R {
8807 #[doc = "Bit 0 - Slave select enable"]
8808 #[inline(always)]
8809 pub fn slave_enable(&self) -> SlaveEnableR {
8810 SlaveEnableR::new((self.bits & 1) != 0)
8811 }
8812 }
8813 impl W {
8814 #[doc = "Bit 0 - Slave select enable"]
8815 #[inline(always)]
8816 pub fn slave_enable(&mut self) -> SlaveEnableW<'_, SpiSlenrSpec> {
8817 SlaveEnableW::new(self, 0)
8818 }
8819 }
8820 #[doc = "Slave enable register (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_slenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_slenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8821 pub struct SpiSlenrSpec;
8822 impl crate::RegisterSpec for SpiSlenrSpec {
8823 type Ux = u32;
8824 }
8825 #[doc = "`read()` method returns [`spi_slenr::R`](R) reader structure"]
8826 impl crate::Readable for SpiSlenrSpec {}
8827 #[doc = "`write(|w| ..)` method takes [`spi_slenr::W`](W) writer structure"]
8828 impl crate::Writable for SpiSlenrSpec {
8829 type Safety = crate::Unsafe;
8830 }
8831 #[doc = "`reset()` method sets SPI_SLENR to value 0"]
8832 impl crate::Resettable for SpiSlenrSpec {}
8833 }
8834 #[doc = "SPI_TWLR (rw) register accessor: TX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_twlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_twlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_twlr`] module"]
8835 #[doc(alias = "SPI_TWLR")]
8836 pub type SpiTwlr = crate::Reg<spi_twlr::SpiTwlrSpec>;
8837 #[doc = "TX FIFO threshold level"]
8838 pub mod spi_twlr {
8839 #[doc = "Register `SPI_TWLR` reader"]
8840 pub type R = crate::R<SpiTwlrSpec>;
8841 #[doc = "Register `SPI_TWLR` writer"]
8842 pub type W = crate::W<SpiTwlrSpec>;
8843 #[doc = "Field `tx_fifo_threshold` reader - TX FIFO threshold level"]
8844 pub type TxFifoThresholdR = crate::FieldReader;
8845 #[doc = "Field `tx_fifo_threshold` writer - TX FIFO threshold level"]
8846 pub type TxFifoThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
8847 impl R {
8848 #[doc = "Bits 0:7 - TX FIFO threshold level"]
8849 #[inline(always)]
8850 pub fn tx_fifo_threshold(&self) -> TxFifoThresholdR {
8851 TxFifoThresholdR::new((self.bits & 0xff) as u8)
8852 }
8853 }
8854 impl W {
8855 #[doc = "Bits 0:7 - TX FIFO threshold level"]
8856 #[inline(always)]
8857 pub fn tx_fifo_threshold(&mut self) -> TxFifoThresholdW<'_, SpiTwlrSpec> {
8858 TxFifoThresholdW::new(self, 0)
8859 }
8860 }
8861 #[doc = "TX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_twlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_twlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8862 pub struct SpiTwlrSpec;
8863 impl crate::RegisterSpec for SpiTwlrSpec {
8864 type Ux = u32;
8865 }
8866 #[doc = "`read()` method returns [`spi_twlr::R`](R) reader structure"]
8867 impl crate::Readable for SpiTwlrSpec {}
8868 #[doc = "`write(|w| ..)` method takes [`spi_twlr::W`](W) writer structure"]
8869 impl crate::Writable for SpiTwlrSpec {
8870 type Safety = crate::Unsafe;
8871 }
8872 #[doc = "`reset()` method sets SPI_TWLR to value 0"]
8873 impl crate::Resettable for SpiTwlrSpec {}
8874 }
8875 #[doc = "SPI_TLR (rw) register accessor: TX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_tlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_tlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_tlr`] module"]
8876 #[doc(alias = "SPI_TLR")]
8877 pub type SpiTlr = crate::Reg<spi_tlr::SpiTlrSpec>;
8878 #[doc = "TX FIFO level register"]
8879 pub mod spi_tlr {
8880 #[doc = "Register `SPI_TLR` reader"]
8881 pub type R = crate::R<SpiTlrSpec>;
8882 #[doc = "Register `SPI_TLR` writer"]
8883 pub type W = crate::W<SpiTlrSpec>;
8884 #[doc = "Field `tx_fifo_level` reader - TX FIFO data level"]
8885 pub type TxFifoLevelR = crate::FieldReader;
8886 impl R {
8887 #[doc = "Bits 0:7 - TX FIFO data level"]
8888 #[inline(always)]
8889 pub fn tx_fifo_level(&self) -> TxFifoLevelR {
8890 TxFifoLevelR::new((self.bits & 0xff) as u8)
8891 }
8892 }
8893 impl W {}
8894 #[doc = "TX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_tlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_tlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8895 pub struct SpiTlrSpec;
8896 impl crate::RegisterSpec for SpiTlrSpec {
8897 type Ux = u32;
8898 }
8899 #[doc = "`read()` method returns [`spi_tlr::R`](R) reader structure"]
8900 impl crate::Readable for SpiTlrSpec {}
8901 #[doc = "`write(|w| ..)` method takes [`spi_tlr::W`](W) writer structure"]
8902 impl crate::Writable for SpiTlrSpec {
8903 type Safety = crate::Unsafe;
8904 }
8905 #[doc = "`reset()` method sets SPI_TLR to value 0"]
8906 impl crate::Resettable for SpiTlrSpec {}
8907 }
8908 #[doc = "SPI_RWLR (rw) register accessor: RX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rwlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rwlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rwlr`] module"]
8909 #[doc(alias = "SPI_RWLR")]
8910 pub type SpiRwlr = crate::Reg<spi_rwlr::SpiRwlrSpec>;
8911 #[doc = "RX FIFO threshold level"]
8912 pub mod spi_rwlr {
8913 #[doc = "Register `SPI_RWLR` reader"]
8914 pub type R = crate::R<SpiRwlrSpec>;
8915 #[doc = "Register `SPI_RWLR` writer"]
8916 pub type W = crate::W<SpiRwlrSpec>;
8917 #[doc = "Field `rx_fifo_threshold` reader - RX FIFO threshold level"]
8918 pub type RxFifoThresholdR = crate::FieldReader;
8919 #[doc = "Field `rx_fifo_threshold` writer - RX FIFO threshold level"]
8920 pub type RxFifoThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
8921 impl R {
8922 #[doc = "Bits 0:7 - RX FIFO threshold level"]
8923 #[inline(always)]
8924 pub fn rx_fifo_threshold(&self) -> RxFifoThresholdR {
8925 RxFifoThresholdR::new((self.bits & 0xff) as u8)
8926 }
8927 }
8928 impl W {
8929 #[doc = "Bits 0:7 - RX FIFO threshold level"]
8930 #[inline(always)]
8931 pub fn rx_fifo_threshold(&mut self) -> RxFifoThresholdW<'_, SpiRwlrSpec> {
8932 RxFifoThresholdW::new(self, 0)
8933 }
8934 }
8935 #[doc = "RX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rwlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rwlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8936 pub struct SpiRwlrSpec;
8937 impl crate::RegisterSpec for SpiRwlrSpec {
8938 type Ux = u32;
8939 }
8940 #[doc = "`read()` method returns [`spi_rwlr::R`](R) reader structure"]
8941 impl crate::Readable for SpiRwlrSpec {}
8942 #[doc = "`write(|w| ..)` method takes [`spi_rwlr::W`](W) writer structure"]
8943 impl crate::Writable for SpiRwlrSpec {
8944 type Safety = crate::Unsafe;
8945 }
8946 #[doc = "`reset()` method sets SPI_RWLR to value 0"]
8947 impl crate::Resettable for SpiRwlrSpec {}
8948 }
8949 #[doc = "SPI_RLR (rw) register accessor: RX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rlr`] module"]
8950 #[doc(alias = "SPI_RLR")]
8951 pub type SpiRlr = crate::Reg<spi_rlr::SpiRlrSpec>;
8952 #[doc = "RX FIFO level register"]
8953 pub mod spi_rlr {
8954 #[doc = "Register `SPI_RLR` reader"]
8955 pub type R = crate::R<SpiRlrSpec>;
8956 #[doc = "Register `SPI_RLR` writer"]
8957 pub type W = crate::W<SpiRlrSpec>;
8958 #[doc = "Field `rx_fifo_level` reader - RX FIFO data level"]
8959 pub type RxFifoLevelR = crate::FieldReader;
8960 impl R {
8961 #[doc = "Bits 0:7 - RX FIFO data level"]
8962 #[inline(always)]
8963 pub fn rx_fifo_level(&self) -> RxFifoLevelR {
8964 RxFifoLevelR::new((self.bits & 0xff) as u8)
8965 }
8966 }
8967 impl W {}
8968 #[doc = "RX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
8969 pub struct SpiRlrSpec;
8970 impl crate::RegisterSpec for SpiRlrSpec {
8971 type Ux = u32;
8972 }
8973 #[doc = "`read()` method returns [`spi_rlr::R`](R) reader structure"]
8974 impl crate::Readable for SpiRlrSpec {}
8975 #[doc = "`write(|w| ..)` method takes [`spi_rlr::W`](W) writer structure"]
8976 impl crate::Writable for SpiRlrSpec {
8977 type Safety = crate::Unsafe;
8978 }
8979 #[doc = "`reset()` method sets SPI_RLR to value 0"]
8980 impl crate::Resettable for SpiRlrSpec {}
8981 }
8982 #[doc = "SPI_WSR (rw) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_wsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_wsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_wsr`] module"]
8983 #[doc(alias = "SPI_WSR")]
8984 pub type SpiWsr = crate::Reg<spi_wsr::SpiWsrSpec>;
8985 #[doc = "Status register"]
8986 pub mod spi_wsr {
8987 #[doc = "Register `SPI_WSR` reader"]
8988 pub type R = crate::R<SpiWsrSpec>;
8989 #[doc = "Register `SPI_WSR` writer"]
8990 pub type W = crate::W<SpiWsrSpec>;
8991 #[doc = "Field `busy` reader - SPI busy flag"]
8992 pub type BusyR = crate::BitReader;
8993 #[doc = "Field `txfnf` reader - TX FIFO not full"]
8994 pub type TxfnfR = crate::BitReader;
8995 #[doc = "Field `txfe` reader - TX FIFO empty"]
8996 pub type TxfeR = crate::BitReader;
8997 #[doc = "Field `rxfne` reader - RX FIFO not empty"]
8998 pub type RxfneR = crate::BitReader;
8999 #[doc = "Field `rxfo` reader - RX FIFO overflow"]
9000 pub type RxfoR = crate::BitReader;
9001 #[doc = "Field `txfo` reader - TX FIFO overflow"]
9002 pub type TxfoR = crate::BitReader;
9003 #[doc = "Field `dcm` reader - Data conflict mask"]
9004 pub type DcmR = crate::BitReader;
9005 impl R {
9006 #[doc = "Bit 0 - SPI busy flag"]
9007 #[inline(always)]
9008 pub fn busy(&self) -> BusyR {
9009 BusyR::new((self.bits & 1) != 0)
9010 }
9011 #[doc = "Bit 1 - TX FIFO not full"]
9012 #[inline(always)]
9013 pub fn txfnf(&self) -> TxfnfR {
9014 TxfnfR::new(((self.bits >> 1) & 1) != 0)
9015 }
9016 #[doc = "Bit 2 - TX FIFO empty"]
9017 #[inline(always)]
9018 pub fn txfe(&self) -> TxfeR {
9019 TxfeR::new(((self.bits >> 2) & 1) != 0)
9020 }
9021 #[doc = "Bit 3 - RX FIFO not empty"]
9022 #[inline(always)]
9023 pub fn rxfne(&self) -> RxfneR {
9024 RxfneR::new(((self.bits >> 3) & 1) != 0)
9025 }
9026 #[doc = "Bit 4 - RX FIFO overflow"]
9027 #[inline(always)]
9028 pub fn rxfo(&self) -> RxfoR {
9029 RxfoR::new(((self.bits >> 4) & 1) != 0)
9030 }
9031 #[doc = "Bit 5 - TX FIFO overflow"]
9032 #[inline(always)]
9033 pub fn txfo(&self) -> TxfoR {
9034 TxfoR::new(((self.bits >> 5) & 1) != 0)
9035 }
9036 #[doc = "Bit 6 - Data conflict mask"]
9037 #[inline(always)]
9038 pub fn dcm(&self) -> DcmR {
9039 DcmR::new(((self.bits >> 6) & 1) != 0)
9040 }
9041 }
9042 impl W {}
9043 #[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_wsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_wsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9044 pub struct SpiWsrSpec;
9045 impl crate::RegisterSpec for SpiWsrSpec {
9046 type Ux = u32;
9047 }
9048 #[doc = "`read()` method returns [`spi_wsr::R`](R) reader structure"]
9049 impl crate::Readable for SpiWsrSpec {}
9050 #[doc = "`write(|w| ..)` method takes [`spi_wsr::W`](W) writer structure"]
9051 impl crate::Writable for SpiWsrSpec {
9052 type Safety = crate::Unsafe;
9053 }
9054 #[doc = "`reset()` method sets SPI_WSR to value 0x06"]
9055 impl crate::Resettable for SpiWsrSpec {
9056 const RESET_VALUE: u32 = 0x06;
9057 }
9058 }
9059 #[doc = "SPI_ICR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_icr`] module"]
9060 #[doc(alias = "SPI_ICR")]
9061 pub type SpiIcr = crate::Reg<spi_icr::SpiIcrSpec>;
9062 #[doc = "Interrupt clear register"]
9063 pub mod spi_icr {
9064 #[doc = "Register `SPI_ICR` reader"]
9065 pub type R = crate::R<SpiIcrSpec>;
9066 #[doc = "Register `SPI_ICR` writer"]
9067 pub type W = crate::W<SpiIcrSpec>;
9068 #[doc = "Field `txo_ic` writer - TX overflow interrupt clear"]
9069 pub type TxoIcW<'a, REG> = crate::BitWriter<'a, REG>;
9070 #[doc = "Field `rxu_ic` writer - RX underflow interrupt clear"]
9071 pub type RxuIcW<'a, REG> = crate::BitWriter<'a, REG>;
9072 #[doc = "Field `rxo_ic` writer - RX overflow interrupt clear"]
9073 pub type RxoIcW<'a, REG> = crate::BitWriter<'a, REG>;
9074 #[doc = "Field `mst_ic` writer - Multi-master interrupt clear"]
9075 pub type MstIcW<'a, REG> = crate::BitWriter<'a, REG>;
9076 impl W {
9077 #[doc = "Bit 0 - TX overflow interrupt clear"]
9078 #[inline(always)]
9079 pub fn txo_ic(&mut self) -> TxoIcW<'_, SpiIcrSpec> {
9080 TxoIcW::new(self, 0)
9081 }
9082 #[doc = "Bit 1 - RX underflow interrupt clear"]
9083 #[inline(always)]
9084 pub fn rxu_ic(&mut self) -> RxuIcW<'_, SpiIcrSpec> {
9085 RxuIcW::new(self, 1)
9086 }
9087 #[doc = "Bit 2 - RX overflow interrupt clear"]
9088 #[inline(always)]
9089 pub fn rxo_ic(&mut self) -> RxoIcW<'_, SpiIcrSpec> {
9090 RxoIcW::new(self, 2)
9091 }
9092 #[doc = "Bit 3 - Multi-master interrupt clear"]
9093 #[inline(always)]
9094 pub fn mst_ic(&mut self) -> MstIcW<'_, SpiIcrSpec> {
9095 MstIcW::new(self, 3)
9096 }
9097 }
9098 #[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9099 pub struct SpiIcrSpec;
9100 impl crate::RegisterSpec for SpiIcrSpec {
9101 type Ux = u32;
9102 }
9103 #[doc = "`read()` method returns [`spi_icr::R`](R) reader structure"]
9104 impl crate::Readable for SpiIcrSpec {}
9105 #[doc = "`write(|w| ..)` method takes [`spi_icr::W`](W) writer structure"]
9106 impl crate::Writable for SpiIcrSpec {
9107 type Safety = crate::Unsafe;
9108 }
9109 #[doc = "`reset()` method sets SPI_ICR to value 0"]
9110 impl crate::Resettable for SpiIcrSpec {}
9111 }
9112}
9113#[doc = "PWM controller with 8 channels"]
9114pub type Pwm = crate::Periph<pwm::RegisterBlock, 0x5209_0000>;
9115impl core::fmt::Debug for Pwm {
9116 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
9117 f.debug_struct("Pwm").finish()
9118 }
9119}
9120#[doc = "PWM controller with 8 channels"]
9121pub mod pwm {
9122 #[repr(C)]
9123 #[doc = "Register block"]
9124 pub struct RegisterBlock {
9125 pwm_sel0: PwmSel0,
9126 pwm_startclrcnt_en0: PwmStartclrcntEn0,
9127 pwm_start0: PwmStart0,
9128 _reserved3: [u8; 0x04],
9129 pwm_sel1: PwmSel1,
9130 pwm_startclrcnt_en1: PwmStartclrcntEn1,
9131 pwm_start1: PwmStart1,
9132 _reserved6: [u8; 0x04],
9133 pwm_sel2: PwmSel2,
9134 pwm_startclrcnt_en2: PwmStartclrcntEn2,
9135 pwm_start2: PwmStart2,
9136 _reserved9: [u8; 0x04],
9137 pwm_sel3: PwmSel3,
9138 pwm_startclrcnt_en3: PwmStartclrcntEn3,
9139 pwm_start3: PwmStart3,
9140 _reserved12: [u8; 0xc4],
9141 pwm_en0: PwmEn0,
9142 pwm_portity0: PwmPortity0,
9143 pwm_oen_cfg0: PwmOenCfg0,
9144 pwm_offset_l0: PwmOffsetL0,
9145 pwm_offset_h0: PwmOffsetH0,
9146 pwm_freq_l0: PwmFreqL0,
9147 pwm_freq_h0: PwmFreqH0,
9148 pwm_duty_l0: PwmDutyL0,
9149 pwm_duty_h0: PwmDutyH0,
9150 pwm_periodload_flag0: PwmPeriodloadFlag0,
9151 pwm_period_val0: PwmPeriodVal0,
9152 pwm_periodcnt0: PwmPeriodcnt0,
9153 _reserved24: [u8; 0x10],
9154 pwm_en1: PwmEn1,
9155 pwm_portity1: PwmPortity1,
9156 pwm_oen_cfg1: PwmOenCfg1,
9157 pwm_offset_l1: PwmOffsetL1,
9158 pwm_offset_h1: PwmOffsetH1,
9159 pwm_freq_l1: PwmFreqL1,
9160 pwm_freq_h1: PwmFreqH1,
9161 pwm_duty_l1: PwmDutyL1,
9162 pwm_duty_h1: PwmDutyH1,
9163 pwm_periodload_flag1: PwmPeriodloadFlag1,
9164 pwm_period_val1: PwmPeriodVal1,
9165 pwm_periodcnt1: PwmPeriodcnt1,
9166 _reserved36: [u8; 0x10],
9167 pwm_en2: PwmEn2,
9168 pwm_portity2: PwmPortity2,
9169 pwm_oen_cfg2: PwmOenCfg2,
9170 pwm_offset_l2: PwmOffsetL2,
9171 pwm_offset_h2: PwmOffsetH2,
9172 pwm_freq_l2: PwmFreqL2,
9173 pwm_freq_h2: PwmFreqH2,
9174 pwm_duty_l2: PwmDutyL2,
9175 pwm_duty_h2: PwmDutyH2,
9176 pwm_periodload_flag2: PwmPeriodloadFlag2,
9177 pwm_period_val2: PwmPeriodVal2,
9178 pwm_periodcnt2: PwmPeriodcnt2,
9179 _reserved48: [u8; 0x10],
9180 pwm_en3: PwmEn3,
9181 pwm_portity3: PwmPortity3,
9182 pwm_oen_cfg3: PwmOenCfg3,
9183 pwm_offset_l3: PwmOffsetL3,
9184 pwm_offset_h3: PwmOffsetH3,
9185 pwm_freq_l3: PwmFreqL3,
9186 pwm_freq_h3: PwmFreqH3,
9187 pwm_duty_l3: PwmDutyL3,
9188 pwm_duty_h3: PwmDutyH3,
9189 pwm_periodload_flag3: PwmPeriodloadFlag3,
9190 pwm_period_val3: PwmPeriodVal3,
9191 pwm_periodcnt3: PwmPeriodcnt3,
9192 _reserved60: [u8; 0x10],
9193 pwm_en4: PwmEn4,
9194 pwm_portity4: PwmPortity4,
9195 pwm_oen_cfg4: PwmOenCfg4,
9196 pwm_offset_l4: PwmOffsetL4,
9197 pwm_offset_h4: PwmOffsetH4,
9198 pwm_freq_l4: PwmFreqL4,
9199 pwm_freq_h4: PwmFreqH4,
9200 pwm_duty_l4: PwmDutyL4,
9201 pwm_duty_h4: PwmDutyH4,
9202 pwm_periodload_flag4: PwmPeriodloadFlag4,
9203 pwm_period_val4: PwmPeriodVal4,
9204 pwm_periodcnt4: PwmPeriodcnt4,
9205 _reserved72: [u8; 0x10],
9206 pwm_en5: PwmEn5,
9207 pwm_portity5: PwmPortity5,
9208 pwm_oen_cfg5: PwmOenCfg5,
9209 pwm_offset_l5: PwmOffsetL5,
9210 pwm_offset_h5: PwmOffsetH5,
9211 pwm_freq_l5: PwmFreqL5,
9212 pwm_freq_h5: PwmFreqH5,
9213 pwm_duty_l5: PwmDutyL5,
9214 pwm_duty_h5: PwmDutyH5,
9215 pwm_periodload_flag5: PwmPeriodloadFlag5,
9216 pwm_period_val5: PwmPeriodVal5,
9217 pwm_periodcnt5: PwmPeriodcnt5,
9218 _reserved84: [u8; 0x10],
9219 pwm_en6: PwmEn6,
9220 pwm_portity6: PwmPortity6,
9221 pwm_oen_cfg6: PwmOenCfg6,
9222 pwm_offset_l6: PwmOffsetL6,
9223 pwm_offset_h6: PwmOffsetH6,
9224 pwm_freq_l6: PwmFreqL6,
9225 pwm_freq_h6: PwmFreqH6,
9226 pwm_duty_l6: PwmDutyL6,
9227 pwm_duty_h6: PwmDutyH6,
9228 pwm_periodload_flag6: PwmPeriodloadFlag6,
9229 pwm_period_val6: PwmPeriodVal6,
9230 pwm_periodcnt6: PwmPeriodcnt6,
9231 _reserved96: [u8; 0x10],
9232 pwm_en7: PwmEn7,
9233 pwm_portity7: PwmPortity7,
9234 pwm_oen_cfg7: PwmOenCfg7,
9235 pwm_offset_l7: PwmOffsetL7,
9236 pwm_offset_h7: PwmOffsetH7,
9237 pwm_freq_l7: PwmFreqL7,
9238 pwm_freq_h7: PwmFreqH7,
9239 pwm_duty_l7: PwmDutyL7,
9240 pwm_duty_h7: PwmDutyH7,
9241 pwm_periodload_flag7: PwmPeriodloadFlag7,
9242 pwm_period_val7: PwmPeriodVal7,
9243 pwm_periodcnt7: PwmPeriodcnt7,
9244 _reserved108: [u8; 0x0210],
9245 pwm_abnor_state0: PwmAbnorState0,
9246 pwm_abnor_state1: PwmAbnorState1,
9247 pwm_abnor_state_clr0: PwmAbnorStateClr0,
9248 pwm_abnor_state_clr1: PwmAbnorStateClr1,
9249 pwm_int_mask: PwmIntMask,
9250 pwm_dma_en: PwmDmaEn,
9251 pwm_cfg_int_clr0: PwmCfgIntClr0,
9252 }
9253 impl RegisterBlock {
9254 #[doc = "0x00 - PWM group 0 select"]
9255 #[inline(always)]
9256 pub const fn pwm_sel0(&self) -> &PwmSel0 {
9257 &self.pwm_sel0
9258 }
9259 #[doc = "0x04 - PWM group 0 start clear counter enable"]
9260 #[inline(always)]
9261 pub const fn pwm_startclrcnt_en0(&self) -> &PwmStartclrcntEn0 {
9262 &self.pwm_startclrcnt_en0
9263 }
9264 #[doc = "0x08 - PWM group 0 start"]
9265 #[inline(always)]
9266 pub const fn pwm_start0(&self) -> &PwmStart0 {
9267 &self.pwm_start0
9268 }
9269 #[doc = "0x10 - PWM group 1 select"]
9270 #[inline(always)]
9271 pub const fn pwm_sel1(&self) -> &PwmSel1 {
9272 &self.pwm_sel1
9273 }
9274 #[doc = "0x14 - PWM group 1 start clear counter enable"]
9275 #[inline(always)]
9276 pub const fn pwm_startclrcnt_en1(&self) -> &PwmStartclrcntEn1 {
9277 &self.pwm_startclrcnt_en1
9278 }
9279 #[doc = "0x18 - PWM group 1 start"]
9280 #[inline(always)]
9281 pub const fn pwm_start1(&self) -> &PwmStart1 {
9282 &self.pwm_start1
9283 }
9284 #[doc = "0x20 - PWM group 2 select"]
9285 #[inline(always)]
9286 pub const fn pwm_sel2(&self) -> &PwmSel2 {
9287 &self.pwm_sel2
9288 }
9289 #[doc = "0x24 - PWM group 2 start clear counter enable"]
9290 #[inline(always)]
9291 pub const fn pwm_startclrcnt_en2(&self) -> &PwmStartclrcntEn2 {
9292 &self.pwm_startclrcnt_en2
9293 }
9294 #[doc = "0x28 - PWM group 2 start"]
9295 #[inline(always)]
9296 pub const fn pwm_start2(&self) -> &PwmStart2 {
9297 &self.pwm_start2
9298 }
9299 #[doc = "0x30 - PWM group 3 select"]
9300 #[inline(always)]
9301 pub const fn pwm_sel3(&self) -> &PwmSel3 {
9302 &self.pwm_sel3
9303 }
9304 #[doc = "0x34 - PWM group 3 start clear counter enable"]
9305 #[inline(always)]
9306 pub const fn pwm_startclrcnt_en3(&self) -> &PwmStartclrcntEn3 {
9307 &self.pwm_startclrcnt_en3
9308 }
9309 #[doc = "0x38 - PWM group 3 start"]
9310 #[inline(always)]
9311 pub const fn pwm_start3(&self) -> &PwmStart3 {
9312 &self.pwm_start3
9313 }
9314 #[doc = "0x100 - PWM0 enable"]
9315 #[inline(always)]
9316 pub const fn pwm_en0(&self) -> &PwmEn0 {
9317 &self.pwm_en0
9318 }
9319 #[doc = "0x104 - PWM0 polarity"]
9320 #[inline(always)]
9321 pub const fn pwm_portity0(&self) -> &PwmPortity0 {
9322 &self.pwm_portity0
9323 }
9324 #[doc = "0x108 - PWM0 high-impedance config"]
9325 #[inline(always)]
9326 pub const fn pwm_oen_cfg0(&self) -> &PwmOenCfg0 {
9327 &self.pwm_oen_cfg0
9328 }
9329 #[doc = "0x10c - PWM0 phase offset low 16 bits"]
9330 #[inline(always)]
9331 pub const fn pwm_offset_l0(&self) -> &PwmOffsetL0 {
9332 &self.pwm_offset_l0
9333 }
9334 #[doc = "0x110 - PWM0 phase offset high 16 bits"]
9335 #[inline(always)]
9336 pub const fn pwm_offset_h0(&self) -> &PwmOffsetH0 {
9337 &self.pwm_offset_h0
9338 }
9339 #[doc = "0x114 - PWM0 frequency low 16 bits"]
9340 #[inline(always)]
9341 pub const fn pwm_freq_l0(&self) -> &PwmFreqL0 {
9342 &self.pwm_freq_l0
9343 }
9344 #[doc = "0x118 - PWM0 frequency high 16 bits"]
9345 #[inline(always)]
9346 pub const fn pwm_freq_h0(&self) -> &PwmFreqH0 {
9347 &self.pwm_freq_h0
9348 }
9349 #[doc = "0x11c - PWM0 duty cycle low 16 bits"]
9350 #[inline(always)]
9351 pub const fn pwm_duty_l0(&self) -> &PwmDutyL0 {
9352 &self.pwm_duty_l0
9353 }
9354 #[doc = "0x120 - PWM0 duty cycle high 16 bits"]
9355 #[inline(always)]
9356 pub const fn pwm_duty_h0(&self) -> &PwmDutyH0 {
9357 &self.pwm_duty_h0
9358 }
9359 #[doc = "0x124 - PWM0 period load flag"]
9360 #[inline(always)]
9361 pub const fn pwm_periodload_flag0(&self) -> &PwmPeriodloadFlag0 {
9362 &self.pwm_periodload_flag0
9363 }
9364 #[doc = "0x128 - PWM0 pulse count value"]
9365 #[inline(always)]
9366 pub const fn pwm_period_val0(&self) -> &PwmPeriodVal0 {
9367 &self.pwm_period_val0
9368 }
9369 #[doc = "0x12c - PWM0 pulse count current value"]
9370 #[inline(always)]
9371 pub const fn pwm_periodcnt0(&self) -> &PwmPeriodcnt0 {
9372 &self.pwm_periodcnt0
9373 }
9374 #[doc = "0x140 - PWM1 enable"]
9375 #[inline(always)]
9376 pub const fn pwm_en1(&self) -> &PwmEn1 {
9377 &self.pwm_en1
9378 }
9379 #[doc = "0x144 - PWM1 polarity"]
9380 #[inline(always)]
9381 pub const fn pwm_portity1(&self) -> &PwmPortity1 {
9382 &self.pwm_portity1
9383 }
9384 #[doc = "0x148 - PWM1 high-impedance config"]
9385 #[inline(always)]
9386 pub const fn pwm_oen_cfg1(&self) -> &PwmOenCfg1 {
9387 &self.pwm_oen_cfg1
9388 }
9389 #[doc = "0x14c - PWM1 phase offset low"]
9390 #[inline(always)]
9391 pub const fn pwm_offset_l1(&self) -> &PwmOffsetL1 {
9392 &self.pwm_offset_l1
9393 }
9394 #[doc = "0x150 - PWM1 phase offset high"]
9395 #[inline(always)]
9396 pub const fn pwm_offset_h1(&self) -> &PwmOffsetH1 {
9397 &self.pwm_offset_h1
9398 }
9399 #[doc = "0x154 - PWM1 frequency low"]
9400 #[inline(always)]
9401 pub const fn pwm_freq_l1(&self) -> &PwmFreqL1 {
9402 &self.pwm_freq_l1
9403 }
9404 #[doc = "0x158 - PWM1 frequency high"]
9405 #[inline(always)]
9406 pub const fn pwm_freq_h1(&self) -> &PwmFreqH1 {
9407 &self.pwm_freq_h1
9408 }
9409 #[doc = "0x15c - PWM1 duty cycle low"]
9410 #[inline(always)]
9411 pub const fn pwm_duty_l1(&self) -> &PwmDutyL1 {
9412 &self.pwm_duty_l1
9413 }
9414 #[doc = "0x160 - PWM1 duty cycle high"]
9415 #[inline(always)]
9416 pub const fn pwm_duty_h1(&self) -> &PwmDutyH1 {
9417 &self.pwm_duty_h1
9418 }
9419 #[doc = "0x164 - PWM1 period load flag"]
9420 #[inline(always)]
9421 pub const fn pwm_periodload_flag1(&self) -> &PwmPeriodloadFlag1 {
9422 &self.pwm_periodload_flag1
9423 }
9424 #[doc = "0x168 - PWM1 pulse count"]
9425 #[inline(always)]
9426 pub const fn pwm_period_val1(&self) -> &PwmPeriodVal1 {
9427 &self.pwm_period_val1
9428 }
9429 #[doc = "0x16c - PWM1 pulse count current"]
9430 #[inline(always)]
9431 pub const fn pwm_periodcnt1(&self) -> &PwmPeriodcnt1 {
9432 &self.pwm_periodcnt1
9433 }
9434 #[doc = "0x180 - PWM2 enable"]
9435 #[inline(always)]
9436 pub const fn pwm_en2(&self) -> &PwmEn2 {
9437 &self.pwm_en2
9438 }
9439 #[doc = "0x184 - PWM2 polarity"]
9440 #[inline(always)]
9441 pub const fn pwm_portity2(&self) -> &PwmPortity2 {
9442 &self.pwm_portity2
9443 }
9444 #[doc = "0x188 - PWM2 high-impedance config"]
9445 #[inline(always)]
9446 pub const fn pwm_oen_cfg2(&self) -> &PwmOenCfg2 {
9447 &self.pwm_oen_cfg2
9448 }
9449 #[doc = "0x18c - PWM2 phase offset low 16 bits"]
9450 #[inline(always)]
9451 pub const fn pwm_offset_l2(&self) -> &PwmOffsetL2 {
9452 &self.pwm_offset_l2
9453 }
9454 #[doc = "0x190 - PWM2 phase offset high 16 bits"]
9455 #[inline(always)]
9456 pub const fn pwm_offset_h2(&self) -> &PwmOffsetH2 {
9457 &self.pwm_offset_h2
9458 }
9459 #[doc = "0x194 - PWM2 frequency low 16 bits"]
9460 #[inline(always)]
9461 pub const fn pwm_freq_l2(&self) -> &PwmFreqL2 {
9462 &self.pwm_freq_l2
9463 }
9464 #[doc = "0x198 - PWM2 frequency high 16 bits"]
9465 #[inline(always)]
9466 pub const fn pwm_freq_h2(&self) -> &PwmFreqH2 {
9467 &self.pwm_freq_h2
9468 }
9469 #[doc = "0x19c - PWM2 duty cycle low 16 bits"]
9470 #[inline(always)]
9471 pub const fn pwm_duty_l2(&self) -> &PwmDutyL2 {
9472 &self.pwm_duty_l2
9473 }
9474 #[doc = "0x1a0 - PWM2 duty cycle high 16 bits"]
9475 #[inline(always)]
9476 pub const fn pwm_duty_h2(&self) -> &PwmDutyH2 {
9477 &self.pwm_duty_h2
9478 }
9479 #[doc = "0x1a4 - PWM2 period load flag"]
9480 #[inline(always)]
9481 pub const fn pwm_periodload_flag2(&self) -> &PwmPeriodloadFlag2 {
9482 &self.pwm_periodload_flag2
9483 }
9484 #[doc = "0x1a8 - PWM2 pulse count value"]
9485 #[inline(always)]
9486 pub const fn pwm_period_val2(&self) -> &PwmPeriodVal2 {
9487 &self.pwm_period_val2
9488 }
9489 #[doc = "0x1ac - PWM2 pulse count current value"]
9490 #[inline(always)]
9491 pub const fn pwm_periodcnt2(&self) -> &PwmPeriodcnt2 {
9492 &self.pwm_periodcnt2
9493 }
9494 #[doc = "0x1c0 - PWM3 enable"]
9495 #[inline(always)]
9496 pub const fn pwm_en3(&self) -> &PwmEn3 {
9497 &self.pwm_en3
9498 }
9499 #[doc = "0x1c4 - PWM3 polarity"]
9500 #[inline(always)]
9501 pub const fn pwm_portity3(&self) -> &PwmPortity3 {
9502 &self.pwm_portity3
9503 }
9504 #[doc = "0x1c8 - PWM3 high-impedance config"]
9505 #[inline(always)]
9506 pub const fn pwm_oen_cfg3(&self) -> &PwmOenCfg3 {
9507 &self.pwm_oen_cfg3
9508 }
9509 #[doc = "0x1cc - PWM3 phase offset low 16 bits"]
9510 #[inline(always)]
9511 pub const fn pwm_offset_l3(&self) -> &PwmOffsetL3 {
9512 &self.pwm_offset_l3
9513 }
9514 #[doc = "0x1d0 - PWM3 phase offset high 16 bits"]
9515 #[inline(always)]
9516 pub const fn pwm_offset_h3(&self) -> &PwmOffsetH3 {
9517 &self.pwm_offset_h3
9518 }
9519 #[doc = "0x1d4 - PWM3 frequency low 16 bits"]
9520 #[inline(always)]
9521 pub const fn pwm_freq_l3(&self) -> &PwmFreqL3 {
9522 &self.pwm_freq_l3
9523 }
9524 #[doc = "0x1d8 - PWM3 frequency high 16 bits"]
9525 #[inline(always)]
9526 pub const fn pwm_freq_h3(&self) -> &PwmFreqH3 {
9527 &self.pwm_freq_h3
9528 }
9529 #[doc = "0x1dc - PWM3 duty cycle low 16 bits"]
9530 #[inline(always)]
9531 pub const fn pwm_duty_l3(&self) -> &PwmDutyL3 {
9532 &self.pwm_duty_l3
9533 }
9534 #[doc = "0x1e0 - PWM3 duty cycle high 16 bits"]
9535 #[inline(always)]
9536 pub const fn pwm_duty_h3(&self) -> &PwmDutyH3 {
9537 &self.pwm_duty_h3
9538 }
9539 #[doc = "0x1e4 - PWM3 period load flag"]
9540 #[inline(always)]
9541 pub const fn pwm_periodload_flag3(&self) -> &PwmPeriodloadFlag3 {
9542 &self.pwm_periodload_flag3
9543 }
9544 #[doc = "0x1e8 - PWM3 pulse count value"]
9545 #[inline(always)]
9546 pub const fn pwm_period_val3(&self) -> &PwmPeriodVal3 {
9547 &self.pwm_period_val3
9548 }
9549 #[doc = "0x1ec - PWM3 pulse count current value"]
9550 #[inline(always)]
9551 pub const fn pwm_periodcnt3(&self) -> &PwmPeriodcnt3 {
9552 &self.pwm_periodcnt3
9553 }
9554 #[doc = "0x200 - PWM4 enable"]
9555 #[inline(always)]
9556 pub const fn pwm_en4(&self) -> &PwmEn4 {
9557 &self.pwm_en4
9558 }
9559 #[doc = "0x204 - PWM4 polarity"]
9560 #[inline(always)]
9561 pub const fn pwm_portity4(&self) -> &PwmPortity4 {
9562 &self.pwm_portity4
9563 }
9564 #[doc = "0x208 - PWM4 high-impedance config"]
9565 #[inline(always)]
9566 pub const fn pwm_oen_cfg4(&self) -> &PwmOenCfg4 {
9567 &self.pwm_oen_cfg4
9568 }
9569 #[doc = "0x20c - PWM4 phase offset low 16 bits"]
9570 #[inline(always)]
9571 pub const fn pwm_offset_l4(&self) -> &PwmOffsetL4 {
9572 &self.pwm_offset_l4
9573 }
9574 #[doc = "0x210 - PWM4 phase offset high 16 bits"]
9575 #[inline(always)]
9576 pub const fn pwm_offset_h4(&self) -> &PwmOffsetH4 {
9577 &self.pwm_offset_h4
9578 }
9579 #[doc = "0x214 - PWM4 frequency low 16 bits"]
9580 #[inline(always)]
9581 pub const fn pwm_freq_l4(&self) -> &PwmFreqL4 {
9582 &self.pwm_freq_l4
9583 }
9584 #[doc = "0x218 - PWM4 frequency high 16 bits"]
9585 #[inline(always)]
9586 pub const fn pwm_freq_h4(&self) -> &PwmFreqH4 {
9587 &self.pwm_freq_h4
9588 }
9589 #[doc = "0x21c - PWM4 duty cycle low 16 bits"]
9590 #[inline(always)]
9591 pub const fn pwm_duty_l4(&self) -> &PwmDutyL4 {
9592 &self.pwm_duty_l4
9593 }
9594 #[doc = "0x220 - PWM4 duty cycle high 16 bits"]
9595 #[inline(always)]
9596 pub const fn pwm_duty_h4(&self) -> &PwmDutyH4 {
9597 &self.pwm_duty_h4
9598 }
9599 #[doc = "0x224 - PWM4 period load flag"]
9600 #[inline(always)]
9601 pub const fn pwm_periodload_flag4(&self) -> &PwmPeriodloadFlag4 {
9602 &self.pwm_periodload_flag4
9603 }
9604 #[doc = "0x228 - PWM4 pulse count value"]
9605 #[inline(always)]
9606 pub const fn pwm_period_val4(&self) -> &PwmPeriodVal4 {
9607 &self.pwm_period_val4
9608 }
9609 #[doc = "0x22c - PWM4 pulse count current value"]
9610 #[inline(always)]
9611 pub const fn pwm_periodcnt4(&self) -> &PwmPeriodcnt4 {
9612 &self.pwm_periodcnt4
9613 }
9614 #[doc = "0x240 - PWM5 enable"]
9615 #[inline(always)]
9616 pub const fn pwm_en5(&self) -> &PwmEn5 {
9617 &self.pwm_en5
9618 }
9619 #[doc = "0x244 - PWM5 polarity"]
9620 #[inline(always)]
9621 pub const fn pwm_portity5(&self) -> &PwmPortity5 {
9622 &self.pwm_portity5
9623 }
9624 #[doc = "0x248 - PWM5 high-impedance config"]
9625 #[inline(always)]
9626 pub const fn pwm_oen_cfg5(&self) -> &PwmOenCfg5 {
9627 &self.pwm_oen_cfg5
9628 }
9629 #[doc = "0x24c - PWM5 phase offset low 16 bits"]
9630 #[inline(always)]
9631 pub const fn pwm_offset_l5(&self) -> &PwmOffsetL5 {
9632 &self.pwm_offset_l5
9633 }
9634 #[doc = "0x250 - PWM5 phase offset high 16 bits"]
9635 #[inline(always)]
9636 pub const fn pwm_offset_h5(&self) -> &PwmOffsetH5 {
9637 &self.pwm_offset_h5
9638 }
9639 #[doc = "0x254 - PWM5 frequency low 16 bits"]
9640 #[inline(always)]
9641 pub const fn pwm_freq_l5(&self) -> &PwmFreqL5 {
9642 &self.pwm_freq_l5
9643 }
9644 #[doc = "0x258 - PWM5 frequency high 16 bits"]
9645 #[inline(always)]
9646 pub const fn pwm_freq_h5(&self) -> &PwmFreqH5 {
9647 &self.pwm_freq_h5
9648 }
9649 #[doc = "0x25c - PWM5 duty cycle low 16 bits"]
9650 #[inline(always)]
9651 pub const fn pwm_duty_l5(&self) -> &PwmDutyL5 {
9652 &self.pwm_duty_l5
9653 }
9654 #[doc = "0x260 - PWM5 duty cycle high 16 bits"]
9655 #[inline(always)]
9656 pub const fn pwm_duty_h5(&self) -> &PwmDutyH5 {
9657 &self.pwm_duty_h5
9658 }
9659 #[doc = "0x264 - PWM5 period load flag"]
9660 #[inline(always)]
9661 pub const fn pwm_periodload_flag5(&self) -> &PwmPeriodloadFlag5 {
9662 &self.pwm_periodload_flag5
9663 }
9664 #[doc = "0x268 - PWM5 pulse count value"]
9665 #[inline(always)]
9666 pub const fn pwm_period_val5(&self) -> &PwmPeriodVal5 {
9667 &self.pwm_period_val5
9668 }
9669 #[doc = "0x26c - PWM5 pulse count current value"]
9670 #[inline(always)]
9671 pub const fn pwm_periodcnt5(&self) -> &PwmPeriodcnt5 {
9672 &self.pwm_periodcnt5
9673 }
9674 #[doc = "0x280 - PWM6 enable"]
9675 #[inline(always)]
9676 pub const fn pwm_en6(&self) -> &PwmEn6 {
9677 &self.pwm_en6
9678 }
9679 #[doc = "0x284 - PWM6 polarity"]
9680 #[inline(always)]
9681 pub const fn pwm_portity6(&self) -> &PwmPortity6 {
9682 &self.pwm_portity6
9683 }
9684 #[doc = "0x288 - PWM6 high-impedance config"]
9685 #[inline(always)]
9686 pub const fn pwm_oen_cfg6(&self) -> &PwmOenCfg6 {
9687 &self.pwm_oen_cfg6
9688 }
9689 #[doc = "0x28c - PWM6 phase offset low 16 bits"]
9690 #[inline(always)]
9691 pub const fn pwm_offset_l6(&self) -> &PwmOffsetL6 {
9692 &self.pwm_offset_l6
9693 }
9694 #[doc = "0x290 - PWM6 phase offset high 16 bits"]
9695 #[inline(always)]
9696 pub const fn pwm_offset_h6(&self) -> &PwmOffsetH6 {
9697 &self.pwm_offset_h6
9698 }
9699 #[doc = "0x294 - PWM6 frequency low 16 bits"]
9700 #[inline(always)]
9701 pub const fn pwm_freq_l6(&self) -> &PwmFreqL6 {
9702 &self.pwm_freq_l6
9703 }
9704 #[doc = "0x298 - PWM6 frequency high 16 bits"]
9705 #[inline(always)]
9706 pub const fn pwm_freq_h6(&self) -> &PwmFreqH6 {
9707 &self.pwm_freq_h6
9708 }
9709 #[doc = "0x29c - PWM6 duty cycle low 16 bits"]
9710 #[inline(always)]
9711 pub const fn pwm_duty_l6(&self) -> &PwmDutyL6 {
9712 &self.pwm_duty_l6
9713 }
9714 #[doc = "0x2a0 - PWM6 duty cycle high 16 bits"]
9715 #[inline(always)]
9716 pub const fn pwm_duty_h6(&self) -> &PwmDutyH6 {
9717 &self.pwm_duty_h6
9718 }
9719 #[doc = "0x2a4 - PWM6 period load flag"]
9720 #[inline(always)]
9721 pub const fn pwm_periodload_flag6(&self) -> &PwmPeriodloadFlag6 {
9722 &self.pwm_periodload_flag6
9723 }
9724 #[doc = "0x2a8 - PWM6 pulse count value"]
9725 #[inline(always)]
9726 pub const fn pwm_period_val6(&self) -> &PwmPeriodVal6 {
9727 &self.pwm_period_val6
9728 }
9729 #[doc = "0x2ac - PWM6 pulse count current value"]
9730 #[inline(always)]
9731 pub const fn pwm_periodcnt6(&self) -> &PwmPeriodcnt6 {
9732 &self.pwm_periodcnt6
9733 }
9734 #[doc = "0x2c0 - PWM7 enable"]
9735 #[inline(always)]
9736 pub const fn pwm_en7(&self) -> &PwmEn7 {
9737 &self.pwm_en7
9738 }
9739 #[doc = "0x2c4 - PWM7 polarity"]
9740 #[inline(always)]
9741 pub const fn pwm_portity7(&self) -> &PwmPortity7 {
9742 &self.pwm_portity7
9743 }
9744 #[doc = "0x2c8 - PWM7 high-impedance config"]
9745 #[inline(always)]
9746 pub const fn pwm_oen_cfg7(&self) -> &PwmOenCfg7 {
9747 &self.pwm_oen_cfg7
9748 }
9749 #[doc = "0x2cc - PWM7 phase offset low 16 bits"]
9750 #[inline(always)]
9751 pub const fn pwm_offset_l7(&self) -> &PwmOffsetL7 {
9752 &self.pwm_offset_l7
9753 }
9754 #[doc = "0x2d0 - PWM7 phase offset high 16 bits"]
9755 #[inline(always)]
9756 pub const fn pwm_offset_h7(&self) -> &PwmOffsetH7 {
9757 &self.pwm_offset_h7
9758 }
9759 #[doc = "0x2d4 - PWM7 frequency low 16 bits"]
9760 #[inline(always)]
9761 pub const fn pwm_freq_l7(&self) -> &PwmFreqL7 {
9762 &self.pwm_freq_l7
9763 }
9764 #[doc = "0x2d8 - PWM7 frequency high 16 bits"]
9765 #[inline(always)]
9766 pub const fn pwm_freq_h7(&self) -> &PwmFreqH7 {
9767 &self.pwm_freq_h7
9768 }
9769 #[doc = "0x2dc - PWM7 duty cycle low 16 bits"]
9770 #[inline(always)]
9771 pub const fn pwm_duty_l7(&self) -> &PwmDutyL7 {
9772 &self.pwm_duty_l7
9773 }
9774 #[doc = "0x2e0 - PWM7 duty cycle high 16 bits"]
9775 #[inline(always)]
9776 pub const fn pwm_duty_h7(&self) -> &PwmDutyH7 {
9777 &self.pwm_duty_h7
9778 }
9779 #[doc = "0x2e4 - PWM7 period load flag"]
9780 #[inline(always)]
9781 pub const fn pwm_periodload_flag7(&self) -> &PwmPeriodloadFlag7 {
9782 &self.pwm_periodload_flag7
9783 }
9784 #[doc = "0x2e8 - PWM7 pulse count value"]
9785 #[inline(always)]
9786 pub const fn pwm_period_val7(&self) -> &PwmPeriodVal7 {
9787 &self.pwm_period_val7
9788 }
9789 #[doc = "0x2ec - PWM7 pulse count current value"]
9790 #[inline(always)]
9791 pub const fn pwm_periodcnt7(&self) -> &PwmPeriodcnt7 {
9792 &self.pwm_periodcnt7
9793 }
9794 #[doc = "0x500 - PWM abnormal state register 0"]
9795 #[inline(always)]
9796 pub const fn pwm_abnor_state0(&self) -> &PwmAbnorState0 {
9797 &self.pwm_abnor_state0
9798 }
9799 #[doc = "0x504 - PWM abnormal state register 1"]
9800 #[inline(always)]
9801 pub const fn pwm_abnor_state1(&self) -> &PwmAbnorState1 {
9802 &self.pwm_abnor_state1
9803 }
9804 #[doc = "0x508 - PWM abnormal state clear 0"]
9805 #[inline(always)]
9806 pub const fn pwm_abnor_state_clr0(&self) -> &PwmAbnorStateClr0 {
9807 &self.pwm_abnor_state_clr0
9808 }
9809 #[doc = "0x50c - PWM abnormal state clear 1"]
9810 #[inline(always)]
9811 pub const fn pwm_abnor_state_clr1(&self) -> &PwmAbnorStateClr1 {
9812 &self.pwm_abnor_state_clr1
9813 }
9814 #[doc = "0x510 - PWM interrupt mask"]
9815 #[inline(always)]
9816 pub const fn pwm_int_mask(&self) -> &PwmIntMask {
9817 &self.pwm_int_mask
9818 }
9819 #[doc = "0x514 - PWM DMA enable"]
9820 #[inline(always)]
9821 pub const fn pwm_dma_en(&self) -> &PwmDmaEn {
9822 &self.pwm_dma_en
9823 }
9824 #[doc = "0x518 - PWM stepping cycle end interrupt clear"]
9825 #[inline(always)]
9826 pub const fn pwm_cfg_int_clr0(&self) -> &PwmCfgIntClr0 {
9827 &self.pwm_cfg_int_clr0
9828 }
9829 }
9830 #[doc = "PWM_SEL0 (rw) register accessor: PWM group 0 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel0`] module"]
9831 #[doc(alias = "PWM_SEL0")]
9832 pub type PwmSel0 = crate::Reg<pwm_sel0::PwmSel0Spec>;
9833 #[doc = "PWM group 0 select"]
9834 pub mod pwm_sel0 {
9835 #[doc = "Register `PWM_SEL0` reader"]
9836 pub type R = crate::R<PwmSel0Spec>;
9837 #[doc = "Register `PWM_SEL0` writer"]
9838 pub type W = crate::W<PwmSel0Spec>;
9839 #[doc = "Field `pwm_sel_0` reader - Group 0 PWM select, each bit corresponds to one PWM channel"]
9840 pub type PwmSel0R = crate::FieldReader<u16>;
9841 #[doc = "Field `pwm_sel_0` writer - Group 0 PWM select, each bit corresponds to one PWM channel"]
9842 pub type PwmSel0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9843 impl R {
9844 #[doc = "Bits 0:15 - Group 0 PWM select, each bit corresponds to one PWM channel"]
9845 #[inline(always)]
9846 pub fn pwm_sel_0(&self) -> PwmSel0R {
9847 PwmSel0R::new((self.bits & 0xffff) as u16)
9848 }
9849 }
9850 impl W {
9851 #[doc = "Bits 0:15 - Group 0 PWM select, each bit corresponds to one PWM channel"]
9852 #[inline(always)]
9853 pub fn pwm_sel_0(&mut self) -> PwmSel0W<'_, PwmSel0Spec> {
9854 PwmSel0W::new(self, 0)
9855 }
9856 }
9857 #[doc = "PWM group 0 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9858 pub struct PwmSel0Spec;
9859 impl crate::RegisterSpec for PwmSel0Spec {
9860 type Ux = u32;
9861 }
9862 #[doc = "`read()` method returns [`pwm_sel0::R`](R) reader structure"]
9863 impl crate::Readable for PwmSel0Spec {}
9864 #[doc = "`write(|w| ..)` method takes [`pwm_sel0::W`](W) writer structure"]
9865 impl crate::Writable for PwmSel0Spec {
9866 type Safety = crate::Unsafe;
9867 }
9868 #[doc = "`reset()` method sets PWM_SEL0 to value 0"]
9869 impl crate::Resettable for PwmSel0Spec {}
9870 }
9871 #[doc = "PWM_STARTCLRCNT_EN0 (rw) register accessor: PWM group 0 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en0`] module"]
9872 #[doc(alias = "PWM_STARTCLRCNT_EN0")]
9873 pub type PwmStartclrcntEn0 = crate::Reg<pwm_startclrcnt_en0::PwmStartclrcntEn0Spec>;
9874 #[doc = "PWM group 0 start clear counter enable"]
9875 pub mod pwm_startclrcnt_en0 {
9876 #[doc = "Register `PWM_STARTCLRCNT_EN0` reader"]
9877 pub type R = crate::R<PwmStartclrcntEn0Spec>;
9878 #[doc = "Register `PWM_STARTCLRCNT_EN0` writer"]
9879 pub type W = crate::W<PwmStartclrcntEn0Spec>;
9880 #[doc = "Field `pwm_startclrcnt_en_0` reader - Start clear counter enable for group 0"]
9881 pub type PwmStartclrcntEn0R = crate::BitReader;
9882 #[doc = "Field `pwm_startclrcnt_en_0` writer - Start clear counter enable for group 0"]
9883 pub type PwmStartclrcntEn0W<'a, REG> = crate::BitWriter<'a, REG>;
9884 impl R {
9885 #[doc = "Bit 0 - Start clear counter enable for group 0"]
9886 #[inline(always)]
9887 pub fn pwm_startclrcnt_en_0(&self) -> PwmStartclrcntEn0R {
9888 PwmStartclrcntEn0R::new((self.bits & 1) != 0)
9889 }
9890 }
9891 impl W {
9892 #[doc = "Bit 0 - Start clear counter enable for group 0"]
9893 #[inline(always)]
9894 pub fn pwm_startclrcnt_en_0(
9895 &mut self,
9896 ) -> PwmStartclrcntEn0W<'_, PwmStartclrcntEn0Spec> {
9897 PwmStartclrcntEn0W::new(self, 0)
9898 }
9899 }
9900 #[doc = "PWM group 0 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9901 pub struct PwmStartclrcntEn0Spec;
9902 impl crate::RegisterSpec for PwmStartclrcntEn0Spec {
9903 type Ux = u32;
9904 }
9905 #[doc = "`read()` method returns [`pwm_startclrcnt_en0::R`](R) reader structure"]
9906 impl crate::Readable for PwmStartclrcntEn0Spec {}
9907 #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en0::W`](W) writer structure"]
9908 impl crate::Writable for PwmStartclrcntEn0Spec {
9909 type Safety = crate::Unsafe;
9910 }
9911 #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN0 to value 0"]
9912 impl crate::Resettable for PwmStartclrcntEn0Spec {}
9913 }
9914 #[doc = "PWM_START0 (rw) register accessor: PWM group 0 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start0`] module"]
9915 #[doc(alias = "PWM_START0")]
9916 pub type PwmStart0 = crate::Reg<pwm_start0::PwmStart0Spec>;
9917 #[doc = "PWM group 0 start"]
9918 pub mod pwm_start0 {
9919 #[doc = "Register `PWM_START0` reader"]
9920 pub type R = crate::R<PwmStart0Spec>;
9921 #[doc = "Register `PWM_START0` writer"]
9922 pub type W = crate::W<PwmStart0Spec>;
9923 #[doc = "Field `pwm_start_0` writer - Start group 0 (self-clearing)"]
9924 pub type PwmStart0W<'a, REG> = crate::BitWriter<'a, REG>;
9925 impl W {
9926 #[doc = "Bit 0 - Start group 0 (self-clearing)"]
9927 #[inline(always)]
9928 pub fn pwm_start_0(&mut self) -> PwmStart0W<'_, PwmStart0Spec> {
9929 PwmStart0W::new(self, 0)
9930 }
9931 }
9932 #[doc = "PWM group 0 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9933 pub struct PwmStart0Spec;
9934 impl crate::RegisterSpec for PwmStart0Spec {
9935 type Ux = u32;
9936 }
9937 #[doc = "`read()` method returns [`pwm_start0::R`](R) reader structure"]
9938 impl crate::Readable for PwmStart0Spec {}
9939 #[doc = "`write(|w| ..)` method takes [`pwm_start0::W`](W) writer structure"]
9940 impl crate::Writable for PwmStart0Spec {
9941 type Safety = crate::Unsafe;
9942 }
9943 #[doc = "`reset()` method sets PWM_START0 to value 0"]
9944 impl crate::Resettable for PwmStart0Spec {}
9945 }
9946 #[doc = "PWM_SEL1 (rw) register accessor: PWM group 1 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel1`] module"]
9947 #[doc(alias = "PWM_SEL1")]
9948 pub type PwmSel1 = crate::Reg<pwm_sel1::PwmSel1Spec>;
9949 #[doc = "PWM group 1 select"]
9950 pub mod pwm_sel1 {
9951 #[doc = "Register `PWM_SEL1` reader"]
9952 pub type R = crate::R<PwmSel1Spec>;
9953 #[doc = "Register `PWM_SEL1` writer"]
9954 pub type W = crate::W<PwmSel1Spec>;
9955 #[doc = "Field `pwm_sel_1` reader - Group 1 PWM select"]
9956 pub type PwmSel1R = crate::FieldReader<u16>;
9957 #[doc = "Field `pwm_sel_1` writer - Group 1 PWM select"]
9958 pub type PwmSel1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9959 impl R {
9960 #[doc = "Bits 0:15 - Group 1 PWM select"]
9961 #[inline(always)]
9962 pub fn pwm_sel_1(&self) -> PwmSel1R {
9963 PwmSel1R::new((self.bits & 0xffff) as u16)
9964 }
9965 }
9966 impl W {
9967 #[doc = "Bits 0:15 - Group 1 PWM select"]
9968 #[inline(always)]
9969 pub fn pwm_sel_1(&mut self) -> PwmSel1W<'_, PwmSel1Spec> {
9970 PwmSel1W::new(self, 0)
9971 }
9972 }
9973 #[doc = "PWM group 1 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
9974 pub struct PwmSel1Spec;
9975 impl crate::RegisterSpec for PwmSel1Spec {
9976 type Ux = u32;
9977 }
9978 #[doc = "`read()` method returns [`pwm_sel1::R`](R) reader structure"]
9979 impl crate::Readable for PwmSel1Spec {}
9980 #[doc = "`write(|w| ..)` method takes [`pwm_sel1::W`](W) writer structure"]
9981 impl crate::Writable for PwmSel1Spec {
9982 type Safety = crate::Unsafe;
9983 }
9984 #[doc = "`reset()` method sets PWM_SEL1 to value 0"]
9985 impl crate::Resettable for PwmSel1Spec {}
9986 }
9987 #[doc = "PWM_STARTCLRCNT_EN1 (rw) register accessor: PWM group 1 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en1`] module"]
9988 #[doc(alias = "PWM_STARTCLRCNT_EN1")]
9989 pub type PwmStartclrcntEn1 = crate::Reg<pwm_startclrcnt_en1::PwmStartclrcntEn1Spec>;
9990 #[doc = "PWM group 1 start clear counter enable"]
9991 pub mod pwm_startclrcnt_en1 {
9992 #[doc = "Register `PWM_STARTCLRCNT_EN1` reader"]
9993 pub type R = crate::R<PwmStartclrcntEn1Spec>;
9994 #[doc = "Register `PWM_STARTCLRCNT_EN1` writer"]
9995 pub type W = crate::W<PwmStartclrcntEn1Spec>;
9996 #[doc = "Field `pwm_startclrcnt_en_1` reader - Start clear counter enable for group 1"]
9997 pub type PwmStartclrcntEn1R = crate::BitReader;
9998 #[doc = "Field `pwm_startclrcnt_en_1` writer - Start clear counter enable for group 1"]
9999 pub type PwmStartclrcntEn1W<'a, REG> = crate::BitWriter<'a, REG>;
10000 impl R {
10001 #[doc = "Bit 0 - Start clear counter enable for group 1"]
10002 #[inline(always)]
10003 pub fn pwm_startclrcnt_en_1(&self) -> PwmStartclrcntEn1R {
10004 PwmStartclrcntEn1R::new((self.bits & 1) != 0)
10005 }
10006 }
10007 impl W {
10008 #[doc = "Bit 0 - Start clear counter enable for group 1"]
10009 #[inline(always)]
10010 pub fn pwm_startclrcnt_en_1(
10011 &mut self,
10012 ) -> PwmStartclrcntEn1W<'_, PwmStartclrcntEn1Spec> {
10013 PwmStartclrcntEn1W::new(self, 0)
10014 }
10015 }
10016 #[doc = "PWM group 1 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10017 pub struct PwmStartclrcntEn1Spec;
10018 impl crate::RegisterSpec for PwmStartclrcntEn1Spec {
10019 type Ux = u32;
10020 }
10021 #[doc = "`read()` method returns [`pwm_startclrcnt_en1::R`](R) reader structure"]
10022 impl crate::Readable for PwmStartclrcntEn1Spec {}
10023 #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en1::W`](W) writer structure"]
10024 impl crate::Writable for PwmStartclrcntEn1Spec {
10025 type Safety = crate::Unsafe;
10026 }
10027 #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN1 to value 0"]
10028 impl crate::Resettable for PwmStartclrcntEn1Spec {}
10029 }
10030 #[doc = "PWM_START1 (rw) register accessor: PWM group 1 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start1`] module"]
10031 #[doc(alias = "PWM_START1")]
10032 pub type PwmStart1 = crate::Reg<pwm_start1::PwmStart1Spec>;
10033 #[doc = "PWM group 1 start"]
10034 pub mod pwm_start1 {
10035 #[doc = "Register `PWM_START1` reader"]
10036 pub type R = crate::R<PwmStart1Spec>;
10037 #[doc = "Register `PWM_START1` writer"]
10038 pub type W = crate::W<PwmStart1Spec>;
10039 #[doc = "Field `pwm_start_1` writer - Start group 1 (self-clearing)"]
10040 pub type PwmStart1W<'a, REG> = crate::BitWriter<'a, REG>;
10041 impl W {
10042 #[doc = "Bit 0 - Start group 1 (self-clearing)"]
10043 #[inline(always)]
10044 pub fn pwm_start_1(&mut self) -> PwmStart1W<'_, PwmStart1Spec> {
10045 PwmStart1W::new(self, 0)
10046 }
10047 }
10048 #[doc = "PWM group 1 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10049 pub struct PwmStart1Spec;
10050 impl crate::RegisterSpec for PwmStart1Spec {
10051 type Ux = u32;
10052 }
10053 #[doc = "`read()` method returns [`pwm_start1::R`](R) reader structure"]
10054 impl crate::Readable for PwmStart1Spec {}
10055 #[doc = "`write(|w| ..)` method takes [`pwm_start1::W`](W) writer structure"]
10056 impl crate::Writable for PwmStart1Spec {
10057 type Safety = crate::Unsafe;
10058 }
10059 #[doc = "`reset()` method sets PWM_START1 to value 0"]
10060 impl crate::Resettable for PwmStart1Spec {}
10061 }
10062 #[doc = "PWM_SEL2 (rw) register accessor: PWM group 2 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel2`] module"]
10063 #[doc(alias = "PWM_SEL2")]
10064 pub type PwmSel2 = crate::Reg<pwm_sel2::PwmSel2Spec>;
10065 #[doc = "PWM group 2 select"]
10066 pub mod pwm_sel2 {
10067 #[doc = "Register `PWM_SEL2` reader"]
10068 pub type R = crate::R<PwmSel2Spec>;
10069 #[doc = "Register `PWM_SEL2` writer"]
10070 pub type W = crate::W<PwmSel2Spec>;
10071 #[doc = "Field `pwm_sel_2` reader - Group 2 PWM select"]
10072 pub type PwmSel2R = crate::FieldReader<u16>;
10073 #[doc = "Field `pwm_sel_2` writer - Group 2 PWM select"]
10074 pub type PwmSel2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10075 impl R {
10076 #[doc = "Bits 0:15 - Group 2 PWM select"]
10077 #[inline(always)]
10078 pub fn pwm_sel_2(&self) -> PwmSel2R {
10079 PwmSel2R::new((self.bits & 0xffff) as u16)
10080 }
10081 }
10082 impl W {
10083 #[doc = "Bits 0:15 - Group 2 PWM select"]
10084 #[inline(always)]
10085 pub fn pwm_sel_2(&mut self) -> PwmSel2W<'_, PwmSel2Spec> {
10086 PwmSel2W::new(self, 0)
10087 }
10088 }
10089 #[doc = "PWM group 2 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10090 pub struct PwmSel2Spec;
10091 impl crate::RegisterSpec for PwmSel2Spec {
10092 type Ux = u32;
10093 }
10094 #[doc = "`read()` method returns [`pwm_sel2::R`](R) reader structure"]
10095 impl crate::Readable for PwmSel2Spec {}
10096 #[doc = "`write(|w| ..)` method takes [`pwm_sel2::W`](W) writer structure"]
10097 impl crate::Writable for PwmSel2Spec {
10098 type Safety = crate::Unsafe;
10099 }
10100 #[doc = "`reset()` method sets PWM_SEL2 to value 0"]
10101 impl crate::Resettable for PwmSel2Spec {}
10102 }
10103 #[doc = "PWM_STARTCLRCNT_EN2 (rw) register accessor: PWM group 2 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en2`] module"]
10104 #[doc(alias = "PWM_STARTCLRCNT_EN2")]
10105 pub type PwmStartclrcntEn2 = crate::Reg<pwm_startclrcnt_en2::PwmStartclrcntEn2Spec>;
10106 #[doc = "PWM group 2 start clear counter enable"]
10107 pub mod pwm_startclrcnt_en2 {
10108 #[doc = "Register `PWM_STARTCLRCNT_EN2` reader"]
10109 pub type R = crate::R<PwmStartclrcntEn2Spec>;
10110 #[doc = "Register `PWM_STARTCLRCNT_EN2` writer"]
10111 pub type W = crate::W<PwmStartclrcntEn2Spec>;
10112 #[doc = "Field `pwm_startclrcnt_en_2` reader - Start clear counter enable for group 2"]
10113 pub type PwmStartclrcntEn2R = crate::BitReader;
10114 #[doc = "Field `pwm_startclrcnt_en_2` writer - Start clear counter enable for group 2"]
10115 pub type PwmStartclrcntEn2W<'a, REG> = crate::BitWriter<'a, REG>;
10116 impl R {
10117 #[doc = "Bit 0 - Start clear counter enable for group 2"]
10118 #[inline(always)]
10119 pub fn pwm_startclrcnt_en_2(&self) -> PwmStartclrcntEn2R {
10120 PwmStartclrcntEn2R::new((self.bits & 1) != 0)
10121 }
10122 }
10123 impl W {
10124 #[doc = "Bit 0 - Start clear counter enable for group 2"]
10125 #[inline(always)]
10126 pub fn pwm_startclrcnt_en_2(
10127 &mut self,
10128 ) -> PwmStartclrcntEn2W<'_, PwmStartclrcntEn2Spec> {
10129 PwmStartclrcntEn2W::new(self, 0)
10130 }
10131 }
10132 #[doc = "PWM group 2 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10133 pub struct PwmStartclrcntEn2Spec;
10134 impl crate::RegisterSpec for PwmStartclrcntEn2Spec {
10135 type Ux = u32;
10136 }
10137 #[doc = "`read()` method returns [`pwm_startclrcnt_en2::R`](R) reader structure"]
10138 impl crate::Readable for PwmStartclrcntEn2Spec {}
10139 #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en2::W`](W) writer structure"]
10140 impl crate::Writable for PwmStartclrcntEn2Spec {
10141 type Safety = crate::Unsafe;
10142 }
10143 #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN2 to value 0"]
10144 impl crate::Resettable for PwmStartclrcntEn2Spec {}
10145 }
10146 #[doc = "PWM_START2 (rw) register accessor: PWM group 2 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start2`] module"]
10147 #[doc(alias = "PWM_START2")]
10148 pub type PwmStart2 = crate::Reg<pwm_start2::PwmStart2Spec>;
10149 #[doc = "PWM group 2 start"]
10150 pub mod pwm_start2 {
10151 #[doc = "Register `PWM_START2` reader"]
10152 pub type R = crate::R<PwmStart2Spec>;
10153 #[doc = "Register `PWM_START2` writer"]
10154 pub type W = crate::W<PwmStart2Spec>;
10155 #[doc = "Field `pwm_start_2` writer - Start group 2 (self-clearing)"]
10156 pub type PwmStart2W<'a, REG> = crate::BitWriter<'a, REG>;
10157 impl W {
10158 #[doc = "Bit 0 - Start group 2 (self-clearing)"]
10159 #[inline(always)]
10160 pub fn pwm_start_2(&mut self) -> PwmStart2W<'_, PwmStart2Spec> {
10161 PwmStart2W::new(self, 0)
10162 }
10163 }
10164 #[doc = "PWM group 2 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10165 pub struct PwmStart2Spec;
10166 impl crate::RegisterSpec for PwmStart2Spec {
10167 type Ux = u32;
10168 }
10169 #[doc = "`read()` method returns [`pwm_start2::R`](R) reader structure"]
10170 impl crate::Readable for PwmStart2Spec {}
10171 #[doc = "`write(|w| ..)` method takes [`pwm_start2::W`](W) writer structure"]
10172 impl crate::Writable for PwmStart2Spec {
10173 type Safety = crate::Unsafe;
10174 }
10175 #[doc = "`reset()` method sets PWM_START2 to value 0"]
10176 impl crate::Resettable for PwmStart2Spec {}
10177 }
10178 #[doc = "PWM_SEL3 (rw) register accessor: PWM group 3 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel3`] module"]
10179 #[doc(alias = "PWM_SEL3")]
10180 pub type PwmSel3 = crate::Reg<pwm_sel3::PwmSel3Spec>;
10181 #[doc = "PWM group 3 select"]
10182 pub mod pwm_sel3 {
10183 #[doc = "Register `PWM_SEL3` reader"]
10184 pub type R = crate::R<PwmSel3Spec>;
10185 #[doc = "Register `PWM_SEL3` writer"]
10186 pub type W = crate::W<PwmSel3Spec>;
10187 #[doc = "Field `pwm_sel_3` reader - Group 3 PWM select"]
10188 pub type PwmSel3R = crate::FieldReader<u16>;
10189 #[doc = "Field `pwm_sel_3` writer - Group 3 PWM select"]
10190 pub type PwmSel3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10191 impl R {
10192 #[doc = "Bits 0:15 - Group 3 PWM select"]
10193 #[inline(always)]
10194 pub fn pwm_sel_3(&self) -> PwmSel3R {
10195 PwmSel3R::new((self.bits & 0xffff) as u16)
10196 }
10197 }
10198 impl W {
10199 #[doc = "Bits 0:15 - Group 3 PWM select"]
10200 #[inline(always)]
10201 pub fn pwm_sel_3(&mut self) -> PwmSel3W<'_, PwmSel3Spec> {
10202 PwmSel3W::new(self, 0)
10203 }
10204 }
10205 #[doc = "PWM group 3 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10206 pub struct PwmSel3Spec;
10207 impl crate::RegisterSpec for PwmSel3Spec {
10208 type Ux = u32;
10209 }
10210 #[doc = "`read()` method returns [`pwm_sel3::R`](R) reader structure"]
10211 impl crate::Readable for PwmSel3Spec {}
10212 #[doc = "`write(|w| ..)` method takes [`pwm_sel3::W`](W) writer structure"]
10213 impl crate::Writable for PwmSel3Spec {
10214 type Safety = crate::Unsafe;
10215 }
10216 #[doc = "`reset()` method sets PWM_SEL3 to value 0"]
10217 impl crate::Resettable for PwmSel3Spec {}
10218 }
10219 #[doc = "PWM_STARTCLRCNT_EN3 (rw) register accessor: PWM group 3 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en3`] module"]
10220 #[doc(alias = "PWM_STARTCLRCNT_EN3")]
10221 pub type PwmStartclrcntEn3 = crate::Reg<pwm_startclrcnt_en3::PwmStartclrcntEn3Spec>;
10222 #[doc = "PWM group 3 start clear counter enable"]
10223 pub mod pwm_startclrcnt_en3 {
10224 #[doc = "Register `PWM_STARTCLRCNT_EN3` reader"]
10225 pub type R = crate::R<PwmStartclrcntEn3Spec>;
10226 #[doc = "Register `PWM_STARTCLRCNT_EN3` writer"]
10227 pub type W = crate::W<PwmStartclrcntEn3Spec>;
10228 #[doc = "Field `pwm_startclrcnt_en_3` reader - Start clear counter enable for group 3"]
10229 pub type PwmStartclrcntEn3R = crate::BitReader;
10230 #[doc = "Field `pwm_startclrcnt_en_3` writer - Start clear counter enable for group 3"]
10231 pub type PwmStartclrcntEn3W<'a, REG> = crate::BitWriter<'a, REG>;
10232 impl R {
10233 #[doc = "Bit 0 - Start clear counter enable for group 3"]
10234 #[inline(always)]
10235 pub fn pwm_startclrcnt_en_3(&self) -> PwmStartclrcntEn3R {
10236 PwmStartclrcntEn3R::new((self.bits & 1) != 0)
10237 }
10238 }
10239 impl W {
10240 #[doc = "Bit 0 - Start clear counter enable for group 3"]
10241 #[inline(always)]
10242 pub fn pwm_startclrcnt_en_3(
10243 &mut self,
10244 ) -> PwmStartclrcntEn3W<'_, PwmStartclrcntEn3Spec> {
10245 PwmStartclrcntEn3W::new(self, 0)
10246 }
10247 }
10248 #[doc = "PWM group 3 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10249 pub struct PwmStartclrcntEn3Spec;
10250 impl crate::RegisterSpec for PwmStartclrcntEn3Spec {
10251 type Ux = u32;
10252 }
10253 #[doc = "`read()` method returns [`pwm_startclrcnt_en3::R`](R) reader structure"]
10254 impl crate::Readable for PwmStartclrcntEn3Spec {}
10255 #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en3::W`](W) writer structure"]
10256 impl crate::Writable for PwmStartclrcntEn3Spec {
10257 type Safety = crate::Unsafe;
10258 }
10259 #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN3 to value 0"]
10260 impl crate::Resettable for PwmStartclrcntEn3Spec {}
10261 }
10262 #[doc = "PWM_START3 (rw) register accessor: PWM group 3 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start3`] module"]
10263 #[doc(alias = "PWM_START3")]
10264 pub type PwmStart3 = crate::Reg<pwm_start3::PwmStart3Spec>;
10265 #[doc = "PWM group 3 start"]
10266 pub mod pwm_start3 {
10267 #[doc = "Register `PWM_START3` reader"]
10268 pub type R = crate::R<PwmStart3Spec>;
10269 #[doc = "Register `PWM_START3` writer"]
10270 pub type W = crate::W<PwmStart3Spec>;
10271 #[doc = "Field `pwm_start_3` writer - Start group 3 (self-clearing)"]
10272 pub type PwmStart3W<'a, REG> = crate::BitWriter<'a, REG>;
10273 impl W {
10274 #[doc = "Bit 0 - Start group 3 (self-clearing)"]
10275 #[inline(always)]
10276 pub fn pwm_start_3(&mut self) -> PwmStart3W<'_, PwmStart3Spec> {
10277 PwmStart3W::new(self, 0)
10278 }
10279 }
10280 #[doc = "PWM group 3 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10281 pub struct PwmStart3Spec;
10282 impl crate::RegisterSpec for PwmStart3Spec {
10283 type Ux = u32;
10284 }
10285 #[doc = "`read()` method returns [`pwm_start3::R`](R) reader structure"]
10286 impl crate::Readable for PwmStart3Spec {}
10287 #[doc = "`write(|w| ..)` method takes [`pwm_start3::W`](W) writer structure"]
10288 impl crate::Writable for PwmStart3Spec {
10289 type Safety = crate::Unsafe;
10290 }
10291 #[doc = "`reset()` method sets PWM_START3 to value 0"]
10292 impl crate::Resettable for PwmStart3Spec {}
10293 }
10294 #[doc = "PWM_EN0 (rw) register accessor: PWM0 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en0`] module"]
10295 #[doc(alias = "PWM_EN0")]
10296 pub type PwmEn0 = crate::Reg<pwm_en0::PwmEn0Spec>;
10297 #[doc = "PWM0 enable"]
10298 pub mod pwm_en0 {
10299 #[doc = "Register `PWM_EN0` reader"]
10300 pub type R = crate::R<PwmEn0Spec>;
10301 #[doc = "Register `PWM_EN0` writer"]
10302 pub type W = crate::W<PwmEn0Spec>;
10303 #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
10304 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10305 pub enum PwmEn0 {
10306 #[doc = "0: PWM disabled, output low"]
10307 Off = 0,
10308 #[doc = "1: PWM enabled"]
10309 On = 1,
10310 }
10311 impl From<PwmEn0> for bool {
10312 #[inline(always)]
10313 fn from(variant: PwmEn0) -> Self {
10314 variant as u8 != 0
10315 }
10316 }
10317 #[doc = "Field `pwm_en_0` reader - PWM0 enable: 0=off; 1=on"]
10318 pub type PwmEn0R = crate::BitReader<PwmEn0>;
10319 impl PwmEn0R {
10320 #[doc = "Get enumerated values variant"]
10321 #[inline(always)]
10322 pub const fn variant(&self) -> PwmEn0 {
10323 match self.bits {
10324 false => PwmEn0::Off,
10325 true => PwmEn0::On,
10326 }
10327 }
10328 #[doc = "PWM disabled, output low"]
10329 #[inline(always)]
10330 pub fn is_off(&self) -> bool {
10331 *self == PwmEn0::Off
10332 }
10333 #[doc = "PWM enabled"]
10334 #[inline(always)]
10335 pub fn is_on(&self) -> bool {
10336 *self == PwmEn0::On
10337 }
10338 }
10339 #[doc = "Field `pwm_en_0` writer - PWM0 enable: 0=off; 1=on"]
10340 pub type PwmEn0W<'a, REG> = crate::BitWriter<'a, REG, PwmEn0>;
10341 impl<'a, REG> PwmEn0W<'a, REG>
10342 where
10343 REG: crate::Writable + crate::RegisterSpec,
10344 {
10345 #[doc = "PWM disabled, output low"]
10346 #[inline(always)]
10347 pub fn off(self) -> &'a mut crate::W<REG> {
10348 self.variant(PwmEn0::Off)
10349 }
10350 #[doc = "PWM enabled"]
10351 #[inline(always)]
10352 pub fn on(self) -> &'a mut crate::W<REG> {
10353 self.variant(PwmEn0::On)
10354 }
10355 }
10356 impl R {
10357 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
10358 #[inline(always)]
10359 pub fn pwm_en_0(&self) -> PwmEn0R {
10360 PwmEn0R::new((self.bits & 1) != 0)
10361 }
10362 }
10363 impl W {
10364 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
10365 #[inline(always)]
10366 pub fn pwm_en_0(&mut self) -> PwmEn0W<'_, PwmEn0Spec> {
10367 PwmEn0W::new(self, 0)
10368 }
10369 }
10370 #[doc = "PWM0 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10371 pub struct PwmEn0Spec;
10372 impl crate::RegisterSpec for PwmEn0Spec {
10373 type Ux = u32;
10374 }
10375 #[doc = "`read()` method returns [`pwm_en0::R`](R) reader structure"]
10376 impl crate::Readable for PwmEn0Spec {}
10377 #[doc = "`write(|w| ..)` method takes [`pwm_en0::W`](W) writer structure"]
10378 impl crate::Writable for PwmEn0Spec {
10379 type Safety = crate::Unsafe;
10380 }
10381 #[doc = "`reset()` method sets PWM_EN0 to value 0"]
10382 impl crate::Resettable for PwmEn0Spec {}
10383 }
10384 #[doc = "PWM_PORTITY0 (rw) register accessor: PWM0 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity0`] module"]
10385 #[doc(alias = "PWM_PORTITY0")]
10386 pub type PwmPortity0 = crate::Reg<pwm_portity0::PwmPortity0Spec>;
10387 #[doc = "PWM0 polarity"]
10388 pub mod pwm_portity0 {
10389 #[doc = "Register `PWM_PORTITY0` reader"]
10390 pub type R = crate::R<PwmPortity0Spec>;
10391 #[doc = "Register `PWM_PORTITY0` writer"]
10392 pub type W = crate::W<PwmPortity0Spec>;
10393 #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
10394 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
10395 pub enum PwmPoarity0 {
10396 #[doc = "0: Normal polarity"]
10397 Normal = 0,
10398 #[doc = "1: Inverted polarity"]
10399 Inverted = 1,
10400 }
10401 impl From<PwmPoarity0> for bool {
10402 #[inline(always)]
10403 fn from(variant: PwmPoarity0) -> Self {
10404 variant as u8 != 0
10405 }
10406 }
10407 #[doc = "Field `pwm_poarity_0` reader - PWM0 polarity: 0=normal; 1=inverted"]
10408 pub type PwmPoarity0R = crate::BitReader<PwmPoarity0>;
10409 impl PwmPoarity0R {
10410 #[doc = "Get enumerated values variant"]
10411 #[inline(always)]
10412 pub const fn variant(&self) -> PwmPoarity0 {
10413 match self.bits {
10414 false => PwmPoarity0::Normal,
10415 true => PwmPoarity0::Inverted,
10416 }
10417 }
10418 #[doc = "Normal polarity"]
10419 #[inline(always)]
10420 pub fn is_normal(&self) -> bool {
10421 *self == PwmPoarity0::Normal
10422 }
10423 #[doc = "Inverted polarity"]
10424 #[inline(always)]
10425 pub fn is_inverted(&self) -> bool {
10426 *self == PwmPoarity0::Inverted
10427 }
10428 }
10429 #[doc = "Field `pwm_poarity_0` writer - PWM0 polarity: 0=normal; 1=inverted"]
10430 pub type PwmPoarity0W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity0>;
10431 impl<'a, REG> PwmPoarity0W<'a, REG>
10432 where
10433 REG: crate::Writable + crate::RegisterSpec,
10434 {
10435 #[doc = "Normal polarity"]
10436 #[inline(always)]
10437 pub fn normal(self) -> &'a mut crate::W<REG> {
10438 self.variant(PwmPoarity0::Normal)
10439 }
10440 #[doc = "Inverted polarity"]
10441 #[inline(always)]
10442 pub fn inverted(self) -> &'a mut crate::W<REG> {
10443 self.variant(PwmPoarity0::Inverted)
10444 }
10445 }
10446 impl R {
10447 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
10448 #[inline(always)]
10449 pub fn pwm_poarity_0(&self) -> PwmPoarity0R {
10450 PwmPoarity0R::new((self.bits & 1) != 0)
10451 }
10452 }
10453 impl W {
10454 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
10455 #[inline(always)]
10456 pub fn pwm_poarity_0(&mut self) -> PwmPoarity0W<'_, PwmPortity0Spec> {
10457 PwmPoarity0W::new(self, 0)
10458 }
10459 }
10460 #[doc = "PWM0 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10461 pub struct PwmPortity0Spec;
10462 impl crate::RegisterSpec for PwmPortity0Spec {
10463 type Ux = u32;
10464 }
10465 #[doc = "`read()` method returns [`pwm_portity0::R`](R) reader structure"]
10466 impl crate::Readable for PwmPortity0Spec {}
10467 #[doc = "`write(|w| ..)` method takes [`pwm_portity0::W`](W) writer structure"]
10468 impl crate::Writable for PwmPortity0Spec {
10469 type Safety = crate::Unsafe;
10470 }
10471 #[doc = "`reset()` method sets PWM_PORTITY0 to value 0"]
10472 impl crate::Resettable for PwmPortity0Spec {}
10473 }
10474 #[doc = "PWM_OEN_CFG0 (rw) register accessor: PWM0 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg0`] module"]
10475 #[doc(alias = "PWM_OEN_CFG0")]
10476 pub type PwmOenCfg0 = crate::Reg<pwm_oen_cfg0::PwmOenCfg0Spec>;
10477 #[doc = "PWM0 high-impedance config"]
10478 pub mod pwm_oen_cfg0 {
10479 #[doc = "Register `PWM_OEN_CFG0` reader"]
10480 pub type R = crate::R<PwmOenCfg0Spec>;
10481 #[doc = "Register `PWM_OEN_CFG0` writer"]
10482 pub type W = crate::W<PwmOenCfg0Spec>;
10483 #[doc = "Field `pwm_oen_cfg_0` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
10484 pub type PwmOenCfg0R = crate::BitReader;
10485 #[doc = "Field `pwm_oen_cfg_0` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
10486 pub type PwmOenCfg0W<'a, REG> = crate::BitWriter<'a, REG>;
10487 impl R {
10488 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
10489 #[inline(always)]
10490 pub fn pwm_oen_cfg_0(&self) -> PwmOenCfg0R {
10491 PwmOenCfg0R::new((self.bits & 1) != 0)
10492 }
10493 }
10494 impl W {
10495 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
10496 #[inline(always)]
10497 pub fn pwm_oen_cfg_0(&mut self) -> PwmOenCfg0W<'_, PwmOenCfg0Spec> {
10498 PwmOenCfg0W::new(self, 0)
10499 }
10500 }
10501 #[doc = "PWM0 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10502 pub struct PwmOenCfg0Spec;
10503 impl crate::RegisterSpec for PwmOenCfg0Spec {
10504 type Ux = u32;
10505 }
10506 #[doc = "`read()` method returns [`pwm_oen_cfg0::R`](R) reader structure"]
10507 impl crate::Readable for PwmOenCfg0Spec {}
10508 #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg0::W`](W) writer structure"]
10509 impl crate::Writable for PwmOenCfg0Spec {
10510 type Safety = crate::Unsafe;
10511 }
10512 #[doc = "`reset()` method sets PWM_OEN_CFG0 to value 0"]
10513 impl crate::Resettable for PwmOenCfg0Spec {}
10514 }
10515 #[doc = "PWM_OFFSET_L0 (rw) register accessor: PWM0 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l0`] module"]
10516 #[doc(alias = "PWM_OFFSET_L0")]
10517 pub type PwmOffsetL0 = crate::Reg<pwm_offset_l0::PwmOffsetL0Spec>;
10518 #[doc = "PWM0 phase offset low 16 bits"]
10519 pub mod pwm_offset_l0 {
10520 #[doc = "Register `PWM_OFFSET_L0` reader"]
10521 pub type R = crate::R<PwmOffsetL0Spec>;
10522 #[doc = "Register `PWM_OFFSET_L0` writer"]
10523 pub type W = crate::W<PwmOffsetL0Spec>;
10524 #[doc = "Field `pwm_offset_l_0` reader - PWM0 phase offset low 16 bits"]
10525 pub type PwmOffsetL0R = crate::FieldReader<u16>;
10526 #[doc = "Field `pwm_offset_l_0` writer - PWM0 phase offset low 16 bits"]
10527 pub type PwmOffsetL0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10528 impl R {
10529 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
10530 #[inline(always)]
10531 pub fn pwm_offset_l_0(&self) -> PwmOffsetL0R {
10532 PwmOffsetL0R::new((self.bits & 0xffff) as u16)
10533 }
10534 }
10535 impl W {
10536 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
10537 #[inline(always)]
10538 pub fn pwm_offset_l_0(&mut self) -> PwmOffsetL0W<'_, PwmOffsetL0Spec> {
10539 PwmOffsetL0W::new(self, 0)
10540 }
10541 }
10542 #[doc = "PWM0 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10543 pub struct PwmOffsetL0Spec;
10544 impl crate::RegisterSpec for PwmOffsetL0Spec {
10545 type Ux = u32;
10546 }
10547 #[doc = "`read()` method returns [`pwm_offset_l0::R`](R) reader structure"]
10548 impl crate::Readable for PwmOffsetL0Spec {}
10549 #[doc = "`write(|w| ..)` method takes [`pwm_offset_l0::W`](W) writer structure"]
10550 impl crate::Writable for PwmOffsetL0Spec {
10551 type Safety = crate::Unsafe;
10552 }
10553 #[doc = "`reset()` method sets PWM_OFFSET_L0 to value 0"]
10554 impl crate::Resettable for PwmOffsetL0Spec {}
10555 }
10556 #[doc = "PWM_OFFSET_H0 (rw) register accessor: PWM0 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h0`] module"]
10557 #[doc(alias = "PWM_OFFSET_H0")]
10558 pub type PwmOffsetH0 = crate::Reg<pwm_offset_h0::PwmOffsetH0Spec>;
10559 #[doc = "PWM0 phase offset high 16 bits"]
10560 pub mod pwm_offset_h0 {
10561 #[doc = "Register `PWM_OFFSET_H0` reader"]
10562 pub type R = crate::R<PwmOffsetH0Spec>;
10563 #[doc = "Register `PWM_OFFSET_H0` writer"]
10564 pub type W = crate::W<PwmOffsetH0Spec>;
10565 #[doc = "Field `pwm_offset_h_0` reader - PWM0 phase offset high 16 bits"]
10566 pub type PwmOffsetH0R = crate::FieldReader<u16>;
10567 #[doc = "Field `pwm_offset_h_0` writer - PWM0 phase offset high 16 bits"]
10568 pub type PwmOffsetH0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10569 impl R {
10570 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
10571 #[inline(always)]
10572 pub fn pwm_offset_h_0(&self) -> PwmOffsetH0R {
10573 PwmOffsetH0R::new((self.bits & 0xffff) as u16)
10574 }
10575 }
10576 impl W {
10577 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
10578 #[inline(always)]
10579 pub fn pwm_offset_h_0(&mut self) -> PwmOffsetH0W<'_, PwmOffsetH0Spec> {
10580 PwmOffsetH0W::new(self, 0)
10581 }
10582 }
10583 #[doc = "PWM0 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10584 pub struct PwmOffsetH0Spec;
10585 impl crate::RegisterSpec for PwmOffsetH0Spec {
10586 type Ux = u32;
10587 }
10588 #[doc = "`read()` method returns [`pwm_offset_h0::R`](R) reader structure"]
10589 impl crate::Readable for PwmOffsetH0Spec {}
10590 #[doc = "`write(|w| ..)` method takes [`pwm_offset_h0::W`](W) writer structure"]
10591 impl crate::Writable for PwmOffsetH0Spec {
10592 type Safety = crate::Unsafe;
10593 }
10594 #[doc = "`reset()` method sets PWM_OFFSET_H0 to value 0"]
10595 impl crate::Resettable for PwmOffsetH0Spec {}
10596 }
10597 #[doc = "PWM_FREQ_L0 (rw) register accessor: PWM0 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l0`] module"]
10598 #[doc(alias = "PWM_FREQ_L0")]
10599 pub type PwmFreqL0 = crate::Reg<pwm_freq_l0::PwmFreqL0Spec>;
10600 #[doc = "PWM0 frequency low 16 bits"]
10601 pub mod pwm_freq_l0 {
10602 #[doc = "Register `PWM_FREQ_L0` reader"]
10603 pub type R = crate::R<PwmFreqL0Spec>;
10604 #[doc = "Register `PWM_FREQ_L0` writer"]
10605 pub type W = crate::W<PwmFreqL0Spec>;
10606 #[doc = "Field `pwm_freq_l_0` reader - PWM0 clock divider low 16 bits"]
10607 pub type PwmFreqL0R = crate::FieldReader<u16>;
10608 #[doc = "Field `pwm_freq_l_0` writer - PWM0 clock divider low 16 bits"]
10609 pub type PwmFreqL0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10610 impl R {
10611 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
10612 #[inline(always)]
10613 pub fn pwm_freq_l_0(&self) -> PwmFreqL0R {
10614 PwmFreqL0R::new((self.bits & 0xffff) as u16)
10615 }
10616 }
10617 impl W {
10618 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
10619 #[inline(always)]
10620 pub fn pwm_freq_l_0(&mut self) -> PwmFreqL0W<'_, PwmFreqL0Spec> {
10621 PwmFreqL0W::new(self, 0)
10622 }
10623 }
10624 #[doc = "PWM0 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10625 pub struct PwmFreqL0Spec;
10626 impl crate::RegisterSpec for PwmFreqL0Spec {
10627 type Ux = u32;
10628 }
10629 #[doc = "`read()` method returns [`pwm_freq_l0::R`](R) reader structure"]
10630 impl crate::Readable for PwmFreqL0Spec {}
10631 #[doc = "`write(|w| ..)` method takes [`pwm_freq_l0::W`](W) writer structure"]
10632 impl crate::Writable for PwmFreqL0Spec {
10633 type Safety = crate::Unsafe;
10634 }
10635 #[doc = "`reset()` method sets PWM_FREQ_L0 to value 0"]
10636 impl crate::Resettable for PwmFreqL0Spec {}
10637 }
10638 #[doc = "PWM_FREQ_H0 (rw) register accessor: PWM0 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h0`] module"]
10639 #[doc(alias = "PWM_FREQ_H0")]
10640 pub type PwmFreqH0 = crate::Reg<pwm_freq_h0::PwmFreqH0Spec>;
10641 #[doc = "PWM0 frequency high 16 bits"]
10642 pub mod pwm_freq_h0 {
10643 #[doc = "Register `PWM_FREQ_H0` reader"]
10644 pub type R = crate::R<PwmFreqH0Spec>;
10645 #[doc = "Register `PWM_FREQ_H0` writer"]
10646 pub type W = crate::W<PwmFreqH0Spec>;
10647 #[doc = "Field `pwm_freq_h_0` reader - PWM0 clock divider high 16 bits"]
10648 pub type PwmFreqH0R = crate::FieldReader<u16>;
10649 #[doc = "Field `pwm_freq_h_0` writer - PWM0 clock divider high 16 bits"]
10650 pub type PwmFreqH0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10651 impl R {
10652 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
10653 #[inline(always)]
10654 pub fn pwm_freq_h_0(&self) -> PwmFreqH0R {
10655 PwmFreqH0R::new((self.bits & 0xffff) as u16)
10656 }
10657 }
10658 impl W {
10659 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
10660 #[inline(always)]
10661 pub fn pwm_freq_h_0(&mut self) -> PwmFreqH0W<'_, PwmFreqH0Spec> {
10662 PwmFreqH0W::new(self, 0)
10663 }
10664 }
10665 #[doc = "PWM0 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10666 pub struct PwmFreqH0Spec;
10667 impl crate::RegisterSpec for PwmFreqH0Spec {
10668 type Ux = u32;
10669 }
10670 #[doc = "`read()` method returns [`pwm_freq_h0::R`](R) reader structure"]
10671 impl crate::Readable for PwmFreqH0Spec {}
10672 #[doc = "`write(|w| ..)` method takes [`pwm_freq_h0::W`](W) writer structure"]
10673 impl crate::Writable for PwmFreqH0Spec {
10674 type Safety = crate::Unsafe;
10675 }
10676 #[doc = "`reset()` method sets PWM_FREQ_H0 to value 0"]
10677 impl crate::Resettable for PwmFreqH0Spec {}
10678 }
10679 #[doc = "PWM_DUTY_L0 (rw) register accessor: PWM0 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l0`] module"]
10680 #[doc(alias = "PWM_DUTY_L0")]
10681 pub type PwmDutyL0 = crate::Reg<pwm_duty_l0::PwmDutyL0Spec>;
10682 #[doc = "PWM0 duty cycle low 16 bits"]
10683 pub mod pwm_duty_l0 {
10684 #[doc = "Register `PWM_DUTY_L0` reader"]
10685 pub type R = crate::R<PwmDutyL0Spec>;
10686 #[doc = "Register `PWM_DUTY_L0` writer"]
10687 pub type W = crate::W<PwmDutyL0Spec>;
10688 #[doc = "Field `pwm_duty_l_0` reader - PWM0 duty cycle low 16 bits"]
10689 pub type PwmDutyL0R = crate::FieldReader<u16>;
10690 #[doc = "Field `pwm_duty_l_0` writer - PWM0 duty cycle low 16 bits"]
10691 pub type PwmDutyL0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10692 impl R {
10693 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
10694 #[inline(always)]
10695 pub fn pwm_duty_l_0(&self) -> PwmDutyL0R {
10696 PwmDutyL0R::new((self.bits & 0xffff) as u16)
10697 }
10698 }
10699 impl W {
10700 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
10701 #[inline(always)]
10702 pub fn pwm_duty_l_0(&mut self) -> PwmDutyL0W<'_, PwmDutyL0Spec> {
10703 PwmDutyL0W::new(self, 0)
10704 }
10705 }
10706 #[doc = "PWM0 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10707 pub struct PwmDutyL0Spec;
10708 impl crate::RegisterSpec for PwmDutyL0Spec {
10709 type Ux = u32;
10710 }
10711 #[doc = "`read()` method returns [`pwm_duty_l0::R`](R) reader structure"]
10712 impl crate::Readable for PwmDutyL0Spec {}
10713 #[doc = "`write(|w| ..)` method takes [`pwm_duty_l0::W`](W) writer structure"]
10714 impl crate::Writable for PwmDutyL0Spec {
10715 type Safety = crate::Unsafe;
10716 }
10717 #[doc = "`reset()` method sets PWM_DUTY_L0 to value 0"]
10718 impl crate::Resettable for PwmDutyL0Spec {}
10719 }
10720 #[doc = "PWM_DUTY_H0 (rw) register accessor: PWM0 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h0`] module"]
10721 #[doc(alias = "PWM_DUTY_H0")]
10722 pub type PwmDutyH0 = crate::Reg<pwm_duty_h0::PwmDutyH0Spec>;
10723 #[doc = "PWM0 duty cycle high 16 bits"]
10724 pub mod pwm_duty_h0 {
10725 #[doc = "Register `PWM_DUTY_H0` reader"]
10726 pub type R = crate::R<PwmDutyH0Spec>;
10727 #[doc = "Register `PWM_DUTY_H0` writer"]
10728 pub type W = crate::W<PwmDutyH0Spec>;
10729 #[doc = "Field `pwm_duty_h_0` reader - PWM0 duty cycle high 16 bits"]
10730 pub type PwmDutyH0R = crate::FieldReader<u16>;
10731 #[doc = "Field `pwm_duty_h_0` writer - PWM0 duty cycle high 16 bits"]
10732 pub type PwmDutyH0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10733 impl R {
10734 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
10735 #[inline(always)]
10736 pub fn pwm_duty_h_0(&self) -> PwmDutyH0R {
10737 PwmDutyH0R::new((self.bits & 0xffff) as u16)
10738 }
10739 }
10740 impl W {
10741 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
10742 #[inline(always)]
10743 pub fn pwm_duty_h_0(&mut self) -> PwmDutyH0W<'_, PwmDutyH0Spec> {
10744 PwmDutyH0W::new(self, 0)
10745 }
10746 }
10747 #[doc = "PWM0 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10748 pub struct PwmDutyH0Spec;
10749 impl crate::RegisterSpec for PwmDutyH0Spec {
10750 type Ux = u32;
10751 }
10752 #[doc = "`read()` method returns [`pwm_duty_h0::R`](R) reader structure"]
10753 impl crate::Readable for PwmDutyH0Spec {}
10754 #[doc = "`write(|w| ..)` method takes [`pwm_duty_h0::W`](W) writer structure"]
10755 impl crate::Writable for PwmDutyH0Spec {
10756 type Safety = crate::Unsafe;
10757 }
10758 #[doc = "`reset()` method sets PWM_DUTY_H0 to value 0"]
10759 impl crate::Resettable for PwmDutyH0Spec {}
10760 }
10761 #[doc = "PWM_PERIODLOAD_FLAG0 (rw) register accessor: PWM0 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag0`] module"]
10762 #[doc(alias = "PWM_PERIODLOAD_FLAG0")]
10763 pub type PwmPeriodloadFlag0 = crate::Reg<pwm_periodload_flag0::PwmPeriodloadFlag0Spec>;
10764 #[doc = "PWM0 period load flag"]
10765 pub mod pwm_periodload_flag0 {
10766 #[doc = "Register `PWM_PERIODLOAD_FLAG0` reader"]
10767 pub type R = crate::R<PwmPeriodloadFlag0Spec>;
10768 #[doc = "Register `PWM_PERIODLOAD_FLAG0` writer"]
10769 pub type W = crate::W<PwmPeriodloadFlag0Spec>;
10770 #[doc = "Field `pwm_periodload_flag_0` reader - Period load complete flag"]
10771 pub type PwmPeriodloadFlag0R = crate::BitReader;
10772 impl R {
10773 #[doc = "Bit 0 - Period load complete flag"]
10774 #[inline(always)]
10775 pub fn pwm_periodload_flag_0(&self) -> PwmPeriodloadFlag0R {
10776 PwmPeriodloadFlag0R::new((self.bits & 1) != 0)
10777 }
10778 }
10779 impl W {}
10780 #[doc = "PWM0 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10781 pub struct PwmPeriodloadFlag0Spec;
10782 impl crate::RegisterSpec for PwmPeriodloadFlag0Spec {
10783 type Ux = u32;
10784 }
10785 #[doc = "`read()` method returns [`pwm_periodload_flag0::R`](R) reader structure"]
10786 impl crate::Readable for PwmPeriodloadFlag0Spec {}
10787 #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag0::W`](W) writer structure"]
10788 impl crate::Writable for PwmPeriodloadFlag0Spec {
10789 type Safety = crate::Unsafe;
10790 }
10791 #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG0 to value 0"]
10792 impl crate::Resettable for PwmPeriodloadFlag0Spec {}
10793 }
10794 #[doc = "PWM_PERIOD_VAL0 (rw) register accessor: PWM0 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val0`] module"]
10795 #[doc(alias = "PWM_PERIOD_VAL0")]
10796 pub type PwmPeriodVal0 = crate::Reg<pwm_period_val0::PwmPeriodVal0Spec>;
10797 #[doc = "PWM0 pulse count value"]
10798 pub mod pwm_period_val0 {
10799 #[doc = "Register `PWM_PERIOD_VAL0` reader"]
10800 pub type R = crate::R<PwmPeriodVal0Spec>;
10801 #[doc = "Register `PWM_PERIOD_VAL0` writer"]
10802 pub type W = crate::W<PwmPeriodVal0Spec>;
10803 #[doc = "Field `pwm_period_val_0` reader - Pulse count for stepping mode"]
10804 pub type PwmPeriodVal0R = crate::FieldReader<u16>;
10805 #[doc = "Field `pwm_period_val_0` writer - Pulse count for stepping mode"]
10806 pub type PwmPeriodVal0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
10807 impl R {
10808 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
10809 #[inline(always)]
10810 pub fn pwm_period_val_0(&self) -> PwmPeriodVal0R {
10811 PwmPeriodVal0R::new((self.bits & 0xffff) as u16)
10812 }
10813 }
10814 impl W {
10815 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
10816 #[inline(always)]
10817 pub fn pwm_period_val_0(&mut self) -> PwmPeriodVal0W<'_, PwmPeriodVal0Spec> {
10818 PwmPeriodVal0W::new(self, 0)
10819 }
10820 }
10821 #[doc = "PWM0 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10822 pub struct PwmPeriodVal0Spec;
10823 impl crate::RegisterSpec for PwmPeriodVal0Spec {
10824 type Ux = u32;
10825 }
10826 #[doc = "`read()` method returns [`pwm_period_val0::R`](R) reader structure"]
10827 impl crate::Readable for PwmPeriodVal0Spec {}
10828 #[doc = "`write(|w| ..)` method takes [`pwm_period_val0::W`](W) writer structure"]
10829 impl crate::Writable for PwmPeriodVal0Spec {
10830 type Safety = crate::Unsafe;
10831 }
10832 #[doc = "`reset()` method sets PWM_PERIOD_VAL0 to value 0"]
10833 impl crate::Resettable for PwmPeriodVal0Spec {}
10834 }
10835 #[doc = "PWM_PERIODCNT0 (rw) register accessor: PWM0 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt0`] module"]
10836 #[doc(alias = "PWM_PERIODCNT0")]
10837 pub type PwmPeriodcnt0 = crate::Reg<pwm_periodcnt0::PwmPeriodcnt0Spec>;
10838 #[doc = "PWM0 pulse count current value"]
10839 pub mod pwm_periodcnt0 {
10840 #[doc = "Register `PWM_PERIODCNT0` reader"]
10841 pub type R = crate::R<PwmPeriodcnt0Spec>;
10842 #[doc = "Register `PWM_PERIODCNT0` writer"]
10843 pub type W = crate::W<PwmPeriodcnt0Spec>;
10844 #[doc = "Field `pwm_periodcnt_0` reader - Current pulse count"]
10845 pub type PwmPeriodcnt0R = crate::FieldReader<u16>;
10846 impl R {
10847 #[doc = "Bits 0:15 - Current pulse count"]
10848 #[inline(always)]
10849 pub fn pwm_periodcnt_0(&self) -> PwmPeriodcnt0R {
10850 PwmPeriodcnt0R::new((self.bits & 0xffff) as u16)
10851 }
10852 }
10853 impl W {}
10854 #[doc = "PWM0 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10855 pub struct PwmPeriodcnt0Spec;
10856 impl crate::RegisterSpec for PwmPeriodcnt0Spec {
10857 type Ux = u32;
10858 }
10859 #[doc = "`read()` method returns [`pwm_periodcnt0::R`](R) reader structure"]
10860 impl crate::Readable for PwmPeriodcnt0Spec {}
10861 #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt0::W`](W) writer structure"]
10862 impl crate::Writable for PwmPeriodcnt0Spec {
10863 type Safety = crate::Unsafe;
10864 }
10865 #[doc = "`reset()` method sets PWM_PERIODCNT0 to value 0"]
10866 impl crate::Resettable for PwmPeriodcnt0Spec {}
10867 }
10868 #[doc = "PWM_EN1 (rw) register accessor: PWM1 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en1`] module"]
10869 #[doc(alias = "PWM_EN1")]
10870 pub type PwmEn1 = crate::Reg<pwm_en1::PwmEn1Spec>;
10871 #[doc = "PWM1 enable"]
10872 pub mod pwm_en1 {
10873 #[doc = "Register `PWM_EN1` reader"]
10874 pub type R = crate::R<PwmEn1Spec>;
10875 #[doc = "Register `PWM_EN1` writer"]
10876 pub type W = crate::W<PwmEn1Spec>;
10877 #[doc = "Field `pwm_en_1` reader - PWM1 enable"]
10878 pub type PwmEn1R = crate::BitReader;
10879 #[doc = "Field `pwm_en_1` writer - PWM1 enable"]
10880 pub type PwmEn1W<'a, REG> = crate::BitWriter<'a, REG>;
10881 impl R {
10882 #[doc = "Bit 0 - PWM1 enable"]
10883 #[inline(always)]
10884 pub fn pwm_en_1(&self) -> PwmEn1R {
10885 PwmEn1R::new((self.bits & 1) != 0)
10886 }
10887 }
10888 impl W {
10889 #[doc = "Bit 0 - PWM1 enable"]
10890 #[inline(always)]
10891 pub fn pwm_en_1(&mut self) -> PwmEn1W<'_, PwmEn1Spec> {
10892 PwmEn1W::new(self, 0)
10893 }
10894 }
10895 #[doc = "PWM1 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10896 pub struct PwmEn1Spec;
10897 impl crate::RegisterSpec for PwmEn1Spec {
10898 type Ux = u32;
10899 }
10900 #[doc = "`read()` method returns [`pwm_en1::R`](R) reader structure"]
10901 impl crate::Readable for PwmEn1Spec {}
10902 #[doc = "`write(|w| ..)` method takes [`pwm_en1::W`](W) writer structure"]
10903 impl crate::Writable for PwmEn1Spec {
10904 type Safety = crate::Unsafe;
10905 }
10906 #[doc = "`reset()` method sets PWM_EN1 to value 0"]
10907 impl crate::Resettable for PwmEn1Spec {}
10908 }
10909 #[doc = "PWM_PORTITY1 (rw) register accessor: PWM1 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity1`] module"]
10910 #[doc(alias = "PWM_PORTITY1")]
10911 pub type PwmPortity1 = crate::Reg<pwm_portity1::PwmPortity1Spec>;
10912 #[doc = "PWM1 polarity"]
10913 pub mod pwm_portity1 {
10914 #[doc = "Register `PWM_PORTITY1` reader"]
10915 pub type R = crate::R<PwmPortity1Spec>;
10916 #[doc = "Register `PWM_PORTITY1` writer"]
10917 pub type W = crate::W<PwmPortity1Spec>;
10918 #[doc = "Field `pwm_poarity_1` reader - PWM1 polarity"]
10919 pub type PwmPoarity1R = crate::BitReader;
10920 #[doc = "Field `pwm_poarity_1` writer - PWM1 polarity"]
10921 pub type PwmPoarity1W<'a, REG> = crate::BitWriter<'a, REG>;
10922 impl R {
10923 #[doc = "Bit 0 - PWM1 polarity"]
10924 #[inline(always)]
10925 pub fn pwm_poarity_1(&self) -> PwmPoarity1R {
10926 PwmPoarity1R::new((self.bits & 1) != 0)
10927 }
10928 }
10929 impl W {
10930 #[doc = "Bit 0 - PWM1 polarity"]
10931 #[inline(always)]
10932 pub fn pwm_poarity_1(&mut self) -> PwmPoarity1W<'_, PwmPortity1Spec> {
10933 PwmPoarity1W::new(self, 0)
10934 }
10935 }
10936 #[doc = "PWM1 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10937 pub struct PwmPortity1Spec;
10938 impl crate::RegisterSpec for PwmPortity1Spec {
10939 type Ux = u32;
10940 }
10941 #[doc = "`read()` method returns [`pwm_portity1::R`](R) reader structure"]
10942 impl crate::Readable for PwmPortity1Spec {}
10943 #[doc = "`write(|w| ..)` method takes [`pwm_portity1::W`](W) writer structure"]
10944 impl crate::Writable for PwmPortity1Spec {
10945 type Safety = crate::Unsafe;
10946 }
10947 #[doc = "`reset()` method sets PWM_PORTITY1 to value 0"]
10948 impl crate::Resettable for PwmPortity1Spec {}
10949 }
10950 #[doc = "PWM_OEN_CFG1 (rw) register accessor: PWM1 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg1`] module"]
10951 #[doc(alias = "PWM_OEN_CFG1")]
10952 pub type PwmOenCfg1 = crate::Reg<pwm_oen_cfg1::PwmOenCfg1Spec>;
10953 #[doc = "PWM1 high-impedance config"]
10954 pub mod pwm_oen_cfg1 {
10955 #[doc = "Register `PWM_OEN_CFG1` reader"]
10956 pub type R = crate::R<PwmOenCfg1Spec>;
10957 #[doc = "Register `PWM_OEN_CFG1` writer"]
10958 pub type W = crate::W<PwmOenCfg1Spec>;
10959 #[doc = "Field `pwm_oen_cfg_1` reader - PWM1 high-Z enable"]
10960 pub type PwmOenCfg1R = crate::BitReader;
10961 #[doc = "Field `pwm_oen_cfg_1` writer - PWM1 high-Z enable"]
10962 pub type PwmOenCfg1W<'a, REG> = crate::BitWriter<'a, REG>;
10963 impl R {
10964 #[doc = "Bit 0 - PWM1 high-Z enable"]
10965 #[inline(always)]
10966 pub fn pwm_oen_cfg_1(&self) -> PwmOenCfg1R {
10967 PwmOenCfg1R::new((self.bits & 1) != 0)
10968 }
10969 }
10970 impl W {
10971 #[doc = "Bit 0 - PWM1 high-Z enable"]
10972 #[inline(always)]
10973 pub fn pwm_oen_cfg_1(&mut self) -> PwmOenCfg1W<'_, PwmOenCfg1Spec> {
10974 PwmOenCfg1W::new(self, 0)
10975 }
10976 }
10977 #[doc = "PWM1 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
10978 pub struct PwmOenCfg1Spec;
10979 impl crate::RegisterSpec for PwmOenCfg1Spec {
10980 type Ux = u32;
10981 }
10982 #[doc = "`read()` method returns [`pwm_oen_cfg1::R`](R) reader structure"]
10983 impl crate::Readable for PwmOenCfg1Spec {}
10984 #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg1::W`](W) writer structure"]
10985 impl crate::Writable for PwmOenCfg1Spec {
10986 type Safety = crate::Unsafe;
10987 }
10988 #[doc = "`reset()` method sets PWM_OEN_CFG1 to value 0"]
10989 impl crate::Resettable for PwmOenCfg1Spec {}
10990 }
10991 #[doc = "PWM_OFFSET_L1 (rw) register accessor: PWM1 phase offset low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l1`] module"]
10992 #[doc(alias = "PWM_OFFSET_L1")]
10993 pub type PwmOffsetL1 = crate::Reg<pwm_offset_l1::PwmOffsetL1Spec>;
10994 #[doc = "PWM1 phase offset low"]
10995 pub mod pwm_offset_l1 {
10996 #[doc = "Register `PWM_OFFSET_L1` reader"]
10997 pub type R = crate::R<PwmOffsetL1Spec>;
10998 #[doc = "Register `PWM_OFFSET_L1` writer"]
10999 pub type W = crate::W<PwmOffsetL1Spec>;
11000 #[doc = "Field `pwm_offset_l_1` reader - PWM1 phase offset low 16 bits"]
11001 pub type PwmOffsetL1R = crate::FieldReader<u16>;
11002 #[doc = "Field `pwm_offset_l_1` writer - PWM1 phase offset low 16 bits"]
11003 pub type PwmOffsetL1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11004 impl R {
11005 #[doc = "Bits 0:15 - PWM1 phase offset low 16 bits"]
11006 #[inline(always)]
11007 pub fn pwm_offset_l_1(&self) -> PwmOffsetL1R {
11008 PwmOffsetL1R::new((self.bits & 0xffff) as u16)
11009 }
11010 }
11011 impl W {
11012 #[doc = "Bits 0:15 - PWM1 phase offset low 16 bits"]
11013 #[inline(always)]
11014 pub fn pwm_offset_l_1(&mut self) -> PwmOffsetL1W<'_, PwmOffsetL1Spec> {
11015 PwmOffsetL1W::new(self, 0)
11016 }
11017 }
11018 #[doc = "PWM1 phase offset low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11019 pub struct PwmOffsetL1Spec;
11020 impl crate::RegisterSpec for PwmOffsetL1Spec {
11021 type Ux = u32;
11022 }
11023 #[doc = "`read()` method returns [`pwm_offset_l1::R`](R) reader structure"]
11024 impl crate::Readable for PwmOffsetL1Spec {}
11025 #[doc = "`write(|w| ..)` method takes [`pwm_offset_l1::W`](W) writer structure"]
11026 impl crate::Writable for PwmOffsetL1Spec {
11027 type Safety = crate::Unsafe;
11028 }
11029 #[doc = "`reset()` method sets PWM_OFFSET_L1 to value 0"]
11030 impl crate::Resettable for PwmOffsetL1Spec {}
11031 }
11032 #[doc = "PWM_OFFSET_H1 (rw) register accessor: PWM1 phase offset high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h1`] module"]
11033 #[doc(alias = "PWM_OFFSET_H1")]
11034 pub type PwmOffsetH1 = crate::Reg<pwm_offset_h1::PwmOffsetH1Spec>;
11035 #[doc = "PWM1 phase offset high"]
11036 pub mod pwm_offset_h1 {
11037 #[doc = "Register `PWM_OFFSET_H1` reader"]
11038 pub type R = crate::R<PwmOffsetH1Spec>;
11039 #[doc = "Register `PWM_OFFSET_H1` writer"]
11040 pub type W = crate::W<PwmOffsetH1Spec>;
11041 #[doc = "Field `pwm_offset_h_1` reader - PWM1 phase offset high 16 bits"]
11042 pub type PwmOffsetH1R = crate::FieldReader<u16>;
11043 #[doc = "Field `pwm_offset_h_1` writer - PWM1 phase offset high 16 bits"]
11044 pub type PwmOffsetH1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11045 impl R {
11046 #[doc = "Bits 0:15 - PWM1 phase offset high 16 bits"]
11047 #[inline(always)]
11048 pub fn pwm_offset_h_1(&self) -> PwmOffsetH1R {
11049 PwmOffsetH1R::new((self.bits & 0xffff) as u16)
11050 }
11051 }
11052 impl W {
11053 #[doc = "Bits 0:15 - PWM1 phase offset high 16 bits"]
11054 #[inline(always)]
11055 pub fn pwm_offset_h_1(&mut self) -> PwmOffsetH1W<'_, PwmOffsetH1Spec> {
11056 PwmOffsetH1W::new(self, 0)
11057 }
11058 }
11059 #[doc = "PWM1 phase offset high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11060 pub struct PwmOffsetH1Spec;
11061 impl crate::RegisterSpec for PwmOffsetH1Spec {
11062 type Ux = u32;
11063 }
11064 #[doc = "`read()` method returns [`pwm_offset_h1::R`](R) reader structure"]
11065 impl crate::Readable for PwmOffsetH1Spec {}
11066 #[doc = "`write(|w| ..)` method takes [`pwm_offset_h1::W`](W) writer structure"]
11067 impl crate::Writable for PwmOffsetH1Spec {
11068 type Safety = crate::Unsafe;
11069 }
11070 #[doc = "`reset()` method sets PWM_OFFSET_H1 to value 0"]
11071 impl crate::Resettable for PwmOffsetH1Spec {}
11072 }
11073 #[doc = "PWM_FREQ_L1 (rw) register accessor: PWM1 frequency low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l1`] module"]
11074 #[doc(alias = "PWM_FREQ_L1")]
11075 pub type PwmFreqL1 = crate::Reg<pwm_freq_l1::PwmFreqL1Spec>;
11076 #[doc = "PWM1 frequency low"]
11077 pub mod pwm_freq_l1 {
11078 #[doc = "Register `PWM_FREQ_L1` reader"]
11079 pub type R = crate::R<PwmFreqL1Spec>;
11080 #[doc = "Register `PWM_FREQ_L1` writer"]
11081 pub type W = crate::W<PwmFreqL1Spec>;
11082 #[doc = "Field `pwm_freq_l_1` reader - PWM1 clock divider low 16 bits"]
11083 pub type PwmFreqL1R = crate::FieldReader<u16>;
11084 #[doc = "Field `pwm_freq_l_1` writer - PWM1 clock divider low 16 bits"]
11085 pub type PwmFreqL1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11086 impl R {
11087 #[doc = "Bits 0:15 - PWM1 clock divider low 16 bits"]
11088 #[inline(always)]
11089 pub fn pwm_freq_l_1(&self) -> PwmFreqL1R {
11090 PwmFreqL1R::new((self.bits & 0xffff) as u16)
11091 }
11092 }
11093 impl W {
11094 #[doc = "Bits 0:15 - PWM1 clock divider low 16 bits"]
11095 #[inline(always)]
11096 pub fn pwm_freq_l_1(&mut self) -> PwmFreqL1W<'_, PwmFreqL1Spec> {
11097 PwmFreqL1W::new(self, 0)
11098 }
11099 }
11100 #[doc = "PWM1 frequency low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11101 pub struct PwmFreqL1Spec;
11102 impl crate::RegisterSpec for PwmFreqL1Spec {
11103 type Ux = u32;
11104 }
11105 #[doc = "`read()` method returns [`pwm_freq_l1::R`](R) reader structure"]
11106 impl crate::Readable for PwmFreqL1Spec {}
11107 #[doc = "`write(|w| ..)` method takes [`pwm_freq_l1::W`](W) writer structure"]
11108 impl crate::Writable for PwmFreqL1Spec {
11109 type Safety = crate::Unsafe;
11110 }
11111 #[doc = "`reset()` method sets PWM_FREQ_L1 to value 0"]
11112 impl crate::Resettable for PwmFreqL1Spec {}
11113 }
11114 #[doc = "PWM_FREQ_H1 (rw) register accessor: PWM1 frequency high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h1`] module"]
11115 #[doc(alias = "PWM_FREQ_H1")]
11116 pub type PwmFreqH1 = crate::Reg<pwm_freq_h1::PwmFreqH1Spec>;
11117 #[doc = "PWM1 frequency high"]
11118 pub mod pwm_freq_h1 {
11119 #[doc = "Register `PWM_FREQ_H1` reader"]
11120 pub type R = crate::R<PwmFreqH1Spec>;
11121 #[doc = "Register `PWM_FREQ_H1` writer"]
11122 pub type W = crate::W<PwmFreqH1Spec>;
11123 #[doc = "Field `pwm_freq_h_1` reader - PWM1 clock divider high 16 bits"]
11124 pub type PwmFreqH1R = crate::FieldReader<u16>;
11125 #[doc = "Field `pwm_freq_h_1` writer - PWM1 clock divider high 16 bits"]
11126 pub type PwmFreqH1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11127 impl R {
11128 #[doc = "Bits 0:15 - PWM1 clock divider high 16 bits"]
11129 #[inline(always)]
11130 pub fn pwm_freq_h_1(&self) -> PwmFreqH1R {
11131 PwmFreqH1R::new((self.bits & 0xffff) as u16)
11132 }
11133 }
11134 impl W {
11135 #[doc = "Bits 0:15 - PWM1 clock divider high 16 bits"]
11136 #[inline(always)]
11137 pub fn pwm_freq_h_1(&mut self) -> PwmFreqH1W<'_, PwmFreqH1Spec> {
11138 PwmFreqH1W::new(self, 0)
11139 }
11140 }
11141 #[doc = "PWM1 frequency high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11142 pub struct PwmFreqH1Spec;
11143 impl crate::RegisterSpec for PwmFreqH1Spec {
11144 type Ux = u32;
11145 }
11146 #[doc = "`read()` method returns [`pwm_freq_h1::R`](R) reader structure"]
11147 impl crate::Readable for PwmFreqH1Spec {}
11148 #[doc = "`write(|w| ..)` method takes [`pwm_freq_h1::W`](W) writer structure"]
11149 impl crate::Writable for PwmFreqH1Spec {
11150 type Safety = crate::Unsafe;
11151 }
11152 #[doc = "`reset()` method sets PWM_FREQ_H1 to value 0"]
11153 impl crate::Resettable for PwmFreqH1Spec {}
11154 }
11155 #[doc = "PWM_DUTY_L1 (rw) register accessor: PWM1 duty cycle low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l1`] module"]
11156 #[doc(alias = "PWM_DUTY_L1")]
11157 pub type PwmDutyL1 = crate::Reg<pwm_duty_l1::PwmDutyL1Spec>;
11158 #[doc = "PWM1 duty cycle low"]
11159 pub mod pwm_duty_l1 {
11160 #[doc = "Register `PWM_DUTY_L1` reader"]
11161 pub type R = crate::R<PwmDutyL1Spec>;
11162 #[doc = "Register `PWM_DUTY_L1` writer"]
11163 pub type W = crate::W<PwmDutyL1Spec>;
11164 #[doc = "Field `pwm_duty_l_1` reader - PWM1 duty low 16 bits"]
11165 pub type PwmDutyL1R = crate::FieldReader<u16>;
11166 #[doc = "Field `pwm_duty_l_1` writer - PWM1 duty low 16 bits"]
11167 pub type PwmDutyL1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11168 impl R {
11169 #[doc = "Bits 0:15 - PWM1 duty low 16 bits"]
11170 #[inline(always)]
11171 pub fn pwm_duty_l_1(&self) -> PwmDutyL1R {
11172 PwmDutyL1R::new((self.bits & 0xffff) as u16)
11173 }
11174 }
11175 impl W {
11176 #[doc = "Bits 0:15 - PWM1 duty low 16 bits"]
11177 #[inline(always)]
11178 pub fn pwm_duty_l_1(&mut self) -> PwmDutyL1W<'_, PwmDutyL1Spec> {
11179 PwmDutyL1W::new(self, 0)
11180 }
11181 }
11182 #[doc = "PWM1 duty cycle low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11183 pub struct PwmDutyL1Spec;
11184 impl crate::RegisterSpec for PwmDutyL1Spec {
11185 type Ux = u32;
11186 }
11187 #[doc = "`read()` method returns [`pwm_duty_l1::R`](R) reader structure"]
11188 impl crate::Readable for PwmDutyL1Spec {}
11189 #[doc = "`write(|w| ..)` method takes [`pwm_duty_l1::W`](W) writer structure"]
11190 impl crate::Writable for PwmDutyL1Spec {
11191 type Safety = crate::Unsafe;
11192 }
11193 #[doc = "`reset()` method sets PWM_DUTY_L1 to value 0"]
11194 impl crate::Resettable for PwmDutyL1Spec {}
11195 }
11196 #[doc = "PWM_DUTY_H1 (rw) register accessor: PWM1 duty cycle high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h1`] module"]
11197 #[doc(alias = "PWM_DUTY_H1")]
11198 pub type PwmDutyH1 = crate::Reg<pwm_duty_h1::PwmDutyH1Spec>;
11199 #[doc = "PWM1 duty cycle high"]
11200 pub mod pwm_duty_h1 {
11201 #[doc = "Register `PWM_DUTY_H1` reader"]
11202 pub type R = crate::R<PwmDutyH1Spec>;
11203 #[doc = "Register `PWM_DUTY_H1` writer"]
11204 pub type W = crate::W<PwmDutyH1Spec>;
11205 #[doc = "Field `pwm_duty_h_1` reader - PWM1 duty high 16 bits"]
11206 pub type PwmDutyH1R = crate::FieldReader<u16>;
11207 #[doc = "Field `pwm_duty_h_1` writer - PWM1 duty high 16 bits"]
11208 pub type PwmDutyH1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11209 impl R {
11210 #[doc = "Bits 0:15 - PWM1 duty high 16 bits"]
11211 #[inline(always)]
11212 pub fn pwm_duty_h_1(&self) -> PwmDutyH1R {
11213 PwmDutyH1R::new((self.bits & 0xffff) as u16)
11214 }
11215 }
11216 impl W {
11217 #[doc = "Bits 0:15 - PWM1 duty high 16 bits"]
11218 #[inline(always)]
11219 pub fn pwm_duty_h_1(&mut self) -> PwmDutyH1W<'_, PwmDutyH1Spec> {
11220 PwmDutyH1W::new(self, 0)
11221 }
11222 }
11223 #[doc = "PWM1 duty cycle high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11224 pub struct PwmDutyH1Spec;
11225 impl crate::RegisterSpec for PwmDutyH1Spec {
11226 type Ux = u32;
11227 }
11228 #[doc = "`read()` method returns [`pwm_duty_h1::R`](R) reader structure"]
11229 impl crate::Readable for PwmDutyH1Spec {}
11230 #[doc = "`write(|w| ..)` method takes [`pwm_duty_h1::W`](W) writer structure"]
11231 impl crate::Writable for PwmDutyH1Spec {
11232 type Safety = crate::Unsafe;
11233 }
11234 #[doc = "`reset()` method sets PWM_DUTY_H1 to value 0"]
11235 impl crate::Resettable for PwmDutyH1Spec {}
11236 }
11237 #[doc = "PWM_PERIODLOAD_FLAG1 (rw) register accessor: PWM1 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag1`] module"]
11238 #[doc(alias = "PWM_PERIODLOAD_FLAG1")]
11239 pub type PwmPeriodloadFlag1 = crate::Reg<pwm_periodload_flag1::PwmPeriodloadFlag1Spec>;
11240 #[doc = "PWM1 period load flag"]
11241 pub mod pwm_periodload_flag1 {
11242 #[doc = "Register `PWM_PERIODLOAD_FLAG1` reader"]
11243 pub type R = crate::R<PwmPeriodloadFlag1Spec>;
11244 #[doc = "Register `PWM_PERIODLOAD_FLAG1` writer"]
11245 pub type W = crate::W<PwmPeriodloadFlag1Spec>;
11246 #[doc = "Field `pwm_periodload_flag_1` reader - Period load flag"]
11247 pub type PwmPeriodloadFlag1R = crate::BitReader;
11248 impl R {
11249 #[doc = "Bit 0 - Period load flag"]
11250 #[inline(always)]
11251 pub fn pwm_periodload_flag_1(&self) -> PwmPeriodloadFlag1R {
11252 PwmPeriodloadFlag1R::new((self.bits & 1) != 0)
11253 }
11254 }
11255 impl W {}
11256 #[doc = "PWM1 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11257 pub struct PwmPeriodloadFlag1Spec;
11258 impl crate::RegisterSpec for PwmPeriodloadFlag1Spec {
11259 type Ux = u32;
11260 }
11261 #[doc = "`read()` method returns [`pwm_periodload_flag1::R`](R) reader structure"]
11262 impl crate::Readable for PwmPeriodloadFlag1Spec {}
11263 #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag1::W`](W) writer structure"]
11264 impl crate::Writable for PwmPeriodloadFlag1Spec {
11265 type Safety = crate::Unsafe;
11266 }
11267 #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG1 to value 0"]
11268 impl crate::Resettable for PwmPeriodloadFlag1Spec {}
11269 }
11270 #[doc = "PWM_PERIOD_VAL1 (rw) register accessor: PWM1 pulse count\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val1`] module"]
11271 #[doc(alias = "PWM_PERIOD_VAL1")]
11272 pub type PwmPeriodVal1 = crate::Reg<pwm_period_val1::PwmPeriodVal1Spec>;
11273 #[doc = "PWM1 pulse count"]
11274 pub mod pwm_period_val1 {
11275 #[doc = "Register `PWM_PERIOD_VAL1` reader"]
11276 pub type R = crate::R<PwmPeriodVal1Spec>;
11277 #[doc = "Register `PWM_PERIOD_VAL1` writer"]
11278 pub type W = crate::W<PwmPeriodVal1Spec>;
11279 #[doc = "Field `pwm_period_val_1` reader - Pulse count"]
11280 pub type PwmPeriodVal1R = crate::FieldReader<u16>;
11281 #[doc = "Field `pwm_period_val_1` writer - Pulse count"]
11282 pub type PwmPeriodVal1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11283 impl R {
11284 #[doc = "Bits 0:15 - Pulse count"]
11285 #[inline(always)]
11286 pub fn pwm_period_val_1(&self) -> PwmPeriodVal1R {
11287 PwmPeriodVal1R::new((self.bits & 0xffff) as u16)
11288 }
11289 }
11290 impl W {
11291 #[doc = "Bits 0:15 - Pulse count"]
11292 #[inline(always)]
11293 pub fn pwm_period_val_1(&mut self) -> PwmPeriodVal1W<'_, PwmPeriodVal1Spec> {
11294 PwmPeriodVal1W::new(self, 0)
11295 }
11296 }
11297 #[doc = "PWM1 pulse count\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11298 pub struct PwmPeriodVal1Spec;
11299 impl crate::RegisterSpec for PwmPeriodVal1Spec {
11300 type Ux = u32;
11301 }
11302 #[doc = "`read()` method returns [`pwm_period_val1::R`](R) reader structure"]
11303 impl crate::Readable for PwmPeriodVal1Spec {}
11304 #[doc = "`write(|w| ..)` method takes [`pwm_period_val1::W`](W) writer structure"]
11305 impl crate::Writable for PwmPeriodVal1Spec {
11306 type Safety = crate::Unsafe;
11307 }
11308 #[doc = "`reset()` method sets PWM_PERIOD_VAL1 to value 0"]
11309 impl crate::Resettable for PwmPeriodVal1Spec {}
11310 }
11311 #[doc = "PWM_PERIODCNT1 (rw) register accessor: PWM1 pulse count current\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt1`] module"]
11312 #[doc(alias = "PWM_PERIODCNT1")]
11313 pub type PwmPeriodcnt1 = crate::Reg<pwm_periodcnt1::PwmPeriodcnt1Spec>;
11314 #[doc = "PWM1 pulse count current"]
11315 pub mod pwm_periodcnt1 {
11316 #[doc = "Register `PWM_PERIODCNT1` reader"]
11317 pub type R = crate::R<PwmPeriodcnt1Spec>;
11318 #[doc = "Register `PWM_PERIODCNT1` writer"]
11319 pub type W = crate::W<PwmPeriodcnt1Spec>;
11320 #[doc = "Field `pwm_periodcnt_1` reader - Current pulse count"]
11321 pub type PwmPeriodcnt1R = crate::FieldReader<u16>;
11322 impl R {
11323 #[doc = "Bits 0:15 - Current pulse count"]
11324 #[inline(always)]
11325 pub fn pwm_periodcnt_1(&self) -> PwmPeriodcnt1R {
11326 PwmPeriodcnt1R::new((self.bits & 0xffff) as u16)
11327 }
11328 }
11329 impl W {}
11330 #[doc = "PWM1 pulse count current\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11331 pub struct PwmPeriodcnt1Spec;
11332 impl crate::RegisterSpec for PwmPeriodcnt1Spec {
11333 type Ux = u32;
11334 }
11335 #[doc = "`read()` method returns [`pwm_periodcnt1::R`](R) reader structure"]
11336 impl crate::Readable for PwmPeriodcnt1Spec {}
11337 #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt1::W`](W) writer structure"]
11338 impl crate::Writable for PwmPeriodcnt1Spec {
11339 type Safety = crate::Unsafe;
11340 }
11341 #[doc = "`reset()` method sets PWM_PERIODCNT1 to value 0"]
11342 impl crate::Resettable for PwmPeriodcnt1Spec {}
11343 }
11344 #[doc = "PWM_ABNOR_STATE0 (rw) register accessor: PWM abnormal state register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state0`] module"]
11345 #[doc(alias = "PWM_ABNOR_STATE0")]
11346 pub type PwmAbnorState0 = crate::Reg<pwm_abnor_state0::PwmAbnorState0Spec>;
11347 #[doc = "PWM abnormal state register 0"]
11348 pub mod pwm_abnor_state0 {
11349 #[doc = "Register `PWM_ABNOR_STATE0` reader"]
11350 pub type R = crate::R<PwmAbnorState0Spec>;
11351 #[doc = "Register `PWM_ABNOR_STATE0` writer"]
11352 pub type W = crate::W<PwmAbnorState0Spec>;
11353 #[doc = "Field `pwm_abnor_state0` reader - Multi-channel config abnormal state, each bit per PWM"]
11354 pub type PwmAbnorState0R = crate::FieldReader<u16>;
11355 impl R {
11356 #[doc = "Bits 0:15 - Multi-channel config abnormal state, each bit per PWM"]
11357 #[inline(always)]
11358 pub fn pwm_abnor_state0(&self) -> PwmAbnorState0R {
11359 PwmAbnorState0R::new((self.bits & 0xffff) as u16)
11360 }
11361 }
11362 impl W {}
11363 #[doc = "PWM abnormal state register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11364 pub struct PwmAbnorState0Spec;
11365 impl crate::RegisterSpec for PwmAbnorState0Spec {
11366 type Ux = u32;
11367 }
11368 #[doc = "`read()` method returns [`pwm_abnor_state0::R`](R) reader structure"]
11369 impl crate::Readable for PwmAbnorState0Spec {}
11370 #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state0::W`](W) writer structure"]
11371 impl crate::Writable for PwmAbnorState0Spec {
11372 type Safety = crate::Unsafe;
11373 }
11374 #[doc = "`reset()` method sets PWM_ABNOR_STATE0 to value 0"]
11375 impl crate::Resettable for PwmAbnorState0Spec {}
11376 }
11377 #[doc = "PWM_ABNOR_STATE1 (rw) register accessor: PWM abnormal state register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state1`] module"]
11378 #[doc(alias = "PWM_ABNOR_STATE1")]
11379 pub type PwmAbnorState1 = crate::Reg<pwm_abnor_state1::PwmAbnorState1Spec>;
11380 #[doc = "PWM abnormal state register 1"]
11381 pub mod pwm_abnor_state1 {
11382 #[doc = "Register `PWM_ABNOR_STATE1` reader"]
11383 pub type R = crate::R<PwmAbnorState1Spec>;
11384 #[doc = "Register `PWM_ABNOR_STATE1` writer"]
11385 pub type W = crate::W<PwmAbnorState1Spec>;
11386 #[doc = "Field `pwm_abnor_state1` reader - Counter config abnormal state, each bit per PWM"]
11387 pub type PwmAbnorState1R = crate::FieldReader<u16>;
11388 impl R {
11389 #[doc = "Bits 0:15 - Counter config abnormal state, each bit per PWM"]
11390 #[inline(always)]
11391 pub fn pwm_abnor_state1(&self) -> PwmAbnorState1R {
11392 PwmAbnorState1R::new((self.bits & 0xffff) as u16)
11393 }
11394 }
11395 impl W {}
11396 #[doc = "PWM abnormal state register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11397 pub struct PwmAbnorState1Spec;
11398 impl crate::RegisterSpec for PwmAbnorState1Spec {
11399 type Ux = u32;
11400 }
11401 #[doc = "`read()` method returns [`pwm_abnor_state1::R`](R) reader structure"]
11402 impl crate::Readable for PwmAbnorState1Spec {}
11403 #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state1::W`](W) writer structure"]
11404 impl crate::Writable for PwmAbnorState1Spec {
11405 type Safety = crate::Unsafe;
11406 }
11407 #[doc = "`reset()` method sets PWM_ABNOR_STATE1 to value 0"]
11408 impl crate::Resettable for PwmAbnorState1Spec {}
11409 }
11410 #[doc = "PWM_ABNOR_STATE_CLR0 (rw) register accessor: PWM abnormal state clear 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state_clr0`] module"]
11411 #[doc(alias = "PWM_ABNOR_STATE_CLR0")]
11412 pub type PwmAbnorStateClr0 = crate::Reg<pwm_abnor_state_clr0::PwmAbnorStateClr0Spec>;
11413 #[doc = "PWM abnormal state clear 0"]
11414 pub mod pwm_abnor_state_clr0 {
11415 #[doc = "Register `PWM_ABNOR_STATE_CLR0` reader"]
11416 pub type R = crate::R<PwmAbnorStateClr0Spec>;
11417 #[doc = "Register `PWM_ABNOR_STATE_CLR0` writer"]
11418 pub type W = crate::W<PwmAbnorStateClr0Spec>;
11419 #[doc = "Field `pwm_abnor_state_clr0` writer - Clear abnormal state 0 (self-clearing)"]
11420 pub type PwmAbnorStateClr0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11421 impl W {
11422 #[doc = "Bits 0:15 - Clear abnormal state 0 (self-clearing)"]
11423 #[inline(always)]
11424 pub fn pwm_abnor_state_clr0(
11425 &mut self,
11426 ) -> PwmAbnorStateClr0W<'_, PwmAbnorStateClr0Spec> {
11427 PwmAbnorStateClr0W::new(self, 0)
11428 }
11429 }
11430 #[doc = "PWM abnormal state clear 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11431 pub struct PwmAbnorStateClr0Spec;
11432 impl crate::RegisterSpec for PwmAbnorStateClr0Spec {
11433 type Ux = u32;
11434 }
11435 #[doc = "`read()` method returns [`pwm_abnor_state_clr0::R`](R) reader structure"]
11436 impl crate::Readable for PwmAbnorStateClr0Spec {}
11437 #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state_clr0::W`](W) writer structure"]
11438 impl crate::Writable for PwmAbnorStateClr0Spec {
11439 type Safety = crate::Unsafe;
11440 }
11441 #[doc = "`reset()` method sets PWM_ABNOR_STATE_CLR0 to value 0"]
11442 impl crate::Resettable for PwmAbnorStateClr0Spec {}
11443 }
11444 #[doc = "PWM_ABNOR_STATE_CLR1 (rw) register accessor: PWM abnormal state clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state_clr1`] module"]
11445 #[doc(alias = "PWM_ABNOR_STATE_CLR1")]
11446 pub type PwmAbnorStateClr1 = crate::Reg<pwm_abnor_state_clr1::PwmAbnorStateClr1Spec>;
11447 #[doc = "PWM abnormal state clear 1"]
11448 pub mod pwm_abnor_state_clr1 {
11449 #[doc = "Register `PWM_ABNOR_STATE_CLR1` reader"]
11450 pub type R = crate::R<PwmAbnorStateClr1Spec>;
11451 #[doc = "Register `PWM_ABNOR_STATE_CLR1` writer"]
11452 pub type W = crate::W<PwmAbnorStateClr1Spec>;
11453 #[doc = "Field `pwm_abnor_state_clr1` writer - Clear abnormal state 1 (self-clearing)"]
11454 pub type PwmAbnorStateClr1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11455 impl W {
11456 #[doc = "Bits 0:15 - Clear abnormal state 1 (self-clearing)"]
11457 #[inline(always)]
11458 pub fn pwm_abnor_state_clr1(
11459 &mut self,
11460 ) -> PwmAbnorStateClr1W<'_, PwmAbnorStateClr1Spec> {
11461 PwmAbnorStateClr1W::new(self, 0)
11462 }
11463 }
11464 #[doc = "PWM abnormal state clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11465 pub struct PwmAbnorStateClr1Spec;
11466 impl crate::RegisterSpec for PwmAbnorStateClr1Spec {
11467 type Ux = u32;
11468 }
11469 #[doc = "`read()` method returns [`pwm_abnor_state_clr1::R`](R) reader structure"]
11470 impl crate::Readable for PwmAbnorStateClr1Spec {}
11471 #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state_clr1::W`](W) writer structure"]
11472 impl crate::Writable for PwmAbnorStateClr1Spec {
11473 type Safety = crate::Unsafe;
11474 }
11475 #[doc = "`reset()` method sets PWM_ABNOR_STATE_CLR1 to value 0"]
11476 impl crate::Resettable for PwmAbnorStateClr1Spec {}
11477 }
11478 #[doc = "PWM_INT_MASK (rw) register accessor: PWM interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_int_mask`] module"]
11479 #[doc(alias = "PWM_INT_MASK")]
11480 pub type PwmIntMask = crate::Reg<pwm_int_mask::PwmIntMaskSpec>;
11481 #[doc = "PWM interrupt mask"]
11482 pub mod pwm_int_mask {
11483 #[doc = "Register `PWM_INT_MASK` reader"]
11484 pub type R = crate::R<PwmIntMaskSpec>;
11485 #[doc = "Register `PWM_INT_MASK` writer"]
11486 pub type W = crate::W<PwmIntMaskSpec>;
11487 #[doc = "Field `pwm_int_mask` reader - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
11488 pub type PwmIntMaskR = crate::FieldReader;
11489 #[doc = "Field `pwm_int_mask` writer - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
11490 pub type PwmIntMaskW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
11491 impl R {
11492 #[doc = "Bits 0:1 - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
11493 #[inline(always)]
11494 pub fn pwm_int_mask(&self) -> PwmIntMaskR {
11495 PwmIntMaskR::new((self.bits & 3) as u8)
11496 }
11497 }
11498 impl W {
11499 #[doc = "Bits 0:1 - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
11500 #[inline(always)]
11501 pub fn pwm_int_mask(&mut self) -> PwmIntMaskW<'_, PwmIntMaskSpec> {
11502 PwmIntMaskW::new(self, 0)
11503 }
11504 }
11505 #[doc = "PWM interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11506 pub struct PwmIntMaskSpec;
11507 impl crate::RegisterSpec for PwmIntMaskSpec {
11508 type Ux = u32;
11509 }
11510 #[doc = "`read()` method returns [`pwm_int_mask::R`](R) reader structure"]
11511 impl crate::Readable for PwmIntMaskSpec {}
11512 #[doc = "`write(|w| ..)` method takes [`pwm_int_mask::W`](W) writer structure"]
11513 impl crate::Writable for PwmIntMaskSpec {
11514 type Safety = crate::Unsafe;
11515 }
11516 #[doc = "`reset()` method sets PWM_INT_MASK to value 0"]
11517 impl crate::Resettable for PwmIntMaskSpec {}
11518 }
11519 #[doc = "PWM_DMA_EN (rw) register accessor: PWM DMA enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_dma_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_dma_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_dma_en`] module"]
11520 #[doc(alias = "PWM_DMA_EN")]
11521 pub type PwmDmaEn = crate::Reg<pwm_dma_en::PwmDmaEnSpec>;
11522 #[doc = "PWM DMA enable"]
11523 pub mod pwm_dma_en {
11524 #[doc = "Register `PWM_DMA_EN` reader"]
11525 pub type R = crate::R<PwmDmaEnSpec>;
11526 #[doc = "Register `PWM_DMA_EN` writer"]
11527 pub type W = crate::W<PwmDmaEnSpec>;
11528 #[doc = "Field `pwm_dma_en` reader - DMA enable: 0=disabled; 1=enabled"]
11529 pub type PwmDmaEnR = crate::BitReader;
11530 #[doc = "Field `pwm_dma_en` writer - DMA enable: 0=disabled; 1=enabled"]
11531 pub type PwmDmaEnW<'a, REG> = crate::BitWriter<'a, REG>;
11532 impl R {
11533 #[doc = "Bit 0 - DMA enable: 0=disabled; 1=enabled"]
11534 #[inline(always)]
11535 pub fn pwm_dma_en(&self) -> PwmDmaEnR {
11536 PwmDmaEnR::new((self.bits & 1) != 0)
11537 }
11538 }
11539 impl W {
11540 #[doc = "Bit 0 - DMA enable: 0=disabled; 1=enabled"]
11541 #[inline(always)]
11542 pub fn pwm_dma_en(&mut self) -> PwmDmaEnW<'_, PwmDmaEnSpec> {
11543 PwmDmaEnW::new(self, 0)
11544 }
11545 }
11546 #[doc = "PWM DMA enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_dma_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_dma_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11547 pub struct PwmDmaEnSpec;
11548 impl crate::RegisterSpec for PwmDmaEnSpec {
11549 type Ux = u32;
11550 }
11551 #[doc = "`read()` method returns [`pwm_dma_en::R`](R) reader structure"]
11552 impl crate::Readable for PwmDmaEnSpec {}
11553 #[doc = "`write(|w| ..)` method takes [`pwm_dma_en::W`](W) writer structure"]
11554 impl crate::Writable for PwmDmaEnSpec {
11555 type Safety = crate::Unsafe;
11556 }
11557 #[doc = "`reset()` method sets PWM_DMA_EN to value 0"]
11558 impl crate::Resettable for PwmDmaEnSpec {}
11559 }
11560 #[doc = "PWM_CFG_INT_CLR0 (rw) register accessor: PWM stepping cycle end interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_cfg_int_clr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_cfg_int_clr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_cfg_int_clr0`] module"]
11561 #[doc(alias = "PWM_CFG_INT_CLR0")]
11562 pub type PwmCfgIntClr0 = crate::Reg<pwm_cfg_int_clr0::PwmCfgIntClr0Spec>;
11563 #[doc = "PWM stepping cycle end interrupt clear"]
11564 pub mod pwm_cfg_int_clr0 {
11565 #[doc = "Register `PWM_CFG_INT_CLR0` reader"]
11566 pub type R = crate::R<PwmCfgIntClr0Spec>;
11567 #[doc = "Register `PWM_CFG_INT_CLR0` writer"]
11568 pub type W = crate::W<PwmCfgIntClr0Spec>;
11569 #[doc = "Field `pwm_cfg_int_clr0` writer - Stepping cycle end interrupt clear (self-clearing)"]
11570 pub type PwmCfgIntClr0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11571 impl W {
11572 #[doc = "Bits 0:15 - Stepping cycle end interrupt clear (self-clearing)"]
11573 #[inline(always)]
11574 pub fn pwm_cfg_int_clr0(&mut self) -> PwmCfgIntClr0W<'_, PwmCfgIntClr0Spec> {
11575 PwmCfgIntClr0W::new(self, 0)
11576 }
11577 }
11578 #[doc = "PWM stepping cycle end interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_cfg_int_clr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_cfg_int_clr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11579 pub struct PwmCfgIntClr0Spec;
11580 impl crate::RegisterSpec for PwmCfgIntClr0Spec {
11581 type Ux = u32;
11582 }
11583 #[doc = "`read()` method returns [`pwm_cfg_int_clr0::R`](R) reader structure"]
11584 impl crate::Readable for PwmCfgIntClr0Spec {}
11585 #[doc = "`write(|w| ..)` method takes [`pwm_cfg_int_clr0::W`](W) writer structure"]
11586 impl crate::Writable for PwmCfgIntClr0Spec {
11587 type Safety = crate::Unsafe;
11588 }
11589 #[doc = "`reset()` method sets PWM_CFG_INT_CLR0 to value 0"]
11590 impl crate::Resettable for PwmCfgIntClr0Spec {}
11591 }
11592 #[doc = "PWM_EN2 (rw) register accessor: PWM2 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en2`] module"]
11593 #[doc(alias = "PWM_EN2")]
11594 pub type PwmEn2 = crate::Reg<pwm_en2::PwmEn2Spec>;
11595 #[doc = "PWM2 enable"]
11596 pub mod pwm_en2 {
11597 #[doc = "Register `PWM_EN2` reader"]
11598 pub type R = crate::R<PwmEn2Spec>;
11599 #[doc = "Register `PWM_EN2` writer"]
11600 pub type W = crate::W<PwmEn2Spec>;
11601 #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
11602 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
11603 pub enum PwmEn2 {
11604 #[doc = "0: PWM disabled, output low"]
11605 Off = 0,
11606 #[doc = "1: PWM enabled"]
11607 On = 1,
11608 }
11609 impl From<PwmEn2> for bool {
11610 #[inline(always)]
11611 fn from(variant: PwmEn2) -> Self {
11612 variant as u8 != 0
11613 }
11614 }
11615 #[doc = "Field `pwm_en_2` reader - PWM0 enable: 0=off; 1=on"]
11616 pub type PwmEn2R = crate::BitReader<PwmEn2>;
11617 impl PwmEn2R {
11618 #[doc = "Get enumerated values variant"]
11619 #[inline(always)]
11620 pub const fn variant(&self) -> PwmEn2 {
11621 match self.bits {
11622 false => PwmEn2::Off,
11623 true => PwmEn2::On,
11624 }
11625 }
11626 #[doc = "PWM disabled, output low"]
11627 #[inline(always)]
11628 pub fn is_off(&self) -> bool {
11629 *self == PwmEn2::Off
11630 }
11631 #[doc = "PWM enabled"]
11632 #[inline(always)]
11633 pub fn is_on(&self) -> bool {
11634 *self == PwmEn2::On
11635 }
11636 }
11637 #[doc = "Field `pwm_en_2` writer - PWM0 enable: 0=off; 1=on"]
11638 pub type PwmEn2W<'a, REG> = crate::BitWriter<'a, REG, PwmEn2>;
11639 impl<'a, REG> PwmEn2W<'a, REG>
11640 where
11641 REG: crate::Writable + crate::RegisterSpec,
11642 {
11643 #[doc = "PWM disabled, output low"]
11644 #[inline(always)]
11645 pub fn off(self) -> &'a mut crate::W<REG> {
11646 self.variant(PwmEn2::Off)
11647 }
11648 #[doc = "PWM enabled"]
11649 #[inline(always)]
11650 pub fn on(self) -> &'a mut crate::W<REG> {
11651 self.variant(PwmEn2::On)
11652 }
11653 }
11654 impl R {
11655 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
11656 #[inline(always)]
11657 pub fn pwm_en_2(&self) -> PwmEn2R {
11658 PwmEn2R::new((self.bits & 1) != 0)
11659 }
11660 }
11661 impl W {
11662 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
11663 #[inline(always)]
11664 pub fn pwm_en_2(&mut self) -> PwmEn2W<'_, PwmEn2Spec> {
11665 PwmEn2W::new(self, 0)
11666 }
11667 }
11668 #[doc = "PWM2 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11669 pub struct PwmEn2Spec;
11670 impl crate::RegisterSpec for PwmEn2Spec {
11671 type Ux = u32;
11672 }
11673 #[doc = "`read()` method returns [`pwm_en2::R`](R) reader structure"]
11674 impl crate::Readable for PwmEn2Spec {}
11675 #[doc = "`write(|w| ..)` method takes [`pwm_en2::W`](W) writer structure"]
11676 impl crate::Writable for PwmEn2Spec {
11677 type Safety = crate::Unsafe;
11678 }
11679 #[doc = "`reset()` method sets PWM_EN2 to value 0"]
11680 impl crate::Resettable for PwmEn2Spec {}
11681 }
11682 #[doc = "PWM_PORTITY2 (rw) register accessor: PWM2 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity2`] module"]
11683 #[doc(alias = "PWM_PORTITY2")]
11684 pub type PwmPortity2 = crate::Reg<pwm_portity2::PwmPortity2Spec>;
11685 #[doc = "PWM2 polarity"]
11686 pub mod pwm_portity2 {
11687 #[doc = "Register `PWM_PORTITY2` reader"]
11688 pub type R = crate::R<PwmPortity2Spec>;
11689 #[doc = "Register `PWM_PORTITY2` writer"]
11690 pub type W = crate::W<PwmPortity2Spec>;
11691 #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
11692 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
11693 pub enum PwmPoarity2 {
11694 #[doc = "0: Normal polarity"]
11695 Normal = 0,
11696 #[doc = "1: Inverted polarity"]
11697 Inverted = 1,
11698 }
11699 impl From<PwmPoarity2> for bool {
11700 #[inline(always)]
11701 fn from(variant: PwmPoarity2) -> Self {
11702 variant as u8 != 0
11703 }
11704 }
11705 #[doc = "Field `pwm_poarity_2` reader - PWM0 polarity: 0=normal; 1=inverted"]
11706 pub type PwmPoarity2R = crate::BitReader<PwmPoarity2>;
11707 impl PwmPoarity2R {
11708 #[doc = "Get enumerated values variant"]
11709 #[inline(always)]
11710 pub const fn variant(&self) -> PwmPoarity2 {
11711 match self.bits {
11712 false => PwmPoarity2::Normal,
11713 true => PwmPoarity2::Inverted,
11714 }
11715 }
11716 #[doc = "Normal polarity"]
11717 #[inline(always)]
11718 pub fn is_normal(&self) -> bool {
11719 *self == PwmPoarity2::Normal
11720 }
11721 #[doc = "Inverted polarity"]
11722 #[inline(always)]
11723 pub fn is_inverted(&self) -> bool {
11724 *self == PwmPoarity2::Inverted
11725 }
11726 }
11727 #[doc = "Field `pwm_poarity_2` writer - PWM0 polarity: 0=normal; 1=inverted"]
11728 pub type PwmPoarity2W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity2>;
11729 impl<'a, REG> PwmPoarity2W<'a, REG>
11730 where
11731 REG: crate::Writable + crate::RegisterSpec,
11732 {
11733 #[doc = "Normal polarity"]
11734 #[inline(always)]
11735 pub fn normal(self) -> &'a mut crate::W<REG> {
11736 self.variant(PwmPoarity2::Normal)
11737 }
11738 #[doc = "Inverted polarity"]
11739 #[inline(always)]
11740 pub fn inverted(self) -> &'a mut crate::W<REG> {
11741 self.variant(PwmPoarity2::Inverted)
11742 }
11743 }
11744 impl R {
11745 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
11746 #[inline(always)]
11747 pub fn pwm_poarity_2(&self) -> PwmPoarity2R {
11748 PwmPoarity2R::new((self.bits & 1) != 0)
11749 }
11750 }
11751 impl W {
11752 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
11753 #[inline(always)]
11754 pub fn pwm_poarity_2(&mut self) -> PwmPoarity2W<'_, PwmPortity2Spec> {
11755 PwmPoarity2W::new(self, 0)
11756 }
11757 }
11758 #[doc = "PWM2 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11759 pub struct PwmPortity2Spec;
11760 impl crate::RegisterSpec for PwmPortity2Spec {
11761 type Ux = u32;
11762 }
11763 #[doc = "`read()` method returns [`pwm_portity2::R`](R) reader structure"]
11764 impl crate::Readable for PwmPortity2Spec {}
11765 #[doc = "`write(|w| ..)` method takes [`pwm_portity2::W`](W) writer structure"]
11766 impl crate::Writable for PwmPortity2Spec {
11767 type Safety = crate::Unsafe;
11768 }
11769 #[doc = "`reset()` method sets PWM_PORTITY2 to value 0"]
11770 impl crate::Resettable for PwmPortity2Spec {}
11771 }
11772 #[doc = "PWM_OEN_CFG2 (rw) register accessor: PWM2 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg2`] module"]
11773 #[doc(alias = "PWM_OEN_CFG2")]
11774 pub type PwmOenCfg2 = crate::Reg<pwm_oen_cfg2::PwmOenCfg2Spec>;
11775 #[doc = "PWM2 high-impedance config"]
11776 pub mod pwm_oen_cfg2 {
11777 #[doc = "Register `PWM_OEN_CFG2` reader"]
11778 pub type R = crate::R<PwmOenCfg2Spec>;
11779 #[doc = "Register `PWM_OEN_CFG2` writer"]
11780 pub type W = crate::W<PwmOenCfg2Spec>;
11781 #[doc = "Field `pwm_oen_cfg_2` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
11782 pub type PwmOenCfg2R = crate::BitReader;
11783 #[doc = "Field `pwm_oen_cfg_2` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
11784 pub type PwmOenCfg2W<'a, REG> = crate::BitWriter<'a, REG>;
11785 impl R {
11786 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
11787 #[inline(always)]
11788 pub fn pwm_oen_cfg_2(&self) -> PwmOenCfg2R {
11789 PwmOenCfg2R::new((self.bits & 1) != 0)
11790 }
11791 }
11792 impl W {
11793 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
11794 #[inline(always)]
11795 pub fn pwm_oen_cfg_2(&mut self) -> PwmOenCfg2W<'_, PwmOenCfg2Spec> {
11796 PwmOenCfg2W::new(self, 0)
11797 }
11798 }
11799 #[doc = "PWM2 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11800 pub struct PwmOenCfg2Spec;
11801 impl crate::RegisterSpec for PwmOenCfg2Spec {
11802 type Ux = u32;
11803 }
11804 #[doc = "`read()` method returns [`pwm_oen_cfg2::R`](R) reader structure"]
11805 impl crate::Readable for PwmOenCfg2Spec {}
11806 #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg2::W`](W) writer structure"]
11807 impl crate::Writable for PwmOenCfg2Spec {
11808 type Safety = crate::Unsafe;
11809 }
11810 #[doc = "`reset()` method sets PWM_OEN_CFG2 to value 0"]
11811 impl crate::Resettable for PwmOenCfg2Spec {}
11812 }
11813 #[doc = "PWM_OFFSET_L2 (rw) register accessor: PWM2 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l2`] module"]
11814 #[doc(alias = "PWM_OFFSET_L2")]
11815 pub type PwmOffsetL2 = crate::Reg<pwm_offset_l2::PwmOffsetL2Spec>;
11816 #[doc = "PWM2 phase offset low 16 bits"]
11817 pub mod pwm_offset_l2 {
11818 #[doc = "Register `PWM_OFFSET_L2` reader"]
11819 pub type R = crate::R<PwmOffsetL2Spec>;
11820 #[doc = "Register `PWM_OFFSET_L2` writer"]
11821 pub type W = crate::W<PwmOffsetL2Spec>;
11822 #[doc = "Field `pwm_offset_l_2` reader - PWM0 phase offset low 16 bits"]
11823 pub type PwmOffsetL2R = crate::FieldReader<u16>;
11824 #[doc = "Field `pwm_offset_l_2` writer - PWM0 phase offset low 16 bits"]
11825 pub type PwmOffsetL2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11826 impl R {
11827 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
11828 #[inline(always)]
11829 pub fn pwm_offset_l_2(&self) -> PwmOffsetL2R {
11830 PwmOffsetL2R::new((self.bits & 0xffff) as u16)
11831 }
11832 }
11833 impl W {
11834 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
11835 #[inline(always)]
11836 pub fn pwm_offset_l_2(&mut self) -> PwmOffsetL2W<'_, PwmOffsetL2Spec> {
11837 PwmOffsetL2W::new(self, 0)
11838 }
11839 }
11840 #[doc = "PWM2 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11841 pub struct PwmOffsetL2Spec;
11842 impl crate::RegisterSpec for PwmOffsetL2Spec {
11843 type Ux = u32;
11844 }
11845 #[doc = "`read()` method returns [`pwm_offset_l2::R`](R) reader structure"]
11846 impl crate::Readable for PwmOffsetL2Spec {}
11847 #[doc = "`write(|w| ..)` method takes [`pwm_offset_l2::W`](W) writer structure"]
11848 impl crate::Writable for PwmOffsetL2Spec {
11849 type Safety = crate::Unsafe;
11850 }
11851 #[doc = "`reset()` method sets PWM_OFFSET_L2 to value 0"]
11852 impl crate::Resettable for PwmOffsetL2Spec {}
11853 }
11854 #[doc = "PWM_OFFSET_H2 (rw) register accessor: PWM2 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h2`] module"]
11855 #[doc(alias = "PWM_OFFSET_H2")]
11856 pub type PwmOffsetH2 = crate::Reg<pwm_offset_h2::PwmOffsetH2Spec>;
11857 #[doc = "PWM2 phase offset high 16 bits"]
11858 pub mod pwm_offset_h2 {
11859 #[doc = "Register `PWM_OFFSET_H2` reader"]
11860 pub type R = crate::R<PwmOffsetH2Spec>;
11861 #[doc = "Register `PWM_OFFSET_H2` writer"]
11862 pub type W = crate::W<PwmOffsetH2Spec>;
11863 #[doc = "Field `pwm_offset_h_2` reader - PWM0 phase offset high 16 bits"]
11864 pub type PwmOffsetH2R = crate::FieldReader<u16>;
11865 #[doc = "Field `pwm_offset_h_2` writer - PWM0 phase offset high 16 bits"]
11866 pub type PwmOffsetH2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11867 impl R {
11868 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
11869 #[inline(always)]
11870 pub fn pwm_offset_h_2(&self) -> PwmOffsetH2R {
11871 PwmOffsetH2R::new((self.bits & 0xffff) as u16)
11872 }
11873 }
11874 impl W {
11875 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
11876 #[inline(always)]
11877 pub fn pwm_offset_h_2(&mut self) -> PwmOffsetH2W<'_, PwmOffsetH2Spec> {
11878 PwmOffsetH2W::new(self, 0)
11879 }
11880 }
11881 #[doc = "PWM2 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11882 pub struct PwmOffsetH2Spec;
11883 impl crate::RegisterSpec for PwmOffsetH2Spec {
11884 type Ux = u32;
11885 }
11886 #[doc = "`read()` method returns [`pwm_offset_h2::R`](R) reader structure"]
11887 impl crate::Readable for PwmOffsetH2Spec {}
11888 #[doc = "`write(|w| ..)` method takes [`pwm_offset_h2::W`](W) writer structure"]
11889 impl crate::Writable for PwmOffsetH2Spec {
11890 type Safety = crate::Unsafe;
11891 }
11892 #[doc = "`reset()` method sets PWM_OFFSET_H2 to value 0"]
11893 impl crate::Resettable for PwmOffsetH2Spec {}
11894 }
11895 #[doc = "PWM_FREQ_L2 (rw) register accessor: PWM2 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l2`] module"]
11896 #[doc(alias = "PWM_FREQ_L2")]
11897 pub type PwmFreqL2 = crate::Reg<pwm_freq_l2::PwmFreqL2Spec>;
11898 #[doc = "PWM2 frequency low 16 bits"]
11899 pub mod pwm_freq_l2 {
11900 #[doc = "Register `PWM_FREQ_L2` reader"]
11901 pub type R = crate::R<PwmFreqL2Spec>;
11902 #[doc = "Register `PWM_FREQ_L2` writer"]
11903 pub type W = crate::W<PwmFreqL2Spec>;
11904 #[doc = "Field `pwm_freq_l_2` reader - PWM0 clock divider low 16 bits"]
11905 pub type PwmFreqL2R = crate::FieldReader<u16>;
11906 #[doc = "Field `pwm_freq_l_2` writer - PWM0 clock divider low 16 bits"]
11907 pub type PwmFreqL2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11908 impl R {
11909 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
11910 #[inline(always)]
11911 pub fn pwm_freq_l_2(&self) -> PwmFreqL2R {
11912 PwmFreqL2R::new((self.bits & 0xffff) as u16)
11913 }
11914 }
11915 impl W {
11916 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
11917 #[inline(always)]
11918 pub fn pwm_freq_l_2(&mut self) -> PwmFreqL2W<'_, PwmFreqL2Spec> {
11919 PwmFreqL2W::new(self, 0)
11920 }
11921 }
11922 #[doc = "PWM2 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11923 pub struct PwmFreqL2Spec;
11924 impl crate::RegisterSpec for PwmFreqL2Spec {
11925 type Ux = u32;
11926 }
11927 #[doc = "`read()` method returns [`pwm_freq_l2::R`](R) reader structure"]
11928 impl crate::Readable for PwmFreqL2Spec {}
11929 #[doc = "`write(|w| ..)` method takes [`pwm_freq_l2::W`](W) writer structure"]
11930 impl crate::Writable for PwmFreqL2Spec {
11931 type Safety = crate::Unsafe;
11932 }
11933 #[doc = "`reset()` method sets PWM_FREQ_L2 to value 0"]
11934 impl crate::Resettable for PwmFreqL2Spec {}
11935 }
11936 #[doc = "PWM_FREQ_H2 (rw) register accessor: PWM2 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h2`] module"]
11937 #[doc(alias = "PWM_FREQ_H2")]
11938 pub type PwmFreqH2 = crate::Reg<pwm_freq_h2::PwmFreqH2Spec>;
11939 #[doc = "PWM2 frequency high 16 bits"]
11940 pub mod pwm_freq_h2 {
11941 #[doc = "Register `PWM_FREQ_H2` reader"]
11942 pub type R = crate::R<PwmFreqH2Spec>;
11943 #[doc = "Register `PWM_FREQ_H2` writer"]
11944 pub type W = crate::W<PwmFreqH2Spec>;
11945 #[doc = "Field `pwm_freq_h_2` reader - PWM0 clock divider high 16 bits"]
11946 pub type PwmFreqH2R = crate::FieldReader<u16>;
11947 #[doc = "Field `pwm_freq_h_2` writer - PWM0 clock divider high 16 bits"]
11948 pub type PwmFreqH2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11949 impl R {
11950 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
11951 #[inline(always)]
11952 pub fn pwm_freq_h_2(&self) -> PwmFreqH2R {
11953 PwmFreqH2R::new((self.bits & 0xffff) as u16)
11954 }
11955 }
11956 impl W {
11957 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
11958 #[inline(always)]
11959 pub fn pwm_freq_h_2(&mut self) -> PwmFreqH2W<'_, PwmFreqH2Spec> {
11960 PwmFreqH2W::new(self, 0)
11961 }
11962 }
11963 #[doc = "PWM2 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
11964 pub struct PwmFreqH2Spec;
11965 impl crate::RegisterSpec for PwmFreqH2Spec {
11966 type Ux = u32;
11967 }
11968 #[doc = "`read()` method returns [`pwm_freq_h2::R`](R) reader structure"]
11969 impl crate::Readable for PwmFreqH2Spec {}
11970 #[doc = "`write(|w| ..)` method takes [`pwm_freq_h2::W`](W) writer structure"]
11971 impl crate::Writable for PwmFreqH2Spec {
11972 type Safety = crate::Unsafe;
11973 }
11974 #[doc = "`reset()` method sets PWM_FREQ_H2 to value 0"]
11975 impl crate::Resettable for PwmFreqH2Spec {}
11976 }
11977 #[doc = "PWM_DUTY_L2 (rw) register accessor: PWM2 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l2`] module"]
11978 #[doc(alias = "PWM_DUTY_L2")]
11979 pub type PwmDutyL2 = crate::Reg<pwm_duty_l2::PwmDutyL2Spec>;
11980 #[doc = "PWM2 duty cycle low 16 bits"]
11981 pub mod pwm_duty_l2 {
11982 #[doc = "Register `PWM_DUTY_L2` reader"]
11983 pub type R = crate::R<PwmDutyL2Spec>;
11984 #[doc = "Register `PWM_DUTY_L2` writer"]
11985 pub type W = crate::W<PwmDutyL2Spec>;
11986 #[doc = "Field `pwm_duty_l_2` reader - PWM0 duty cycle low 16 bits"]
11987 pub type PwmDutyL2R = crate::FieldReader<u16>;
11988 #[doc = "Field `pwm_duty_l_2` writer - PWM0 duty cycle low 16 bits"]
11989 pub type PwmDutyL2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11990 impl R {
11991 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
11992 #[inline(always)]
11993 pub fn pwm_duty_l_2(&self) -> PwmDutyL2R {
11994 PwmDutyL2R::new((self.bits & 0xffff) as u16)
11995 }
11996 }
11997 impl W {
11998 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
11999 #[inline(always)]
12000 pub fn pwm_duty_l_2(&mut self) -> PwmDutyL2W<'_, PwmDutyL2Spec> {
12001 PwmDutyL2W::new(self, 0)
12002 }
12003 }
12004 #[doc = "PWM2 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12005 pub struct PwmDutyL2Spec;
12006 impl crate::RegisterSpec for PwmDutyL2Spec {
12007 type Ux = u32;
12008 }
12009 #[doc = "`read()` method returns [`pwm_duty_l2::R`](R) reader structure"]
12010 impl crate::Readable for PwmDutyL2Spec {}
12011 #[doc = "`write(|w| ..)` method takes [`pwm_duty_l2::W`](W) writer structure"]
12012 impl crate::Writable for PwmDutyL2Spec {
12013 type Safety = crate::Unsafe;
12014 }
12015 #[doc = "`reset()` method sets PWM_DUTY_L2 to value 0"]
12016 impl crate::Resettable for PwmDutyL2Spec {}
12017 }
12018 #[doc = "PWM_DUTY_H2 (rw) register accessor: PWM2 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h2`] module"]
12019 #[doc(alias = "PWM_DUTY_H2")]
12020 pub type PwmDutyH2 = crate::Reg<pwm_duty_h2::PwmDutyH2Spec>;
12021 #[doc = "PWM2 duty cycle high 16 bits"]
12022 pub mod pwm_duty_h2 {
12023 #[doc = "Register `PWM_DUTY_H2` reader"]
12024 pub type R = crate::R<PwmDutyH2Spec>;
12025 #[doc = "Register `PWM_DUTY_H2` writer"]
12026 pub type W = crate::W<PwmDutyH2Spec>;
12027 #[doc = "Field `pwm_duty_h_2` reader - PWM0 duty cycle high 16 bits"]
12028 pub type PwmDutyH2R = crate::FieldReader<u16>;
12029 #[doc = "Field `pwm_duty_h_2` writer - PWM0 duty cycle high 16 bits"]
12030 pub type PwmDutyH2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12031 impl R {
12032 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
12033 #[inline(always)]
12034 pub fn pwm_duty_h_2(&self) -> PwmDutyH2R {
12035 PwmDutyH2R::new((self.bits & 0xffff) as u16)
12036 }
12037 }
12038 impl W {
12039 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
12040 #[inline(always)]
12041 pub fn pwm_duty_h_2(&mut self) -> PwmDutyH2W<'_, PwmDutyH2Spec> {
12042 PwmDutyH2W::new(self, 0)
12043 }
12044 }
12045 #[doc = "PWM2 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12046 pub struct PwmDutyH2Spec;
12047 impl crate::RegisterSpec for PwmDutyH2Spec {
12048 type Ux = u32;
12049 }
12050 #[doc = "`read()` method returns [`pwm_duty_h2::R`](R) reader structure"]
12051 impl crate::Readable for PwmDutyH2Spec {}
12052 #[doc = "`write(|w| ..)` method takes [`pwm_duty_h2::W`](W) writer structure"]
12053 impl crate::Writable for PwmDutyH2Spec {
12054 type Safety = crate::Unsafe;
12055 }
12056 #[doc = "`reset()` method sets PWM_DUTY_H2 to value 0"]
12057 impl crate::Resettable for PwmDutyH2Spec {}
12058 }
12059 #[doc = "PWM_PERIODLOAD_FLAG2 (rw) register accessor: PWM2 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag2`] module"]
12060 #[doc(alias = "PWM_PERIODLOAD_FLAG2")]
12061 pub type PwmPeriodloadFlag2 = crate::Reg<pwm_periodload_flag2::PwmPeriodloadFlag2Spec>;
12062 #[doc = "PWM2 period load flag"]
12063 pub mod pwm_periodload_flag2 {
12064 #[doc = "Register `PWM_PERIODLOAD_FLAG2` reader"]
12065 pub type R = crate::R<PwmPeriodloadFlag2Spec>;
12066 #[doc = "Register `PWM_PERIODLOAD_FLAG2` writer"]
12067 pub type W = crate::W<PwmPeriodloadFlag2Spec>;
12068 #[doc = "Field `pwm_periodload_flag_2` reader - Period load complete flag"]
12069 pub type PwmPeriodloadFlag2R = crate::BitReader;
12070 impl R {
12071 #[doc = "Bit 0 - Period load complete flag"]
12072 #[inline(always)]
12073 pub fn pwm_periodload_flag_2(&self) -> PwmPeriodloadFlag2R {
12074 PwmPeriodloadFlag2R::new((self.bits & 1) != 0)
12075 }
12076 }
12077 impl W {}
12078 #[doc = "PWM2 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12079 pub struct PwmPeriodloadFlag2Spec;
12080 impl crate::RegisterSpec for PwmPeriodloadFlag2Spec {
12081 type Ux = u32;
12082 }
12083 #[doc = "`read()` method returns [`pwm_periodload_flag2::R`](R) reader structure"]
12084 impl crate::Readable for PwmPeriodloadFlag2Spec {}
12085 #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag2::W`](W) writer structure"]
12086 impl crate::Writable for PwmPeriodloadFlag2Spec {
12087 type Safety = crate::Unsafe;
12088 }
12089 #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG2 to value 0"]
12090 impl crate::Resettable for PwmPeriodloadFlag2Spec {}
12091 }
12092 #[doc = "PWM_PERIOD_VAL2 (rw) register accessor: PWM2 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val2`] module"]
12093 #[doc(alias = "PWM_PERIOD_VAL2")]
12094 pub type PwmPeriodVal2 = crate::Reg<pwm_period_val2::PwmPeriodVal2Spec>;
12095 #[doc = "PWM2 pulse count value"]
12096 pub mod pwm_period_val2 {
12097 #[doc = "Register `PWM_PERIOD_VAL2` reader"]
12098 pub type R = crate::R<PwmPeriodVal2Spec>;
12099 #[doc = "Register `PWM_PERIOD_VAL2` writer"]
12100 pub type W = crate::W<PwmPeriodVal2Spec>;
12101 #[doc = "Field `pwm_period_val_2` reader - Pulse count for stepping mode"]
12102 pub type PwmPeriodVal2R = crate::FieldReader<u16>;
12103 #[doc = "Field `pwm_period_val_2` writer - Pulse count for stepping mode"]
12104 pub type PwmPeriodVal2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12105 impl R {
12106 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
12107 #[inline(always)]
12108 pub fn pwm_period_val_2(&self) -> PwmPeriodVal2R {
12109 PwmPeriodVal2R::new((self.bits & 0xffff) as u16)
12110 }
12111 }
12112 impl W {
12113 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
12114 #[inline(always)]
12115 pub fn pwm_period_val_2(&mut self) -> PwmPeriodVal2W<'_, PwmPeriodVal2Spec> {
12116 PwmPeriodVal2W::new(self, 0)
12117 }
12118 }
12119 #[doc = "PWM2 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12120 pub struct PwmPeriodVal2Spec;
12121 impl crate::RegisterSpec for PwmPeriodVal2Spec {
12122 type Ux = u32;
12123 }
12124 #[doc = "`read()` method returns [`pwm_period_val2::R`](R) reader structure"]
12125 impl crate::Readable for PwmPeriodVal2Spec {}
12126 #[doc = "`write(|w| ..)` method takes [`pwm_period_val2::W`](W) writer structure"]
12127 impl crate::Writable for PwmPeriodVal2Spec {
12128 type Safety = crate::Unsafe;
12129 }
12130 #[doc = "`reset()` method sets PWM_PERIOD_VAL2 to value 0"]
12131 impl crate::Resettable for PwmPeriodVal2Spec {}
12132 }
12133 #[doc = "PWM_PERIODCNT2 (rw) register accessor: PWM2 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt2`] module"]
12134 #[doc(alias = "PWM_PERIODCNT2")]
12135 pub type PwmPeriodcnt2 = crate::Reg<pwm_periodcnt2::PwmPeriodcnt2Spec>;
12136 #[doc = "PWM2 pulse count current value"]
12137 pub mod pwm_periodcnt2 {
12138 #[doc = "Register `PWM_PERIODCNT2` reader"]
12139 pub type R = crate::R<PwmPeriodcnt2Spec>;
12140 #[doc = "Register `PWM_PERIODCNT2` writer"]
12141 pub type W = crate::W<PwmPeriodcnt2Spec>;
12142 #[doc = "Field `pwm_periodcnt_2` reader - Current pulse count"]
12143 pub type PwmPeriodcnt2R = crate::FieldReader<u16>;
12144 impl R {
12145 #[doc = "Bits 0:15 - Current pulse count"]
12146 #[inline(always)]
12147 pub fn pwm_periodcnt_2(&self) -> PwmPeriodcnt2R {
12148 PwmPeriodcnt2R::new((self.bits & 0xffff) as u16)
12149 }
12150 }
12151 impl W {}
12152 #[doc = "PWM2 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12153 pub struct PwmPeriodcnt2Spec;
12154 impl crate::RegisterSpec for PwmPeriodcnt2Spec {
12155 type Ux = u32;
12156 }
12157 #[doc = "`read()` method returns [`pwm_periodcnt2::R`](R) reader structure"]
12158 impl crate::Readable for PwmPeriodcnt2Spec {}
12159 #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt2::W`](W) writer structure"]
12160 impl crate::Writable for PwmPeriodcnt2Spec {
12161 type Safety = crate::Unsafe;
12162 }
12163 #[doc = "`reset()` method sets PWM_PERIODCNT2 to value 0"]
12164 impl crate::Resettable for PwmPeriodcnt2Spec {}
12165 }
12166 #[doc = "PWM_EN3 (rw) register accessor: PWM3 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en3`] module"]
12167 #[doc(alias = "PWM_EN3")]
12168 pub type PwmEn3 = crate::Reg<pwm_en3::PwmEn3Spec>;
12169 #[doc = "PWM3 enable"]
12170 pub mod pwm_en3 {
12171 #[doc = "Register `PWM_EN3` reader"]
12172 pub type R = crate::R<PwmEn3Spec>;
12173 #[doc = "Register `PWM_EN3` writer"]
12174 pub type W = crate::W<PwmEn3Spec>;
12175 #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
12176 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
12177 pub enum PwmEn3 {
12178 #[doc = "0: PWM disabled, output low"]
12179 Off = 0,
12180 #[doc = "1: PWM enabled"]
12181 On = 1,
12182 }
12183 impl From<PwmEn3> for bool {
12184 #[inline(always)]
12185 fn from(variant: PwmEn3) -> Self {
12186 variant as u8 != 0
12187 }
12188 }
12189 #[doc = "Field `pwm_en_3` reader - PWM0 enable: 0=off; 1=on"]
12190 pub type PwmEn3R = crate::BitReader<PwmEn3>;
12191 impl PwmEn3R {
12192 #[doc = "Get enumerated values variant"]
12193 #[inline(always)]
12194 pub const fn variant(&self) -> PwmEn3 {
12195 match self.bits {
12196 false => PwmEn3::Off,
12197 true => PwmEn3::On,
12198 }
12199 }
12200 #[doc = "PWM disabled, output low"]
12201 #[inline(always)]
12202 pub fn is_off(&self) -> bool {
12203 *self == PwmEn3::Off
12204 }
12205 #[doc = "PWM enabled"]
12206 #[inline(always)]
12207 pub fn is_on(&self) -> bool {
12208 *self == PwmEn3::On
12209 }
12210 }
12211 #[doc = "Field `pwm_en_3` writer - PWM0 enable: 0=off; 1=on"]
12212 pub type PwmEn3W<'a, REG> = crate::BitWriter<'a, REG, PwmEn3>;
12213 impl<'a, REG> PwmEn3W<'a, REG>
12214 where
12215 REG: crate::Writable + crate::RegisterSpec,
12216 {
12217 #[doc = "PWM disabled, output low"]
12218 #[inline(always)]
12219 pub fn off(self) -> &'a mut crate::W<REG> {
12220 self.variant(PwmEn3::Off)
12221 }
12222 #[doc = "PWM enabled"]
12223 #[inline(always)]
12224 pub fn on(self) -> &'a mut crate::W<REG> {
12225 self.variant(PwmEn3::On)
12226 }
12227 }
12228 impl R {
12229 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
12230 #[inline(always)]
12231 pub fn pwm_en_3(&self) -> PwmEn3R {
12232 PwmEn3R::new((self.bits & 1) != 0)
12233 }
12234 }
12235 impl W {
12236 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
12237 #[inline(always)]
12238 pub fn pwm_en_3(&mut self) -> PwmEn3W<'_, PwmEn3Spec> {
12239 PwmEn3W::new(self, 0)
12240 }
12241 }
12242 #[doc = "PWM3 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12243 pub struct PwmEn3Spec;
12244 impl crate::RegisterSpec for PwmEn3Spec {
12245 type Ux = u32;
12246 }
12247 #[doc = "`read()` method returns [`pwm_en3::R`](R) reader structure"]
12248 impl crate::Readable for PwmEn3Spec {}
12249 #[doc = "`write(|w| ..)` method takes [`pwm_en3::W`](W) writer structure"]
12250 impl crate::Writable for PwmEn3Spec {
12251 type Safety = crate::Unsafe;
12252 }
12253 #[doc = "`reset()` method sets PWM_EN3 to value 0"]
12254 impl crate::Resettable for PwmEn3Spec {}
12255 }
12256 #[doc = "PWM_PORTITY3 (rw) register accessor: PWM3 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity3`] module"]
12257 #[doc(alias = "PWM_PORTITY3")]
12258 pub type PwmPortity3 = crate::Reg<pwm_portity3::PwmPortity3Spec>;
12259 #[doc = "PWM3 polarity"]
12260 pub mod pwm_portity3 {
12261 #[doc = "Register `PWM_PORTITY3` reader"]
12262 pub type R = crate::R<PwmPortity3Spec>;
12263 #[doc = "Register `PWM_PORTITY3` writer"]
12264 pub type W = crate::W<PwmPortity3Spec>;
12265 #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
12266 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
12267 pub enum PwmPoarity3 {
12268 #[doc = "0: Normal polarity"]
12269 Normal = 0,
12270 #[doc = "1: Inverted polarity"]
12271 Inverted = 1,
12272 }
12273 impl From<PwmPoarity3> for bool {
12274 #[inline(always)]
12275 fn from(variant: PwmPoarity3) -> Self {
12276 variant as u8 != 0
12277 }
12278 }
12279 #[doc = "Field `pwm_poarity_3` reader - PWM0 polarity: 0=normal; 1=inverted"]
12280 pub type PwmPoarity3R = crate::BitReader<PwmPoarity3>;
12281 impl PwmPoarity3R {
12282 #[doc = "Get enumerated values variant"]
12283 #[inline(always)]
12284 pub const fn variant(&self) -> PwmPoarity3 {
12285 match self.bits {
12286 false => PwmPoarity3::Normal,
12287 true => PwmPoarity3::Inverted,
12288 }
12289 }
12290 #[doc = "Normal polarity"]
12291 #[inline(always)]
12292 pub fn is_normal(&self) -> bool {
12293 *self == PwmPoarity3::Normal
12294 }
12295 #[doc = "Inverted polarity"]
12296 #[inline(always)]
12297 pub fn is_inverted(&self) -> bool {
12298 *self == PwmPoarity3::Inverted
12299 }
12300 }
12301 #[doc = "Field `pwm_poarity_3` writer - PWM0 polarity: 0=normal; 1=inverted"]
12302 pub type PwmPoarity3W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity3>;
12303 impl<'a, REG> PwmPoarity3W<'a, REG>
12304 where
12305 REG: crate::Writable + crate::RegisterSpec,
12306 {
12307 #[doc = "Normal polarity"]
12308 #[inline(always)]
12309 pub fn normal(self) -> &'a mut crate::W<REG> {
12310 self.variant(PwmPoarity3::Normal)
12311 }
12312 #[doc = "Inverted polarity"]
12313 #[inline(always)]
12314 pub fn inverted(self) -> &'a mut crate::W<REG> {
12315 self.variant(PwmPoarity3::Inverted)
12316 }
12317 }
12318 impl R {
12319 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
12320 #[inline(always)]
12321 pub fn pwm_poarity_3(&self) -> PwmPoarity3R {
12322 PwmPoarity3R::new((self.bits & 1) != 0)
12323 }
12324 }
12325 impl W {
12326 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
12327 #[inline(always)]
12328 pub fn pwm_poarity_3(&mut self) -> PwmPoarity3W<'_, PwmPortity3Spec> {
12329 PwmPoarity3W::new(self, 0)
12330 }
12331 }
12332 #[doc = "PWM3 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12333 pub struct PwmPortity3Spec;
12334 impl crate::RegisterSpec for PwmPortity3Spec {
12335 type Ux = u32;
12336 }
12337 #[doc = "`read()` method returns [`pwm_portity3::R`](R) reader structure"]
12338 impl crate::Readable for PwmPortity3Spec {}
12339 #[doc = "`write(|w| ..)` method takes [`pwm_portity3::W`](W) writer structure"]
12340 impl crate::Writable for PwmPortity3Spec {
12341 type Safety = crate::Unsafe;
12342 }
12343 #[doc = "`reset()` method sets PWM_PORTITY3 to value 0"]
12344 impl crate::Resettable for PwmPortity3Spec {}
12345 }
12346 #[doc = "PWM_OEN_CFG3 (rw) register accessor: PWM3 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg3`] module"]
12347 #[doc(alias = "PWM_OEN_CFG3")]
12348 pub type PwmOenCfg3 = crate::Reg<pwm_oen_cfg3::PwmOenCfg3Spec>;
12349 #[doc = "PWM3 high-impedance config"]
12350 pub mod pwm_oen_cfg3 {
12351 #[doc = "Register `PWM_OEN_CFG3` reader"]
12352 pub type R = crate::R<PwmOenCfg3Spec>;
12353 #[doc = "Register `PWM_OEN_CFG3` writer"]
12354 pub type W = crate::W<PwmOenCfg3Spec>;
12355 #[doc = "Field `pwm_oen_cfg_3` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12356 pub type PwmOenCfg3R = crate::BitReader;
12357 #[doc = "Field `pwm_oen_cfg_3` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12358 pub type PwmOenCfg3W<'a, REG> = crate::BitWriter<'a, REG>;
12359 impl R {
12360 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12361 #[inline(always)]
12362 pub fn pwm_oen_cfg_3(&self) -> PwmOenCfg3R {
12363 PwmOenCfg3R::new((self.bits & 1) != 0)
12364 }
12365 }
12366 impl W {
12367 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12368 #[inline(always)]
12369 pub fn pwm_oen_cfg_3(&mut self) -> PwmOenCfg3W<'_, PwmOenCfg3Spec> {
12370 PwmOenCfg3W::new(self, 0)
12371 }
12372 }
12373 #[doc = "PWM3 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12374 pub struct PwmOenCfg3Spec;
12375 impl crate::RegisterSpec for PwmOenCfg3Spec {
12376 type Ux = u32;
12377 }
12378 #[doc = "`read()` method returns [`pwm_oen_cfg3::R`](R) reader structure"]
12379 impl crate::Readable for PwmOenCfg3Spec {}
12380 #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg3::W`](W) writer structure"]
12381 impl crate::Writable for PwmOenCfg3Spec {
12382 type Safety = crate::Unsafe;
12383 }
12384 #[doc = "`reset()` method sets PWM_OEN_CFG3 to value 0"]
12385 impl crate::Resettable for PwmOenCfg3Spec {}
12386 }
12387 #[doc = "PWM_OFFSET_L3 (rw) register accessor: PWM3 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l3`] module"]
12388 #[doc(alias = "PWM_OFFSET_L3")]
12389 pub type PwmOffsetL3 = crate::Reg<pwm_offset_l3::PwmOffsetL3Spec>;
12390 #[doc = "PWM3 phase offset low 16 bits"]
12391 pub mod pwm_offset_l3 {
12392 #[doc = "Register `PWM_OFFSET_L3` reader"]
12393 pub type R = crate::R<PwmOffsetL3Spec>;
12394 #[doc = "Register `PWM_OFFSET_L3` writer"]
12395 pub type W = crate::W<PwmOffsetL3Spec>;
12396 #[doc = "Field `pwm_offset_l_3` reader - PWM0 phase offset low 16 bits"]
12397 pub type PwmOffsetL3R = crate::FieldReader<u16>;
12398 #[doc = "Field `pwm_offset_l_3` writer - PWM0 phase offset low 16 bits"]
12399 pub type PwmOffsetL3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12400 impl R {
12401 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
12402 #[inline(always)]
12403 pub fn pwm_offset_l_3(&self) -> PwmOffsetL3R {
12404 PwmOffsetL3R::new((self.bits & 0xffff) as u16)
12405 }
12406 }
12407 impl W {
12408 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
12409 #[inline(always)]
12410 pub fn pwm_offset_l_3(&mut self) -> PwmOffsetL3W<'_, PwmOffsetL3Spec> {
12411 PwmOffsetL3W::new(self, 0)
12412 }
12413 }
12414 #[doc = "PWM3 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12415 pub struct PwmOffsetL3Spec;
12416 impl crate::RegisterSpec for PwmOffsetL3Spec {
12417 type Ux = u32;
12418 }
12419 #[doc = "`read()` method returns [`pwm_offset_l3::R`](R) reader structure"]
12420 impl crate::Readable for PwmOffsetL3Spec {}
12421 #[doc = "`write(|w| ..)` method takes [`pwm_offset_l3::W`](W) writer structure"]
12422 impl crate::Writable for PwmOffsetL3Spec {
12423 type Safety = crate::Unsafe;
12424 }
12425 #[doc = "`reset()` method sets PWM_OFFSET_L3 to value 0"]
12426 impl crate::Resettable for PwmOffsetL3Spec {}
12427 }
12428 #[doc = "PWM_OFFSET_H3 (rw) register accessor: PWM3 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h3`] module"]
12429 #[doc(alias = "PWM_OFFSET_H3")]
12430 pub type PwmOffsetH3 = crate::Reg<pwm_offset_h3::PwmOffsetH3Spec>;
12431 #[doc = "PWM3 phase offset high 16 bits"]
12432 pub mod pwm_offset_h3 {
12433 #[doc = "Register `PWM_OFFSET_H3` reader"]
12434 pub type R = crate::R<PwmOffsetH3Spec>;
12435 #[doc = "Register `PWM_OFFSET_H3` writer"]
12436 pub type W = crate::W<PwmOffsetH3Spec>;
12437 #[doc = "Field `pwm_offset_h_3` reader - PWM0 phase offset high 16 bits"]
12438 pub type PwmOffsetH3R = crate::FieldReader<u16>;
12439 #[doc = "Field `pwm_offset_h_3` writer - PWM0 phase offset high 16 bits"]
12440 pub type PwmOffsetH3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12441 impl R {
12442 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
12443 #[inline(always)]
12444 pub fn pwm_offset_h_3(&self) -> PwmOffsetH3R {
12445 PwmOffsetH3R::new((self.bits & 0xffff) as u16)
12446 }
12447 }
12448 impl W {
12449 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
12450 #[inline(always)]
12451 pub fn pwm_offset_h_3(&mut self) -> PwmOffsetH3W<'_, PwmOffsetH3Spec> {
12452 PwmOffsetH3W::new(self, 0)
12453 }
12454 }
12455 #[doc = "PWM3 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12456 pub struct PwmOffsetH3Spec;
12457 impl crate::RegisterSpec for PwmOffsetH3Spec {
12458 type Ux = u32;
12459 }
12460 #[doc = "`read()` method returns [`pwm_offset_h3::R`](R) reader structure"]
12461 impl crate::Readable for PwmOffsetH3Spec {}
12462 #[doc = "`write(|w| ..)` method takes [`pwm_offset_h3::W`](W) writer structure"]
12463 impl crate::Writable for PwmOffsetH3Spec {
12464 type Safety = crate::Unsafe;
12465 }
12466 #[doc = "`reset()` method sets PWM_OFFSET_H3 to value 0"]
12467 impl crate::Resettable for PwmOffsetH3Spec {}
12468 }
12469 #[doc = "PWM_FREQ_L3 (rw) register accessor: PWM3 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l3`] module"]
12470 #[doc(alias = "PWM_FREQ_L3")]
12471 pub type PwmFreqL3 = crate::Reg<pwm_freq_l3::PwmFreqL3Spec>;
12472 #[doc = "PWM3 frequency low 16 bits"]
12473 pub mod pwm_freq_l3 {
12474 #[doc = "Register `PWM_FREQ_L3` reader"]
12475 pub type R = crate::R<PwmFreqL3Spec>;
12476 #[doc = "Register `PWM_FREQ_L3` writer"]
12477 pub type W = crate::W<PwmFreqL3Spec>;
12478 #[doc = "Field `pwm_freq_l_3` reader - PWM0 clock divider low 16 bits"]
12479 pub type PwmFreqL3R = crate::FieldReader<u16>;
12480 #[doc = "Field `pwm_freq_l_3` writer - PWM0 clock divider low 16 bits"]
12481 pub type PwmFreqL3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12482 impl R {
12483 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
12484 #[inline(always)]
12485 pub fn pwm_freq_l_3(&self) -> PwmFreqL3R {
12486 PwmFreqL3R::new((self.bits & 0xffff) as u16)
12487 }
12488 }
12489 impl W {
12490 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
12491 #[inline(always)]
12492 pub fn pwm_freq_l_3(&mut self) -> PwmFreqL3W<'_, PwmFreqL3Spec> {
12493 PwmFreqL3W::new(self, 0)
12494 }
12495 }
12496 #[doc = "PWM3 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12497 pub struct PwmFreqL3Spec;
12498 impl crate::RegisterSpec for PwmFreqL3Spec {
12499 type Ux = u32;
12500 }
12501 #[doc = "`read()` method returns [`pwm_freq_l3::R`](R) reader structure"]
12502 impl crate::Readable for PwmFreqL3Spec {}
12503 #[doc = "`write(|w| ..)` method takes [`pwm_freq_l3::W`](W) writer structure"]
12504 impl crate::Writable for PwmFreqL3Spec {
12505 type Safety = crate::Unsafe;
12506 }
12507 #[doc = "`reset()` method sets PWM_FREQ_L3 to value 0"]
12508 impl crate::Resettable for PwmFreqL3Spec {}
12509 }
12510 #[doc = "PWM_FREQ_H3 (rw) register accessor: PWM3 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h3`] module"]
12511 #[doc(alias = "PWM_FREQ_H3")]
12512 pub type PwmFreqH3 = crate::Reg<pwm_freq_h3::PwmFreqH3Spec>;
12513 #[doc = "PWM3 frequency high 16 bits"]
12514 pub mod pwm_freq_h3 {
12515 #[doc = "Register `PWM_FREQ_H3` reader"]
12516 pub type R = crate::R<PwmFreqH3Spec>;
12517 #[doc = "Register `PWM_FREQ_H3` writer"]
12518 pub type W = crate::W<PwmFreqH3Spec>;
12519 #[doc = "Field `pwm_freq_h_3` reader - PWM0 clock divider high 16 bits"]
12520 pub type PwmFreqH3R = crate::FieldReader<u16>;
12521 #[doc = "Field `pwm_freq_h_3` writer - PWM0 clock divider high 16 bits"]
12522 pub type PwmFreqH3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12523 impl R {
12524 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
12525 #[inline(always)]
12526 pub fn pwm_freq_h_3(&self) -> PwmFreqH3R {
12527 PwmFreqH3R::new((self.bits & 0xffff) as u16)
12528 }
12529 }
12530 impl W {
12531 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
12532 #[inline(always)]
12533 pub fn pwm_freq_h_3(&mut self) -> PwmFreqH3W<'_, PwmFreqH3Spec> {
12534 PwmFreqH3W::new(self, 0)
12535 }
12536 }
12537 #[doc = "PWM3 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12538 pub struct PwmFreqH3Spec;
12539 impl crate::RegisterSpec for PwmFreqH3Spec {
12540 type Ux = u32;
12541 }
12542 #[doc = "`read()` method returns [`pwm_freq_h3::R`](R) reader structure"]
12543 impl crate::Readable for PwmFreqH3Spec {}
12544 #[doc = "`write(|w| ..)` method takes [`pwm_freq_h3::W`](W) writer structure"]
12545 impl crate::Writable for PwmFreqH3Spec {
12546 type Safety = crate::Unsafe;
12547 }
12548 #[doc = "`reset()` method sets PWM_FREQ_H3 to value 0"]
12549 impl crate::Resettable for PwmFreqH3Spec {}
12550 }
12551 #[doc = "PWM_DUTY_L3 (rw) register accessor: PWM3 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l3`] module"]
12552 #[doc(alias = "PWM_DUTY_L3")]
12553 pub type PwmDutyL3 = crate::Reg<pwm_duty_l3::PwmDutyL3Spec>;
12554 #[doc = "PWM3 duty cycle low 16 bits"]
12555 pub mod pwm_duty_l3 {
12556 #[doc = "Register `PWM_DUTY_L3` reader"]
12557 pub type R = crate::R<PwmDutyL3Spec>;
12558 #[doc = "Register `PWM_DUTY_L3` writer"]
12559 pub type W = crate::W<PwmDutyL3Spec>;
12560 #[doc = "Field `pwm_duty_l_3` reader - PWM0 duty cycle low 16 bits"]
12561 pub type PwmDutyL3R = crate::FieldReader<u16>;
12562 #[doc = "Field `pwm_duty_l_3` writer - PWM0 duty cycle low 16 bits"]
12563 pub type PwmDutyL3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12564 impl R {
12565 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
12566 #[inline(always)]
12567 pub fn pwm_duty_l_3(&self) -> PwmDutyL3R {
12568 PwmDutyL3R::new((self.bits & 0xffff) as u16)
12569 }
12570 }
12571 impl W {
12572 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
12573 #[inline(always)]
12574 pub fn pwm_duty_l_3(&mut self) -> PwmDutyL3W<'_, PwmDutyL3Spec> {
12575 PwmDutyL3W::new(self, 0)
12576 }
12577 }
12578 #[doc = "PWM3 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12579 pub struct PwmDutyL3Spec;
12580 impl crate::RegisterSpec for PwmDutyL3Spec {
12581 type Ux = u32;
12582 }
12583 #[doc = "`read()` method returns [`pwm_duty_l3::R`](R) reader structure"]
12584 impl crate::Readable for PwmDutyL3Spec {}
12585 #[doc = "`write(|w| ..)` method takes [`pwm_duty_l3::W`](W) writer structure"]
12586 impl crate::Writable for PwmDutyL3Spec {
12587 type Safety = crate::Unsafe;
12588 }
12589 #[doc = "`reset()` method sets PWM_DUTY_L3 to value 0"]
12590 impl crate::Resettable for PwmDutyL3Spec {}
12591 }
12592 #[doc = "PWM_DUTY_H3 (rw) register accessor: PWM3 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h3`] module"]
12593 #[doc(alias = "PWM_DUTY_H3")]
12594 pub type PwmDutyH3 = crate::Reg<pwm_duty_h3::PwmDutyH3Spec>;
12595 #[doc = "PWM3 duty cycle high 16 bits"]
12596 pub mod pwm_duty_h3 {
12597 #[doc = "Register `PWM_DUTY_H3` reader"]
12598 pub type R = crate::R<PwmDutyH3Spec>;
12599 #[doc = "Register `PWM_DUTY_H3` writer"]
12600 pub type W = crate::W<PwmDutyH3Spec>;
12601 #[doc = "Field `pwm_duty_h_3` reader - PWM0 duty cycle high 16 bits"]
12602 pub type PwmDutyH3R = crate::FieldReader<u16>;
12603 #[doc = "Field `pwm_duty_h_3` writer - PWM0 duty cycle high 16 bits"]
12604 pub type PwmDutyH3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12605 impl R {
12606 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
12607 #[inline(always)]
12608 pub fn pwm_duty_h_3(&self) -> PwmDutyH3R {
12609 PwmDutyH3R::new((self.bits & 0xffff) as u16)
12610 }
12611 }
12612 impl W {
12613 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
12614 #[inline(always)]
12615 pub fn pwm_duty_h_3(&mut self) -> PwmDutyH3W<'_, PwmDutyH3Spec> {
12616 PwmDutyH3W::new(self, 0)
12617 }
12618 }
12619 #[doc = "PWM3 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12620 pub struct PwmDutyH3Spec;
12621 impl crate::RegisterSpec for PwmDutyH3Spec {
12622 type Ux = u32;
12623 }
12624 #[doc = "`read()` method returns [`pwm_duty_h3::R`](R) reader structure"]
12625 impl crate::Readable for PwmDutyH3Spec {}
12626 #[doc = "`write(|w| ..)` method takes [`pwm_duty_h3::W`](W) writer structure"]
12627 impl crate::Writable for PwmDutyH3Spec {
12628 type Safety = crate::Unsafe;
12629 }
12630 #[doc = "`reset()` method sets PWM_DUTY_H3 to value 0"]
12631 impl crate::Resettable for PwmDutyH3Spec {}
12632 }
12633 #[doc = "PWM_PERIODLOAD_FLAG3 (rw) register accessor: PWM3 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag3`] module"]
12634 #[doc(alias = "PWM_PERIODLOAD_FLAG3")]
12635 pub type PwmPeriodloadFlag3 = crate::Reg<pwm_periodload_flag3::PwmPeriodloadFlag3Spec>;
12636 #[doc = "PWM3 period load flag"]
12637 pub mod pwm_periodload_flag3 {
12638 #[doc = "Register `PWM_PERIODLOAD_FLAG3` reader"]
12639 pub type R = crate::R<PwmPeriodloadFlag3Spec>;
12640 #[doc = "Register `PWM_PERIODLOAD_FLAG3` writer"]
12641 pub type W = crate::W<PwmPeriodloadFlag3Spec>;
12642 #[doc = "Field `pwm_periodload_flag_3` reader - Period load complete flag"]
12643 pub type PwmPeriodloadFlag3R = crate::BitReader;
12644 impl R {
12645 #[doc = "Bit 0 - Period load complete flag"]
12646 #[inline(always)]
12647 pub fn pwm_periodload_flag_3(&self) -> PwmPeriodloadFlag3R {
12648 PwmPeriodloadFlag3R::new((self.bits & 1) != 0)
12649 }
12650 }
12651 impl W {}
12652 #[doc = "PWM3 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12653 pub struct PwmPeriodloadFlag3Spec;
12654 impl crate::RegisterSpec for PwmPeriodloadFlag3Spec {
12655 type Ux = u32;
12656 }
12657 #[doc = "`read()` method returns [`pwm_periodload_flag3::R`](R) reader structure"]
12658 impl crate::Readable for PwmPeriodloadFlag3Spec {}
12659 #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag3::W`](W) writer structure"]
12660 impl crate::Writable for PwmPeriodloadFlag3Spec {
12661 type Safety = crate::Unsafe;
12662 }
12663 #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG3 to value 0"]
12664 impl crate::Resettable for PwmPeriodloadFlag3Spec {}
12665 }
12666 #[doc = "PWM_PERIOD_VAL3 (rw) register accessor: PWM3 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val3`] module"]
12667 #[doc(alias = "PWM_PERIOD_VAL3")]
12668 pub type PwmPeriodVal3 = crate::Reg<pwm_period_val3::PwmPeriodVal3Spec>;
12669 #[doc = "PWM3 pulse count value"]
12670 pub mod pwm_period_val3 {
12671 #[doc = "Register `PWM_PERIOD_VAL3` reader"]
12672 pub type R = crate::R<PwmPeriodVal3Spec>;
12673 #[doc = "Register `PWM_PERIOD_VAL3` writer"]
12674 pub type W = crate::W<PwmPeriodVal3Spec>;
12675 #[doc = "Field `pwm_period_val_3` reader - Pulse count for stepping mode"]
12676 pub type PwmPeriodVal3R = crate::FieldReader<u16>;
12677 #[doc = "Field `pwm_period_val_3` writer - Pulse count for stepping mode"]
12678 pub type PwmPeriodVal3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12679 impl R {
12680 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
12681 #[inline(always)]
12682 pub fn pwm_period_val_3(&self) -> PwmPeriodVal3R {
12683 PwmPeriodVal3R::new((self.bits & 0xffff) as u16)
12684 }
12685 }
12686 impl W {
12687 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
12688 #[inline(always)]
12689 pub fn pwm_period_val_3(&mut self) -> PwmPeriodVal3W<'_, PwmPeriodVal3Spec> {
12690 PwmPeriodVal3W::new(self, 0)
12691 }
12692 }
12693 #[doc = "PWM3 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12694 pub struct PwmPeriodVal3Spec;
12695 impl crate::RegisterSpec for PwmPeriodVal3Spec {
12696 type Ux = u32;
12697 }
12698 #[doc = "`read()` method returns [`pwm_period_val3::R`](R) reader structure"]
12699 impl crate::Readable for PwmPeriodVal3Spec {}
12700 #[doc = "`write(|w| ..)` method takes [`pwm_period_val3::W`](W) writer structure"]
12701 impl crate::Writable for PwmPeriodVal3Spec {
12702 type Safety = crate::Unsafe;
12703 }
12704 #[doc = "`reset()` method sets PWM_PERIOD_VAL3 to value 0"]
12705 impl crate::Resettable for PwmPeriodVal3Spec {}
12706 }
12707 #[doc = "PWM_PERIODCNT3 (rw) register accessor: PWM3 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt3`] module"]
12708 #[doc(alias = "PWM_PERIODCNT3")]
12709 pub type PwmPeriodcnt3 = crate::Reg<pwm_periodcnt3::PwmPeriodcnt3Spec>;
12710 #[doc = "PWM3 pulse count current value"]
12711 pub mod pwm_periodcnt3 {
12712 #[doc = "Register `PWM_PERIODCNT3` reader"]
12713 pub type R = crate::R<PwmPeriodcnt3Spec>;
12714 #[doc = "Register `PWM_PERIODCNT3` writer"]
12715 pub type W = crate::W<PwmPeriodcnt3Spec>;
12716 #[doc = "Field `pwm_periodcnt_3` reader - Current pulse count"]
12717 pub type PwmPeriodcnt3R = crate::FieldReader<u16>;
12718 impl R {
12719 #[doc = "Bits 0:15 - Current pulse count"]
12720 #[inline(always)]
12721 pub fn pwm_periodcnt_3(&self) -> PwmPeriodcnt3R {
12722 PwmPeriodcnt3R::new((self.bits & 0xffff) as u16)
12723 }
12724 }
12725 impl W {}
12726 #[doc = "PWM3 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12727 pub struct PwmPeriodcnt3Spec;
12728 impl crate::RegisterSpec for PwmPeriodcnt3Spec {
12729 type Ux = u32;
12730 }
12731 #[doc = "`read()` method returns [`pwm_periodcnt3::R`](R) reader structure"]
12732 impl crate::Readable for PwmPeriodcnt3Spec {}
12733 #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt3::W`](W) writer structure"]
12734 impl crate::Writable for PwmPeriodcnt3Spec {
12735 type Safety = crate::Unsafe;
12736 }
12737 #[doc = "`reset()` method sets PWM_PERIODCNT3 to value 0"]
12738 impl crate::Resettable for PwmPeriodcnt3Spec {}
12739 }
12740 #[doc = "PWM_EN4 (rw) register accessor: PWM4 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en4`] module"]
12741 #[doc(alias = "PWM_EN4")]
12742 pub type PwmEn4 = crate::Reg<pwm_en4::PwmEn4Spec>;
12743 #[doc = "PWM4 enable"]
12744 pub mod pwm_en4 {
12745 #[doc = "Register `PWM_EN4` reader"]
12746 pub type R = crate::R<PwmEn4Spec>;
12747 #[doc = "Register `PWM_EN4` writer"]
12748 pub type W = crate::W<PwmEn4Spec>;
12749 #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
12750 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
12751 pub enum PwmEn4 {
12752 #[doc = "0: PWM disabled, output low"]
12753 Off = 0,
12754 #[doc = "1: PWM enabled"]
12755 On = 1,
12756 }
12757 impl From<PwmEn4> for bool {
12758 #[inline(always)]
12759 fn from(variant: PwmEn4) -> Self {
12760 variant as u8 != 0
12761 }
12762 }
12763 #[doc = "Field `pwm_en_4` reader - PWM0 enable: 0=off; 1=on"]
12764 pub type PwmEn4R = crate::BitReader<PwmEn4>;
12765 impl PwmEn4R {
12766 #[doc = "Get enumerated values variant"]
12767 #[inline(always)]
12768 pub const fn variant(&self) -> PwmEn4 {
12769 match self.bits {
12770 false => PwmEn4::Off,
12771 true => PwmEn4::On,
12772 }
12773 }
12774 #[doc = "PWM disabled, output low"]
12775 #[inline(always)]
12776 pub fn is_off(&self) -> bool {
12777 *self == PwmEn4::Off
12778 }
12779 #[doc = "PWM enabled"]
12780 #[inline(always)]
12781 pub fn is_on(&self) -> bool {
12782 *self == PwmEn4::On
12783 }
12784 }
12785 #[doc = "Field `pwm_en_4` writer - PWM0 enable: 0=off; 1=on"]
12786 pub type PwmEn4W<'a, REG> = crate::BitWriter<'a, REG, PwmEn4>;
12787 impl<'a, REG> PwmEn4W<'a, REG>
12788 where
12789 REG: crate::Writable + crate::RegisterSpec,
12790 {
12791 #[doc = "PWM disabled, output low"]
12792 #[inline(always)]
12793 pub fn off(self) -> &'a mut crate::W<REG> {
12794 self.variant(PwmEn4::Off)
12795 }
12796 #[doc = "PWM enabled"]
12797 #[inline(always)]
12798 pub fn on(self) -> &'a mut crate::W<REG> {
12799 self.variant(PwmEn4::On)
12800 }
12801 }
12802 impl R {
12803 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
12804 #[inline(always)]
12805 pub fn pwm_en_4(&self) -> PwmEn4R {
12806 PwmEn4R::new((self.bits & 1) != 0)
12807 }
12808 }
12809 impl W {
12810 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
12811 #[inline(always)]
12812 pub fn pwm_en_4(&mut self) -> PwmEn4W<'_, PwmEn4Spec> {
12813 PwmEn4W::new(self, 0)
12814 }
12815 }
12816 #[doc = "PWM4 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12817 pub struct PwmEn4Spec;
12818 impl crate::RegisterSpec for PwmEn4Spec {
12819 type Ux = u32;
12820 }
12821 #[doc = "`read()` method returns [`pwm_en4::R`](R) reader structure"]
12822 impl crate::Readable for PwmEn4Spec {}
12823 #[doc = "`write(|w| ..)` method takes [`pwm_en4::W`](W) writer structure"]
12824 impl crate::Writable for PwmEn4Spec {
12825 type Safety = crate::Unsafe;
12826 }
12827 #[doc = "`reset()` method sets PWM_EN4 to value 0"]
12828 impl crate::Resettable for PwmEn4Spec {}
12829 }
12830 #[doc = "PWM_PORTITY4 (rw) register accessor: PWM4 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity4`] module"]
12831 #[doc(alias = "PWM_PORTITY4")]
12832 pub type PwmPortity4 = crate::Reg<pwm_portity4::PwmPortity4Spec>;
12833 #[doc = "PWM4 polarity"]
12834 pub mod pwm_portity4 {
12835 #[doc = "Register `PWM_PORTITY4` reader"]
12836 pub type R = crate::R<PwmPortity4Spec>;
12837 #[doc = "Register `PWM_PORTITY4` writer"]
12838 pub type W = crate::W<PwmPortity4Spec>;
12839 #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
12840 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
12841 pub enum PwmPoarity4 {
12842 #[doc = "0: Normal polarity"]
12843 Normal = 0,
12844 #[doc = "1: Inverted polarity"]
12845 Inverted = 1,
12846 }
12847 impl From<PwmPoarity4> for bool {
12848 #[inline(always)]
12849 fn from(variant: PwmPoarity4) -> Self {
12850 variant as u8 != 0
12851 }
12852 }
12853 #[doc = "Field `pwm_poarity_4` reader - PWM0 polarity: 0=normal; 1=inverted"]
12854 pub type PwmPoarity4R = crate::BitReader<PwmPoarity4>;
12855 impl PwmPoarity4R {
12856 #[doc = "Get enumerated values variant"]
12857 #[inline(always)]
12858 pub const fn variant(&self) -> PwmPoarity4 {
12859 match self.bits {
12860 false => PwmPoarity4::Normal,
12861 true => PwmPoarity4::Inverted,
12862 }
12863 }
12864 #[doc = "Normal polarity"]
12865 #[inline(always)]
12866 pub fn is_normal(&self) -> bool {
12867 *self == PwmPoarity4::Normal
12868 }
12869 #[doc = "Inverted polarity"]
12870 #[inline(always)]
12871 pub fn is_inverted(&self) -> bool {
12872 *self == PwmPoarity4::Inverted
12873 }
12874 }
12875 #[doc = "Field `pwm_poarity_4` writer - PWM0 polarity: 0=normal; 1=inverted"]
12876 pub type PwmPoarity4W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity4>;
12877 impl<'a, REG> PwmPoarity4W<'a, REG>
12878 where
12879 REG: crate::Writable + crate::RegisterSpec,
12880 {
12881 #[doc = "Normal polarity"]
12882 #[inline(always)]
12883 pub fn normal(self) -> &'a mut crate::W<REG> {
12884 self.variant(PwmPoarity4::Normal)
12885 }
12886 #[doc = "Inverted polarity"]
12887 #[inline(always)]
12888 pub fn inverted(self) -> &'a mut crate::W<REG> {
12889 self.variant(PwmPoarity4::Inverted)
12890 }
12891 }
12892 impl R {
12893 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
12894 #[inline(always)]
12895 pub fn pwm_poarity_4(&self) -> PwmPoarity4R {
12896 PwmPoarity4R::new((self.bits & 1) != 0)
12897 }
12898 }
12899 impl W {
12900 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
12901 #[inline(always)]
12902 pub fn pwm_poarity_4(&mut self) -> PwmPoarity4W<'_, PwmPortity4Spec> {
12903 PwmPoarity4W::new(self, 0)
12904 }
12905 }
12906 #[doc = "PWM4 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12907 pub struct PwmPortity4Spec;
12908 impl crate::RegisterSpec for PwmPortity4Spec {
12909 type Ux = u32;
12910 }
12911 #[doc = "`read()` method returns [`pwm_portity4::R`](R) reader structure"]
12912 impl crate::Readable for PwmPortity4Spec {}
12913 #[doc = "`write(|w| ..)` method takes [`pwm_portity4::W`](W) writer structure"]
12914 impl crate::Writable for PwmPortity4Spec {
12915 type Safety = crate::Unsafe;
12916 }
12917 #[doc = "`reset()` method sets PWM_PORTITY4 to value 0"]
12918 impl crate::Resettable for PwmPortity4Spec {}
12919 }
12920 #[doc = "PWM_OEN_CFG4 (rw) register accessor: PWM4 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg4`] module"]
12921 #[doc(alias = "PWM_OEN_CFG4")]
12922 pub type PwmOenCfg4 = crate::Reg<pwm_oen_cfg4::PwmOenCfg4Spec>;
12923 #[doc = "PWM4 high-impedance config"]
12924 pub mod pwm_oen_cfg4 {
12925 #[doc = "Register `PWM_OEN_CFG4` reader"]
12926 pub type R = crate::R<PwmOenCfg4Spec>;
12927 #[doc = "Register `PWM_OEN_CFG4` writer"]
12928 pub type W = crate::W<PwmOenCfg4Spec>;
12929 #[doc = "Field `pwm_oen_cfg_4` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12930 pub type PwmOenCfg4R = crate::BitReader;
12931 #[doc = "Field `pwm_oen_cfg_4` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12932 pub type PwmOenCfg4W<'a, REG> = crate::BitWriter<'a, REG>;
12933 impl R {
12934 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12935 #[inline(always)]
12936 pub fn pwm_oen_cfg_4(&self) -> PwmOenCfg4R {
12937 PwmOenCfg4R::new((self.bits & 1) != 0)
12938 }
12939 }
12940 impl W {
12941 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
12942 #[inline(always)]
12943 pub fn pwm_oen_cfg_4(&mut self) -> PwmOenCfg4W<'_, PwmOenCfg4Spec> {
12944 PwmOenCfg4W::new(self, 0)
12945 }
12946 }
12947 #[doc = "PWM4 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12948 pub struct PwmOenCfg4Spec;
12949 impl crate::RegisterSpec for PwmOenCfg4Spec {
12950 type Ux = u32;
12951 }
12952 #[doc = "`read()` method returns [`pwm_oen_cfg4::R`](R) reader structure"]
12953 impl crate::Readable for PwmOenCfg4Spec {}
12954 #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg4::W`](W) writer structure"]
12955 impl crate::Writable for PwmOenCfg4Spec {
12956 type Safety = crate::Unsafe;
12957 }
12958 #[doc = "`reset()` method sets PWM_OEN_CFG4 to value 0"]
12959 impl crate::Resettable for PwmOenCfg4Spec {}
12960 }
12961 #[doc = "PWM_OFFSET_L4 (rw) register accessor: PWM4 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l4`] module"]
12962 #[doc(alias = "PWM_OFFSET_L4")]
12963 pub type PwmOffsetL4 = crate::Reg<pwm_offset_l4::PwmOffsetL4Spec>;
12964 #[doc = "PWM4 phase offset low 16 bits"]
12965 pub mod pwm_offset_l4 {
12966 #[doc = "Register `PWM_OFFSET_L4` reader"]
12967 pub type R = crate::R<PwmOffsetL4Spec>;
12968 #[doc = "Register `PWM_OFFSET_L4` writer"]
12969 pub type W = crate::W<PwmOffsetL4Spec>;
12970 #[doc = "Field `pwm_offset_l_4` reader - PWM0 phase offset low 16 bits"]
12971 pub type PwmOffsetL4R = crate::FieldReader<u16>;
12972 #[doc = "Field `pwm_offset_l_4` writer - PWM0 phase offset low 16 bits"]
12973 pub type PwmOffsetL4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
12974 impl R {
12975 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
12976 #[inline(always)]
12977 pub fn pwm_offset_l_4(&self) -> PwmOffsetL4R {
12978 PwmOffsetL4R::new((self.bits & 0xffff) as u16)
12979 }
12980 }
12981 impl W {
12982 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
12983 #[inline(always)]
12984 pub fn pwm_offset_l_4(&mut self) -> PwmOffsetL4W<'_, PwmOffsetL4Spec> {
12985 PwmOffsetL4W::new(self, 0)
12986 }
12987 }
12988 #[doc = "PWM4 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
12989 pub struct PwmOffsetL4Spec;
12990 impl crate::RegisterSpec for PwmOffsetL4Spec {
12991 type Ux = u32;
12992 }
12993 #[doc = "`read()` method returns [`pwm_offset_l4::R`](R) reader structure"]
12994 impl crate::Readable for PwmOffsetL4Spec {}
12995 #[doc = "`write(|w| ..)` method takes [`pwm_offset_l4::W`](W) writer structure"]
12996 impl crate::Writable for PwmOffsetL4Spec {
12997 type Safety = crate::Unsafe;
12998 }
12999 #[doc = "`reset()` method sets PWM_OFFSET_L4 to value 0"]
13000 impl crate::Resettable for PwmOffsetL4Spec {}
13001 }
13002 #[doc = "PWM_OFFSET_H4 (rw) register accessor: PWM4 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h4`] module"]
13003 #[doc(alias = "PWM_OFFSET_H4")]
13004 pub type PwmOffsetH4 = crate::Reg<pwm_offset_h4::PwmOffsetH4Spec>;
13005 #[doc = "PWM4 phase offset high 16 bits"]
13006 pub mod pwm_offset_h4 {
13007 #[doc = "Register `PWM_OFFSET_H4` reader"]
13008 pub type R = crate::R<PwmOffsetH4Spec>;
13009 #[doc = "Register `PWM_OFFSET_H4` writer"]
13010 pub type W = crate::W<PwmOffsetH4Spec>;
13011 #[doc = "Field `pwm_offset_h_4` reader - PWM0 phase offset high 16 bits"]
13012 pub type PwmOffsetH4R = crate::FieldReader<u16>;
13013 #[doc = "Field `pwm_offset_h_4` writer - PWM0 phase offset high 16 bits"]
13014 pub type PwmOffsetH4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13015 impl R {
13016 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
13017 #[inline(always)]
13018 pub fn pwm_offset_h_4(&self) -> PwmOffsetH4R {
13019 PwmOffsetH4R::new((self.bits & 0xffff) as u16)
13020 }
13021 }
13022 impl W {
13023 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
13024 #[inline(always)]
13025 pub fn pwm_offset_h_4(&mut self) -> PwmOffsetH4W<'_, PwmOffsetH4Spec> {
13026 PwmOffsetH4W::new(self, 0)
13027 }
13028 }
13029 #[doc = "PWM4 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13030 pub struct PwmOffsetH4Spec;
13031 impl crate::RegisterSpec for PwmOffsetH4Spec {
13032 type Ux = u32;
13033 }
13034 #[doc = "`read()` method returns [`pwm_offset_h4::R`](R) reader structure"]
13035 impl crate::Readable for PwmOffsetH4Spec {}
13036 #[doc = "`write(|w| ..)` method takes [`pwm_offset_h4::W`](W) writer structure"]
13037 impl crate::Writable for PwmOffsetH4Spec {
13038 type Safety = crate::Unsafe;
13039 }
13040 #[doc = "`reset()` method sets PWM_OFFSET_H4 to value 0"]
13041 impl crate::Resettable for PwmOffsetH4Spec {}
13042 }
13043 #[doc = "PWM_FREQ_L4 (rw) register accessor: PWM4 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l4`] module"]
13044 #[doc(alias = "PWM_FREQ_L4")]
13045 pub type PwmFreqL4 = crate::Reg<pwm_freq_l4::PwmFreqL4Spec>;
13046 #[doc = "PWM4 frequency low 16 bits"]
13047 pub mod pwm_freq_l4 {
13048 #[doc = "Register `PWM_FREQ_L4` reader"]
13049 pub type R = crate::R<PwmFreqL4Spec>;
13050 #[doc = "Register `PWM_FREQ_L4` writer"]
13051 pub type W = crate::W<PwmFreqL4Spec>;
13052 #[doc = "Field `pwm_freq_l_4` reader - PWM0 clock divider low 16 bits"]
13053 pub type PwmFreqL4R = crate::FieldReader<u16>;
13054 #[doc = "Field `pwm_freq_l_4` writer - PWM0 clock divider low 16 bits"]
13055 pub type PwmFreqL4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13056 impl R {
13057 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
13058 #[inline(always)]
13059 pub fn pwm_freq_l_4(&self) -> PwmFreqL4R {
13060 PwmFreqL4R::new((self.bits & 0xffff) as u16)
13061 }
13062 }
13063 impl W {
13064 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
13065 #[inline(always)]
13066 pub fn pwm_freq_l_4(&mut self) -> PwmFreqL4W<'_, PwmFreqL4Spec> {
13067 PwmFreqL4W::new(self, 0)
13068 }
13069 }
13070 #[doc = "PWM4 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13071 pub struct PwmFreqL4Spec;
13072 impl crate::RegisterSpec for PwmFreqL4Spec {
13073 type Ux = u32;
13074 }
13075 #[doc = "`read()` method returns [`pwm_freq_l4::R`](R) reader structure"]
13076 impl crate::Readable for PwmFreqL4Spec {}
13077 #[doc = "`write(|w| ..)` method takes [`pwm_freq_l4::W`](W) writer structure"]
13078 impl crate::Writable for PwmFreqL4Spec {
13079 type Safety = crate::Unsafe;
13080 }
13081 #[doc = "`reset()` method sets PWM_FREQ_L4 to value 0"]
13082 impl crate::Resettable for PwmFreqL4Spec {}
13083 }
13084 #[doc = "PWM_FREQ_H4 (rw) register accessor: PWM4 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h4`] module"]
13085 #[doc(alias = "PWM_FREQ_H4")]
13086 pub type PwmFreqH4 = crate::Reg<pwm_freq_h4::PwmFreqH4Spec>;
13087 #[doc = "PWM4 frequency high 16 bits"]
13088 pub mod pwm_freq_h4 {
13089 #[doc = "Register `PWM_FREQ_H4` reader"]
13090 pub type R = crate::R<PwmFreqH4Spec>;
13091 #[doc = "Register `PWM_FREQ_H4` writer"]
13092 pub type W = crate::W<PwmFreqH4Spec>;
13093 #[doc = "Field `pwm_freq_h_4` reader - PWM0 clock divider high 16 bits"]
13094 pub type PwmFreqH4R = crate::FieldReader<u16>;
13095 #[doc = "Field `pwm_freq_h_4` writer - PWM0 clock divider high 16 bits"]
13096 pub type PwmFreqH4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13097 impl R {
13098 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
13099 #[inline(always)]
13100 pub fn pwm_freq_h_4(&self) -> PwmFreqH4R {
13101 PwmFreqH4R::new((self.bits & 0xffff) as u16)
13102 }
13103 }
13104 impl W {
13105 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
13106 #[inline(always)]
13107 pub fn pwm_freq_h_4(&mut self) -> PwmFreqH4W<'_, PwmFreqH4Spec> {
13108 PwmFreqH4W::new(self, 0)
13109 }
13110 }
13111 #[doc = "PWM4 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13112 pub struct PwmFreqH4Spec;
13113 impl crate::RegisterSpec for PwmFreqH4Spec {
13114 type Ux = u32;
13115 }
13116 #[doc = "`read()` method returns [`pwm_freq_h4::R`](R) reader structure"]
13117 impl crate::Readable for PwmFreqH4Spec {}
13118 #[doc = "`write(|w| ..)` method takes [`pwm_freq_h4::W`](W) writer structure"]
13119 impl crate::Writable for PwmFreqH4Spec {
13120 type Safety = crate::Unsafe;
13121 }
13122 #[doc = "`reset()` method sets PWM_FREQ_H4 to value 0"]
13123 impl crate::Resettable for PwmFreqH4Spec {}
13124 }
13125 #[doc = "PWM_DUTY_L4 (rw) register accessor: PWM4 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l4`] module"]
13126 #[doc(alias = "PWM_DUTY_L4")]
13127 pub type PwmDutyL4 = crate::Reg<pwm_duty_l4::PwmDutyL4Spec>;
13128 #[doc = "PWM4 duty cycle low 16 bits"]
13129 pub mod pwm_duty_l4 {
13130 #[doc = "Register `PWM_DUTY_L4` reader"]
13131 pub type R = crate::R<PwmDutyL4Spec>;
13132 #[doc = "Register `PWM_DUTY_L4` writer"]
13133 pub type W = crate::W<PwmDutyL4Spec>;
13134 #[doc = "Field `pwm_duty_l_4` reader - PWM0 duty cycle low 16 bits"]
13135 pub type PwmDutyL4R = crate::FieldReader<u16>;
13136 #[doc = "Field `pwm_duty_l_4` writer - PWM0 duty cycle low 16 bits"]
13137 pub type PwmDutyL4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13138 impl R {
13139 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
13140 #[inline(always)]
13141 pub fn pwm_duty_l_4(&self) -> PwmDutyL4R {
13142 PwmDutyL4R::new((self.bits & 0xffff) as u16)
13143 }
13144 }
13145 impl W {
13146 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
13147 #[inline(always)]
13148 pub fn pwm_duty_l_4(&mut self) -> PwmDutyL4W<'_, PwmDutyL4Spec> {
13149 PwmDutyL4W::new(self, 0)
13150 }
13151 }
13152 #[doc = "PWM4 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13153 pub struct PwmDutyL4Spec;
13154 impl crate::RegisterSpec for PwmDutyL4Spec {
13155 type Ux = u32;
13156 }
13157 #[doc = "`read()` method returns [`pwm_duty_l4::R`](R) reader structure"]
13158 impl crate::Readable for PwmDutyL4Spec {}
13159 #[doc = "`write(|w| ..)` method takes [`pwm_duty_l4::W`](W) writer structure"]
13160 impl crate::Writable for PwmDutyL4Spec {
13161 type Safety = crate::Unsafe;
13162 }
13163 #[doc = "`reset()` method sets PWM_DUTY_L4 to value 0"]
13164 impl crate::Resettable for PwmDutyL4Spec {}
13165 }
13166 #[doc = "PWM_DUTY_H4 (rw) register accessor: PWM4 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h4`] module"]
13167 #[doc(alias = "PWM_DUTY_H4")]
13168 pub type PwmDutyH4 = crate::Reg<pwm_duty_h4::PwmDutyH4Spec>;
13169 #[doc = "PWM4 duty cycle high 16 bits"]
13170 pub mod pwm_duty_h4 {
13171 #[doc = "Register `PWM_DUTY_H4` reader"]
13172 pub type R = crate::R<PwmDutyH4Spec>;
13173 #[doc = "Register `PWM_DUTY_H4` writer"]
13174 pub type W = crate::W<PwmDutyH4Spec>;
13175 #[doc = "Field `pwm_duty_h_4` reader - PWM0 duty cycle high 16 bits"]
13176 pub type PwmDutyH4R = crate::FieldReader<u16>;
13177 #[doc = "Field `pwm_duty_h_4` writer - PWM0 duty cycle high 16 bits"]
13178 pub type PwmDutyH4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13179 impl R {
13180 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
13181 #[inline(always)]
13182 pub fn pwm_duty_h_4(&self) -> PwmDutyH4R {
13183 PwmDutyH4R::new((self.bits & 0xffff) as u16)
13184 }
13185 }
13186 impl W {
13187 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
13188 #[inline(always)]
13189 pub fn pwm_duty_h_4(&mut self) -> PwmDutyH4W<'_, PwmDutyH4Spec> {
13190 PwmDutyH4W::new(self, 0)
13191 }
13192 }
13193 #[doc = "PWM4 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13194 pub struct PwmDutyH4Spec;
13195 impl crate::RegisterSpec for PwmDutyH4Spec {
13196 type Ux = u32;
13197 }
13198 #[doc = "`read()` method returns [`pwm_duty_h4::R`](R) reader structure"]
13199 impl crate::Readable for PwmDutyH4Spec {}
13200 #[doc = "`write(|w| ..)` method takes [`pwm_duty_h4::W`](W) writer structure"]
13201 impl crate::Writable for PwmDutyH4Spec {
13202 type Safety = crate::Unsafe;
13203 }
13204 #[doc = "`reset()` method sets PWM_DUTY_H4 to value 0"]
13205 impl crate::Resettable for PwmDutyH4Spec {}
13206 }
13207 #[doc = "PWM_PERIODLOAD_FLAG4 (rw) register accessor: PWM4 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag4`] module"]
13208 #[doc(alias = "PWM_PERIODLOAD_FLAG4")]
13209 pub type PwmPeriodloadFlag4 = crate::Reg<pwm_periodload_flag4::PwmPeriodloadFlag4Spec>;
13210 #[doc = "PWM4 period load flag"]
13211 pub mod pwm_periodload_flag4 {
13212 #[doc = "Register `PWM_PERIODLOAD_FLAG4` reader"]
13213 pub type R = crate::R<PwmPeriodloadFlag4Spec>;
13214 #[doc = "Register `PWM_PERIODLOAD_FLAG4` writer"]
13215 pub type W = crate::W<PwmPeriodloadFlag4Spec>;
13216 #[doc = "Field `pwm_periodload_flag_4` reader - Period load complete flag"]
13217 pub type PwmPeriodloadFlag4R = crate::BitReader;
13218 impl R {
13219 #[doc = "Bit 0 - Period load complete flag"]
13220 #[inline(always)]
13221 pub fn pwm_periodload_flag_4(&self) -> PwmPeriodloadFlag4R {
13222 PwmPeriodloadFlag4R::new((self.bits & 1) != 0)
13223 }
13224 }
13225 impl W {}
13226 #[doc = "PWM4 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13227 pub struct PwmPeriodloadFlag4Spec;
13228 impl crate::RegisterSpec for PwmPeriodloadFlag4Spec {
13229 type Ux = u32;
13230 }
13231 #[doc = "`read()` method returns [`pwm_periodload_flag4::R`](R) reader structure"]
13232 impl crate::Readable for PwmPeriodloadFlag4Spec {}
13233 #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag4::W`](W) writer structure"]
13234 impl crate::Writable for PwmPeriodloadFlag4Spec {
13235 type Safety = crate::Unsafe;
13236 }
13237 #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG4 to value 0"]
13238 impl crate::Resettable for PwmPeriodloadFlag4Spec {}
13239 }
13240 #[doc = "PWM_PERIOD_VAL4 (rw) register accessor: PWM4 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val4`] module"]
13241 #[doc(alias = "PWM_PERIOD_VAL4")]
13242 pub type PwmPeriodVal4 = crate::Reg<pwm_period_val4::PwmPeriodVal4Spec>;
13243 #[doc = "PWM4 pulse count value"]
13244 pub mod pwm_period_val4 {
13245 #[doc = "Register `PWM_PERIOD_VAL4` reader"]
13246 pub type R = crate::R<PwmPeriodVal4Spec>;
13247 #[doc = "Register `PWM_PERIOD_VAL4` writer"]
13248 pub type W = crate::W<PwmPeriodVal4Spec>;
13249 #[doc = "Field `pwm_period_val_4` reader - Pulse count for stepping mode"]
13250 pub type PwmPeriodVal4R = crate::FieldReader<u16>;
13251 #[doc = "Field `pwm_period_val_4` writer - Pulse count for stepping mode"]
13252 pub type PwmPeriodVal4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13253 impl R {
13254 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
13255 #[inline(always)]
13256 pub fn pwm_period_val_4(&self) -> PwmPeriodVal4R {
13257 PwmPeriodVal4R::new((self.bits & 0xffff) as u16)
13258 }
13259 }
13260 impl W {
13261 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
13262 #[inline(always)]
13263 pub fn pwm_period_val_4(&mut self) -> PwmPeriodVal4W<'_, PwmPeriodVal4Spec> {
13264 PwmPeriodVal4W::new(self, 0)
13265 }
13266 }
13267 #[doc = "PWM4 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13268 pub struct PwmPeriodVal4Spec;
13269 impl crate::RegisterSpec for PwmPeriodVal4Spec {
13270 type Ux = u32;
13271 }
13272 #[doc = "`read()` method returns [`pwm_period_val4::R`](R) reader structure"]
13273 impl crate::Readable for PwmPeriodVal4Spec {}
13274 #[doc = "`write(|w| ..)` method takes [`pwm_period_val4::W`](W) writer structure"]
13275 impl crate::Writable for PwmPeriodVal4Spec {
13276 type Safety = crate::Unsafe;
13277 }
13278 #[doc = "`reset()` method sets PWM_PERIOD_VAL4 to value 0"]
13279 impl crate::Resettable for PwmPeriodVal4Spec {}
13280 }
13281 #[doc = "PWM_PERIODCNT4 (rw) register accessor: PWM4 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt4`] module"]
13282 #[doc(alias = "PWM_PERIODCNT4")]
13283 pub type PwmPeriodcnt4 = crate::Reg<pwm_periodcnt4::PwmPeriodcnt4Spec>;
13284 #[doc = "PWM4 pulse count current value"]
13285 pub mod pwm_periodcnt4 {
13286 #[doc = "Register `PWM_PERIODCNT4` reader"]
13287 pub type R = crate::R<PwmPeriodcnt4Spec>;
13288 #[doc = "Register `PWM_PERIODCNT4` writer"]
13289 pub type W = crate::W<PwmPeriodcnt4Spec>;
13290 #[doc = "Field `pwm_periodcnt_4` reader - Current pulse count"]
13291 pub type PwmPeriodcnt4R = crate::FieldReader<u16>;
13292 impl R {
13293 #[doc = "Bits 0:15 - Current pulse count"]
13294 #[inline(always)]
13295 pub fn pwm_periodcnt_4(&self) -> PwmPeriodcnt4R {
13296 PwmPeriodcnt4R::new((self.bits & 0xffff) as u16)
13297 }
13298 }
13299 impl W {}
13300 #[doc = "PWM4 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13301 pub struct PwmPeriodcnt4Spec;
13302 impl crate::RegisterSpec for PwmPeriodcnt4Spec {
13303 type Ux = u32;
13304 }
13305 #[doc = "`read()` method returns [`pwm_periodcnt4::R`](R) reader structure"]
13306 impl crate::Readable for PwmPeriodcnt4Spec {}
13307 #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt4::W`](W) writer structure"]
13308 impl crate::Writable for PwmPeriodcnt4Spec {
13309 type Safety = crate::Unsafe;
13310 }
13311 #[doc = "`reset()` method sets PWM_PERIODCNT4 to value 0"]
13312 impl crate::Resettable for PwmPeriodcnt4Spec {}
13313 }
13314 #[doc = "PWM_EN5 (rw) register accessor: PWM5 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en5`] module"]
13315 #[doc(alias = "PWM_EN5")]
13316 pub type PwmEn5 = crate::Reg<pwm_en5::PwmEn5Spec>;
13317 #[doc = "PWM5 enable"]
13318 pub mod pwm_en5 {
13319 #[doc = "Register `PWM_EN5` reader"]
13320 pub type R = crate::R<PwmEn5Spec>;
13321 #[doc = "Register `PWM_EN5` writer"]
13322 pub type W = crate::W<PwmEn5Spec>;
13323 #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
13324 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
13325 pub enum PwmEn5 {
13326 #[doc = "0: PWM disabled, output low"]
13327 Off = 0,
13328 #[doc = "1: PWM enabled"]
13329 On = 1,
13330 }
13331 impl From<PwmEn5> for bool {
13332 #[inline(always)]
13333 fn from(variant: PwmEn5) -> Self {
13334 variant as u8 != 0
13335 }
13336 }
13337 #[doc = "Field `pwm_en_5` reader - PWM0 enable: 0=off; 1=on"]
13338 pub type PwmEn5R = crate::BitReader<PwmEn5>;
13339 impl PwmEn5R {
13340 #[doc = "Get enumerated values variant"]
13341 #[inline(always)]
13342 pub const fn variant(&self) -> PwmEn5 {
13343 match self.bits {
13344 false => PwmEn5::Off,
13345 true => PwmEn5::On,
13346 }
13347 }
13348 #[doc = "PWM disabled, output low"]
13349 #[inline(always)]
13350 pub fn is_off(&self) -> bool {
13351 *self == PwmEn5::Off
13352 }
13353 #[doc = "PWM enabled"]
13354 #[inline(always)]
13355 pub fn is_on(&self) -> bool {
13356 *self == PwmEn5::On
13357 }
13358 }
13359 #[doc = "Field `pwm_en_5` writer - PWM0 enable: 0=off; 1=on"]
13360 pub type PwmEn5W<'a, REG> = crate::BitWriter<'a, REG, PwmEn5>;
13361 impl<'a, REG> PwmEn5W<'a, REG>
13362 where
13363 REG: crate::Writable + crate::RegisterSpec,
13364 {
13365 #[doc = "PWM disabled, output low"]
13366 #[inline(always)]
13367 pub fn off(self) -> &'a mut crate::W<REG> {
13368 self.variant(PwmEn5::Off)
13369 }
13370 #[doc = "PWM enabled"]
13371 #[inline(always)]
13372 pub fn on(self) -> &'a mut crate::W<REG> {
13373 self.variant(PwmEn5::On)
13374 }
13375 }
13376 impl R {
13377 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
13378 #[inline(always)]
13379 pub fn pwm_en_5(&self) -> PwmEn5R {
13380 PwmEn5R::new((self.bits & 1) != 0)
13381 }
13382 }
13383 impl W {
13384 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
13385 #[inline(always)]
13386 pub fn pwm_en_5(&mut self) -> PwmEn5W<'_, PwmEn5Spec> {
13387 PwmEn5W::new(self, 0)
13388 }
13389 }
13390 #[doc = "PWM5 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13391 pub struct PwmEn5Spec;
13392 impl crate::RegisterSpec for PwmEn5Spec {
13393 type Ux = u32;
13394 }
13395 #[doc = "`read()` method returns [`pwm_en5::R`](R) reader structure"]
13396 impl crate::Readable for PwmEn5Spec {}
13397 #[doc = "`write(|w| ..)` method takes [`pwm_en5::W`](W) writer structure"]
13398 impl crate::Writable for PwmEn5Spec {
13399 type Safety = crate::Unsafe;
13400 }
13401 #[doc = "`reset()` method sets PWM_EN5 to value 0"]
13402 impl crate::Resettable for PwmEn5Spec {}
13403 }
13404 #[doc = "PWM_PORTITY5 (rw) register accessor: PWM5 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity5`] module"]
13405 #[doc(alias = "PWM_PORTITY5")]
13406 pub type PwmPortity5 = crate::Reg<pwm_portity5::PwmPortity5Spec>;
13407 #[doc = "PWM5 polarity"]
13408 pub mod pwm_portity5 {
13409 #[doc = "Register `PWM_PORTITY5` reader"]
13410 pub type R = crate::R<PwmPortity5Spec>;
13411 #[doc = "Register `PWM_PORTITY5` writer"]
13412 pub type W = crate::W<PwmPortity5Spec>;
13413 #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
13414 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
13415 pub enum PwmPoarity5 {
13416 #[doc = "0: Normal polarity"]
13417 Normal = 0,
13418 #[doc = "1: Inverted polarity"]
13419 Inverted = 1,
13420 }
13421 impl From<PwmPoarity5> for bool {
13422 #[inline(always)]
13423 fn from(variant: PwmPoarity5) -> Self {
13424 variant as u8 != 0
13425 }
13426 }
13427 #[doc = "Field `pwm_poarity_5` reader - PWM0 polarity: 0=normal; 1=inverted"]
13428 pub type PwmPoarity5R = crate::BitReader<PwmPoarity5>;
13429 impl PwmPoarity5R {
13430 #[doc = "Get enumerated values variant"]
13431 #[inline(always)]
13432 pub const fn variant(&self) -> PwmPoarity5 {
13433 match self.bits {
13434 false => PwmPoarity5::Normal,
13435 true => PwmPoarity5::Inverted,
13436 }
13437 }
13438 #[doc = "Normal polarity"]
13439 #[inline(always)]
13440 pub fn is_normal(&self) -> bool {
13441 *self == PwmPoarity5::Normal
13442 }
13443 #[doc = "Inverted polarity"]
13444 #[inline(always)]
13445 pub fn is_inverted(&self) -> bool {
13446 *self == PwmPoarity5::Inverted
13447 }
13448 }
13449 #[doc = "Field `pwm_poarity_5` writer - PWM0 polarity: 0=normal; 1=inverted"]
13450 pub type PwmPoarity5W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity5>;
13451 impl<'a, REG> PwmPoarity5W<'a, REG>
13452 where
13453 REG: crate::Writable + crate::RegisterSpec,
13454 {
13455 #[doc = "Normal polarity"]
13456 #[inline(always)]
13457 pub fn normal(self) -> &'a mut crate::W<REG> {
13458 self.variant(PwmPoarity5::Normal)
13459 }
13460 #[doc = "Inverted polarity"]
13461 #[inline(always)]
13462 pub fn inverted(self) -> &'a mut crate::W<REG> {
13463 self.variant(PwmPoarity5::Inverted)
13464 }
13465 }
13466 impl R {
13467 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
13468 #[inline(always)]
13469 pub fn pwm_poarity_5(&self) -> PwmPoarity5R {
13470 PwmPoarity5R::new((self.bits & 1) != 0)
13471 }
13472 }
13473 impl W {
13474 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
13475 #[inline(always)]
13476 pub fn pwm_poarity_5(&mut self) -> PwmPoarity5W<'_, PwmPortity5Spec> {
13477 PwmPoarity5W::new(self, 0)
13478 }
13479 }
13480 #[doc = "PWM5 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13481 pub struct PwmPortity5Spec;
13482 impl crate::RegisterSpec for PwmPortity5Spec {
13483 type Ux = u32;
13484 }
13485 #[doc = "`read()` method returns [`pwm_portity5::R`](R) reader structure"]
13486 impl crate::Readable for PwmPortity5Spec {}
13487 #[doc = "`write(|w| ..)` method takes [`pwm_portity5::W`](W) writer structure"]
13488 impl crate::Writable for PwmPortity5Spec {
13489 type Safety = crate::Unsafe;
13490 }
13491 #[doc = "`reset()` method sets PWM_PORTITY5 to value 0"]
13492 impl crate::Resettable for PwmPortity5Spec {}
13493 }
13494 #[doc = "PWM_OEN_CFG5 (rw) register accessor: PWM5 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg5`] module"]
13495 #[doc(alias = "PWM_OEN_CFG5")]
13496 pub type PwmOenCfg5 = crate::Reg<pwm_oen_cfg5::PwmOenCfg5Spec>;
13497 #[doc = "PWM5 high-impedance config"]
13498 pub mod pwm_oen_cfg5 {
13499 #[doc = "Register `PWM_OEN_CFG5` reader"]
13500 pub type R = crate::R<PwmOenCfg5Spec>;
13501 #[doc = "Register `PWM_OEN_CFG5` writer"]
13502 pub type W = crate::W<PwmOenCfg5Spec>;
13503 #[doc = "Field `pwm_oen_cfg_5` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
13504 pub type PwmOenCfg5R = crate::BitReader;
13505 #[doc = "Field `pwm_oen_cfg_5` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
13506 pub type PwmOenCfg5W<'a, REG> = crate::BitWriter<'a, REG>;
13507 impl R {
13508 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
13509 #[inline(always)]
13510 pub fn pwm_oen_cfg_5(&self) -> PwmOenCfg5R {
13511 PwmOenCfg5R::new((self.bits & 1) != 0)
13512 }
13513 }
13514 impl W {
13515 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
13516 #[inline(always)]
13517 pub fn pwm_oen_cfg_5(&mut self) -> PwmOenCfg5W<'_, PwmOenCfg5Spec> {
13518 PwmOenCfg5W::new(self, 0)
13519 }
13520 }
13521 #[doc = "PWM5 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13522 pub struct PwmOenCfg5Spec;
13523 impl crate::RegisterSpec for PwmOenCfg5Spec {
13524 type Ux = u32;
13525 }
13526 #[doc = "`read()` method returns [`pwm_oen_cfg5::R`](R) reader structure"]
13527 impl crate::Readable for PwmOenCfg5Spec {}
13528 #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg5::W`](W) writer structure"]
13529 impl crate::Writable for PwmOenCfg5Spec {
13530 type Safety = crate::Unsafe;
13531 }
13532 #[doc = "`reset()` method sets PWM_OEN_CFG5 to value 0"]
13533 impl crate::Resettable for PwmOenCfg5Spec {}
13534 }
13535 #[doc = "PWM_OFFSET_L5 (rw) register accessor: PWM5 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l5`] module"]
13536 #[doc(alias = "PWM_OFFSET_L5")]
13537 pub type PwmOffsetL5 = crate::Reg<pwm_offset_l5::PwmOffsetL5Spec>;
13538 #[doc = "PWM5 phase offset low 16 bits"]
13539 pub mod pwm_offset_l5 {
13540 #[doc = "Register `PWM_OFFSET_L5` reader"]
13541 pub type R = crate::R<PwmOffsetL5Spec>;
13542 #[doc = "Register `PWM_OFFSET_L5` writer"]
13543 pub type W = crate::W<PwmOffsetL5Spec>;
13544 #[doc = "Field `pwm_offset_l_5` reader - PWM0 phase offset low 16 bits"]
13545 pub type PwmOffsetL5R = crate::FieldReader<u16>;
13546 #[doc = "Field `pwm_offset_l_5` writer - PWM0 phase offset low 16 bits"]
13547 pub type PwmOffsetL5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13548 impl R {
13549 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
13550 #[inline(always)]
13551 pub fn pwm_offset_l_5(&self) -> PwmOffsetL5R {
13552 PwmOffsetL5R::new((self.bits & 0xffff) as u16)
13553 }
13554 }
13555 impl W {
13556 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
13557 #[inline(always)]
13558 pub fn pwm_offset_l_5(&mut self) -> PwmOffsetL5W<'_, PwmOffsetL5Spec> {
13559 PwmOffsetL5W::new(self, 0)
13560 }
13561 }
13562 #[doc = "PWM5 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13563 pub struct PwmOffsetL5Spec;
13564 impl crate::RegisterSpec for PwmOffsetL5Spec {
13565 type Ux = u32;
13566 }
13567 #[doc = "`read()` method returns [`pwm_offset_l5::R`](R) reader structure"]
13568 impl crate::Readable for PwmOffsetL5Spec {}
13569 #[doc = "`write(|w| ..)` method takes [`pwm_offset_l5::W`](W) writer structure"]
13570 impl crate::Writable for PwmOffsetL5Spec {
13571 type Safety = crate::Unsafe;
13572 }
13573 #[doc = "`reset()` method sets PWM_OFFSET_L5 to value 0"]
13574 impl crate::Resettable for PwmOffsetL5Spec {}
13575 }
13576 #[doc = "PWM_OFFSET_H5 (rw) register accessor: PWM5 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h5`] module"]
13577 #[doc(alias = "PWM_OFFSET_H5")]
13578 pub type PwmOffsetH5 = crate::Reg<pwm_offset_h5::PwmOffsetH5Spec>;
13579 #[doc = "PWM5 phase offset high 16 bits"]
13580 pub mod pwm_offset_h5 {
13581 #[doc = "Register `PWM_OFFSET_H5` reader"]
13582 pub type R = crate::R<PwmOffsetH5Spec>;
13583 #[doc = "Register `PWM_OFFSET_H5` writer"]
13584 pub type W = crate::W<PwmOffsetH5Spec>;
13585 #[doc = "Field `pwm_offset_h_5` reader - PWM0 phase offset high 16 bits"]
13586 pub type PwmOffsetH5R = crate::FieldReader<u16>;
13587 #[doc = "Field `pwm_offset_h_5` writer - PWM0 phase offset high 16 bits"]
13588 pub type PwmOffsetH5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13589 impl R {
13590 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
13591 #[inline(always)]
13592 pub fn pwm_offset_h_5(&self) -> PwmOffsetH5R {
13593 PwmOffsetH5R::new((self.bits & 0xffff) as u16)
13594 }
13595 }
13596 impl W {
13597 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
13598 #[inline(always)]
13599 pub fn pwm_offset_h_5(&mut self) -> PwmOffsetH5W<'_, PwmOffsetH5Spec> {
13600 PwmOffsetH5W::new(self, 0)
13601 }
13602 }
13603 #[doc = "PWM5 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13604 pub struct PwmOffsetH5Spec;
13605 impl crate::RegisterSpec for PwmOffsetH5Spec {
13606 type Ux = u32;
13607 }
13608 #[doc = "`read()` method returns [`pwm_offset_h5::R`](R) reader structure"]
13609 impl crate::Readable for PwmOffsetH5Spec {}
13610 #[doc = "`write(|w| ..)` method takes [`pwm_offset_h5::W`](W) writer structure"]
13611 impl crate::Writable for PwmOffsetH5Spec {
13612 type Safety = crate::Unsafe;
13613 }
13614 #[doc = "`reset()` method sets PWM_OFFSET_H5 to value 0"]
13615 impl crate::Resettable for PwmOffsetH5Spec {}
13616 }
13617 #[doc = "PWM_FREQ_L5 (rw) register accessor: PWM5 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l5`] module"]
13618 #[doc(alias = "PWM_FREQ_L5")]
13619 pub type PwmFreqL5 = crate::Reg<pwm_freq_l5::PwmFreqL5Spec>;
13620 #[doc = "PWM5 frequency low 16 bits"]
13621 pub mod pwm_freq_l5 {
13622 #[doc = "Register `PWM_FREQ_L5` reader"]
13623 pub type R = crate::R<PwmFreqL5Spec>;
13624 #[doc = "Register `PWM_FREQ_L5` writer"]
13625 pub type W = crate::W<PwmFreqL5Spec>;
13626 #[doc = "Field `pwm_freq_l_5` reader - PWM0 clock divider low 16 bits"]
13627 pub type PwmFreqL5R = crate::FieldReader<u16>;
13628 #[doc = "Field `pwm_freq_l_5` writer - PWM0 clock divider low 16 bits"]
13629 pub type PwmFreqL5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13630 impl R {
13631 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
13632 #[inline(always)]
13633 pub fn pwm_freq_l_5(&self) -> PwmFreqL5R {
13634 PwmFreqL5R::new((self.bits & 0xffff) as u16)
13635 }
13636 }
13637 impl W {
13638 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
13639 #[inline(always)]
13640 pub fn pwm_freq_l_5(&mut self) -> PwmFreqL5W<'_, PwmFreqL5Spec> {
13641 PwmFreqL5W::new(self, 0)
13642 }
13643 }
13644 #[doc = "PWM5 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13645 pub struct PwmFreqL5Spec;
13646 impl crate::RegisterSpec for PwmFreqL5Spec {
13647 type Ux = u32;
13648 }
13649 #[doc = "`read()` method returns [`pwm_freq_l5::R`](R) reader structure"]
13650 impl crate::Readable for PwmFreqL5Spec {}
13651 #[doc = "`write(|w| ..)` method takes [`pwm_freq_l5::W`](W) writer structure"]
13652 impl crate::Writable for PwmFreqL5Spec {
13653 type Safety = crate::Unsafe;
13654 }
13655 #[doc = "`reset()` method sets PWM_FREQ_L5 to value 0"]
13656 impl crate::Resettable for PwmFreqL5Spec {}
13657 }
13658 #[doc = "PWM_FREQ_H5 (rw) register accessor: PWM5 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h5`] module"]
13659 #[doc(alias = "PWM_FREQ_H5")]
13660 pub type PwmFreqH5 = crate::Reg<pwm_freq_h5::PwmFreqH5Spec>;
13661 #[doc = "PWM5 frequency high 16 bits"]
13662 pub mod pwm_freq_h5 {
13663 #[doc = "Register `PWM_FREQ_H5` reader"]
13664 pub type R = crate::R<PwmFreqH5Spec>;
13665 #[doc = "Register `PWM_FREQ_H5` writer"]
13666 pub type W = crate::W<PwmFreqH5Spec>;
13667 #[doc = "Field `pwm_freq_h_5` reader - PWM0 clock divider high 16 bits"]
13668 pub type PwmFreqH5R = crate::FieldReader<u16>;
13669 #[doc = "Field `pwm_freq_h_5` writer - PWM0 clock divider high 16 bits"]
13670 pub type PwmFreqH5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13671 impl R {
13672 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
13673 #[inline(always)]
13674 pub fn pwm_freq_h_5(&self) -> PwmFreqH5R {
13675 PwmFreqH5R::new((self.bits & 0xffff) as u16)
13676 }
13677 }
13678 impl W {
13679 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
13680 #[inline(always)]
13681 pub fn pwm_freq_h_5(&mut self) -> PwmFreqH5W<'_, PwmFreqH5Spec> {
13682 PwmFreqH5W::new(self, 0)
13683 }
13684 }
13685 #[doc = "PWM5 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13686 pub struct PwmFreqH5Spec;
13687 impl crate::RegisterSpec for PwmFreqH5Spec {
13688 type Ux = u32;
13689 }
13690 #[doc = "`read()` method returns [`pwm_freq_h5::R`](R) reader structure"]
13691 impl crate::Readable for PwmFreqH5Spec {}
13692 #[doc = "`write(|w| ..)` method takes [`pwm_freq_h5::W`](W) writer structure"]
13693 impl crate::Writable for PwmFreqH5Spec {
13694 type Safety = crate::Unsafe;
13695 }
13696 #[doc = "`reset()` method sets PWM_FREQ_H5 to value 0"]
13697 impl crate::Resettable for PwmFreqH5Spec {}
13698 }
13699 #[doc = "PWM_DUTY_L5 (rw) register accessor: PWM5 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l5`] module"]
13700 #[doc(alias = "PWM_DUTY_L5")]
13701 pub type PwmDutyL5 = crate::Reg<pwm_duty_l5::PwmDutyL5Spec>;
13702 #[doc = "PWM5 duty cycle low 16 bits"]
13703 pub mod pwm_duty_l5 {
13704 #[doc = "Register `PWM_DUTY_L5` reader"]
13705 pub type R = crate::R<PwmDutyL5Spec>;
13706 #[doc = "Register `PWM_DUTY_L5` writer"]
13707 pub type W = crate::W<PwmDutyL5Spec>;
13708 #[doc = "Field `pwm_duty_l_5` reader - PWM0 duty cycle low 16 bits"]
13709 pub type PwmDutyL5R = crate::FieldReader<u16>;
13710 #[doc = "Field `pwm_duty_l_5` writer - PWM0 duty cycle low 16 bits"]
13711 pub type PwmDutyL5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13712 impl R {
13713 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
13714 #[inline(always)]
13715 pub fn pwm_duty_l_5(&self) -> PwmDutyL5R {
13716 PwmDutyL5R::new((self.bits & 0xffff) as u16)
13717 }
13718 }
13719 impl W {
13720 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
13721 #[inline(always)]
13722 pub fn pwm_duty_l_5(&mut self) -> PwmDutyL5W<'_, PwmDutyL5Spec> {
13723 PwmDutyL5W::new(self, 0)
13724 }
13725 }
13726 #[doc = "PWM5 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13727 pub struct PwmDutyL5Spec;
13728 impl crate::RegisterSpec for PwmDutyL5Spec {
13729 type Ux = u32;
13730 }
13731 #[doc = "`read()` method returns [`pwm_duty_l5::R`](R) reader structure"]
13732 impl crate::Readable for PwmDutyL5Spec {}
13733 #[doc = "`write(|w| ..)` method takes [`pwm_duty_l5::W`](W) writer structure"]
13734 impl crate::Writable for PwmDutyL5Spec {
13735 type Safety = crate::Unsafe;
13736 }
13737 #[doc = "`reset()` method sets PWM_DUTY_L5 to value 0"]
13738 impl crate::Resettable for PwmDutyL5Spec {}
13739 }
13740 #[doc = "PWM_DUTY_H5 (rw) register accessor: PWM5 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h5`] module"]
13741 #[doc(alias = "PWM_DUTY_H5")]
13742 pub type PwmDutyH5 = crate::Reg<pwm_duty_h5::PwmDutyH5Spec>;
13743 #[doc = "PWM5 duty cycle high 16 bits"]
13744 pub mod pwm_duty_h5 {
13745 #[doc = "Register `PWM_DUTY_H5` reader"]
13746 pub type R = crate::R<PwmDutyH5Spec>;
13747 #[doc = "Register `PWM_DUTY_H5` writer"]
13748 pub type W = crate::W<PwmDutyH5Spec>;
13749 #[doc = "Field `pwm_duty_h_5` reader - PWM0 duty cycle high 16 bits"]
13750 pub type PwmDutyH5R = crate::FieldReader<u16>;
13751 #[doc = "Field `pwm_duty_h_5` writer - PWM0 duty cycle high 16 bits"]
13752 pub type PwmDutyH5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13753 impl R {
13754 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
13755 #[inline(always)]
13756 pub fn pwm_duty_h_5(&self) -> PwmDutyH5R {
13757 PwmDutyH5R::new((self.bits & 0xffff) as u16)
13758 }
13759 }
13760 impl W {
13761 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
13762 #[inline(always)]
13763 pub fn pwm_duty_h_5(&mut self) -> PwmDutyH5W<'_, PwmDutyH5Spec> {
13764 PwmDutyH5W::new(self, 0)
13765 }
13766 }
13767 #[doc = "PWM5 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13768 pub struct PwmDutyH5Spec;
13769 impl crate::RegisterSpec for PwmDutyH5Spec {
13770 type Ux = u32;
13771 }
13772 #[doc = "`read()` method returns [`pwm_duty_h5::R`](R) reader structure"]
13773 impl crate::Readable for PwmDutyH5Spec {}
13774 #[doc = "`write(|w| ..)` method takes [`pwm_duty_h5::W`](W) writer structure"]
13775 impl crate::Writable for PwmDutyH5Spec {
13776 type Safety = crate::Unsafe;
13777 }
13778 #[doc = "`reset()` method sets PWM_DUTY_H5 to value 0"]
13779 impl crate::Resettable for PwmDutyH5Spec {}
13780 }
13781 #[doc = "PWM_PERIODLOAD_FLAG5 (rw) register accessor: PWM5 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag5`] module"]
13782 #[doc(alias = "PWM_PERIODLOAD_FLAG5")]
13783 pub type PwmPeriodloadFlag5 = crate::Reg<pwm_periodload_flag5::PwmPeriodloadFlag5Spec>;
13784 #[doc = "PWM5 period load flag"]
13785 pub mod pwm_periodload_flag5 {
13786 #[doc = "Register `PWM_PERIODLOAD_FLAG5` reader"]
13787 pub type R = crate::R<PwmPeriodloadFlag5Spec>;
13788 #[doc = "Register `PWM_PERIODLOAD_FLAG5` writer"]
13789 pub type W = crate::W<PwmPeriodloadFlag5Spec>;
13790 #[doc = "Field `pwm_periodload_flag_5` reader - Period load complete flag"]
13791 pub type PwmPeriodloadFlag5R = crate::BitReader;
13792 impl R {
13793 #[doc = "Bit 0 - Period load complete flag"]
13794 #[inline(always)]
13795 pub fn pwm_periodload_flag_5(&self) -> PwmPeriodloadFlag5R {
13796 PwmPeriodloadFlag5R::new((self.bits & 1) != 0)
13797 }
13798 }
13799 impl W {}
13800 #[doc = "PWM5 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13801 pub struct PwmPeriodloadFlag5Spec;
13802 impl crate::RegisterSpec for PwmPeriodloadFlag5Spec {
13803 type Ux = u32;
13804 }
13805 #[doc = "`read()` method returns [`pwm_periodload_flag5::R`](R) reader structure"]
13806 impl crate::Readable for PwmPeriodloadFlag5Spec {}
13807 #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag5::W`](W) writer structure"]
13808 impl crate::Writable for PwmPeriodloadFlag5Spec {
13809 type Safety = crate::Unsafe;
13810 }
13811 #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG5 to value 0"]
13812 impl crate::Resettable for PwmPeriodloadFlag5Spec {}
13813 }
13814 #[doc = "PWM_PERIOD_VAL5 (rw) register accessor: PWM5 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val5`] module"]
13815 #[doc(alias = "PWM_PERIOD_VAL5")]
13816 pub type PwmPeriodVal5 = crate::Reg<pwm_period_val5::PwmPeriodVal5Spec>;
13817 #[doc = "PWM5 pulse count value"]
13818 pub mod pwm_period_val5 {
13819 #[doc = "Register `PWM_PERIOD_VAL5` reader"]
13820 pub type R = crate::R<PwmPeriodVal5Spec>;
13821 #[doc = "Register `PWM_PERIOD_VAL5` writer"]
13822 pub type W = crate::W<PwmPeriodVal5Spec>;
13823 #[doc = "Field `pwm_period_val_5` reader - Pulse count for stepping mode"]
13824 pub type PwmPeriodVal5R = crate::FieldReader<u16>;
13825 #[doc = "Field `pwm_period_val_5` writer - Pulse count for stepping mode"]
13826 pub type PwmPeriodVal5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13827 impl R {
13828 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
13829 #[inline(always)]
13830 pub fn pwm_period_val_5(&self) -> PwmPeriodVal5R {
13831 PwmPeriodVal5R::new((self.bits & 0xffff) as u16)
13832 }
13833 }
13834 impl W {
13835 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
13836 #[inline(always)]
13837 pub fn pwm_period_val_5(&mut self) -> PwmPeriodVal5W<'_, PwmPeriodVal5Spec> {
13838 PwmPeriodVal5W::new(self, 0)
13839 }
13840 }
13841 #[doc = "PWM5 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13842 pub struct PwmPeriodVal5Spec;
13843 impl crate::RegisterSpec for PwmPeriodVal5Spec {
13844 type Ux = u32;
13845 }
13846 #[doc = "`read()` method returns [`pwm_period_val5::R`](R) reader structure"]
13847 impl crate::Readable for PwmPeriodVal5Spec {}
13848 #[doc = "`write(|w| ..)` method takes [`pwm_period_val5::W`](W) writer structure"]
13849 impl crate::Writable for PwmPeriodVal5Spec {
13850 type Safety = crate::Unsafe;
13851 }
13852 #[doc = "`reset()` method sets PWM_PERIOD_VAL5 to value 0"]
13853 impl crate::Resettable for PwmPeriodVal5Spec {}
13854 }
13855 #[doc = "PWM_PERIODCNT5 (rw) register accessor: PWM5 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt5`] module"]
13856 #[doc(alias = "PWM_PERIODCNT5")]
13857 pub type PwmPeriodcnt5 = crate::Reg<pwm_periodcnt5::PwmPeriodcnt5Spec>;
13858 #[doc = "PWM5 pulse count current value"]
13859 pub mod pwm_periodcnt5 {
13860 #[doc = "Register `PWM_PERIODCNT5` reader"]
13861 pub type R = crate::R<PwmPeriodcnt5Spec>;
13862 #[doc = "Register `PWM_PERIODCNT5` writer"]
13863 pub type W = crate::W<PwmPeriodcnt5Spec>;
13864 #[doc = "Field `pwm_periodcnt_5` reader - Current pulse count"]
13865 pub type PwmPeriodcnt5R = crate::FieldReader<u16>;
13866 impl R {
13867 #[doc = "Bits 0:15 - Current pulse count"]
13868 #[inline(always)]
13869 pub fn pwm_periodcnt_5(&self) -> PwmPeriodcnt5R {
13870 PwmPeriodcnt5R::new((self.bits & 0xffff) as u16)
13871 }
13872 }
13873 impl W {}
13874 #[doc = "PWM5 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13875 pub struct PwmPeriodcnt5Spec;
13876 impl crate::RegisterSpec for PwmPeriodcnt5Spec {
13877 type Ux = u32;
13878 }
13879 #[doc = "`read()` method returns [`pwm_periodcnt5::R`](R) reader structure"]
13880 impl crate::Readable for PwmPeriodcnt5Spec {}
13881 #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt5::W`](W) writer structure"]
13882 impl crate::Writable for PwmPeriodcnt5Spec {
13883 type Safety = crate::Unsafe;
13884 }
13885 #[doc = "`reset()` method sets PWM_PERIODCNT5 to value 0"]
13886 impl crate::Resettable for PwmPeriodcnt5Spec {}
13887 }
13888 #[doc = "PWM_EN6 (rw) register accessor: PWM6 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en6`] module"]
13889 #[doc(alias = "PWM_EN6")]
13890 pub type PwmEn6 = crate::Reg<pwm_en6::PwmEn6Spec>;
13891 #[doc = "PWM6 enable"]
13892 pub mod pwm_en6 {
13893 #[doc = "Register `PWM_EN6` reader"]
13894 pub type R = crate::R<PwmEn6Spec>;
13895 #[doc = "Register `PWM_EN6` writer"]
13896 pub type W = crate::W<PwmEn6Spec>;
13897 #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
13898 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
13899 pub enum PwmEn6 {
13900 #[doc = "0: PWM disabled, output low"]
13901 Off = 0,
13902 #[doc = "1: PWM enabled"]
13903 On = 1,
13904 }
13905 impl From<PwmEn6> for bool {
13906 #[inline(always)]
13907 fn from(variant: PwmEn6) -> Self {
13908 variant as u8 != 0
13909 }
13910 }
13911 #[doc = "Field `pwm_en_6` reader - PWM0 enable: 0=off; 1=on"]
13912 pub type PwmEn6R = crate::BitReader<PwmEn6>;
13913 impl PwmEn6R {
13914 #[doc = "Get enumerated values variant"]
13915 #[inline(always)]
13916 pub const fn variant(&self) -> PwmEn6 {
13917 match self.bits {
13918 false => PwmEn6::Off,
13919 true => PwmEn6::On,
13920 }
13921 }
13922 #[doc = "PWM disabled, output low"]
13923 #[inline(always)]
13924 pub fn is_off(&self) -> bool {
13925 *self == PwmEn6::Off
13926 }
13927 #[doc = "PWM enabled"]
13928 #[inline(always)]
13929 pub fn is_on(&self) -> bool {
13930 *self == PwmEn6::On
13931 }
13932 }
13933 #[doc = "Field `pwm_en_6` writer - PWM0 enable: 0=off; 1=on"]
13934 pub type PwmEn6W<'a, REG> = crate::BitWriter<'a, REG, PwmEn6>;
13935 impl<'a, REG> PwmEn6W<'a, REG>
13936 where
13937 REG: crate::Writable + crate::RegisterSpec,
13938 {
13939 #[doc = "PWM disabled, output low"]
13940 #[inline(always)]
13941 pub fn off(self) -> &'a mut crate::W<REG> {
13942 self.variant(PwmEn6::Off)
13943 }
13944 #[doc = "PWM enabled"]
13945 #[inline(always)]
13946 pub fn on(self) -> &'a mut crate::W<REG> {
13947 self.variant(PwmEn6::On)
13948 }
13949 }
13950 impl R {
13951 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
13952 #[inline(always)]
13953 pub fn pwm_en_6(&self) -> PwmEn6R {
13954 PwmEn6R::new((self.bits & 1) != 0)
13955 }
13956 }
13957 impl W {
13958 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
13959 #[inline(always)]
13960 pub fn pwm_en_6(&mut self) -> PwmEn6W<'_, PwmEn6Spec> {
13961 PwmEn6W::new(self, 0)
13962 }
13963 }
13964 #[doc = "PWM6 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13965 pub struct PwmEn6Spec;
13966 impl crate::RegisterSpec for PwmEn6Spec {
13967 type Ux = u32;
13968 }
13969 #[doc = "`read()` method returns [`pwm_en6::R`](R) reader structure"]
13970 impl crate::Readable for PwmEn6Spec {}
13971 #[doc = "`write(|w| ..)` method takes [`pwm_en6::W`](W) writer structure"]
13972 impl crate::Writable for PwmEn6Spec {
13973 type Safety = crate::Unsafe;
13974 }
13975 #[doc = "`reset()` method sets PWM_EN6 to value 0"]
13976 impl crate::Resettable for PwmEn6Spec {}
13977 }
13978 #[doc = "PWM_PORTITY6 (rw) register accessor: PWM6 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity6`] module"]
13979 #[doc(alias = "PWM_PORTITY6")]
13980 pub type PwmPortity6 = crate::Reg<pwm_portity6::PwmPortity6Spec>;
13981 #[doc = "PWM6 polarity"]
13982 pub mod pwm_portity6 {
13983 #[doc = "Register `PWM_PORTITY6` reader"]
13984 pub type R = crate::R<PwmPortity6Spec>;
13985 #[doc = "Register `PWM_PORTITY6` writer"]
13986 pub type W = crate::W<PwmPortity6Spec>;
13987 #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
13988 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
13989 pub enum PwmPoarity6 {
13990 #[doc = "0: Normal polarity"]
13991 Normal = 0,
13992 #[doc = "1: Inverted polarity"]
13993 Inverted = 1,
13994 }
13995 impl From<PwmPoarity6> for bool {
13996 #[inline(always)]
13997 fn from(variant: PwmPoarity6) -> Self {
13998 variant as u8 != 0
13999 }
14000 }
14001 #[doc = "Field `pwm_poarity_6` reader - PWM0 polarity: 0=normal; 1=inverted"]
14002 pub type PwmPoarity6R = crate::BitReader<PwmPoarity6>;
14003 impl PwmPoarity6R {
14004 #[doc = "Get enumerated values variant"]
14005 #[inline(always)]
14006 pub const fn variant(&self) -> PwmPoarity6 {
14007 match self.bits {
14008 false => PwmPoarity6::Normal,
14009 true => PwmPoarity6::Inverted,
14010 }
14011 }
14012 #[doc = "Normal polarity"]
14013 #[inline(always)]
14014 pub fn is_normal(&self) -> bool {
14015 *self == PwmPoarity6::Normal
14016 }
14017 #[doc = "Inverted polarity"]
14018 #[inline(always)]
14019 pub fn is_inverted(&self) -> bool {
14020 *self == PwmPoarity6::Inverted
14021 }
14022 }
14023 #[doc = "Field `pwm_poarity_6` writer - PWM0 polarity: 0=normal; 1=inverted"]
14024 pub type PwmPoarity6W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity6>;
14025 impl<'a, REG> PwmPoarity6W<'a, REG>
14026 where
14027 REG: crate::Writable + crate::RegisterSpec,
14028 {
14029 #[doc = "Normal polarity"]
14030 #[inline(always)]
14031 pub fn normal(self) -> &'a mut crate::W<REG> {
14032 self.variant(PwmPoarity6::Normal)
14033 }
14034 #[doc = "Inverted polarity"]
14035 #[inline(always)]
14036 pub fn inverted(self) -> &'a mut crate::W<REG> {
14037 self.variant(PwmPoarity6::Inverted)
14038 }
14039 }
14040 impl R {
14041 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
14042 #[inline(always)]
14043 pub fn pwm_poarity_6(&self) -> PwmPoarity6R {
14044 PwmPoarity6R::new((self.bits & 1) != 0)
14045 }
14046 }
14047 impl W {
14048 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
14049 #[inline(always)]
14050 pub fn pwm_poarity_6(&mut self) -> PwmPoarity6W<'_, PwmPortity6Spec> {
14051 PwmPoarity6W::new(self, 0)
14052 }
14053 }
14054 #[doc = "PWM6 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14055 pub struct PwmPortity6Spec;
14056 impl crate::RegisterSpec for PwmPortity6Spec {
14057 type Ux = u32;
14058 }
14059 #[doc = "`read()` method returns [`pwm_portity6::R`](R) reader structure"]
14060 impl crate::Readable for PwmPortity6Spec {}
14061 #[doc = "`write(|w| ..)` method takes [`pwm_portity6::W`](W) writer structure"]
14062 impl crate::Writable for PwmPortity6Spec {
14063 type Safety = crate::Unsafe;
14064 }
14065 #[doc = "`reset()` method sets PWM_PORTITY6 to value 0"]
14066 impl crate::Resettable for PwmPortity6Spec {}
14067 }
14068 #[doc = "PWM_OEN_CFG6 (rw) register accessor: PWM6 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg6`] module"]
14069 #[doc(alias = "PWM_OEN_CFG6")]
14070 pub type PwmOenCfg6 = crate::Reg<pwm_oen_cfg6::PwmOenCfg6Spec>;
14071 #[doc = "PWM6 high-impedance config"]
14072 pub mod pwm_oen_cfg6 {
14073 #[doc = "Register `PWM_OEN_CFG6` reader"]
14074 pub type R = crate::R<PwmOenCfg6Spec>;
14075 #[doc = "Register `PWM_OEN_CFG6` writer"]
14076 pub type W = crate::W<PwmOenCfg6Spec>;
14077 #[doc = "Field `pwm_oen_cfg_6` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14078 pub type PwmOenCfg6R = crate::BitReader;
14079 #[doc = "Field `pwm_oen_cfg_6` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14080 pub type PwmOenCfg6W<'a, REG> = crate::BitWriter<'a, REG>;
14081 impl R {
14082 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14083 #[inline(always)]
14084 pub fn pwm_oen_cfg_6(&self) -> PwmOenCfg6R {
14085 PwmOenCfg6R::new((self.bits & 1) != 0)
14086 }
14087 }
14088 impl W {
14089 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14090 #[inline(always)]
14091 pub fn pwm_oen_cfg_6(&mut self) -> PwmOenCfg6W<'_, PwmOenCfg6Spec> {
14092 PwmOenCfg6W::new(self, 0)
14093 }
14094 }
14095 #[doc = "PWM6 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14096 pub struct PwmOenCfg6Spec;
14097 impl crate::RegisterSpec for PwmOenCfg6Spec {
14098 type Ux = u32;
14099 }
14100 #[doc = "`read()` method returns [`pwm_oen_cfg6::R`](R) reader structure"]
14101 impl crate::Readable for PwmOenCfg6Spec {}
14102 #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg6::W`](W) writer structure"]
14103 impl crate::Writable for PwmOenCfg6Spec {
14104 type Safety = crate::Unsafe;
14105 }
14106 #[doc = "`reset()` method sets PWM_OEN_CFG6 to value 0"]
14107 impl crate::Resettable for PwmOenCfg6Spec {}
14108 }
14109 #[doc = "PWM_OFFSET_L6 (rw) register accessor: PWM6 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l6`] module"]
14110 #[doc(alias = "PWM_OFFSET_L6")]
14111 pub type PwmOffsetL6 = crate::Reg<pwm_offset_l6::PwmOffsetL6Spec>;
14112 #[doc = "PWM6 phase offset low 16 bits"]
14113 pub mod pwm_offset_l6 {
14114 #[doc = "Register `PWM_OFFSET_L6` reader"]
14115 pub type R = crate::R<PwmOffsetL6Spec>;
14116 #[doc = "Register `PWM_OFFSET_L6` writer"]
14117 pub type W = crate::W<PwmOffsetL6Spec>;
14118 #[doc = "Field `pwm_offset_l_6` reader - PWM0 phase offset low 16 bits"]
14119 pub type PwmOffsetL6R = crate::FieldReader<u16>;
14120 #[doc = "Field `pwm_offset_l_6` writer - PWM0 phase offset low 16 bits"]
14121 pub type PwmOffsetL6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14122 impl R {
14123 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
14124 #[inline(always)]
14125 pub fn pwm_offset_l_6(&self) -> PwmOffsetL6R {
14126 PwmOffsetL6R::new((self.bits & 0xffff) as u16)
14127 }
14128 }
14129 impl W {
14130 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
14131 #[inline(always)]
14132 pub fn pwm_offset_l_6(&mut self) -> PwmOffsetL6W<'_, PwmOffsetL6Spec> {
14133 PwmOffsetL6W::new(self, 0)
14134 }
14135 }
14136 #[doc = "PWM6 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14137 pub struct PwmOffsetL6Spec;
14138 impl crate::RegisterSpec for PwmOffsetL6Spec {
14139 type Ux = u32;
14140 }
14141 #[doc = "`read()` method returns [`pwm_offset_l6::R`](R) reader structure"]
14142 impl crate::Readable for PwmOffsetL6Spec {}
14143 #[doc = "`write(|w| ..)` method takes [`pwm_offset_l6::W`](W) writer structure"]
14144 impl crate::Writable for PwmOffsetL6Spec {
14145 type Safety = crate::Unsafe;
14146 }
14147 #[doc = "`reset()` method sets PWM_OFFSET_L6 to value 0"]
14148 impl crate::Resettable for PwmOffsetL6Spec {}
14149 }
14150 #[doc = "PWM_OFFSET_H6 (rw) register accessor: PWM6 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h6`] module"]
14151 #[doc(alias = "PWM_OFFSET_H6")]
14152 pub type PwmOffsetH6 = crate::Reg<pwm_offset_h6::PwmOffsetH6Spec>;
14153 #[doc = "PWM6 phase offset high 16 bits"]
14154 pub mod pwm_offset_h6 {
14155 #[doc = "Register `PWM_OFFSET_H6` reader"]
14156 pub type R = crate::R<PwmOffsetH6Spec>;
14157 #[doc = "Register `PWM_OFFSET_H6` writer"]
14158 pub type W = crate::W<PwmOffsetH6Spec>;
14159 #[doc = "Field `pwm_offset_h_6` reader - PWM0 phase offset high 16 bits"]
14160 pub type PwmOffsetH6R = crate::FieldReader<u16>;
14161 #[doc = "Field `pwm_offset_h_6` writer - PWM0 phase offset high 16 bits"]
14162 pub type PwmOffsetH6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14163 impl R {
14164 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
14165 #[inline(always)]
14166 pub fn pwm_offset_h_6(&self) -> PwmOffsetH6R {
14167 PwmOffsetH6R::new((self.bits & 0xffff) as u16)
14168 }
14169 }
14170 impl W {
14171 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
14172 #[inline(always)]
14173 pub fn pwm_offset_h_6(&mut self) -> PwmOffsetH6W<'_, PwmOffsetH6Spec> {
14174 PwmOffsetH6W::new(self, 0)
14175 }
14176 }
14177 #[doc = "PWM6 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14178 pub struct PwmOffsetH6Spec;
14179 impl crate::RegisterSpec for PwmOffsetH6Spec {
14180 type Ux = u32;
14181 }
14182 #[doc = "`read()` method returns [`pwm_offset_h6::R`](R) reader structure"]
14183 impl crate::Readable for PwmOffsetH6Spec {}
14184 #[doc = "`write(|w| ..)` method takes [`pwm_offset_h6::W`](W) writer structure"]
14185 impl crate::Writable for PwmOffsetH6Spec {
14186 type Safety = crate::Unsafe;
14187 }
14188 #[doc = "`reset()` method sets PWM_OFFSET_H6 to value 0"]
14189 impl crate::Resettable for PwmOffsetH6Spec {}
14190 }
14191 #[doc = "PWM_FREQ_L6 (rw) register accessor: PWM6 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l6`] module"]
14192 #[doc(alias = "PWM_FREQ_L6")]
14193 pub type PwmFreqL6 = crate::Reg<pwm_freq_l6::PwmFreqL6Spec>;
14194 #[doc = "PWM6 frequency low 16 bits"]
14195 pub mod pwm_freq_l6 {
14196 #[doc = "Register `PWM_FREQ_L6` reader"]
14197 pub type R = crate::R<PwmFreqL6Spec>;
14198 #[doc = "Register `PWM_FREQ_L6` writer"]
14199 pub type W = crate::W<PwmFreqL6Spec>;
14200 #[doc = "Field `pwm_freq_l_6` reader - PWM0 clock divider low 16 bits"]
14201 pub type PwmFreqL6R = crate::FieldReader<u16>;
14202 #[doc = "Field `pwm_freq_l_6` writer - PWM0 clock divider low 16 bits"]
14203 pub type PwmFreqL6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14204 impl R {
14205 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
14206 #[inline(always)]
14207 pub fn pwm_freq_l_6(&self) -> PwmFreqL6R {
14208 PwmFreqL6R::new((self.bits & 0xffff) as u16)
14209 }
14210 }
14211 impl W {
14212 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
14213 #[inline(always)]
14214 pub fn pwm_freq_l_6(&mut self) -> PwmFreqL6W<'_, PwmFreqL6Spec> {
14215 PwmFreqL6W::new(self, 0)
14216 }
14217 }
14218 #[doc = "PWM6 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14219 pub struct PwmFreqL6Spec;
14220 impl crate::RegisterSpec for PwmFreqL6Spec {
14221 type Ux = u32;
14222 }
14223 #[doc = "`read()` method returns [`pwm_freq_l6::R`](R) reader structure"]
14224 impl crate::Readable for PwmFreqL6Spec {}
14225 #[doc = "`write(|w| ..)` method takes [`pwm_freq_l6::W`](W) writer structure"]
14226 impl crate::Writable for PwmFreqL6Spec {
14227 type Safety = crate::Unsafe;
14228 }
14229 #[doc = "`reset()` method sets PWM_FREQ_L6 to value 0"]
14230 impl crate::Resettable for PwmFreqL6Spec {}
14231 }
14232 #[doc = "PWM_FREQ_H6 (rw) register accessor: PWM6 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h6`] module"]
14233 #[doc(alias = "PWM_FREQ_H6")]
14234 pub type PwmFreqH6 = crate::Reg<pwm_freq_h6::PwmFreqH6Spec>;
14235 #[doc = "PWM6 frequency high 16 bits"]
14236 pub mod pwm_freq_h6 {
14237 #[doc = "Register `PWM_FREQ_H6` reader"]
14238 pub type R = crate::R<PwmFreqH6Spec>;
14239 #[doc = "Register `PWM_FREQ_H6` writer"]
14240 pub type W = crate::W<PwmFreqH6Spec>;
14241 #[doc = "Field `pwm_freq_h_6` reader - PWM0 clock divider high 16 bits"]
14242 pub type PwmFreqH6R = crate::FieldReader<u16>;
14243 #[doc = "Field `pwm_freq_h_6` writer - PWM0 clock divider high 16 bits"]
14244 pub type PwmFreqH6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14245 impl R {
14246 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
14247 #[inline(always)]
14248 pub fn pwm_freq_h_6(&self) -> PwmFreqH6R {
14249 PwmFreqH6R::new((self.bits & 0xffff) as u16)
14250 }
14251 }
14252 impl W {
14253 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
14254 #[inline(always)]
14255 pub fn pwm_freq_h_6(&mut self) -> PwmFreqH6W<'_, PwmFreqH6Spec> {
14256 PwmFreqH6W::new(self, 0)
14257 }
14258 }
14259 #[doc = "PWM6 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14260 pub struct PwmFreqH6Spec;
14261 impl crate::RegisterSpec for PwmFreqH6Spec {
14262 type Ux = u32;
14263 }
14264 #[doc = "`read()` method returns [`pwm_freq_h6::R`](R) reader structure"]
14265 impl crate::Readable for PwmFreqH6Spec {}
14266 #[doc = "`write(|w| ..)` method takes [`pwm_freq_h6::W`](W) writer structure"]
14267 impl crate::Writable for PwmFreqH6Spec {
14268 type Safety = crate::Unsafe;
14269 }
14270 #[doc = "`reset()` method sets PWM_FREQ_H6 to value 0"]
14271 impl crate::Resettable for PwmFreqH6Spec {}
14272 }
14273 #[doc = "PWM_DUTY_L6 (rw) register accessor: PWM6 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l6`] module"]
14274 #[doc(alias = "PWM_DUTY_L6")]
14275 pub type PwmDutyL6 = crate::Reg<pwm_duty_l6::PwmDutyL6Spec>;
14276 #[doc = "PWM6 duty cycle low 16 bits"]
14277 pub mod pwm_duty_l6 {
14278 #[doc = "Register `PWM_DUTY_L6` reader"]
14279 pub type R = crate::R<PwmDutyL6Spec>;
14280 #[doc = "Register `PWM_DUTY_L6` writer"]
14281 pub type W = crate::W<PwmDutyL6Spec>;
14282 #[doc = "Field `pwm_duty_l_6` reader - PWM0 duty cycle low 16 bits"]
14283 pub type PwmDutyL6R = crate::FieldReader<u16>;
14284 #[doc = "Field `pwm_duty_l_6` writer - PWM0 duty cycle low 16 bits"]
14285 pub type PwmDutyL6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14286 impl R {
14287 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
14288 #[inline(always)]
14289 pub fn pwm_duty_l_6(&self) -> PwmDutyL6R {
14290 PwmDutyL6R::new((self.bits & 0xffff) as u16)
14291 }
14292 }
14293 impl W {
14294 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
14295 #[inline(always)]
14296 pub fn pwm_duty_l_6(&mut self) -> PwmDutyL6W<'_, PwmDutyL6Spec> {
14297 PwmDutyL6W::new(self, 0)
14298 }
14299 }
14300 #[doc = "PWM6 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14301 pub struct PwmDutyL6Spec;
14302 impl crate::RegisterSpec for PwmDutyL6Spec {
14303 type Ux = u32;
14304 }
14305 #[doc = "`read()` method returns [`pwm_duty_l6::R`](R) reader structure"]
14306 impl crate::Readable for PwmDutyL6Spec {}
14307 #[doc = "`write(|w| ..)` method takes [`pwm_duty_l6::W`](W) writer structure"]
14308 impl crate::Writable for PwmDutyL6Spec {
14309 type Safety = crate::Unsafe;
14310 }
14311 #[doc = "`reset()` method sets PWM_DUTY_L6 to value 0"]
14312 impl crate::Resettable for PwmDutyL6Spec {}
14313 }
14314 #[doc = "PWM_DUTY_H6 (rw) register accessor: PWM6 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h6`] module"]
14315 #[doc(alias = "PWM_DUTY_H6")]
14316 pub type PwmDutyH6 = crate::Reg<pwm_duty_h6::PwmDutyH6Spec>;
14317 #[doc = "PWM6 duty cycle high 16 bits"]
14318 pub mod pwm_duty_h6 {
14319 #[doc = "Register `PWM_DUTY_H6` reader"]
14320 pub type R = crate::R<PwmDutyH6Spec>;
14321 #[doc = "Register `PWM_DUTY_H6` writer"]
14322 pub type W = crate::W<PwmDutyH6Spec>;
14323 #[doc = "Field `pwm_duty_h_6` reader - PWM0 duty cycle high 16 bits"]
14324 pub type PwmDutyH6R = crate::FieldReader<u16>;
14325 #[doc = "Field `pwm_duty_h_6` writer - PWM0 duty cycle high 16 bits"]
14326 pub type PwmDutyH6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14327 impl R {
14328 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
14329 #[inline(always)]
14330 pub fn pwm_duty_h_6(&self) -> PwmDutyH6R {
14331 PwmDutyH6R::new((self.bits & 0xffff) as u16)
14332 }
14333 }
14334 impl W {
14335 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
14336 #[inline(always)]
14337 pub fn pwm_duty_h_6(&mut self) -> PwmDutyH6W<'_, PwmDutyH6Spec> {
14338 PwmDutyH6W::new(self, 0)
14339 }
14340 }
14341 #[doc = "PWM6 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14342 pub struct PwmDutyH6Spec;
14343 impl crate::RegisterSpec for PwmDutyH6Spec {
14344 type Ux = u32;
14345 }
14346 #[doc = "`read()` method returns [`pwm_duty_h6::R`](R) reader structure"]
14347 impl crate::Readable for PwmDutyH6Spec {}
14348 #[doc = "`write(|w| ..)` method takes [`pwm_duty_h6::W`](W) writer structure"]
14349 impl crate::Writable for PwmDutyH6Spec {
14350 type Safety = crate::Unsafe;
14351 }
14352 #[doc = "`reset()` method sets PWM_DUTY_H6 to value 0"]
14353 impl crate::Resettable for PwmDutyH6Spec {}
14354 }
14355 #[doc = "PWM_PERIODLOAD_FLAG6 (rw) register accessor: PWM6 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag6`] module"]
14356 #[doc(alias = "PWM_PERIODLOAD_FLAG6")]
14357 pub type PwmPeriodloadFlag6 = crate::Reg<pwm_periodload_flag6::PwmPeriodloadFlag6Spec>;
14358 #[doc = "PWM6 period load flag"]
14359 pub mod pwm_periodload_flag6 {
14360 #[doc = "Register `PWM_PERIODLOAD_FLAG6` reader"]
14361 pub type R = crate::R<PwmPeriodloadFlag6Spec>;
14362 #[doc = "Register `PWM_PERIODLOAD_FLAG6` writer"]
14363 pub type W = crate::W<PwmPeriodloadFlag6Spec>;
14364 #[doc = "Field `pwm_periodload_flag_6` reader - Period load complete flag"]
14365 pub type PwmPeriodloadFlag6R = crate::BitReader;
14366 impl R {
14367 #[doc = "Bit 0 - Period load complete flag"]
14368 #[inline(always)]
14369 pub fn pwm_periodload_flag_6(&self) -> PwmPeriodloadFlag6R {
14370 PwmPeriodloadFlag6R::new((self.bits & 1) != 0)
14371 }
14372 }
14373 impl W {}
14374 #[doc = "PWM6 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14375 pub struct PwmPeriodloadFlag6Spec;
14376 impl crate::RegisterSpec for PwmPeriodloadFlag6Spec {
14377 type Ux = u32;
14378 }
14379 #[doc = "`read()` method returns [`pwm_periodload_flag6::R`](R) reader structure"]
14380 impl crate::Readable for PwmPeriodloadFlag6Spec {}
14381 #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag6::W`](W) writer structure"]
14382 impl crate::Writable for PwmPeriodloadFlag6Spec {
14383 type Safety = crate::Unsafe;
14384 }
14385 #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG6 to value 0"]
14386 impl crate::Resettable for PwmPeriodloadFlag6Spec {}
14387 }
14388 #[doc = "PWM_PERIOD_VAL6 (rw) register accessor: PWM6 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val6`] module"]
14389 #[doc(alias = "PWM_PERIOD_VAL6")]
14390 pub type PwmPeriodVal6 = crate::Reg<pwm_period_val6::PwmPeriodVal6Spec>;
14391 #[doc = "PWM6 pulse count value"]
14392 pub mod pwm_period_val6 {
14393 #[doc = "Register `PWM_PERIOD_VAL6` reader"]
14394 pub type R = crate::R<PwmPeriodVal6Spec>;
14395 #[doc = "Register `PWM_PERIOD_VAL6` writer"]
14396 pub type W = crate::W<PwmPeriodVal6Spec>;
14397 #[doc = "Field `pwm_period_val_6` reader - Pulse count for stepping mode"]
14398 pub type PwmPeriodVal6R = crate::FieldReader<u16>;
14399 #[doc = "Field `pwm_period_val_6` writer - Pulse count for stepping mode"]
14400 pub type PwmPeriodVal6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14401 impl R {
14402 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
14403 #[inline(always)]
14404 pub fn pwm_period_val_6(&self) -> PwmPeriodVal6R {
14405 PwmPeriodVal6R::new((self.bits & 0xffff) as u16)
14406 }
14407 }
14408 impl W {
14409 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
14410 #[inline(always)]
14411 pub fn pwm_period_val_6(&mut self) -> PwmPeriodVal6W<'_, PwmPeriodVal6Spec> {
14412 PwmPeriodVal6W::new(self, 0)
14413 }
14414 }
14415 #[doc = "PWM6 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14416 pub struct PwmPeriodVal6Spec;
14417 impl crate::RegisterSpec for PwmPeriodVal6Spec {
14418 type Ux = u32;
14419 }
14420 #[doc = "`read()` method returns [`pwm_period_val6::R`](R) reader structure"]
14421 impl crate::Readable for PwmPeriodVal6Spec {}
14422 #[doc = "`write(|w| ..)` method takes [`pwm_period_val6::W`](W) writer structure"]
14423 impl crate::Writable for PwmPeriodVal6Spec {
14424 type Safety = crate::Unsafe;
14425 }
14426 #[doc = "`reset()` method sets PWM_PERIOD_VAL6 to value 0"]
14427 impl crate::Resettable for PwmPeriodVal6Spec {}
14428 }
14429 #[doc = "PWM_PERIODCNT6 (rw) register accessor: PWM6 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt6`] module"]
14430 #[doc(alias = "PWM_PERIODCNT6")]
14431 pub type PwmPeriodcnt6 = crate::Reg<pwm_periodcnt6::PwmPeriodcnt6Spec>;
14432 #[doc = "PWM6 pulse count current value"]
14433 pub mod pwm_periodcnt6 {
14434 #[doc = "Register `PWM_PERIODCNT6` reader"]
14435 pub type R = crate::R<PwmPeriodcnt6Spec>;
14436 #[doc = "Register `PWM_PERIODCNT6` writer"]
14437 pub type W = crate::W<PwmPeriodcnt6Spec>;
14438 #[doc = "Field `pwm_periodcnt_6` reader - Current pulse count"]
14439 pub type PwmPeriodcnt6R = crate::FieldReader<u16>;
14440 impl R {
14441 #[doc = "Bits 0:15 - Current pulse count"]
14442 #[inline(always)]
14443 pub fn pwm_periodcnt_6(&self) -> PwmPeriodcnt6R {
14444 PwmPeriodcnt6R::new((self.bits & 0xffff) as u16)
14445 }
14446 }
14447 impl W {}
14448 #[doc = "PWM6 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14449 pub struct PwmPeriodcnt6Spec;
14450 impl crate::RegisterSpec for PwmPeriodcnt6Spec {
14451 type Ux = u32;
14452 }
14453 #[doc = "`read()` method returns [`pwm_periodcnt6::R`](R) reader structure"]
14454 impl crate::Readable for PwmPeriodcnt6Spec {}
14455 #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt6::W`](W) writer structure"]
14456 impl crate::Writable for PwmPeriodcnt6Spec {
14457 type Safety = crate::Unsafe;
14458 }
14459 #[doc = "`reset()` method sets PWM_PERIODCNT6 to value 0"]
14460 impl crate::Resettable for PwmPeriodcnt6Spec {}
14461 }
14462 #[doc = "PWM_EN7 (rw) register accessor: PWM7 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en7`] module"]
14463 #[doc(alias = "PWM_EN7")]
14464 pub type PwmEn7 = crate::Reg<pwm_en7::PwmEn7Spec>;
14465 #[doc = "PWM7 enable"]
14466 pub mod pwm_en7 {
14467 #[doc = "Register `PWM_EN7` reader"]
14468 pub type R = crate::R<PwmEn7Spec>;
14469 #[doc = "Register `PWM_EN7` writer"]
14470 pub type W = crate::W<PwmEn7Spec>;
14471 #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
14472 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
14473 pub enum PwmEn7 {
14474 #[doc = "0: PWM disabled, output low"]
14475 Off = 0,
14476 #[doc = "1: PWM enabled"]
14477 On = 1,
14478 }
14479 impl From<PwmEn7> for bool {
14480 #[inline(always)]
14481 fn from(variant: PwmEn7) -> Self {
14482 variant as u8 != 0
14483 }
14484 }
14485 #[doc = "Field `pwm_en_7` reader - PWM0 enable: 0=off; 1=on"]
14486 pub type PwmEn7R = crate::BitReader<PwmEn7>;
14487 impl PwmEn7R {
14488 #[doc = "Get enumerated values variant"]
14489 #[inline(always)]
14490 pub const fn variant(&self) -> PwmEn7 {
14491 match self.bits {
14492 false => PwmEn7::Off,
14493 true => PwmEn7::On,
14494 }
14495 }
14496 #[doc = "PWM disabled, output low"]
14497 #[inline(always)]
14498 pub fn is_off(&self) -> bool {
14499 *self == PwmEn7::Off
14500 }
14501 #[doc = "PWM enabled"]
14502 #[inline(always)]
14503 pub fn is_on(&self) -> bool {
14504 *self == PwmEn7::On
14505 }
14506 }
14507 #[doc = "Field `pwm_en_7` writer - PWM0 enable: 0=off; 1=on"]
14508 pub type PwmEn7W<'a, REG> = crate::BitWriter<'a, REG, PwmEn7>;
14509 impl<'a, REG> PwmEn7W<'a, REG>
14510 where
14511 REG: crate::Writable + crate::RegisterSpec,
14512 {
14513 #[doc = "PWM disabled, output low"]
14514 #[inline(always)]
14515 pub fn off(self) -> &'a mut crate::W<REG> {
14516 self.variant(PwmEn7::Off)
14517 }
14518 #[doc = "PWM enabled"]
14519 #[inline(always)]
14520 pub fn on(self) -> &'a mut crate::W<REG> {
14521 self.variant(PwmEn7::On)
14522 }
14523 }
14524 impl R {
14525 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
14526 #[inline(always)]
14527 pub fn pwm_en_7(&self) -> PwmEn7R {
14528 PwmEn7R::new((self.bits & 1) != 0)
14529 }
14530 }
14531 impl W {
14532 #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
14533 #[inline(always)]
14534 pub fn pwm_en_7(&mut self) -> PwmEn7W<'_, PwmEn7Spec> {
14535 PwmEn7W::new(self, 0)
14536 }
14537 }
14538 #[doc = "PWM7 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14539 pub struct PwmEn7Spec;
14540 impl crate::RegisterSpec for PwmEn7Spec {
14541 type Ux = u32;
14542 }
14543 #[doc = "`read()` method returns [`pwm_en7::R`](R) reader structure"]
14544 impl crate::Readable for PwmEn7Spec {}
14545 #[doc = "`write(|w| ..)` method takes [`pwm_en7::W`](W) writer structure"]
14546 impl crate::Writable for PwmEn7Spec {
14547 type Safety = crate::Unsafe;
14548 }
14549 #[doc = "`reset()` method sets PWM_EN7 to value 0"]
14550 impl crate::Resettable for PwmEn7Spec {}
14551 }
14552 #[doc = "PWM_PORTITY7 (rw) register accessor: PWM7 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity7`] module"]
14553 #[doc(alias = "PWM_PORTITY7")]
14554 pub type PwmPortity7 = crate::Reg<pwm_portity7::PwmPortity7Spec>;
14555 #[doc = "PWM7 polarity"]
14556 pub mod pwm_portity7 {
14557 #[doc = "Register `PWM_PORTITY7` reader"]
14558 pub type R = crate::R<PwmPortity7Spec>;
14559 #[doc = "Register `PWM_PORTITY7` writer"]
14560 pub type W = crate::W<PwmPortity7Spec>;
14561 #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
14562 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
14563 pub enum PwmPoarity7 {
14564 #[doc = "0: Normal polarity"]
14565 Normal = 0,
14566 #[doc = "1: Inverted polarity"]
14567 Inverted = 1,
14568 }
14569 impl From<PwmPoarity7> for bool {
14570 #[inline(always)]
14571 fn from(variant: PwmPoarity7) -> Self {
14572 variant as u8 != 0
14573 }
14574 }
14575 #[doc = "Field `pwm_poarity_7` reader - PWM0 polarity: 0=normal; 1=inverted"]
14576 pub type PwmPoarity7R = crate::BitReader<PwmPoarity7>;
14577 impl PwmPoarity7R {
14578 #[doc = "Get enumerated values variant"]
14579 #[inline(always)]
14580 pub const fn variant(&self) -> PwmPoarity7 {
14581 match self.bits {
14582 false => PwmPoarity7::Normal,
14583 true => PwmPoarity7::Inverted,
14584 }
14585 }
14586 #[doc = "Normal polarity"]
14587 #[inline(always)]
14588 pub fn is_normal(&self) -> bool {
14589 *self == PwmPoarity7::Normal
14590 }
14591 #[doc = "Inverted polarity"]
14592 #[inline(always)]
14593 pub fn is_inverted(&self) -> bool {
14594 *self == PwmPoarity7::Inverted
14595 }
14596 }
14597 #[doc = "Field `pwm_poarity_7` writer - PWM0 polarity: 0=normal; 1=inverted"]
14598 pub type PwmPoarity7W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity7>;
14599 impl<'a, REG> PwmPoarity7W<'a, REG>
14600 where
14601 REG: crate::Writable + crate::RegisterSpec,
14602 {
14603 #[doc = "Normal polarity"]
14604 #[inline(always)]
14605 pub fn normal(self) -> &'a mut crate::W<REG> {
14606 self.variant(PwmPoarity7::Normal)
14607 }
14608 #[doc = "Inverted polarity"]
14609 #[inline(always)]
14610 pub fn inverted(self) -> &'a mut crate::W<REG> {
14611 self.variant(PwmPoarity7::Inverted)
14612 }
14613 }
14614 impl R {
14615 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
14616 #[inline(always)]
14617 pub fn pwm_poarity_7(&self) -> PwmPoarity7R {
14618 PwmPoarity7R::new((self.bits & 1) != 0)
14619 }
14620 }
14621 impl W {
14622 #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
14623 #[inline(always)]
14624 pub fn pwm_poarity_7(&mut self) -> PwmPoarity7W<'_, PwmPortity7Spec> {
14625 PwmPoarity7W::new(self, 0)
14626 }
14627 }
14628 #[doc = "PWM7 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14629 pub struct PwmPortity7Spec;
14630 impl crate::RegisterSpec for PwmPortity7Spec {
14631 type Ux = u32;
14632 }
14633 #[doc = "`read()` method returns [`pwm_portity7::R`](R) reader structure"]
14634 impl crate::Readable for PwmPortity7Spec {}
14635 #[doc = "`write(|w| ..)` method takes [`pwm_portity7::W`](W) writer structure"]
14636 impl crate::Writable for PwmPortity7Spec {
14637 type Safety = crate::Unsafe;
14638 }
14639 #[doc = "`reset()` method sets PWM_PORTITY7 to value 0"]
14640 impl crate::Resettable for PwmPortity7Spec {}
14641 }
14642 #[doc = "PWM_OEN_CFG7 (rw) register accessor: PWM7 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg7`] module"]
14643 #[doc(alias = "PWM_OEN_CFG7")]
14644 pub type PwmOenCfg7 = crate::Reg<pwm_oen_cfg7::PwmOenCfg7Spec>;
14645 #[doc = "PWM7 high-impedance config"]
14646 pub mod pwm_oen_cfg7 {
14647 #[doc = "Register `PWM_OEN_CFG7` reader"]
14648 pub type R = crate::R<PwmOenCfg7Spec>;
14649 #[doc = "Register `PWM_OEN_CFG7` writer"]
14650 pub type W = crate::W<PwmOenCfg7Spec>;
14651 #[doc = "Field `pwm_oen_cfg_7` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14652 pub type PwmOenCfg7R = crate::BitReader;
14653 #[doc = "Field `pwm_oen_cfg_7` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14654 pub type PwmOenCfg7W<'a, REG> = crate::BitWriter<'a, REG>;
14655 impl R {
14656 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14657 #[inline(always)]
14658 pub fn pwm_oen_cfg_7(&self) -> PwmOenCfg7R {
14659 PwmOenCfg7R::new((self.bits & 1) != 0)
14660 }
14661 }
14662 impl W {
14663 #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
14664 #[inline(always)]
14665 pub fn pwm_oen_cfg_7(&mut self) -> PwmOenCfg7W<'_, PwmOenCfg7Spec> {
14666 PwmOenCfg7W::new(self, 0)
14667 }
14668 }
14669 #[doc = "PWM7 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14670 pub struct PwmOenCfg7Spec;
14671 impl crate::RegisterSpec for PwmOenCfg7Spec {
14672 type Ux = u32;
14673 }
14674 #[doc = "`read()` method returns [`pwm_oen_cfg7::R`](R) reader structure"]
14675 impl crate::Readable for PwmOenCfg7Spec {}
14676 #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg7::W`](W) writer structure"]
14677 impl crate::Writable for PwmOenCfg7Spec {
14678 type Safety = crate::Unsafe;
14679 }
14680 #[doc = "`reset()` method sets PWM_OEN_CFG7 to value 0"]
14681 impl crate::Resettable for PwmOenCfg7Spec {}
14682 }
14683 #[doc = "PWM_OFFSET_L7 (rw) register accessor: PWM7 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l7`] module"]
14684 #[doc(alias = "PWM_OFFSET_L7")]
14685 pub type PwmOffsetL7 = crate::Reg<pwm_offset_l7::PwmOffsetL7Spec>;
14686 #[doc = "PWM7 phase offset low 16 bits"]
14687 pub mod pwm_offset_l7 {
14688 #[doc = "Register `PWM_OFFSET_L7` reader"]
14689 pub type R = crate::R<PwmOffsetL7Spec>;
14690 #[doc = "Register `PWM_OFFSET_L7` writer"]
14691 pub type W = crate::W<PwmOffsetL7Spec>;
14692 #[doc = "Field `pwm_offset_l_7` reader - PWM0 phase offset low 16 bits"]
14693 pub type PwmOffsetL7R = crate::FieldReader<u16>;
14694 #[doc = "Field `pwm_offset_l_7` writer - PWM0 phase offset low 16 bits"]
14695 pub type PwmOffsetL7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14696 impl R {
14697 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
14698 #[inline(always)]
14699 pub fn pwm_offset_l_7(&self) -> PwmOffsetL7R {
14700 PwmOffsetL7R::new((self.bits & 0xffff) as u16)
14701 }
14702 }
14703 impl W {
14704 #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
14705 #[inline(always)]
14706 pub fn pwm_offset_l_7(&mut self) -> PwmOffsetL7W<'_, PwmOffsetL7Spec> {
14707 PwmOffsetL7W::new(self, 0)
14708 }
14709 }
14710 #[doc = "PWM7 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14711 pub struct PwmOffsetL7Spec;
14712 impl crate::RegisterSpec for PwmOffsetL7Spec {
14713 type Ux = u32;
14714 }
14715 #[doc = "`read()` method returns [`pwm_offset_l7::R`](R) reader structure"]
14716 impl crate::Readable for PwmOffsetL7Spec {}
14717 #[doc = "`write(|w| ..)` method takes [`pwm_offset_l7::W`](W) writer structure"]
14718 impl crate::Writable for PwmOffsetL7Spec {
14719 type Safety = crate::Unsafe;
14720 }
14721 #[doc = "`reset()` method sets PWM_OFFSET_L7 to value 0"]
14722 impl crate::Resettable for PwmOffsetL7Spec {}
14723 }
14724 #[doc = "PWM_OFFSET_H7 (rw) register accessor: PWM7 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h7`] module"]
14725 #[doc(alias = "PWM_OFFSET_H7")]
14726 pub type PwmOffsetH7 = crate::Reg<pwm_offset_h7::PwmOffsetH7Spec>;
14727 #[doc = "PWM7 phase offset high 16 bits"]
14728 pub mod pwm_offset_h7 {
14729 #[doc = "Register `PWM_OFFSET_H7` reader"]
14730 pub type R = crate::R<PwmOffsetH7Spec>;
14731 #[doc = "Register `PWM_OFFSET_H7` writer"]
14732 pub type W = crate::W<PwmOffsetH7Spec>;
14733 #[doc = "Field `pwm_offset_h_7` reader - PWM0 phase offset high 16 bits"]
14734 pub type PwmOffsetH7R = crate::FieldReader<u16>;
14735 #[doc = "Field `pwm_offset_h_7` writer - PWM0 phase offset high 16 bits"]
14736 pub type PwmOffsetH7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14737 impl R {
14738 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
14739 #[inline(always)]
14740 pub fn pwm_offset_h_7(&self) -> PwmOffsetH7R {
14741 PwmOffsetH7R::new((self.bits & 0xffff) as u16)
14742 }
14743 }
14744 impl W {
14745 #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
14746 #[inline(always)]
14747 pub fn pwm_offset_h_7(&mut self) -> PwmOffsetH7W<'_, PwmOffsetH7Spec> {
14748 PwmOffsetH7W::new(self, 0)
14749 }
14750 }
14751 #[doc = "PWM7 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14752 pub struct PwmOffsetH7Spec;
14753 impl crate::RegisterSpec for PwmOffsetH7Spec {
14754 type Ux = u32;
14755 }
14756 #[doc = "`read()` method returns [`pwm_offset_h7::R`](R) reader structure"]
14757 impl crate::Readable for PwmOffsetH7Spec {}
14758 #[doc = "`write(|w| ..)` method takes [`pwm_offset_h7::W`](W) writer structure"]
14759 impl crate::Writable for PwmOffsetH7Spec {
14760 type Safety = crate::Unsafe;
14761 }
14762 #[doc = "`reset()` method sets PWM_OFFSET_H7 to value 0"]
14763 impl crate::Resettable for PwmOffsetH7Spec {}
14764 }
14765 #[doc = "PWM_FREQ_L7 (rw) register accessor: PWM7 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l7`] module"]
14766 #[doc(alias = "PWM_FREQ_L7")]
14767 pub type PwmFreqL7 = crate::Reg<pwm_freq_l7::PwmFreqL7Spec>;
14768 #[doc = "PWM7 frequency low 16 bits"]
14769 pub mod pwm_freq_l7 {
14770 #[doc = "Register `PWM_FREQ_L7` reader"]
14771 pub type R = crate::R<PwmFreqL7Spec>;
14772 #[doc = "Register `PWM_FREQ_L7` writer"]
14773 pub type W = crate::W<PwmFreqL7Spec>;
14774 #[doc = "Field `pwm_freq_l_7` reader - PWM0 clock divider low 16 bits"]
14775 pub type PwmFreqL7R = crate::FieldReader<u16>;
14776 #[doc = "Field `pwm_freq_l_7` writer - PWM0 clock divider low 16 bits"]
14777 pub type PwmFreqL7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14778 impl R {
14779 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
14780 #[inline(always)]
14781 pub fn pwm_freq_l_7(&self) -> PwmFreqL7R {
14782 PwmFreqL7R::new((self.bits & 0xffff) as u16)
14783 }
14784 }
14785 impl W {
14786 #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
14787 #[inline(always)]
14788 pub fn pwm_freq_l_7(&mut self) -> PwmFreqL7W<'_, PwmFreqL7Spec> {
14789 PwmFreqL7W::new(self, 0)
14790 }
14791 }
14792 #[doc = "PWM7 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14793 pub struct PwmFreqL7Spec;
14794 impl crate::RegisterSpec for PwmFreqL7Spec {
14795 type Ux = u32;
14796 }
14797 #[doc = "`read()` method returns [`pwm_freq_l7::R`](R) reader structure"]
14798 impl crate::Readable for PwmFreqL7Spec {}
14799 #[doc = "`write(|w| ..)` method takes [`pwm_freq_l7::W`](W) writer structure"]
14800 impl crate::Writable for PwmFreqL7Spec {
14801 type Safety = crate::Unsafe;
14802 }
14803 #[doc = "`reset()` method sets PWM_FREQ_L7 to value 0"]
14804 impl crate::Resettable for PwmFreqL7Spec {}
14805 }
14806 #[doc = "PWM_FREQ_H7 (rw) register accessor: PWM7 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h7`] module"]
14807 #[doc(alias = "PWM_FREQ_H7")]
14808 pub type PwmFreqH7 = crate::Reg<pwm_freq_h7::PwmFreqH7Spec>;
14809 #[doc = "PWM7 frequency high 16 bits"]
14810 pub mod pwm_freq_h7 {
14811 #[doc = "Register `PWM_FREQ_H7` reader"]
14812 pub type R = crate::R<PwmFreqH7Spec>;
14813 #[doc = "Register `PWM_FREQ_H7` writer"]
14814 pub type W = crate::W<PwmFreqH7Spec>;
14815 #[doc = "Field `pwm_freq_h_7` reader - PWM0 clock divider high 16 bits"]
14816 pub type PwmFreqH7R = crate::FieldReader<u16>;
14817 #[doc = "Field `pwm_freq_h_7` writer - PWM0 clock divider high 16 bits"]
14818 pub type PwmFreqH7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14819 impl R {
14820 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
14821 #[inline(always)]
14822 pub fn pwm_freq_h_7(&self) -> PwmFreqH7R {
14823 PwmFreqH7R::new((self.bits & 0xffff) as u16)
14824 }
14825 }
14826 impl W {
14827 #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
14828 #[inline(always)]
14829 pub fn pwm_freq_h_7(&mut self) -> PwmFreqH7W<'_, PwmFreqH7Spec> {
14830 PwmFreqH7W::new(self, 0)
14831 }
14832 }
14833 #[doc = "PWM7 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14834 pub struct PwmFreqH7Spec;
14835 impl crate::RegisterSpec for PwmFreqH7Spec {
14836 type Ux = u32;
14837 }
14838 #[doc = "`read()` method returns [`pwm_freq_h7::R`](R) reader structure"]
14839 impl crate::Readable for PwmFreqH7Spec {}
14840 #[doc = "`write(|w| ..)` method takes [`pwm_freq_h7::W`](W) writer structure"]
14841 impl crate::Writable for PwmFreqH7Spec {
14842 type Safety = crate::Unsafe;
14843 }
14844 #[doc = "`reset()` method sets PWM_FREQ_H7 to value 0"]
14845 impl crate::Resettable for PwmFreqH7Spec {}
14846 }
14847 #[doc = "PWM_DUTY_L7 (rw) register accessor: PWM7 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l7`] module"]
14848 #[doc(alias = "PWM_DUTY_L7")]
14849 pub type PwmDutyL7 = crate::Reg<pwm_duty_l7::PwmDutyL7Spec>;
14850 #[doc = "PWM7 duty cycle low 16 bits"]
14851 pub mod pwm_duty_l7 {
14852 #[doc = "Register `PWM_DUTY_L7` reader"]
14853 pub type R = crate::R<PwmDutyL7Spec>;
14854 #[doc = "Register `PWM_DUTY_L7` writer"]
14855 pub type W = crate::W<PwmDutyL7Spec>;
14856 #[doc = "Field `pwm_duty_l_7` reader - PWM0 duty cycle low 16 bits"]
14857 pub type PwmDutyL7R = crate::FieldReader<u16>;
14858 #[doc = "Field `pwm_duty_l_7` writer - PWM0 duty cycle low 16 bits"]
14859 pub type PwmDutyL7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14860 impl R {
14861 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
14862 #[inline(always)]
14863 pub fn pwm_duty_l_7(&self) -> PwmDutyL7R {
14864 PwmDutyL7R::new((self.bits & 0xffff) as u16)
14865 }
14866 }
14867 impl W {
14868 #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
14869 #[inline(always)]
14870 pub fn pwm_duty_l_7(&mut self) -> PwmDutyL7W<'_, PwmDutyL7Spec> {
14871 PwmDutyL7W::new(self, 0)
14872 }
14873 }
14874 #[doc = "PWM7 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14875 pub struct PwmDutyL7Spec;
14876 impl crate::RegisterSpec for PwmDutyL7Spec {
14877 type Ux = u32;
14878 }
14879 #[doc = "`read()` method returns [`pwm_duty_l7::R`](R) reader structure"]
14880 impl crate::Readable for PwmDutyL7Spec {}
14881 #[doc = "`write(|w| ..)` method takes [`pwm_duty_l7::W`](W) writer structure"]
14882 impl crate::Writable for PwmDutyL7Spec {
14883 type Safety = crate::Unsafe;
14884 }
14885 #[doc = "`reset()` method sets PWM_DUTY_L7 to value 0"]
14886 impl crate::Resettable for PwmDutyL7Spec {}
14887 }
14888 #[doc = "PWM_DUTY_H7 (rw) register accessor: PWM7 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h7`] module"]
14889 #[doc(alias = "PWM_DUTY_H7")]
14890 pub type PwmDutyH7 = crate::Reg<pwm_duty_h7::PwmDutyH7Spec>;
14891 #[doc = "PWM7 duty cycle high 16 bits"]
14892 pub mod pwm_duty_h7 {
14893 #[doc = "Register `PWM_DUTY_H7` reader"]
14894 pub type R = crate::R<PwmDutyH7Spec>;
14895 #[doc = "Register `PWM_DUTY_H7` writer"]
14896 pub type W = crate::W<PwmDutyH7Spec>;
14897 #[doc = "Field `pwm_duty_h_7` reader - PWM0 duty cycle high 16 bits"]
14898 pub type PwmDutyH7R = crate::FieldReader<u16>;
14899 #[doc = "Field `pwm_duty_h_7` writer - PWM0 duty cycle high 16 bits"]
14900 pub type PwmDutyH7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14901 impl R {
14902 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
14903 #[inline(always)]
14904 pub fn pwm_duty_h_7(&self) -> PwmDutyH7R {
14905 PwmDutyH7R::new((self.bits & 0xffff) as u16)
14906 }
14907 }
14908 impl W {
14909 #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
14910 #[inline(always)]
14911 pub fn pwm_duty_h_7(&mut self) -> PwmDutyH7W<'_, PwmDutyH7Spec> {
14912 PwmDutyH7W::new(self, 0)
14913 }
14914 }
14915 #[doc = "PWM7 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14916 pub struct PwmDutyH7Spec;
14917 impl crate::RegisterSpec for PwmDutyH7Spec {
14918 type Ux = u32;
14919 }
14920 #[doc = "`read()` method returns [`pwm_duty_h7::R`](R) reader structure"]
14921 impl crate::Readable for PwmDutyH7Spec {}
14922 #[doc = "`write(|w| ..)` method takes [`pwm_duty_h7::W`](W) writer structure"]
14923 impl crate::Writable for PwmDutyH7Spec {
14924 type Safety = crate::Unsafe;
14925 }
14926 #[doc = "`reset()` method sets PWM_DUTY_H7 to value 0"]
14927 impl crate::Resettable for PwmDutyH7Spec {}
14928 }
14929 #[doc = "PWM_PERIODLOAD_FLAG7 (rw) register accessor: PWM7 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag7`] module"]
14930 #[doc(alias = "PWM_PERIODLOAD_FLAG7")]
14931 pub type PwmPeriodloadFlag7 = crate::Reg<pwm_periodload_flag7::PwmPeriodloadFlag7Spec>;
14932 #[doc = "PWM7 period load flag"]
14933 pub mod pwm_periodload_flag7 {
14934 #[doc = "Register `PWM_PERIODLOAD_FLAG7` reader"]
14935 pub type R = crate::R<PwmPeriodloadFlag7Spec>;
14936 #[doc = "Register `PWM_PERIODLOAD_FLAG7` writer"]
14937 pub type W = crate::W<PwmPeriodloadFlag7Spec>;
14938 #[doc = "Field `pwm_periodload_flag_7` reader - Period load complete flag"]
14939 pub type PwmPeriodloadFlag7R = crate::BitReader;
14940 impl R {
14941 #[doc = "Bit 0 - Period load complete flag"]
14942 #[inline(always)]
14943 pub fn pwm_periodload_flag_7(&self) -> PwmPeriodloadFlag7R {
14944 PwmPeriodloadFlag7R::new((self.bits & 1) != 0)
14945 }
14946 }
14947 impl W {}
14948 #[doc = "PWM7 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14949 pub struct PwmPeriodloadFlag7Spec;
14950 impl crate::RegisterSpec for PwmPeriodloadFlag7Spec {
14951 type Ux = u32;
14952 }
14953 #[doc = "`read()` method returns [`pwm_periodload_flag7::R`](R) reader structure"]
14954 impl crate::Readable for PwmPeriodloadFlag7Spec {}
14955 #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag7::W`](W) writer structure"]
14956 impl crate::Writable for PwmPeriodloadFlag7Spec {
14957 type Safety = crate::Unsafe;
14958 }
14959 #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG7 to value 0"]
14960 impl crate::Resettable for PwmPeriodloadFlag7Spec {}
14961 }
14962 #[doc = "PWM_PERIOD_VAL7 (rw) register accessor: PWM7 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val7`] module"]
14963 #[doc(alias = "PWM_PERIOD_VAL7")]
14964 pub type PwmPeriodVal7 = crate::Reg<pwm_period_val7::PwmPeriodVal7Spec>;
14965 #[doc = "PWM7 pulse count value"]
14966 pub mod pwm_period_val7 {
14967 #[doc = "Register `PWM_PERIOD_VAL7` reader"]
14968 pub type R = crate::R<PwmPeriodVal7Spec>;
14969 #[doc = "Register `PWM_PERIOD_VAL7` writer"]
14970 pub type W = crate::W<PwmPeriodVal7Spec>;
14971 #[doc = "Field `pwm_period_val_7` reader - Pulse count for stepping mode"]
14972 pub type PwmPeriodVal7R = crate::FieldReader<u16>;
14973 #[doc = "Field `pwm_period_val_7` writer - Pulse count for stepping mode"]
14974 pub type PwmPeriodVal7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
14975 impl R {
14976 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
14977 #[inline(always)]
14978 pub fn pwm_period_val_7(&self) -> PwmPeriodVal7R {
14979 PwmPeriodVal7R::new((self.bits & 0xffff) as u16)
14980 }
14981 }
14982 impl W {
14983 #[doc = "Bits 0:15 - Pulse count for stepping mode"]
14984 #[inline(always)]
14985 pub fn pwm_period_val_7(&mut self) -> PwmPeriodVal7W<'_, PwmPeriodVal7Spec> {
14986 PwmPeriodVal7W::new(self, 0)
14987 }
14988 }
14989 #[doc = "PWM7 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
14990 pub struct PwmPeriodVal7Spec;
14991 impl crate::RegisterSpec for PwmPeriodVal7Spec {
14992 type Ux = u32;
14993 }
14994 #[doc = "`read()` method returns [`pwm_period_val7::R`](R) reader structure"]
14995 impl crate::Readable for PwmPeriodVal7Spec {}
14996 #[doc = "`write(|w| ..)` method takes [`pwm_period_val7::W`](W) writer structure"]
14997 impl crate::Writable for PwmPeriodVal7Spec {
14998 type Safety = crate::Unsafe;
14999 }
15000 #[doc = "`reset()` method sets PWM_PERIOD_VAL7 to value 0"]
15001 impl crate::Resettable for PwmPeriodVal7Spec {}
15002 }
15003 #[doc = "PWM_PERIODCNT7 (rw) register accessor: PWM7 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt7`] module"]
15004 #[doc(alias = "PWM_PERIODCNT7")]
15005 pub type PwmPeriodcnt7 = crate::Reg<pwm_periodcnt7::PwmPeriodcnt7Spec>;
15006 #[doc = "PWM7 pulse count current value"]
15007 pub mod pwm_periodcnt7 {
15008 #[doc = "Register `PWM_PERIODCNT7` reader"]
15009 pub type R = crate::R<PwmPeriodcnt7Spec>;
15010 #[doc = "Register `PWM_PERIODCNT7` writer"]
15011 pub type W = crate::W<PwmPeriodcnt7Spec>;
15012 #[doc = "Field `pwm_periodcnt_7` reader - Current pulse count"]
15013 pub type PwmPeriodcnt7R = crate::FieldReader<u16>;
15014 impl R {
15015 #[doc = "Bits 0:15 - Current pulse count"]
15016 #[inline(always)]
15017 pub fn pwm_periodcnt_7(&self) -> PwmPeriodcnt7R {
15018 PwmPeriodcnt7R::new((self.bits & 0xffff) as u16)
15019 }
15020 }
15021 impl W {}
15022 #[doc = "PWM7 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15023 pub struct PwmPeriodcnt7Spec;
15024 impl crate::RegisterSpec for PwmPeriodcnt7Spec {
15025 type Ux = u32;
15026 }
15027 #[doc = "`read()` method returns [`pwm_periodcnt7::R`](R) reader structure"]
15028 impl crate::Readable for PwmPeriodcnt7Spec {}
15029 #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt7::W`](W) writer structure"]
15030 impl crate::Writable for PwmPeriodcnt7Spec {
15031 type Safety = crate::Unsafe;
15032 }
15033 #[doc = "`reset()` method sets PWM_PERIODCNT7 to value 0"]
15034 impl crate::Resettable for PwmPeriodcnt7Spec {}
15035 }
15036}
15037#[doc = "DMA controller with 4 channels"]
15038pub type Dma = crate::Periph<dma::RegisterBlock, 0x5207_0000>;
15039impl core::fmt::Debug for Dma {
15040 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15041 f.debug_struct("Dma").finish()
15042 }
15043}
15044#[doc = "DMA controller with 4 channels"]
15045pub mod dma {
15046 #[repr(C)]
15047 #[doc = "Register block"]
15048 pub struct RegisterBlock {
15049 _reserved0: [u8; 0x04],
15050 dmac_int_st: DmacIntSt,
15051 dmac_int_clr: DmacIntClr,
15052 dmac_ori_int_st: DmacOriIntSt,
15053 dmac_en_chns: DmacEnChns,
15054 dmac_burst_req: DmacBurstReq,
15055 dmac_single_req: DmacSingleReq,
15056 dmac_config: DmacConfig,
15057 dmac_sync: DmacSync,
15058 _reserved8: [u8; 0xdc],
15059 dmac_lli_0: (),
15060 _reserved9: [u8; 0x04],
15061 dmac_d_addr_0: (),
15062 _reserved10: [u8; 0x04],
15063 dmac_chn_config_0: (),
15064 _reserved11: [u8; 0x08],
15065 dmac_s_addr_0: (),
15066 _reserved12: [u8; 0x04],
15067 dmac_chn_control_0: (),
15068 }
15069 impl RegisterBlock {
15070 #[doc = "0x04 - Interrupt status register"]
15071 #[inline(always)]
15072 pub const fn dmac_int_st(&self) -> &DmacIntSt {
15073 &self.dmac_int_st
15074 }
15075 #[doc = "0x08 - Interrupt clear register"]
15076 #[inline(always)]
15077 pub const fn dmac_int_clr(&self) -> &DmacIntClr {
15078 &self.dmac_int_clr
15079 }
15080 #[doc = "0x0c - Raw interrupt status register"]
15081 #[inline(always)]
15082 pub const fn dmac_ori_int_st(&self) -> &DmacOriIntSt {
15083 &self.dmac_ori_int_st
15084 }
15085 #[doc = "0x10 - Channel enable query register"]
15086 #[inline(always)]
15087 pub const fn dmac_en_chns(&self) -> &DmacEnChns {
15088 &self.dmac_en_chns
15089 }
15090 #[doc = "0x14 - Burst software request register"]
15091 #[inline(always)]
15092 pub const fn dmac_burst_req(&self) -> &DmacBurstReq {
15093 &self.dmac_burst_req
15094 }
15095 #[doc = "0x18 - Single software request register"]
15096 #[inline(always)]
15097 pub const fn dmac_single_req(&self) -> &DmacSingleReq {
15098 &self.dmac_single_req
15099 }
15100 #[doc = "0x1c - DMA configuration register"]
15101 #[inline(always)]
15102 pub const fn dmac_config(&self) -> &DmacConfig {
15103 &self.dmac_config
15104 }
15105 #[doc = "0x20 - DMA sync register"]
15106 #[inline(always)]
15107 pub const fn dmac_sync(&self) -> &DmacSync {
15108 &self.dmac_sync
15109 }
15110 #[doc = "0x100..0x110 - Channel %s \\[dim=4\\] linked list register"]
15111 #[inline(always)]
15112 pub const fn dmac_lli_0(&self, n: usize) -> &DmacLli_ {
15113 #[allow(clippy::no_effect)]
15114 [(); 4][n];
15115 unsafe {
15116 &*core::ptr::from_ref(self)
15117 .cast::<u8>()
15118 .add(256)
15119 .add(32 * n)
15120 .cast()
15121 }
15122 }
15123 #[doc = "Iterator for array of:"]
15124 #[doc = "0x100..0x110 - Channel %s \\[dim=4\\] linked list register"]
15125 #[inline(always)]
15126 pub fn dmac_lli_0_iter(&self) -> impl Iterator<Item = &DmacLli_> {
15127 (0..4).map(move |n| unsafe {
15128 &*core::ptr::from_ref(self)
15129 .cast::<u8>()
15130 .add(256)
15131 .add(32 * n)
15132 .cast()
15133 })
15134 }
15135 #[doc = "0x104..0x114 - Channel %s \\[dim=4\\] destination address"]
15136 #[inline(always)]
15137 pub const fn dmac_d_addr_0(&self, n: usize) -> &DmacDAddr_ {
15138 #[allow(clippy::no_effect)]
15139 [(); 4][n];
15140 unsafe {
15141 &*core::ptr::from_ref(self)
15142 .cast::<u8>()
15143 .add(260)
15144 .add(32 * n)
15145 .cast()
15146 }
15147 }
15148 #[doc = "Iterator for array of:"]
15149 #[doc = "0x104..0x114 - Channel %s \\[dim=4\\] destination address"]
15150 #[inline(always)]
15151 pub fn dmac_d_addr_0_iter(&self) -> impl Iterator<Item = &DmacDAddr_> {
15152 (0..4).map(move |n| unsafe {
15153 &*core::ptr::from_ref(self)
15154 .cast::<u8>()
15155 .add(260)
15156 .add(32 * n)
15157 .cast()
15158 })
15159 }
15160 #[doc = "0x108..0x118 - Channel %s \\[dim=4\\] configuration register"]
15161 #[inline(always)]
15162 pub const fn dmac_chn_config_0(&self, n: usize) -> &DmacChnConfig_ {
15163 #[allow(clippy::no_effect)]
15164 [(); 4][n];
15165 unsafe {
15166 &*core::ptr::from_ref(self)
15167 .cast::<u8>()
15168 .add(264)
15169 .add(32 * n)
15170 .cast()
15171 }
15172 }
15173 #[doc = "Iterator for array of:"]
15174 #[doc = "0x108..0x118 - Channel %s \\[dim=4\\] configuration register"]
15175 #[inline(always)]
15176 pub fn dmac_chn_config_0_iter(&self) -> impl Iterator<Item = &DmacChnConfig_> {
15177 (0..4).map(move |n| unsafe {
15178 &*core::ptr::from_ref(self)
15179 .cast::<u8>()
15180 .add(264)
15181 .add(32 * n)
15182 .cast()
15183 })
15184 }
15185 #[doc = "0x110..0x120 - Channel %s \\[dim=4\\] source address"]
15186 #[inline(always)]
15187 pub const fn dmac_s_addr_0(&self, n: usize) -> &DmacSAddr_ {
15188 #[allow(clippy::no_effect)]
15189 [(); 4][n];
15190 unsafe {
15191 &*core::ptr::from_ref(self)
15192 .cast::<u8>()
15193 .add(272)
15194 .add(32 * n)
15195 .cast()
15196 }
15197 }
15198 #[doc = "Iterator for array of:"]
15199 #[doc = "0x110..0x120 - Channel %s \\[dim=4\\] source address"]
15200 #[inline(always)]
15201 pub fn dmac_s_addr_0_iter(&self) -> impl Iterator<Item = &DmacSAddr_> {
15202 (0..4).map(move |n| unsafe {
15203 &*core::ptr::from_ref(self)
15204 .cast::<u8>()
15205 .add(272)
15206 .add(32 * n)
15207 .cast()
15208 })
15209 }
15210 #[doc = "0x114..0x124 - Channel %s \\[dim=4\\] control register"]
15211 #[inline(always)]
15212 pub const fn dmac_chn_control_0(&self, n: usize) -> &DmacChnControl_ {
15213 #[allow(clippy::no_effect)]
15214 [(); 4][n];
15215 unsafe {
15216 &*core::ptr::from_ref(self)
15217 .cast::<u8>()
15218 .add(276)
15219 .add(32 * n)
15220 .cast()
15221 }
15222 }
15223 #[doc = "Iterator for array of:"]
15224 #[doc = "0x114..0x124 - Channel %s \\[dim=4\\] control register"]
15225 #[inline(always)]
15226 pub fn dmac_chn_control_0_iter(&self) -> impl Iterator<Item = &DmacChnControl_> {
15227 (0..4).map(move |n| unsafe {
15228 &*core::ptr::from_ref(self)
15229 .cast::<u8>()
15230 .add(276)
15231 .add(32 * n)
15232 .cast()
15233 })
15234 }
15235 }
15236 #[doc = "DMAC_INT_ST (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_int_st`] module"]
15237 #[doc(alias = "DMAC_INT_ST")]
15238 pub type DmacIntSt = crate::Reg<dmac_int_st::DmacIntStSpec>;
15239 #[doc = "Interrupt status register"]
15240 pub mod dmac_int_st {
15241 #[doc = "Register `DMAC_INT_ST` reader"]
15242 pub type R = crate::R<DmacIntStSpec>;
15243 #[doc = "Register `DMAC_INT_ST` writer"]
15244 pub type W = crate::W<DmacIntStSpec>;
15245 #[doc = "Field `int_st` reader - Channel interrupt status (after mask)"]
15246 pub type IntStR = crate::FieldReader;
15247 #[doc = "Field `int_trans_st` reader - Channel transfer interrupt status (after mask)"]
15248 pub type IntTransStR = crate::FieldReader;
15249 #[doc = "Field `int_err_st` reader - Channel error interrupt status (after mask)"]
15250 pub type IntErrStR = crate::FieldReader;
15251 impl R {
15252 #[doc = "Bits 0:7 - Channel interrupt status (after mask)"]
15253 #[inline(always)]
15254 pub fn int_st(&self) -> IntStR {
15255 IntStR::new((self.bits & 0xff) as u8)
15256 }
15257 #[doc = "Bits 8:15 - Channel transfer interrupt status (after mask)"]
15258 #[inline(always)]
15259 pub fn int_trans_st(&self) -> IntTransStR {
15260 IntTransStR::new(((self.bits >> 8) & 0xff) as u8)
15261 }
15262 #[doc = "Bits 16:23 - Channel error interrupt status (after mask)"]
15263 #[inline(always)]
15264 pub fn int_err_st(&self) -> IntErrStR {
15265 IntErrStR::new(((self.bits >> 16) & 0xff) as u8)
15266 }
15267 }
15268 impl W {}
15269 #[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15270 pub struct DmacIntStSpec;
15271 impl crate::RegisterSpec for DmacIntStSpec {
15272 type Ux = u32;
15273 }
15274 #[doc = "`read()` method returns [`dmac_int_st::R`](R) reader structure"]
15275 impl crate::Readable for DmacIntStSpec {}
15276 #[doc = "`write(|w| ..)` method takes [`dmac_int_st::W`](W) writer structure"]
15277 impl crate::Writable for DmacIntStSpec {
15278 type Safety = crate::Unsafe;
15279 }
15280 #[doc = "`reset()` method sets DMAC_INT_ST to value 0"]
15281 impl crate::Resettable for DmacIntStSpec {}
15282 }
15283 #[doc = "DMAC_INT_CLR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_int_clr`] module"]
15284 #[doc(alias = "DMAC_INT_CLR")]
15285 pub type DmacIntClr = crate::Reg<dmac_int_clr::DmacIntClrSpec>;
15286 #[doc = "Interrupt clear register"]
15287 pub mod dmac_int_clr {
15288 #[doc = "Register `DMAC_INT_CLR` reader"]
15289 pub type R = crate::R<DmacIntClrSpec>;
15290 #[doc = "Register `DMAC_INT_CLR` writer"]
15291 pub type W = crate::W<DmacIntClrSpec>;
15292 #[doc = "Field `int_trans_clr` reader - Clear channel transfer interrupt"]
15293 pub type IntTransClrR = crate::FieldReader;
15294 #[doc = "Field `int_trans_clr` writer - Clear channel transfer interrupt"]
15295 pub type IntTransClrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
15296 #[doc = "Field `int_err_clr` reader - Clear channel error interrupt"]
15297 pub type IntErrClrR = crate::FieldReader;
15298 #[doc = "Field `int_err_clr` writer - Clear channel error interrupt"]
15299 pub type IntErrClrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
15300 impl R {
15301 #[doc = "Bits 0:7 - Clear channel transfer interrupt"]
15302 #[inline(always)]
15303 pub fn int_trans_clr(&self) -> IntTransClrR {
15304 IntTransClrR::new((self.bits & 0xff) as u8)
15305 }
15306 #[doc = "Bits 8:15 - Clear channel error interrupt"]
15307 #[inline(always)]
15308 pub fn int_err_clr(&self) -> IntErrClrR {
15309 IntErrClrR::new(((self.bits >> 8) & 0xff) as u8)
15310 }
15311 }
15312 impl W {
15313 #[doc = "Bits 0:7 - Clear channel transfer interrupt"]
15314 #[inline(always)]
15315 pub fn int_trans_clr(&mut self) -> IntTransClrW<'_, DmacIntClrSpec> {
15316 IntTransClrW::new(self, 0)
15317 }
15318 #[doc = "Bits 8:15 - Clear channel error interrupt"]
15319 #[inline(always)]
15320 pub fn int_err_clr(&mut self) -> IntErrClrW<'_, DmacIntClrSpec> {
15321 IntErrClrW::new(self, 8)
15322 }
15323 }
15324 #[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15325 pub struct DmacIntClrSpec;
15326 impl crate::RegisterSpec for DmacIntClrSpec {
15327 type Ux = u32;
15328 }
15329 #[doc = "`read()` method returns [`dmac_int_clr::R`](R) reader structure"]
15330 impl crate::Readable for DmacIntClrSpec {}
15331 #[doc = "`write(|w| ..)` method takes [`dmac_int_clr::W`](W) writer structure"]
15332 impl crate::Writable for DmacIntClrSpec {
15333 type Safety = crate::Unsafe;
15334 }
15335 #[doc = "`reset()` method sets DMAC_INT_CLR to value 0"]
15336 impl crate::Resettable for DmacIntClrSpec {}
15337 }
15338 #[doc = "DMAC_ORI_INT_ST (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_ori_int_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_ori_int_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_ori_int_st`] module"]
15339 #[doc(alias = "DMAC_ORI_INT_ST")]
15340 pub type DmacOriIntSt = crate::Reg<dmac_ori_int_st::DmacOriIntStSpec>;
15341 #[doc = "Raw interrupt status register"]
15342 pub mod dmac_ori_int_st {
15343 #[doc = "Register `DMAC_ORI_INT_ST` reader"]
15344 pub type R = crate::R<DmacOriIntStSpec>;
15345 #[doc = "Register `DMAC_ORI_INT_ST` writer"]
15346 pub type W = crate::W<DmacOriIntStSpec>;
15347 #[doc = "Field `ori_int_trans_st` reader - Raw transfer interrupt status (before mask)"]
15348 pub type OriIntTransStR = crate::FieldReader;
15349 #[doc = "Field `ori_int_err_st` reader - Raw error interrupt status (before mask)"]
15350 pub type OriIntErrStR = crate::FieldReader;
15351 impl R {
15352 #[doc = "Bits 0:7 - Raw transfer interrupt status (before mask)"]
15353 #[inline(always)]
15354 pub fn ori_int_trans_st(&self) -> OriIntTransStR {
15355 OriIntTransStR::new((self.bits & 0xff) as u8)
15356 }
15357 #[doc = "Bits 8:15 - Raw error interrupt status (before mask)"]
15358 #[inline(always)]
15359 pub fn ori_int_err_st(&self) -> OriIntErrStR {
15360 OriIntErrStR::new(((self.bits >> 8) & 0xff) as u8)
15361 }
15362 }
15363 impl W {}
15364 #[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_ori_int_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_ori_int_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15365 pub struct DmacOriIntStSpec;
15366 impl crate::RegisterSpec for DmacOriIntStSpec {
15367 type Ux = u32;
15368 }
15369 #[doc = "`read()` method returns [`dmac_ori_int_st::R`](R) reader structure"]
15370 impl crate::Readable for DmacOriIntStSpec {}
15371 #[doc = "`write(|w| ..)` method takes [`dmac_ori_int_st::W`](W) writer structure"]
15372 impl crate::Writable for DmacOriIntStSpec {
15373 type Safety = crate::Unsafe;
15374 }
15375 #[doc = "`reset()` method sets DMAC_ORI_INT_ST to value 0"]
15376 impl crate::Resettable for DmacOriIntStSpec {}
15377 }
15378 #[doc = "DMAC_EN_CHNS (rw) register accessor: Channel enable query register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_en_chns::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_en_chns::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_en_chns`] module"]
15379 #[doc(alias = "DMAC_EN_CHNS")]
15380 pub type DmacEnChns = crate::Reg<dmac_en_chns::DmacEnChnsSpec>;
15381 #[doc = "Channel enable query register"]
15382 pub mod dmac_en_chns {
15383 #[doc = "Register `DMAC_EN_CHNS` reader"]
15384 pub type R = crate::R<DmacEnChnsSpec>;
15385 #[doc = "Register `DMAC_EN_CHNS` writer"]
15386 pub type W = crate::W<DmacEnChnsSpec>;
15387 #[doc = "Field `en_chns` reader - Channel enable status: 0=disabled; 1=enabled"]
15388 pub type EnChnsR = crate::FieldReader;
15389 impl R {
15390 #[doc = "Bits 0:7 - Channel enable status: 0=disabled; 1=enabled"]
15391 #[inline(always)]
15392 pub fn en_chns(&self) -> EnChnsR {
15393 EnChnsR::new((self.bits & 0xff) as u8)
15394 }
15395 }
15396 impl W {}
15397 #[doc = "Channel enable query register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_en_chns::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_en_chns::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15398 pub struct DmacEnChnsSpec;
15399 impl crate::RegisterSpec for DmacEnChnsSpec {
15400 type Ux = u32;
15401 }
15402 #[doc = "`read()` method returns [`dmac_en_chns::R`](R) reader structure"]
15403 impl crate::Readable for DmacEnChnsSpec {}
15404 #[doc = "`write(|w| ..)` method takes [`dmac_en_chns::W`](W) writer structure"]
15405 impl crate::Writable for DmacEnChnsSpec {
15406 type Safety = crate::Unsafe;
15407 }
15408 #[doc = "`reset()` method sets DMAC_EN_CHNS to value 0"]
15409 impl crate::Resettable for DmacEnChnsSpec {}
15410 }
15411 #[doc = "DMAC_BURST_REQ (rw) register accessor: Burst software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_burst_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_burst_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_burst_req`] module"]
15412 #[doc(alias = "DMAC_BURST_REQ")]
15413 pub type DmacBurstReq = crate::Reg<dmac_burst_req::DmacBurstReqSpec>;
15414 #[doc = "Burst software request register"]
15415 pub mod dmac_burst_req {
15416 #[doc = "Register `DMAC_BURST_REQ` reader"]
15417 pub type R = crate::R<DmacBurstReqSpec>;
15418 #[doc = "Register `DMAC_BURST_REQ` writer"]
15419 pub type W = crate::W<DmacBurstReqSpec>;
15420 #[doc = "Field `last_burst_req` reader - Last burst request per peripheral"]
15421 pub type LastBurstReqR = crate::FieldReader<u16>;
15422 #[doc = "Field `last_burst_req` writer - Last burst request per peripheral"]
15423 pub type LastBurstReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15424 #[doc = "Field `burst_req` reader - Burst request per peripheral"]
15425 pub type BurstReqR = crate::FieldReader<u16>;
15426 #[doc = "Field `burst_req` writer - Burst request per peripheral"]
15427 pub type BurstReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15428 impl R {
15429 #[doc = "Bits 0:15 - Last burst request per peripheral"]
15430 #[inline(always)]
15431 pub fn last_burst_req(&self) -> LastBurstReqR {
15432 LastBurstReqR::new((self.bits & 0xffff) as u16)
15433 }
15434 #[doc = "Bits 16:31 - Burst request per peripheral"]
15435 #[inline(always)]
15436 pub fn burst_req(&self) -> BurstReqR {
15437 BurstReqR::new(((self.bits >> 16) & 0xffff) as u16)
15438 }
15439 }
15440 impl W {
15441 #[doc = "Bits 0:15 - Last burst request per peripheral"]
15442 #[inline(always)]
15443 pub fn last_burst_req(&mut self) -> LastBurstReqW<'_, DmacBurstReqSpec> {
15444 LastBurstReqW::new(self, 0)
15445 }
15446 #[doc = "Bits 16:31 - Burst request per peripheral"]
15447 #[inline(always)]
15448 pub fn burst_req(&mut self) -> BurstReqW<'_, DmacBurstReqSpec> {
15449 BurstReqW::new(self, 16)
15450 }
15451 }
15452 #[doc = "Burst software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_burst_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_burst_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15453 pub struct DmacBurstReqSpec;
15454 impl crate::RegisterSpec for DmacBurstReqSpec {
15455 type Ux = u32;
15456 }
15457 #[doc = "`read()` method returns [`dmac_burst_req::R`](R) reader structure"]
15458 impl crate::Readable for DmacBurstReqSpec {}
15459 #[doc = "`write(|w| ..)` method takes [`dmac_burst_req::W`](W) writer structure"]
15460 impl crate::Writable for DmacBurstReqSpec {
15461 type Safety = crate::Unsafe;
15462 }
15463 #[doc = "`reset()` method sets DMAC_BURST_REQ to value 0"]
15464 impl crate::Resettable for DmacBurstReqSpec {}
15465 }
15466 #[doc = "DMAC_SINGLE_REQ (rw) register accessor: Single software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_single_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_single_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_single_req`] module"]
15467 #[doc(alias = "DMAC_SINGLE_REQ")]
15468 pub type DmacSingleReq = crate::Reg<dmac_single_req::DmacSingleReqSpec>;
15469 #[doc = "Single software request register"]
15470 pub mod dmac_single_req {
15471 #[doc = "Register `DMAC_SINGLE_REQ` reader"]
15472 pub type R = crate::R<DmacSingleReqSpec>;
15473 #[doc = "Register `DMAC_SINGLE_REQ` writer"]
15474 pub type W = crate::W<DmacSingleReqSpec>;
15475 #[doc = "Field `last_single_req` reader - Last single request per peripheral"]
15476 pub type LastSingleReqR = crate::FieldReader<u16>;
15477 #[doc = "Field `last_single_req` writer - Last single request per peripheral"]
15478 pub type LastSingleReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15479 #[doc = "Field `single_req` reader - Single request per peripheral"]
15480 pub type SingleReqR = crate::FieldReader<u16>;
15481 #[doc = "Field `single_req` writer - Single request per peripheral"]
15482 pub type SingleReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15483 impl R {
15484 #[doc = "Bits 0:15 - Last single request per peripheral"]
15485 #[inline(always)]
15486 pub fn last_single_req(&self) -> LastSingleReqR {
15487 LastSingleReqR::new((self.bits & 0xffff) as u16)
15488 }
15489 #[doc = "Bits 16:31 - Single request per peripheral"]
15490 #[inline(always)]
15491 pub fn single_req(&self) -> SingleReqR {
15492 SingleReqR::new(((self.bits >> 16) & 0xffff) as u16)
15493 }
15494 }
15495 impl W {
15496 #[doc = "Bits 0:15 - Last single request per peripheral"]
15497 #[inline(always)]
15498 pub fn last_single_req(&mut self) -> LastSingleReqW<'_, DmacSingleReqSpec> {
15499 LastSingleReqW::new(self, 0)
15500 }
15501 #[doc = "Bits 16:31 - Single request per peripheral"]
15502 #[inline(always)]
15503 pub fn single_req(&mut self) -> SingleReqW<'_, DmacSingleReqSpec> {
15504 SingleReqW::new(self, 16)
15505 }
15506 }
15507 #[doc = "Single software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_single_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_single_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15508 pub struct DmacSingleReqSpec;
15509 impl crate::RegisterSpec for DmacSingleReqSpec {
15510 type Ux = u32;
15511 }
15512 #[doc = "`read()` method returns [`dmac_single_req::R`](R) reader structure"]
15513 impl crate::Readable for DmacSingleReqSpec {}
15514 #[doc = "`write(|w| ..)` method takes [`dmac_single_req::W`](W) writer structure"]
15515 impl crate::Writable for DmacSingleReqSpec {
15516 type Safety = crate::Unsafe;
15517 }
15518 #[doc = "`reset()` method sets DMAC_SINGLE_REQ to value 0"]
15519 impl crate::Resettable for DmacSingleReqSpec {}
15520 }
15521 #[doc = "DMAC_CONFIG (rw) register accessor: DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_config`] module"]
15522 #[doc(alias = "DMAC_CONFIG")]
15523 pub type DmacConfig = crate::Reg<dmac_config::DmacConfigSpec>;
15524 #[doc = "DMA configuration register"]
15525 pub mod dmac_config {
15526 #[doc = "Register `DMAC_CONFIG` reader"]
15527 pub type R = crate::R<DmacConfigSpec>;
15528 #[doc = "Register `DMAC_CONFIG` writer"]
15529 pub type W = crate::W<DmacConfigSpec>;
15530 #[doc = "Field `dmac_en` reader - DMAC enable: 0=disabled; 1=enabled"]
15531 pub type DmacEnR = crate::BitReader;
15532 #[doc = "Field `dmac_en` writer - DMAC enable: 0=disabled; 1=enabled"]
15533 pub type DmacEnW<'a, REG> = crate::BitWriter<'a, REG>;
15534 #[doc = "Field `dmac_m1` reader - Master 1 endianness: 0=little; 1=big"]
15535 pub type DmacM1R = crate::BitReader;
15536 #[doc = "Field `dmac_m1` writer - Master 1 endianness: 0=little; 1=big"]
15537 pub type DmacM1W<'a, REG> = crate::BitWriter<'a, REG>;
15538 #[doc = "Field `dmac_m2` reader - Master 2 endianness: 0=little; 1=big"]
15539 pub type DmacM2R = crate::BitReader;
15540 #[doc = "Field `dmac_m2` writer - Master 2 endianness: 0=little; 1=big"]
15541 pub type DmacM2W<'a, REG> = crate::BitWriter<'a, REG>;
15542 impl R {
15543 #[doc = "Bit 0 - DMAC enable: 0=disabled; 1=enabled"]
15544 #[inline(always)]
15545 pub fn dmac_en(&self) -> DmacEnR {
15546 DmacEnR::new((self.bits & 1) != 0)
15547 }
15548 #[doc = "Bit 1 - Master 1 endianness: 0=little; 1=big"]
15549 #[inline(always)]
15550 pub fn dmac_m1(&self) -> DmacM1R {
15551 DmacM1R::new(((self.bits >> 1) & 1) != 0)
15552 }
15553 #[doc = "Bit 2 - Master 2 endianness: 0=little; 1=big"]
15554 #[inline(always)]
15555 pub fn dmac_m2(&self) -> DmacM2R {
15556 DmacM2R::new(((self.bits >> 2) & 1) != 0)
15557 }
15558 }
15559 impl W {
15560 #[doc = "Bit 0 - DMAC enable: 0=disabled; 1=enabled"]
15561 #[inline(always)]
15562 pub fn dmac_en(&mut self) -> DmacEnW<'_, DmacConfigSpec> {
15563 DmacEnW::new(self, 0)
15564 }
15565 #[doc = "Bit 1 - Master 1 endianness: 0=little; 1=big"]
15566 #[inline(always)]
15567 pub fn dmac_m1(&mut self) -> DmacM1W<'_, DmacConfigSpec> {
15568 DmacM1W::new(self, 1)
15569 }
15570 #[doc = "Bit 2 - Master 2 endianness: 0=little; 1=big"]
15571 #[inline(always)]
15572 pub fn dmac_m2(&mut self) -> DmacM2W<'_, DmacConfigSpec> {
15573 DmacM2W::new(self, 2)
15574 }
15575 }
15576 #[doc = "DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15577 pub struct DmacConfigSpec;
15578 impl crate::RegisterSpec for DmacConfigSpec {
15579 type Ux = u32;
15580 }
15581 #[doc = "`read()` method returns [`dmac_config::R`](R) reader structure"]
15582 impl crate::Readable for DmacConfigSpec {}
15583 #[doc = "`write(|w| ..)` method takes [`dmac_config::W`](W) writer structure"]
15584 impl crate::Writable for DmacConfigSpec {
15585 type Safety = crate::Unsafe;
15586 }
15587 #[doc = "`reset()` method sets DMAC_CONFIG to value 0"]
15588 impl crate::Resettable for DmacConfigSpec {}
15589 }
15590 #[doc = "DMAC_SYNC (rw) register accessor: DMA sync register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_sync`] module"]
15591 #[doc(alias = "DMAC_SYNC")]
15592 pub type DmacSync = crate::Reg<dmac_sync::DmacSyncSpec>;
15593 #[doc = "DMA sync register"]
15594 pub mod dmac_sync {
15595 #[doc = "Register `DMAC_SYNC` reader"]
15596 pub type R = crate::R<DmacSyncSpec>;
15597 #[doc = "Register `DMAC_SYNC` writer"]
15598 pub type W = crate::W<DmacSyncSpec>;
15599 #[doc = "Field `damc_sync` reader - DMA request sync: 0=enable sync; 1=disable sync"]
15600 pub type DamcSyncR = crate::FieldReader<u16>;
15601 #[doc = "Field `damc_sync` writer - DMA request sync: 0=enable sync; 1=disable sync"]
15602 pub type DamcSyncW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
15603 impl R {
15604 #[doc = "Bits 0:15 - DMA request sync: 0=enable sync; 1=disable sync"]
15605 #[inline(always)]
15606 pub fn damc_sync(&self) -> DamcSyncR {
15607 DamcSyncR::new((self.bits & 0xffff) as u16)
15608 }
15609 }
15610 impl W {
15611 #[doc = "Bits 0:15 - DMA request sync: 0=enable sync; 1=disable sync"]
15612 #[inline(always)]
15613 pub fn damc_sync(&mut self) -> DamcSyncW<'_, DmacSyncSpec> {
15614 DamcSyncW::new(self, 0)
15615 }
15616 }
15617 #[doc = "DMA sync register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15618 pub struct DmacSyncSpec;
15619 impl crate::RegisterSpec for DmacSyncSpec {
15620 type Ux = u32;
15621 }
15622 #[doc = "`read()` method returns [`dmac_sync::R`](R) reader structure"]
15623 impl crate::Readable for DmacSyncSpec {}
15624 #[doc = "`write(|w| ..)` method takes [`dmac_sync::W`](W) writer structure"]
15625 impl crate::Writable for DmacSyncSpec {
15626 type Safety = crate::Unsafe;
15627 }
15628 #[doc = "`reset()` method sets DMAC_SYNC to value 0"]
15629 impl crate::Resettable for DmacSyncSpec {}
15630 }
15631 #[doc = "DMAC_D_ADDR_ (rw) register accessor: Channel %s \\[dim=4\\] destination address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_d_addr_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_d_addr_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_d_addr_`] module"]
15632 #[doc(alias = "DMAC_D_ADDR_")]
15633 pub type DmacDAddr_ = crate::Reg<dmac_d_addr_::DmacDAddr_Spec>;
15634 #[doc = "Channel %s \\[dim=4\\] destination address"]
15635 pub mod dmac_d_addr_ {
15636 #[doc = "Register `DMAC_D_ADDR_%s` reader"]
15637 pub type R = crate::R<DmacDAddr_Spec>;
15638 #[doc = "Register `DMAC_D_ADDR_%s` writer"]
15639 pub type W = crate::W<DmacDAddr_Spec>;
15640 #[doc = "Field `dmac_d_addr_0` reader - Channel 0 destination address"]
15641 pub type DmacDAddr0R = crate::FieldReader<u32>;
15642 #[doc = "Field `dmac_d_addr_0` writer - Channel 0 destination address"]
15643 pub type DmacDAddr0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
15644 impl R {
15645 #[doc = "Bits 0:31 - Channel 0 destination address"]
15646 #[inline(always)]
15647 pub fn dmac_d_addr_0(&self) -> DmacDAddr0R {
15648 DmacDAddr0R::new(self.bits)
15649 }
15650 }
15651 impl W {
15652 #[doc = "Bits 0:31 - Channel 0 destination address"]
15653 #[inline(always)]
15654 pub fn dmac_d_addr_0(&mut self) -> DmacDAddr0W<'_, DmacDAddr_Spec> {
15655 DmacDAddr0W::new(self, 0)
15656 }
15657 }
15658 #[doc = "Channel %s \\[dim=4\\] destination address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_d_addr_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_d_addr_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15659 pub struct DmacDAddr_Spec;
15660 impl crate::RegisterSpec for DmacDAddr_Spec {
15661 type Ux = u32;
15662 }
15663 #[doc = "`read()` method returns [`dmac_d_addr_::R`](R) reader structure"]
15664 impl crate::Readable for DmacDAddr_Spec {}
15665 #[doc = "`write(|w| ..)` method takes [`dmac_d_addr_::W`](W) writer structure"]
15666 impl crate::Writable for DmacDAddr_Spec {
15667 type Safety = crate::Unsafe;
15668 }
15669 #[doc = "`reset()` method sets DMAC_D_ADDR_%s to value 0"]
15670 impl crate::Resettable for DmacDAddr_Spec {}
15671 }
15672 #[doc = "DMAC_LLI_ (rw) register accessor: Channel %s \\[dim=4\\] linked list register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_lli_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_lli_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_lli_`] module"]
15673 #[doc(alias = "DMAC_LLI_")]
15674 pub type DmacLli_ = crate::Reg<dmac_lli_::DmacLli_Spec>;
15675 #[doc = "Channel %s \\[dim=4\\] linked list register"]
15676 pub mod dmac_lli_ {
15677 #[doc = "Register `DMAC_LLI_%s` reader"]
15678 pub type R = crate::R<DmacLli_Spec>;
15679 #[doc = "Register `DMAC_LLI_%s` writer"]
15680 pub type W = crate::W<DmacLli_Spec>;
15681 #[doc = "Field `dmac_lm_0` reader - Master for next LLI node: 0=Master1; 1=Master2"]
15682 pub type DmacLm0R = crate::BitReader;
15683 #[doc = "Field `dmac_lm_0` writer - Master for next LLI node: 0=Master1; 1=Master2"]
15684 pub type DmacLm0W<'a, REG> = crate::BitWriter<'a, REG>;
15685 #[doc = "Field `dmac_lli_0` reader - Linked list address \\[31:2\\]"]
15686 pub type DmacLli0R = crate::FieldReader<u32>;
15687 #[doc = "Field `dmac_lli_0` writer - Linked list address \\[31:2\\]"]
15688 pub type DmacLli0W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
15689 impl R {
15690 #[doc = "Bit 0 - Master for next LLI node: 0=Master1; 1=Master2"]
15691 #[inline(always)]
15692 pub fn dmac_lm_0(&self) -> DmacLm0R {
15693 DmacLm0R::new((self.bits & 1) != 0)
15694 }
15695 #[doc = "Bits 2:31 - Linked list address \\[31:2\\]"]
15696 #[inline(always)]
15697 pub fn dmac_lli_0(&self) -> DmacLli0R {
15698 DmacLli0R::new((self.bits >> 2) & 0x3fff_ffff)
15699 }
15700 }
15701 impl W {
15702 #[doc = "Bit 0 - Master for next LLI node: 0=Master1; 1=Master2"]
15703 #[inline(always)]
15704 pub fn dmac_lm_0(&mut self) -> DmacLm0W<'_, DmacLli_Spec> {
15705 DmacLm0W::new(self, 0)
15706 }
15707 #[doc = "Bits 2:31 - Linked list address \\[31:2\\]"]
15708 #[inline(always)]
15709 pub fn dmac_lli_0(&mut self) -> DmacLli0W<'_, DmacLli_Spec> {
15710 DmacLli0W::new(self, 2)
15711 }
15712 }
15713 #[doc = "Channel %s \\[dim=4\\] linked list register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_lli_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_lli_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15714 pub struct DmacLli_Spec;
15715 impl crate::RegisterSpec for DmacLli_Spec {
15716 type Ux = u32;
15717 }
15718 #[doc = "`read()` method returns [`dmac_lli_::R`](R) reader structure"]
15719 impl crate::Readable for DmacLli_Spec {}
15720 #[doc = "`write(|w| ..)` method takes [`dmac_lli_::W`](W) writer structure"]
15721 impl crate::Writable for DmacLli_Spec {
15722 type Safety = crate::Unsafe;
15723 }
15724 #[doc = "`reset()` method sets DMAC_LLI_%s to value 0"]
15725 impl crate::Resettable for DmacLli_Spec {}
15726 }
15727 #[doc = "DMAC_S_ADDR_ (rw) register accessor: Channel %s \\[dim=4\\] source address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_s_addr_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_s_addr_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_s_addr_`] module"]
15728 #[doc(alias = "DMAC_S_ADDR_")]
15729 pub type DmacSAddr_ = crate::Reg<dmac_s_addr_::DmacSAddr_Spec>;
15730 #[doc = "Channel %s \\[dim=4\\] source address"]
15731 pub mod dmac_s_addr_ {
15732 #[doc = "Register `DMAC_S_ADDR_%s` reader"]
15733 pub type R = crate::R<DmacSAddr_Spec>;
15734 #[doc = "Register `DMAC_S_ADDR_%s` writer"]
15735 pub type W = crate::W<DmacSAddr_Spec>;
15736 #[doc = "Field `dmac_s_addr_0` reader - Channel 0 source address"]
15737 pub type DmacSAddr0R = crate::FieldReader<u32>;
15738 #[doc = "Field `dmac_s_addr_0` writer - Channel 0 source address"]
15739 pub type DmacSAddr0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
15740 impl R {
15741 #[doc = "Bits 0:31 - Channel 0 source address"]
15742 #[inline(always)]
15743 pub fn dmac_s_addr_0(&self) -> DmacSAddr0R {
15744 DmacSAddr0R::new(self.bits)
15745 }
15746 }
15747 impl W {
15748 #[doc = "Bits 0:31 - Channel 0 source address"]
15749 #[inline(always)]
15750 pub fn dmac_s_addr_0(&mut self) -> DmacSAddr0W<'_, DmacSAddr_Spec> {
15751 DmacSAddr0W::new(self, 0)
15752 }
15753 }
15754 #[doc = "Channel %s \\[dim=4\\] source address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_s_addr_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_s_addr_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
15755 pub struct DmacSAddr_Spec;
15756 impl crate::RegisterSpec for DmacSAddr_Spec {
15757 type Ux = u32;
15758 }
15759 #[doc = "`read()` method returns [`dmac_s_addr_::R`](R) reader structure"]
15760 impl crate::Readable for DmacSAddr_Spec {}
15761 #[doc = "`write(|w| ..)` method takes [`dmac_s_addr_::W`](W) writer structure"]
15762 impl crate::Writable for DmacSAddr_Spec {
15763 type Safety = crate::Unsafe;
15764 }
15765 #[doc = "`reset()` method sets DMAC_S_ADDR_%s to value 0"]
15766 impl crate::Resettable for DmacSAddr_Spec {}
15767 }
15768 #[doc = "DMAC_CHN_CONTROL_ (rw) register accessor: Channel %s \\[dim=4\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_control_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_control_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_chn_control_`] module"]
15769 #[doc(alias = "DMAC_CHN_CONTROL_")]
15770 pub type DmacChnControl_ = crate::Reg<dmac_chn_control_::DmacChnControl_Spec>;
15771 #[doc = "Channel %s \\[dim=4\\] control register"]
15772 pub mod dmac_chn_control_ {
15773 #[doc = "Register `DMAC_CHN_CONTROL_%s` reader"]
15774 pub type R = crate::R<DmacChnControl_Spec>;
15775 #[doc = "Register `DMAC_CHN_CONTROL_%s` writer"]
15776 pub type W = crate::W<DmacChnControl_Spec>;
15777 #[doc = "Field `dmac_trans_size_0` reader - Transfer size"]
15778 pub type DmacTransSize0R = crate::FieldReader<u16>;
15779 #[doc = "Field `dmac_trans_size_0` writer - Transfer size"]
15780 pub type DmacTransSize0W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
15781 #[doc = "Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256\n\nValue on reset: 0"]
15782 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
15783 #[repr(u8)]
15784 pub enum DmacSBsize0 {
15785 #[doc = "0: Burst size 1"]
15786 Bs1 = 0,
15787 #[doc = "1: Burst size 4"]
15788 Bs4 = 1,
15789 #[doc = "2: Burst size 8"]
15790 Bs8 = 2,
15791 #[doc = "3: Burst size 16"]
15792 Bs16 = 3,
15793 #[doc = "4: Burst size 32"]
15794 Bs32 = 4,
15795 #[doc = "5: Burst size 64"]
15796 Bs64 = 5,
15797 #[doc = "6: Burst size 128"]
15798 Bs128 = 6,
15799 #[doc = "7: Burst size 256"]
15800 Bs256 = 7,
15801 }
15802 impl From<DmacSBsize0> for u8 {
15803 #[inline(always)]
15804 fn from(variant: DmacSBsize0) -> Self {
15805 variant as _
15806 }
15807 }
15808 impl crate::FieldSpec for DmacSBsize0 {
15809 type Ux = u8;
15810 }
15811 impl crate::IsEnum for DmacSBsize0 {}
15812 #[doc = "Field `dmac_s_bsize_0` reader - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
15813 pub type DmacSBsize0R = crate::FieldReader<DmacSBsize0>;
15814 impl DmacSBsize0R {
15815 #[doc = "Get enumerated values variant"]
15816 #[inline(always)]
15817 pub const fn variant(&self) -> DmacSBsize0 {
15818 match self.bits {
15819 0 => DmacSBsize0::Bs1,
15820 1 => DmacSBsize0::Bs4,
15821 2 => DmacSBsize0::Bs8,
15822 3 => DmacSBsize0::Bs16,
15823 4 => DmacSBsize0::Bs32,
15824 5 => DmacSBsize0::Bs64,
15825 6 => DmacSBsize0::Bs128,
15826 7 => DmacSBsize0::Bs256,
15827 _ => unreachable!(),
15828 }
15829 }
15830 #[doc = "Burst size 1"]
15831 #[inline(always)]
15832 pub fn is_bs1(&self) -> bool {
15833 *self == DmacSBsize0::Bs1
15834 }
15835 #[doc = "Burst size 4"]
15836 #[inline(always)]
15837 pub fn is_bs4(&self) -> bool {
15838 *self == DmacSBsize0::Bs4
15839 }
15840 #[doc = "Burst size 8"]
15841 #[inline(always)]
15842 pub fn is_bs8(&self) -> bool {
15843 *self == DmacSBsize0::Bs8
15844 }
15845 #[doc = "Burst size 16"]
15846 #[inline(always)]
15847 pub fn is_bs16(&self) -> bool {
15848 *self == DmacSBsize0::Bs16
15849 }
15850 #[doc = "Burst size 32"]
15851 #[inline(always)]
15852 pub fn is_bs32(&self) -> bool {
15853 *self == DmacSBsize0::Bs32
15854 }
15855 #[doc = "Burst size 64"]
15856 #[inline(always)]
15857 pub fn is_bs64(&self) -> bool {
15858 *self == DmacSBsize0::Bs64
15859 }
15860 #[doc = "Burst size 128"]
15861 #[inline(always)]
15862 pub fn is_bs128(&self) -> bool {
15863 *self == DmacSBsize0::Bs128
15864 }
15865 #[doc = "Burst size 256"]
15866 #[inline(always)]
15867 pub fn is_bs256(&self) -> bool {
15868 *self == DmacSBsize0::Bs256
15869 }
15870 }
15871 #[doc = "Field `dmac_s_bsize_0` writer - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
15872 pub type DmacSBsize0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacSBsize0, crate::Safe>;
15873 impl<'a, REG> DmacSBsize0W<'a, REG>
15874 where
15875 REG: crate::Writable + crate::RegisterSpec,
15876 REG::Ux: From<u8>,
15877 {
15878 #[doc = "Burst size 1"]
15879 #[inline(always)]
15880 pub fn bs1(self) -> &'a mut crate::W<REG> {
15881 self.variant(DmacSBsize0::Bs1)
15882 }
15883 #[doc = "Burst size 4"]
15884 #[inline(always)]
15885 pub fn bs4(self) -> &'a mut crate::W<REG> {
15886 self.variant(DmacSBsize0::Bs4)
15887 }
15888 #[doc = "Burst size 8"]
15889 #[inline(always)]
15890 pub fn bs8(self) -> &'a mut crate::W<REG> {
15891 self.variant(DmacSBsize0::Bs8)
15892 }
15893 #[doc = "Burst size 16"]
15894 #[inline(always)]
15895 pub fn bs16(self) -> &'a mut crate::W<REG> {
15896 self.variant(DmacSBsize0::Bs16)
15897 }
15898 #[doc = "Burst size 32"]
15899 #[inline(always)]
15900 pub fn bs32(self) -> &'a mut crate::W<REG> {
15901 self.variant(DmacSBsize0::Bs32)
15902 }
15903 #[doc = "Burst size 64"]
15904 #[inline(always)]
15905 pub fn bs64(self) -> &'a mut crate::W<REG> {
15906 self.variant(DmacSBsize0::Bs64)
15907 }
15908 #[doc = "Burst size 128"]
15909 #[inline(always)]
15910 pub fn bs128(self) -> &'a mut crate::W<REG> {
15911 self.variant(DmacSBsize0::Bs128)
15912 }
15913 #[doc = "Burst size 256"]
15914 #[inline(always)]
15915 pub fn bs256(self) -> &'a mut crate::W<REG> {
15916 self.variant(DmacSBsize0::Bs256)
15917 }
15918 }
15919 #[doc = "Field `dmac_d_bsize_0` reader - Destination burst size"]
15920 pub type DmacDBsize0R = crate::FieldReader;
15921 #[doc = "Field `dmac_d_bsize_0` writer - Destination burst size"]
15922 pub type DmacDBsize0W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
15923 #[doc = "Source width: 000=8bit; 001=16bit; 010=32bit\n\nValue on reset: 0"]
15924 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
15925 #[repr(u8)]
15926 pub enum DmacSWidth0 {
15927 #[doc = "0: 8-bit"]
15928 Byte = 0,
15929 #[doc = "1: 16-bit"]
15930 Halfword = 1,
15931 #[doc = "2: 32-bit"]
15932 Word = 2,
15933 }
15934 impl From<DmacSWidth0> for u8 {
15935 #[inline(always)]
15936 fn from(variant: DmacSWidth0) -> Self {
15937 variant as _
15938 }
15939 }
15940 impl crate::FieldSpec for DmacSWidth0 {
15941 type Ux = u8;
15942 }
15943 impl crate::IsEnum for DmacSWidth0 {}
15944 #[doc = "Field `dmac_s_width_0` reader - Source width: 000=8bit; 001=16bit; 010=32bit"]
15945 pub type DmacSWidth0R = crate::FieldReader<DmacSWidth0>;
15946 impl DmacSWidth0R {
15947 #[doc = "Get enumerated values variant"]
15948 #[inline(always)]
15949 pub const fn variant(&self) -> Option<DmacSWidth0> {
15950 match self.bits {
15951 0 => Some(DmacSWidth0::Byte),
15952 1 => Some(DmacSWidth0::Halfword),
15953 2 => Some(DmacSWidth0::Word),
15954 _ => None,
15955 }
15956 }
15957 #[doc = "8-bit"]
15958 #[inline(always)]
15959 pub fn is_byte(&self) -> bool {
15960 *self == DmacSWidth0::Byte
15961 }
15962 #[doc = "16-bit"]
15963 #[inline(always)]
15964 pub fn is_halfword(&self) -> bool {
15965 *self == DmacSWidth0::Halfword
15966 }
15967 #[doc = "32-bit"]
15968 #[inline(always)]
15969 pub fn is_word(&self) -> bool {
15970 *self == DmacSWidth0::Word
15971 }
15972 }
15973 #[doc = "Field `dmac_s_width_0` writer - Source width: 000=8bit; 001=16bit; 010=32bit"]
15974 pub type DmacSWidth0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacSWidth0>;
15975 impl<'a, REG> DmacSWidth0W<'a, REG>
15976 where
15977 REG: crate::Writable + crate::RegisterSpec,
15978 REG::Ux: From<u8>,
15979 {
15980 #[doc = "8-bit"]
15981 #[inline(always)]
15982 pub fn byte(self) -> &'a mut crate::W<REG> {
15983 self.variant(DmacSWidth0::Byte)
15984 }
15985 #[doc = "16-bit"]
15986 #[inline(always)]
15987 pub fn halfword(self) -> &'a mut crate::W<REG> {
15988 self.variant(DmacSWidth0::Halfword)
15989 }
15990 #[doc = "32-bit"]
15991 #[inline(always)]
15992 pub fn word(self) -> &'a mut crate::W<REG> {
15993 self.variant(DmacSWidth0::Word)
15994 }
15995 }
15996 #[doc = "Destination width\n\nValue on reset: 0"]
15997 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
15998 #[repr(u8)]
15999 pub enum DmacDWidth0 {
16000 #[doc = "0: 8-bit"]
16001 Byte = 0,
16002 #[doc = "1: 16-bit"]
16003 Halfword = 1,
16004 #[doc = "2: 32-bit"]
16005 Word = 2,
16006 }
16007 impl From<DmacDWidth0> for u8 {
16008 #[inline(always)]
16009 fn from(variant: DmacDWidth0) -> Self {
16010 variant as _
16011 }
16012 }
16013 impl crate::FieldSpec for DmacDWidth0 {
16014 type Ux = u8;
16015 }
16016 impl crate::IsEnum for DmacDWidth0 {}
16017 #[doc = "Field `dmac_d_width_0` reader - Destination width"]
16018 pub type DmacDWidth0R = crate::FieldReader<DmacDWidth0>;
16019 impl DmacDWidth0R {
16020 #[doc = "Get enumerated values variant"]
16021 #[inline(always)]
16022 pub const fn variant(&self) -> Option<DmacDWidth0> {
16023 match self.bits {
16024 0 => Some(DmacDWidth0::Byte),
16025 1 => Some(DmacDWidth0::Halfword),
16026 2 => Some(DmacDWidth0::Word),
16027 _ => None,
16028 }
16029 }
16030 #[doc = "8-bit"]
16031 #[inline(always)]
16032 pub fn is_byte(&self) -> bool {
16033 *self == DmacDWidth0::Byte
16034 }
16035 #[doc = "16-bit"]
16036 #[inline(always)]
16037 pub fn is_halfword(&self) -> bool {
16038 *self == DmacDWidth0::Halfword
16039 }
16040 #[doc = "32-bit"]
16041 #[inline(always)]
16042 pub fn is_word(&self) -> bool {
16043 *self == DmacDWidth0::Word
16044 }
16045 }
16046 #[doc = "Field `dmac_d_width_0` writer - Destination width"]
16047 pub type DmacDWidth0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacDWidth0>;
16048 impl<'a, REG> DmacDWidth0W<'a, REG>
16049 where
16050 REG: crate::Writable + crate::RegisterSpec,
16051 REG::Ux: From<u8>,
16052 {
16053 #[doc = "8-bit"]
16054 #[inline(always)]
16055 pub fn byte(self) -> &'a mut crate::W<REG> {
16056 self.variant(DmacDWidth0::Byte)
16057 }
16058 #[doc = "16-bit"]
16059 #[inline(always)]
16060 pub fn halfword(self) -> &'a mut crate::W<REG> {
16061 self.variant(DmacDWidth0::Halfword)
16062 }
16063 #[doc = "32-bit"]
16064 #[inline(always)]
16065 pub fn word(self) -> &'a mut crate::W<REG> {
16066 self.variant(DmacDWidth0::Word)
16067 }
16068 }
16069 #[doc = "Field `dmac_s_master_0` reader - Source master: 0=Master1; 1=Master2"]
16070 pub type DmacSMaster0R = crate::BitReader;
16071 #[doc = "Field `dmac_s_master_0` writer - Source master: 0=Master1; 1=Master2"]
16072 pub type DmacSMaster0W<'a, REG> = crate::BitWriter<'a, REG>;
16073 #[doc = "Field `dmac_d_master_0` reader - Destination master"]
16074 pub type DmacDMaster0R = crate::BitReader;
16075 #[doc = "Field `dmac_d_master_0` writer - Destination master"]
16076 pub type DmacDMaster0W<'a, REG> = crate::BitWriter<'a, REG>;
16077 #[doc = "Field `dmac_s_inc_0` reader - Source address increment: 0=no; 1=yes"]
16078 pub type DmacSInc0R = crate::BitReader;
16079 #[doc = "Field `dmac_s_inc_0` writer - Source address increment: 0=no; 1=yes"]
16080 pub type DmacSInc0W<'a, REG> = crate::BitWriter<'a, REG>;
16081 #[doc = "Field `dmac_d_inc_0` reader - Destination address increment"]
16082 pub type DmacDInc0R = crate::BitReader;
16083 #[doc = "Field `dmac_d_inc_0` writer - Destination address increment"]
16084 pub type DmacDInc0W<'a, REG> = crate::BitWriter<'a, REG>;
16085 #[doc = "Field `dmac_prot_0` reader - Protection HPROT\\[2:0\\]"]
16086 pub type DmacProt0R = crate::FieldReader;
16087 #[doc = "Field `dmac_prot_0` writer - Protection HPROT\\[2:0\\]"]
16088 pub type DmacProt0W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
16089 #[doc = "Field `dmac_trans_int_0` reader - Transfer complete interrupt enable"]
16090 pub type DmacTransInt0R = crate::BitReader;
16091 #[doc = "Field `dmac_trans_int_0` writer - Transfer complete interrupt enable"]
16092 pub type DmacTransInt0W<'a, REG> = crate::BitWriter<'a, REG>;
16093 impl R {
16094 #[doc = "Bits 0:11 - Transfer size"]
16095 #[inline(always)]
16096 pub fn dmac_trans_size_0(&self) -> DmacTransSize0R {
16097 DmacTransSize0R::new((self.bits & 0x0fff) as u16)
16098 }
16099 #[doc = "Bits 12:14 - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
16100 #[inline(always)]
16101 pub fn dmac_s_bsize_0(&self) -> DmacSBsize0R {
16102 DmacSBsize0R::new(((self.bits >> 12) & 7) as u8)
16103 }
16104 #[doc = "Bits 15:17 - Destination burst size"]
16105 #[inline(always)]
16106 pub fn dmac_d_bsize_0(&self) -> DmacDBsize0R {
16107 DmacDBsize0R::new(((self.bits >> 15) & 7) as u8)
16108 }
16109 #[doc = "Bits 18:20 - Source width: 000=8bit; 001=16bit; 010=32bit"]
16110 #[inline(always)]
16111 pub fn dmac_s_width_0(&self) -> DmacSWidth0R {
16112 DmacSWidth0R::new(((self.bits >> 18) & 7) as u8)
16113 }
16114 #[doc = "Bits 21:23 - Destination width"]
16115 #[inline(always)]
16116 pub fn dmac_d_width_0(&self) -> DmacDWidth0R {
16117 DmacDWidth0R::new(((self.bits >> 21) & 7) as u8)
16118 }
16119 #[doc = "Bit 24 - Source master: 0=Master1; 1=Master2"]
16120 #[inline(always)]
16121 pub fn dmac_s_master_0(&self) -> DmacSMaster0R {
16122 DmacSMaster0R::new(((self.bits >> 24) & 1) != 0)
16123 }
16124 #[doc = "Bit 25 - Destination master"]
16125 #[inline(always)]
16126 pub fn dmac_d_master_0(&self) -> DmacDMaster0R {
16127 DmacDMaster0R::new(((self.bits >> 25) & 1) != 0)
16128 }
16129 #[doc = "Bit 26 - Source address increment: 0=no; 1=yes"]
16130 #[inline(always)]
16131 pub fn dmac_s_inc_0(&self) -> DmacSInc0R {
16132 DmacSInc0R::new(((self.bits >> 26) & 1) != 0)
16133 }
16134 #[doc = "Bit 27 - Destination address increment"]
16135 #[inline(always)]
16136 pub fn dmac_d_inc_0(&self) -> DmacDInc0R {
16137 DmacDInc0R::new(((self.bits >> 27) & 1) != 0)
16138 }
16139 #[doc = "Bits 28:30 - Protection HPROT\\[2:0\\]"]
16140 #[inline(always)]
16141 pub fn dmac_prot_0(&self) -> DmacProt0R {
16142 DmacProt0R::new(((self.bits >> 28) & 7) as u8)
16143 }
16144 #[doc = "Bit 31 - Transfer complete interrupt enable"]
16145 #[inline(always)]
16146 pub fn dmac_trans_int_0(&self) -> DmacTransInt0R {
16147 DmacTransInt0R::new(((self.bits >> 31) & 1) != 0)
16148 }
16149 }
16150 impl W {
16151 #[doc = "Bits 0:11 - Transfer size"]
16152 #[inline(always)]
16153 pub fn dmac_trans_size_0(&mut self) -> DmacTransSize0W<'_, DmacChnControl_Spec> {
16154 DmacTransSize0W::new(self, 0)
16155 }
16156 #[doc = "Bits 12:14 - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
16157 #[inline(always)]
16158 pub fn dmac_s_bsize_0(&mut self) -> DmacSBsize0W<'_, DmacChnControl_Spec> {
16159 DmacSBsize0W::new(self, 12)
16160 }
16161 #[doc = "Bits 15:17 - Destination burst size"]
16162 #[inline(always)]
16163 pub fn dmac_d_bsize_0(&mut self) -> DmacDBsize0W<'_, DmacChnControl_Spec> {
16164 DmacDBsize0W::new(self, 15)
16165 }
16166 #[doc = "Bits 18:20 - Source width: 000=8bit; 001=16bit; 010=32bit"]
16167 #[inline(always)]
16168 pub fn dmac_s_width_0(&mut self) -> DmacSWidth0W<'_, DmacChnControl_Spec> {
16169 DmacSWidth0W::new(self, 18)
16170 }
16171 #[doc = "Bits 21:23 - Destination width"]
16172 #[inline(always)]
16173 pub fn dmac_d_width_0(&mut self) -> DmacDWidth0W<'_, DmacChnControl_Spec> {
16174 DmacDWidth0W::new(self, 21)
16175 }
16176 #[doc = "Bit 24 - Source master: 0=Master1; 1=Master2"]
16177 #[inline(always)]
16178 pub fn dmac_s_master_0(&mut self) -> DmacSMaster0W<'_, DmacChnControl_Spec> {
16179 DmacSMaster0W::new(self, 24)
16180 }
16181 #[doc = "Bit 25 - Destination master"]
16182 #[inline(always)]
16183 pub fn dmac_d_master_0(&mut self) -> DmacDMaster0W<'_, DmacChnControl_Spec> {
16184 DmacDMaster0W::new(self, 25)
16185 }
16186 #[doc = "Bit 26 - Source address increment: 0=no; 1=yes"]
16187 #[inline(always)]
16188 pub fn dmac_s_inc_0(&mut self) -> DmacSInc0W<'_, DmacChnControl_Spec> {
16189 DmacSInc0W::new(self, 26)
16190 }
16191 #[doc = "Bit 27 - Destination address increment"]
16192 #[inline(always)]
16193 pub fn dmac_d_inc_0(&mut self) -> DmacDInc0W<'_, DmacChnControl_Spec> {
16194 DmacDInc0W::new(self, 27)
16195 }
16196 #[doc = "Bits 28:30 - Protection HPROT\\[2:0\\]"]
16197 #[inline(always)]
16198 pub fn dmac_prot_0(&mut self) -> DmacProt0W<'_, DmacChnControl_Spec> {
16199 DmacProt0W::new(self, 28)
16200 }
16201 #[doc = "Bit 31 - Transfer complete interrupt enable"]
16202 #[inline(always)]
16203 pub fn dmac_trans_int_0(&mut self) -> DmacTransInt0W<'_, DmacChnControl_Spec> {
16204 DmacTransInt0W::new(self, 31)
16205 }
16206 }
16207 #[doc = "Channel %s \\[dim=4\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_control_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_control_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16208 pub struct DmacChnControl_Spec;
16209 impl crate::RegisterSpec for DmacChnControl_Spec {
16210 type Ux = u32;
16211 }
16212 #[doc = "`read()` method returns [`dmac_chn_control_::R`](R) reader structure"]
16213 impl crate::Readable for DmacChnControl_Spec {}
16214 #[doc = "`write(|w| ..)` method takes [`dmac_chn_control_::W`](W) writer structure"]
16215 impl crate::Writable for DmacChnControl_Spec {
16216 type Safety = crate::Unsafe;
16217 }
16218 #[doc = "`reset()` method sets DMAC_CHN_CONTROL_%s to value 0"]
16219 impl crate::Resettable for DmacChnControl_Spec {}
16220 }
16221 #[doc = "DMAC_CHN_CONFIG_ (rw) register accessor: Channel %s \\[dim=4\\] configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_config_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_config_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_chn_config_`] module"]
16222 #[doc(alias = "DMAC_CHN_CONFIG_")]
16223 pub type DmacChnConfig_ = crate::Reg<dmac_chn_config_::DmacChnConfig_Spec>;
16224 #[doc = "Channel %s \\[dim=4\\] configuration register"]
16225 pub mod dmac_chn_config_ {
16226 #[doc = "Register `DMAC_CHN_CONFIG_%s` reader"]
16227 pub type R = crate::R<DmacChnConfig_Spec>;
16228 #[doc = "Register `DMAC_CHN_CONFIG_%s` writer"]
16229 pub type W = crate::W<DmacChnConfig_Spec>;
16230 #[doc = "Field `dmac_chn_en_0` reader - Channel enable: 0=disable; 1=enable"]
16231 pub type DmacChnEn0R = crate::BitReader;
16232 #[doc = "Field `dmac_chn_en_0` writer - Channel enable: 0=disable; 1=enable"]
16233 pub type DmacChnEn0W<'a, REG> = crate::BitWriter<'a, REG>;
16234 #[doc = "Field `dmac_s_peripheral_0` reader - Source peripheral select"]
16235 pub type DmacSPeripheral0R = crate::FieldReader;
16236 #[doc = "Field `dmac_s_peripheral_0` writer - Source peripheral select"]
16237 pub type DmacSPeripheral0W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
16238 #[doc = "Field `dmac_d_peripheral_0` reader - Destination peripheral select"]
16239 pub type DmacDPeripheral0R = crate::FieldReader;
16240 #[doc = "Field `dmac_d_peripheral_0` writer - Destination peripheral select"]
16241 pub type DmacDPeripheral0W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
16242 #[doc = "Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)\n\nValue on reset: 0"]
16243 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
16244 #[repr(u8)]
16245 pub enum DmacFlowCtl0 {
16246 #[doc = "0: Memory to Memory, DMAC flow control"]
16247 Mem2memDmac = 0,
16248 #[doc = "1: Memory to Peripheral, DMAC flow control"]
16249 Mem2perDmac = 1,
16250 #[doc = "2: Peripheral to Memory, DMAC flow control"]
16251 Per2memDmac = 2,
16252 #[doc = "3: Peripheral to Peripheral, DMAC flow control"]
16253 Per2perDmac = 3,
16254 #[doc = "4: Peripheral to Peripheral, Destination flow control"]
16255 Per2perDst = 4,
16256 #[doc = "5: Memory to Peripheral, Destination flow control"]
16257 Mem2perDst = 5,
16258 #[doc = "6: Peripheral to Memory, Source flow control"]
16259 Per2memSrc = 6,
16260 #[doc = "7: Peripheral to Peripheral, Source flow control"]
16261 Per2perSrc = 7,
16262 }
16263 impl From<DmacFlowCtl0> for u8 {
16264 #[inline(always)]
16265 fn from(variant: DmacFlowCtl0) -> Self {
16266 variant as _
16267 }
16268 }
16269 impl crate::FieldSpec for DmacFlowCtl0 {
16270 type Ux = u8;
16271 }
16272 impl crate::IsEnum for DmacFlowCtl0 {}
16273 #[doc = "Field `dmac_flow_ctl_0` reader - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
16274 pub type DmacFlowCtl0R = crate::FieldReader<DmacFlowCtl0>;
16275 impl DmacFlowCtl0R {
16276 #[doc = "Get enumerated values variant"]
16277 #[inline(always)]
16278 pub const fn variant(&self) -> DmacFlowCtl0 {
16279 match self.bits {
16280 0 => DmacFlowCtl0::Mem2memDmac,
16281 1 => DmacFlowCtl0::Mem2perDmac,
16282 2 => DmacFlowCtl0::Per2memDmac,
16283 3 => DmacFlowCtl0::Per2perDmac,
16284 4 => DmacFlowCtl0::Per2perDst,
16285 5 => DmacFlowCtl0::Mem2perDst,
16286 6 => DmacFlowCtl0::Per2memSrc,
16287 7 => DmacFlowCtl0::Per2perSrc,
16288 _ => unreachable!(),
16289 }
16290 }
16291 #[doc = "Memory to Memory, DMAC flow control"]
16292 #[inline(always)]
16293 pub fn is_mem2mem_dmac(&self) -> bool {
16294 *self == DmacFlowCtl0::Mem2memDmac
16295 }
16296 #[doc = "Memory to Peripheral, DMAC flow control"]
16297 #[inline(always)]
16298 pub fn is_mem2per_dmac(&self) -> bool {
16299 *self == DmacFlowCtl0::Mem2perDmac
16300 }
16301 #[doc = "Peripheral to Memory, DMAC flow control"]
16302 #[inline(always)]
16303 pub fn is_per2mem_dmac(&self) -> bool {
16304 *self == DmacFlowCtl0::Per2memDmac
16305 }
16306 #[doc = "Peripheral to Peripheral, DMAC flow control"]
16307 #[inline(always)]
16308 pub fn is_per2per_dmac(&self) -> bool {
16309 *self == DmacFlowCtl0::Per2perDmac
16310 }
16311 #[doc = "Peripheral to Peripheral, Destination flow control"]
16312 #[inline(always)]
16313 pub fn is_per2per_dst(&self) -> bool {
16314 *self == DmacFlowCtl0::Per2perDst
16315 }
16316 #[doc = "Memory to Peripheral, Destination flow control"]
16317 #[inline(always)]
16318 pub fn is_mem2per_dst(&self) -> bool {
16319 *self == DmacFlowCtl0::Mem2perDst
16320 }
16321 #[doc = "Peripheral to Memory, Source flow control"]
16322 #[inline(always)]
16323 pub fn is_per2mem_src(&self) -> bool {
16324 *self == DmacFlowCtl0::Per2memSrc
16325 }
16326 #[doc = "Peripheral to Peripheral, Source flow control"]
16327 #[inline(always)]
16328 pub fn is_per2per_src(&self) -> bool {
16329 *self == DmacFlowCtl0::Per2perSrc
16330 }
16331 }
16332 #[doc = "Field `dmac_flow_ctl_0` writer - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
16333 pub type DmacFlowCtl0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacFlowCtl0, crate::Safe>;
16334 impl<'a, REG> DmacFlowCtl0W<'a, REG>
16335 where
16336 REG: crate::Writable + crate::RegisterSpec,
16337 REG::Ux: From<u8>,
16338 {
16339 #[doc = "Memory to Memory, DMAC flow control"]
16340 #[inline(always)]
16341 pub fn mem2mem_dmac(self) -> &'a mut crate::W<REG> {
16342 self.variant(DmacFlowCtl0::Mem2memDmac)
16343 }
16344 #[doc = "Memory to Peripheral, DMAC flow control"]
16345 #[inline(always)]
16346 pub fn mem2per_dmac(self) -> &'a mut crate::W<REG> {
16347 self.variant(DmacFlowCtl0::Mem2perDmac)
16348 }
16349 #[doc = "Peripheral to Memory, DMAC flow control"]
16350 #[inline(always)]
16351 pub fn per2mem_dmac(self) -> &'a mut crate::W<REG> {
16352 self.variant(DmacFlowCtl0::Per2memDmac)
16353 }
16354 #[doc = "Peripheral to Peripheral, DMAC flow control"]
16355 #[inline(always)]
16356 pub fn per2per_dmac(self) -> &'a mut crate::W<REG> {
16357 self.variant(DmacFlowCtl0::Per2perDmac)
16358 }
16359 #[doc = "Peripheral to Peripheral, Destination flow control"]
16360 #[inline(always)]
16361 pub fn per2per_dst(self) -> &'a mut crate::W<REG> {
16362 self.variant(DmacFlowCtl0::Per2perDst)
16363 }
16364 #[doc = "Memory to Peripheral, Destination flow control"]
16365 #[inline(always)]
16366 pub fn mem2per_dst(self) -> &'a mut crate::W<REG> {
16367 self.variant(DmacFlowCtl0::Mem2perDst)
16368 }
16369 #[doc = "Peripheral to Memory, Source flow control"]
16370 #[inline(always)]
16371 pub fn per2mem_src(self) -> &'a mut crate::W<REG> {
16372 self.variant(DmacFlowCtl0::Per2memSrc)
16373 }
16374 #[doc = "Peripheral to Peripheral, Source flow control"]
16375 #[inline(always)]
16376 pub fn per2per_src(self) -> &'a mut crate::W<REG> {
16377 self.variant(DmacFlowCtl0::Per2perSrc)
16378 }
16379 }
16380 #[doc = "Field `dmac_int_en_0` reader - Error interrupt mask: 0=masked; 1=unmasked"]
16381 pub type DmacIntEn0R = crate::BitReader;
16382 #[doc = "Field `dmac_int_en_0` writer - Error interrupt mask: 0=masked; 1=unmasked"]
16383 pub type DmacIntEn0W<'a, REG> = crate::BitWriter<'a, REG>;
16384 #[doc = "Field `dmac_int_tc_0` reader - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
16385 pub type DmacIntTc0R = crate::BitReader;
16386 #[doc = "Field `dmac_int_tc_0` writer - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
16387 pub type DmacIntTc0W<'a, REG> = crate::BitWriter<'a, REG>;
16388 #[doc = "Field `dmac_lock_0` reader - Bus lock: 0=disabled; 1=enabled"]
16389 pub type DmacLock0R = crate::BitReader;
16390 #[doc = "Field `dmac_lock_0` writer - Bus lock: 0=disabled; 1=enabled"]
16391 pub type DmacLock0W<'a, REG> = crate::BitWriter<'a, REG>;
16392 #[doc = "Field `dmac_active_0` reader - FIFO has data: 0=no; 1=yes"]
16393 pub type DmacActive0R = crate::BitReader;
16394 #[doc = "Field `dmac_halt_0` reader - Halt: 0=allow DMA; 1=ignore DMA requests"]
16395 pub type DmacHalt0R = crate::BitReader;
16396 #[doc = "Field `dmac_halt_0` writer - Halt: 0=allow DMA; 1=ignore DMA requests"]
16397 pub type DmacHalt0W<'a, REG> = crate::BitWriter<'a, REG>;
16398 impl R {
16399 #[doc = "Bit 0 - Channel enable: 0=disable; 1=enable"]
16400 #[inline(always)]
16401 pub fn dmac_chn_en_0(&self) -> DmacChnEn0R {
16402 DmacChnEn0R::new((self.bits & 1) != 0)
16403 }
16404 #[doc = "Bits 1:4 - Source peripheral select"]
16405 #[inline(always)]
16406 pub fn dmac_s_peripheral_0(&self) -> DmacSPeripheral0R {
16407 DmacSPeripheral0R::new(((self.bits >> 1) & 0x0f) as u8)
16408 }
16409 #[doc = "Bits 5:8 - Destination peripheral select"]
16410 #[inline(always)]
16411 pub fn dmac_d_peripheral_0(&self) -> DmacDPeripheral0R {
16412 DmacDPeripheral0R::new(((self.bits >> 5) & 0x0f) as u8)
16413 }
16414 #[doc = "Bits 9:11 - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
16415 #[inline(always)]
16416 pub fn dmac_flow_ctl_0(&self) -> DmacFlowCtl0R {
16417 DmacFlowCtl0R::new(((self.bits >> 9) & 7) as u8)
16418 }
16419 #[doc = "Bit 12 - Error interrupt mask: 0=masked; 1=unmasked"]
16420 #[inline(always)]
16421 pub fn dmac_int_en_0(&self) -> DmacIntEn0R {
16422 DmacIntEn0R::new(((self.bits >> 12) & 1) != 0)
16423 }
16424 #[doc = "Bit 13 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
16425 #[inline(always)]
16426 pub fn dmac_int_tc_0(&self) -> DmacIntTc0R {
16427 DmacIntTc0R::new(((self.bits >> 13) & 1) != 0)
16428 }
16429 #[doc = "Bit 14 - Bus lock: 0=disabled; 1=enabled"]
16430 #[inline(always)]
16431 pub fn dmac_lock_0(&self) -> DmacLock0R {
16432 DmacLock0R::new(((self.bits >> 14) & 1) != 0)
16433 }
16434 #[doc = "Bit 15 - FIFO has data: 0=no; 1=yes"]
16435 #[inline(always)]
16436 pub fn dmac_active_0(&self) -> DmacActive0R {
16437 DmacActive0R::new(((self.bits >> 15) & 1) != 0)
16438 }
16439 #[doc = "Bit 16 - Halt: 0=allow DMA; 1=ignore DMA requests"]
16440 #[inline(always)]
16441 pub fn dmac_halt_0(&self) -> DmacHalt0R {
16442 DmacHalt0R::new(((self.bits >> 16) & 1) != 0)
16443 }
16444 }
16445 impl W {
16446 #[doc = "Bit 0 - Channel enable: 0=disable; 1=enable"]
16447 #[inline(always)]
16448 pub fn dmac_chn_en_0(&mut self) -> DmacChnEn0W<'_, DmacChnConfig_Spec> {
16449 DmacChnEn0W::new(self, 0)
16450 }
16451 #[doc = "Bits 1:4 - Source peripheral select"]
16452 #[inline(always)]
16453 pub fn dmac_s_peripheral_0(&mut self) -> DmacSPeripheral0W<'_, DmacChnConfig_Spec> {
16454 DmacSPeripheral0W::new(self, 1)
16455 }
16456 #[doc = "Bits 5:8 - Destination peripheral select"]
16457 #[inline(always)]
16458 pub fn dmac_d_peripheral_0(&mut self) -> DmacDPeripheral0W<'_, DmacChnConfig_Spec> {
16459 DmacDPeripheral0W::new(self, 5)
16460 }
16461 #[doc = "Bits 9:11 - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
16462 #[inline(always)]
16463 pub fn dmac_flow_ctl_0(&mut self) -> DmacFlowCtl0W<'_, DmacChnConfig_Spec> {
16464 DmacFlowCtl0W::new(self, 9)
16465 }
16466 #[doc = "Bit 12 - Error interrupt mask: 0=masked; 1=unmasked"]
16467 #[inline(always)]
16468 pub fn dmac_int_en_0(&mut self) -> DmacIntEn0W<'_, DmacChnConfig_Spec> {
16469 DmacIntEn0W::new(self, 12)
16470 }
16471 #[doc = "Bit 13 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
16472 #[inline(always)]
16473 pub fn dmac_int_tc_0(&mut self) -> DmacIntTc0W<'_, DmacChnConfig_Spec> {
16474 DmacIntTc0W::new(self, 13)
16475 }
16476 #[doc = "Bit 14 - Bus lock: 0=disabled; 1=enabled"]
16477 #[inline(always)]
16478 pub fn dmac_lock_0(&mut self) -> DmacLock0W<'_, DmacChnConfig_Spec> {
16479 DmacLock0W::new(self, 14)
16480 }
16481 #[doc = "Bit 16 - Halt: 0=allow DMA; 1=ignore DMA requests"]
16482 #[inline(always)]
16483 pub fn dmac_halt_0(&mut self) -> DmacHalt0W<'_, DmacChnConfig_Spec> {
16484 DmacHalt0W::new(self, 16)
16485 }
16486 }
16487 #[doc = "Channel %s \\[dim=4\\] configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_config_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_config_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16488 pub struct DmacChnConfig_Spec;
16489 impl crate::RegisterSpec for DmacChnConfig_Spec {
16490 type Ux = u32;
16491 }
16492 #[doc = "`read()` method returns [`dmac_chn_config_::R`](R) reader structure"]
16493 impl crate::Readable for DmacChnConfig_Spec {}
16494 #[doc = "`write(|w| ..)` method takes [`dmac_chn_config_::W`](W) writer structure"]
16495 impl crate::Writable for DmacChnConfig_Spec {
16496 type Safety = crate::Unsafe;
16497 }
16498 #[doc = "`reset()` method sets DMAC_CHN_CONFIG_%s to value 0"]
16499 impl crate::Resettable for DmacChnConfig_Spec {}
16500 }
16501}
16502#[doc = "RTC instance 0 (rtc_unified IP v150)"]
16503pub type Rtc = crate::Periph<rtc::RegisterBlock, 0x5702_4100>;
16504impl core::fmt::Debug for Rtc {
16505 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
16506 f.debug_struct("Rtc").finish()
16507 }
16508}
16509#[doc = "RTC instance 0 (rtc_unified IP v150)"]
16510pub mod rtc {
16511 #[repr(C)]
16512 #[doc = "Register block"]
16513 pub struct RegisterBlock {
16514 load_count0: LoadCount0,
16515 load_count1: LoadCount1,
16516 current_value0: CurrentValue0,
16517 current_value1: CurrentValue1,
16518 control: Control,
16519 eoi_ren: EoiRen,
16520 raw_intr: RawIntr,
16521 intr: Intr,
16522 }
16523 impl RegisterBlock {
16524 #[doc = "0x00 - LOAD_COUNT0"]
16525 #[inline(always)]
16526 pub const fn load_count0(&self) -> &LoadCount0 {
16527 &self.load_count0
16528 }
16529 #[doc = "0x04 - LOAD_COUNT1"]
16530 #[inline(always)]
16531 pub const fn load_count1(&self) -> &LoadCount1 {
16532 &self.load_count1
16533 }
16534 #[doc = "0x08 - CURRENT_VALUE0"]
16535 #[inline(always)]
16536 pub const fn current_value0(&self) -> &CurrentValue0 {
16537 &self.current_value0
16538 }
16539 #[doc = "0x0c - CURRENT_VALUE1"]
16540 #[inline(always)]
16541 pub const fn current_value1(&self) -> &CurrentValue1 {
16542 &self.current_value1
16543 }
16544 #[doc = "0x10 - CONTROL"]
16545 #[inline(always)]
16546 pub const fn control(&self) -> &Control {
16547 &self.control
16548 }
16549 #[doc = "0x14 - EOI_REN"]
16550 #[inline(always)]
16551 pub const fn eoi_ren(&self) -> &EoiRen {
16552 &self.eoi_ren
16553 }
16554 #[doc = "0x18 - RAW_INTR"]
16555 #[inline(always)]
16556 pub const fn raw_intr(&self) -> &RawIntr {
16557 &self.raw_intr
16558 }
16559 #[doc = "0x1c - INTR"]
16560 #[inline(always)]
16561 pub const fn intr(&self) -> &Intr {
16562 &self.intr
16563 }
16564 }
16565 #[doc = "LOAD_COUNT0 (rw) register accessor: LOAD_COUNT0\n\nYou can [`read`](crate::Reg::read) this register and get [`load_count0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load_count0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load_count0`] module"]
16566 #[doc(alias = "LOAD_COUNT0")]
16567 pub type LoadCount0 = crate::Reg<load_count0::LoadCount0Spec>;
16568 #[doc = "LOAD_COUNT0"]
16569 pub mod load_count0 {
16570 #[doc = "Register `LOAD_COUNT0` reader"]
16571 pub type R = crate::R<LoadCount0Spec>;
16572 #[doc = "Register `LOAD_COUNT0` writer"]
16573 pub type W = crate::W<LoadCount0Spec>;
16574 #[doc = "Field `load_count0` reader - "]
16575 pub type LoadCount0R = crate::FieldReader<u32>;
16576 #[doc = "Field `load_count0` writer - "]
16577 pub type LoadCount0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
16578 impl R {
16579 #[doc = "Bits 0:31"]
16580 #[inline(always)]
16581 pub fn load_count0(&self) -> LoadCount0R {
16582 LoadCount0R::new(self.bits)
16583 }
16584 }
16585 impl W {
16586 #[doc = "Bits 0:31"]
16587 #[inline(always)]
16588 pub fn load_count0(&mut self) -> LoadCount0W<'_, LoadCount0Spec> {
16589 LoadCount0W::new(self, 0)
16590 }
16591 }
16592 #[doc = "LOAD_COUNT0\n\nYou can [`read`](crate::Reg::read) this register and get [`load_count0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load_count0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16593 pub struct LoadCount0Spec;
16594 impl crate::RegisterSpec for LoadCount0Spec {
16595 type Ux = u32;
16596 }
16597 #[doc = "`read()` method returns [`load_count0::R`](R) reader structure"]
16598 impl crate::Readable for LoadCount0Spec {}
16599 #[doc = "`write(|w| ..)` method takes [`load_count0::W`](W) writer structure"]
16600 impl crate::Writable for LoadCount0Spec {
16601 type Safety = crate::Unsafe;
16602 }
16603 #[doc = "`reset()` method sets LOAD_COUNT0 to value 0"]
16604 impl crate::Resettable for LoadCount0Spec {}
16605 }
16606 #[doc = "LOAD_COUNT1 (rw) register accessor: LOAD_COUNT1\n\nYou can [`read`](crate::Reg::read) this register and get [`load_count1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load_count1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load_count1`] module"]
16607 #[doc(alias = "LOAD_COUNT1")]
16608 pub type LoadCount1 = crate::Reg<load_count1::LoadCount1Spec>;
16609 #[doc = "LOAD_COUNT1"]
16610 pub mod load_count1 {
16611 #[doc = "Register `LOAD_COUNT1` reader"]
16612 pub type R = crate::R<LoadCount1Spec>;
16613 #[doc = "Register `LOAD_COUNT1` writer"]
16614 pub type W = crate::W<LoadCount1Spec>;
16615 #[doc = "Field `load_count1` reader - "]
16616 pub type LoadCount1R = crate::FieldReader<u32>;
16617 #[doc = "Field `load_count1` writer - "]
16618 pub type LoadCount1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
16619 impl R {
16620 #[doc = "Bits 0:31"]
16621 #[inline(always)]
16622 pub fn load_count1(&self) -> LoadCount1R {
16623 LoadCount1R::new(self.bits)
16624 }
16625 }
16626 impl W {
16627 #[doc = "Bits 0:31"]
16628 #[inline(always)]
16629 pub fn load_count1(&mut self) -> LoadCount1W<'_, LoadCount1Spec> {
16630 LoadCount1W::new(self, 0)
16631 }
16632 }
16633 #[doc = "LOAD_COUNT1\n\nYou can [`read`](crate::Reg::read) this register and get [`load_count1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load_count1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16634 pub struct LoadCount1Spec;
16635 impl crate::RegisterSpec for LoadCount1Spec {
16636 type Ux = u32;
16637 }
16638 #[doc = "`read()` method returns [`load_count1::R`](R) reader structure"]
16639 impl crate::Readable for LoadCount1Spec {}
16640 #[doc = "`write(|w| ..)` method takes [`load_count1::W`](W) writer structure"]
16641 impl crate::Writable for LoadCount1Spec {
16642 type Safety = crate::Unsafe;
16643 }
16644 #[doc = "`reset()` method sets LOAD_COUNT1 to value 0"]
16645 impl crate::Resettable for LoadCount1Spec {}
16646 }
16647 #[doc = "CURRENT_VALUE0 (r) register accessor: CURRENT_VALUE0\n\nYou can [`read`](crate::Reg::read) this register and get [`current_value0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@current_value0`] module"]
16648 #[doc(alias = "CURRENT_VALUE0")]
16649 pub type CurrentValue0 = crate::Reg<current_value0::CurrentValue0Spec>;
16650 #[doc = "CURRENT_VALUE0"]
16651 pub mod current_value0 {
16652 #[doc = "Register `CURRENT_VALUE0` reader"]
16653 pub type R = crate::R<CurrentValue0Spec>;
16654 #[doc = "Field `current_value0` reader - "]
16655 pub type CurrentValue0R = crate::FieldReader<u32>;
16656 impl R {
16657 #[doc = "Bits 0:31"]
16658 #[inline(always)]
16659 pub fn current_value0(&self) -> CurrentValue0R {
16660 CurrentValue0R::new(self.bits)
16661 }
16662 }
16663 #[doc = "CURRENT_VALUE0\n\nYou can [`read`](crate::Reg::read) this register and get [`current_value0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16664 pub struct CurrentValue0Spec;
16665 impl crate::RegisterSpec for CurrentValue0Spec {
16666 type Ux = u32;
16667 }
16668 #[doc = "`read()` method returns [`current_value0::R`](R) reader structure"]
16669 impl crate::Readable for CurrentValue0Spec {}
16670 #[doc = "`reset()` method sets CURRENT_VALUE0 to value 0"]
16671 impl crate::Resettable for CurrentValue0Spec {}
16672 }
16673 #[doc = "CURRENT_VALUE1 (r) register accessor: CURRENT_VALUE1\n\nYou can [`read`](crate::Reg::read) this register and get [`current_value1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@current_value1`] module"]
16674 #[doc(alias = "CURRENT_VALUE1")]
16675 pub type CurrentValue1 = crate::Reg<current_value1::CurrentValue1Spec>;
16676 #[doc = "CURRENT_VALUE1"]
16677 pub mod current_value1 {
16678 #[doc = "Register `CURRENT_VALUE1` reader"]
16679 pub type R = crate::R<CurrentValue1Spec>;
16680 #[doc = "Field `current_value1` reader - "]
16681 pub type CurrentValue1R = crate::FieldReader<u32>;
16682 impl R {
16683 #[doc = "Bits 0:31"]
16684 #[inline(always)]
16685 pub fn current_value1(&self) -> CurrentValue1R {
16686 CurrentValue1R::new(self.bits)
16687 }
16688 }
16689 #[doc = "CURRENT_VALUE1\n\nYou can [`read`](crate::Reg::read) this register and get [`current_value1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16690 pub struct CurrentValue1Spec;
16691 impl crate::RegisterSpec for CurrentValue1Spec {
16692 type Ux = u32;
16693 }
16694 #[doc = "`read()` method returns [`current_value1::R`](R) reader structure"]
16695 impl crate::Readable for CurrentValue1Spec {}
16696 #[doc = "`reset()` method sets CURRENT_VALUE1 to value 0"]
16697 impl crate::Resettable for CurrentValue1Spec {}
16698 }
16699 #[doc = "CONTROL (rw) register accessor: CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`] module"]
16700 #[doc(alias = "CONTROL")]
16701 pub type Control = crate::Reg<control::ControlSpec>;
16702 #[doc = "CONTROL"]
16703 pub mod control {
16704 #[doc = "Register `CONTROL` reader"]
16705 pub type R = crate::R<ControlSpec>;
16706 #[doc = "Register `CONTROL` writer"]
16707 pub type W = crate::W<ControlSpec>;
16708 #[doc = "Field `enable` reader - "]
16709 pub type EnableR = crate::BitReader;
16710 #[doc = "Field `enable` writer - "]
16711 pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
16712 #[doc = "Field `mode` reader - "]
16713 pub type ModeR = crate::FieldReader;
16714 #[doc = "Field `mode` writer - "]
16715 pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
16716 #[doc = "Field `int_mask` reader - "]
16717 pub type IntMaskR = crate::BitReader;
16718 #[doc = "Field `int_mask` writer - "]
16719 pub type IntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
16720 #[doc = "Field `rstfsm` reader - "]
16721 pub type RstfsmR = crate::BitReader;
16722 #[doc = "Field `rstfsm` writer - "]
16723 pub type RstfsmW<'a, REG> = crate::BitWriter<'a, REG>;
16724 #[doc = "Field `cnt_req` reader - "]
16725 pub type CntReqR = crate::BitReader;
16726 #[doc = "Field `cnt_req` writer - "]
16727 pub type CntReqW<'a, REG> = crate::BitWriter<'a, REG>;
16728 #[doc = "Field `cnt_lock` reader - "]
16729 pub type CntLockR = crate::BitReader;
16730 impl R {
16731 #[doc = "Bit 0"]
16732 #[inline(always)]
16733 pub fn enable(&self) -> EnableR {
16734 EnableR::new((self.bits & 1) != 0)
16735 }
16736 #[doc = "Bits 1:2"]
16737 #[inline(always)]
16738 pub fn mode(&self) -> ModeR {
16739 ModeR::new(((self.bits >> 1) & 3) as u8)
16740 }
16741 #[doc = "Bit 3"]
16742 #[inline(always)]
16743 pub fn int_mask(&self) -> IntMaskR {
16744 IntMaskR::new(((self.bits >> 3) & 1) != 0)
16745 }
16746 #[doc = "Bit 4"]
16747 #[inline(always)]
16748 pub fn rstfsm(&self) -> RstfsmR {
16749 RstfsmR::new(((self.bits >> 4) & 1) != 0)
16750 }
16751 #[doc = "Bit 5"]
16752 #[inline(always)]
16753 pub fn cnt_req(&self) -> CntReqR {
16754 CntReqR::new(((self.bits >> 5) & 1) != 0)
16755 }
16756 #[doc = "Bit 6"]
16757 #[inline(always)]
16758 pub fn cnt_lock(&self) -> CntLockR {
16759 CntLockR::new(((self.bits >> 6) & 1) != 0)
16760 }
16761 }
16762 impl W {
16763 #[doc = "Bit 0"]
16764 #[inline(always)]
16765 pub fn enable(&mut self) -> EnableW<'_, ControlSpec> {
16766 EnableW::new(self, 0)
16767 }
16768 #[doc = "Bits 1:2"]
16769 #[inline(always)]
16770 pub fn mode(&mut self) -> ModeW<'_, ControlSpec> {
16771 ModeW::new(self, 1)
16772 }
16773 #[doc = "Bit 3"]
16774 #[inline(always)]
16775 pub fn int_mask(&mut self) -> IntMaskW<'_, ControlSpec> {
16776 IntMaskW::new(self, 3)
16777 }
16778 #[doc = "Bit 4"]
16779 #[inline(always)]
16780 pub fn rstfsm(&mut self) -> RstfsmW<'_, ControlSpec> {
16781 RstfsmW::new(self, 4)
16782 }
16783 #[doc = "Bit 5"]
16784 #[inline(always)]
16785 pub fn cnt_req(&mut self) -> CntReqW<'_, ControlSpec> {
16786 CntReqW::new(self, 5)
16787 }
16788 }
16789 #[doc = "CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16790 pub struct ControlSpec;
16791 impl crate::RegisterSpec for ControlSpec {
16792 type Ux = u32;
16793 }
16794 #[doc = "`read()` method returns [`control::R`](R) reader structure"]
16795 impl crate::Readable for ControlSpec {}
16796 #[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"]
16797 impl crate::Writable for ControlSpec {
16798 type Safety = crate::Unsafe;
16799 }
16800 #[doc = "`reset()` method sets CONTROL to value 0"]
16801 impl crate::Resettable for ControlSpec {}
16802 }
16803 #[doc = "EOI_REN (r) register accessor: EOI_REN\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi_ren`] module"]
16804 #[doc(alias = "EOI_REN")]
16805 pub type EoiRen = crate::Reg<eoi_ren::EoiRenSpec>;
16806 #[doc = "EOI_REN"]
16807 pub mod eoi_ren {
16808 #[doc = "Register `EOI_REN` reader"]
16809 pub type R = crate::R<EoiRenSpec>;
16810 #[doc = "Field `eoi` reader - "]
16811 pub type EoiR = crate::BitReader;
16812 impl R {
16813 #[doc = "Bit 0"]
16814 #[inline(always)]
16815 pub fn eoi(&self) -> EoiR {
16816 EoiR::new((self.bits & 1) != 0)
16817 }
16818 }
16819 #[doc = "EOI_REN\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16820 pub struct EoiRenSpec;
16821 impl crate::RegisterSpec for EoiRenSpec {
16822 type Ux = u32;
16823 }
16824 #[doc = "`read()` method returns [`eoi_ren::R`](R) reader structure"]
16825 impl crate::Readable for EoiRenSpec {}
16826 #[doc = "`reset()` method sets EOI_REN to value 0"]
16827 impl crate::Resettable for EoiRenSpec {}
16828 }
16829 #[doc = "RAW_INTR (r) register accessor: RAW_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr`] module"]
16830 #[doc(alias = "RAW_INTR")]
16831 pub type RawIntr = crate::Reg<raw_intr::RawIntrSpec>;
16832 #[doc = "RAW_INTR"]
16833 pub mod raw_intr {
16834 #[doc = "Register `RAW_INTR` reader"]
16835 pub type R = crate::R<RawIntrSpec>;
16836 #[doc = "Field `int_status` reader - "]
16837 pub type IntStatusR = crate::BitReader;
16838 impl R {
16839 #[doc = "Bit 0"]
16840 #[inline(always)]
16841 pub fn int_status(&self) -> IntStatusR {
16842 IntStatusR::new((self.bits & 1) != 0)
16843 }
16844 }
16845 #[doc = "RAW_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16846 pub struct RawIntrSpec;
16847 impl crate::RegisterSpec for RawIntrSpec {
16848 type Ux = u32;
16849 }
16850 #[doc = "`read()` method returns [`raw_intr::R`](R) reader structure"]
16851 impl crate::Readable for RawIntrSpec {}
16852 #[doc = "`reset()` method sets RAW_INTR to value 0"]
16853 impl crate::Resettable for RawIntrSpec {}
16854 }
16855 #[doc = "INTR (r) register accessor: INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr`] module"]
16856 #[doc(alias = "INTR")]
16857 pub type Intr = crate::Reg<intr::IntrSpec>;
16858 #[doc = "INTR"]
16859 pub mod intr {
16860 #[doc = "Register `INTR` reader"]
16861 pub type R = crate::R<IntrSpec>;
16862 #[doc = "Field `int_status` reader - "]
16863 pub type IntStatusR = crate::BitReader;
16864 impl R {
16865 #[doc = "Bit 0"]
16866 #[inline(always)]
16867 pub fn int_status(&self) -> IntStatusR {
16868 IntStatusR::new((self.bits & 1) != 0)
16869 }
16870 }
16871 #[doc = "INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
16872 pub struct IntrSpec;
16873 impl crate::RegisterSpec for IntrSpec {
16874 type Ux = u32;
16875 }
16876 #[doc = "`read()` method returns [`intr::R`](R) reader structure"]
16877 impl crate::Readable for IntrSpec {}
16878 #[doc = "`reset()` method sets INTR to value 0"]
16879 impl crate::Resettable for IntrSpec {}
16880 }
16881}
16882#[doc = "True Random Number Generator"]
16883pub type Trng = crate::Periph<trng::RegisterBlock, 0x5200_9000>;
16884impl core::fmt::Debug for Trng {
16885 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
16886 f.debug_struct("Trng").finish()
16887 }
16888}
16889#[doc = "True Random Number Generator"]
16890pub mod trng {
16891 #[repr(C)]
16892 #[doc = "Register block"]
16893 pub struct RegisterBlock {
16894 trng_ctrl: TrngCtrl,
16895 _reserved1: [u8; 0x20],
16896 trng_ring_en: TrngRingEn,
16897 _reserved2: [u8; 0xd8],
16898 trng_fifo_data: TrngFifoData,
16899 trng_fifo_ready: TrngFifoReady,
16900 trng_data_st: TrngDataSt,
16901 _reserved5: [u8; 0x68],
16902 trng_fro_sample_clk_sel: TrngFroSampleClkSel,
16903 trng_fro_div_cnt: TrngFroDivCnt,
16904 }
16905 impl RegisterBlock {
16906 #[doc = "0x00 - TRNG_CTRL"]
16907 #[inline(always)]
16908 pub const fn trng_ctrl(&self) -> &TrngCtrl {
16909 &self.trng_ctrl
16910 }
16911 #[doc = "0x24 - TRNG_RING_EN"]
16912 #[inline(always)]
16913 pub const fn trng_ring_en(&self) -> &TrngRingEn {
16914 &self.trng_ring_en
16915 }
16916 #[doc = "0x100 - TRNG FIFO data output register"]
16917 #[inline(always)]
16918 pub const fn trng_fifo_data(&self) -> &TrngFifoData {
16919 &self.trng_fifo_data
16920 }
16921 #[doc = "0x104 - TRNG FIFO ready status"]
16922 #[inline(always)]
16923 pub const fn trng_fifo_ready(&self) -> &TrngFifoReady {
16924 &self.trng_fifo_ready
16925 }
16926 #[doc = "0x108 - TRNG data status register"]
16927 #[inline(always)]
16928 pub const fn trng_data_st(&self) -> &TrngDataSt {
16929 &self.trng_data_st
16930 }
16931 #[doc = "0x174 - TRNG FRO sample clock select"]
16932 #[inline(always)]
16933 pub const fn trng_fro_sample_clk_sel(&self) -> &TrngFroSampleClkSel {
16934 &self.trng_fro_sample_clk_sel
16935 }
16936 #[doc = "0x178 - TRNG FRO divider count"]
16937 #[inline(always)]
16938 pub const fn trng_fro_div_cnt(&self) -> &TrngFroDivCnt {
16939 &self.trng_fro_div_cnt
16940 }
16941 }
16942 #[doc = "TRNG_CTRL (rw) register accessor: TRNG_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_ctrl`] module"]
16943 #[doc(alias = "TRNG_CTRL")]
16944 pub type TrngCtrl = crate::Reg<trng_ctrl::TrngCtrlSpec>;
16945 #[doc = "TRNG_CTRL"]
16946 pub mod trng_ctrl {
16947 #[doc = "Register `TRNG_CTRL` reader"]
16948 pub type R = crate::R<TrngCtrlSpec>;
16949 #[doc = "Register `TRNG_CTRL` writer"]
16950 pub type W = crate::W<TrngCtrlSpec>;
16951 #[doc = "Field `health_test_en` reader - "]
16952 pub type HealthTestEnR = crate::BitReader;
16953 #[doc = "Field `health_test_en` writer - "]
16954 pub type HealthTestEnW<'a, REG> = crate::BitWriter<'a, REG>;
16955 #[doc = "Field `online_test_en` reader - "]
16956 pub type OnlineTestEnR = crate::BitReader;
16957 #[doc = "Field `online_test_en` writer - "]
16958 pub type OnlineTestEnW<'a, REG> = crate::BitWriter<'a, REG>;
16959 #[doc = "Field `post_proc_en` reader - "]
16960 pub type PostProcEnR = crate::BitReader;
16961 #[doc = "Field `post_proc_en` writer - "]
16962 pub type PostProcEnW<'a, REG> = crate::BitWriter<'a, REG>;
16963 #[doc = "Field `rnd_chk_en` reader - "]
16964 pub type RndChkEnR = crate::BitReader;
16965 #[doc = "Field `rnd_chk_en` writer - "]
16966 pub type RndChkEnW<'a, REG> = crate::BitWriter<'a, REG>;
16967 #[doc = "Field `lfsr_reseed_en` reader - "]
16968 pub type LfsrReseedEnR = crate::BitReader;
16969 #[doc = "Field `lfsr_reseed_en` writer - "]
16970 pub type LfsrReseedEnW<'a, REG> = crate::BitWriter<'a, REG>;
16971 #[doc = "Field `private_en` reader - "]
16972 pub type PrivateEnR = crate::BitReader;
16973 #[doc = "Field `private_en` writer - "]
16974 pub type PrivateEnW<'a, REG> = crate::BitWriter<'a, REG>;
16975 impl R {
16976 #[doc = "Bit 0"]
16977 #[inline(always)]
16978 pub fn health_test_en(&self) -> HealthTestEnR {
16979 HealthTestEnR::new((self.bits & 1) != 0)
16980 }
16981 #[doc = "Bit 1"]
16982 #[inline(always)]
16983 pub fn online_test_en(&self) -> OnlineTestEnR {
16984 OnlineTestEnR::new(((self.bits >> 1) & 1) != 0)
16985 }
16986 #[doc = "Bit 2"]
16987 #[inline(always)]
16988 pub fn post_proc_en(&self) -> PostProcEnR {
16989 PostProcEnR::new(((self.bits >> 2) & 1) != 0)
16990 }
16991 #[doc = "Bit 3"]
16992 #[inline(always)]
16993 pub fn rnd_chk_en(&self) -> RndChkEnR {
16994 RndChkEnR::new(((self.bits >> 3) & 1) != 0)
16995 }
16996 #[doc = "Bit 4"]
16997 #[inline(always)]
16998 pub fn lfsr_reseed_en(&self) -> LfsrReseedEnR {
16999 LfsrReseedEnR::new(((self.bits >> 4) & 1) != 0)
17000 }
17001 #[doc = "Bit 5"]
17002 #[inline(always)]
17003 pub fn private_en(&self) -> PrivateEnR {
17004 PrivateEnR::new(((self.bits >> 5) & 1) != 0)
17005 }
17006 }
17007 impl W {
17008 #[doc = "Bit 0"]
17009 #[inline(always)]
17010 pub fn health_test_en(&mut self) -> HealthTestEnW<'_, TrngCtrlSpec> {
17011 HealthTestEnW::new(self, 0)
17012 }
17013 #[doc = "Bit 1"]
17014 #[inline(always)]
17015 pub fn online_test_en(&mut self) -> OnlineTestEnW<'_, TrngCtrlSpec> {
17016 OnlineTestEnW::new(self, 1)
17017 }
17018 #[doc = "Bit 2"]
17019 #[inline(always)]
17020 pub fn post_proc_en(&mut self) -> PostProcEnW<'_, TrngCtrlSpec> {
17021 PostProcEnW::new(self, 2)
17022 }
17023 #[doc = "Bit 3"]
17024 #[inline(always)]
17025 pub fn rnd_chk_en(&mut self) -> RndChkEnW<'_, TrngCtrlSpec> {
17026 RndChkEnW::new(self, 3)
17027 }
17028 #[doc = "Bit 4"]
17029 #[inline(always)]
17030 pub fn lfsr_reseed_en(&mut self) -> LfsrReseedEnW<'_, TrngCtrlSpec> {
17031 LfsrReseedEnW::new(self, 4)
17032 }
17033 #[doc = "Bit 5"]
17034 #[inline(always)]
17035 pub fn private_en(&mut self) -> PrivateEnW<'_, TrngCtrlSpec> {
17036 PrivateEnW::new(self, 5)
17037 }
17038 }
17039 #[doc = "TRNG_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17040 pub struct TrngCtrlSpec;
17041 impl crate::RegisterSpec for TrngCtrlSpec {
17042 type Ux = u32;
17043 }
17044 #[doc = "`read()` method returns [`trng_ctrl::R`](R) reader structure"]
17045 impl crate::Readable for TrngCtrlSpec {}
17046 #[doc = "`write(|w| ..)` method takes [`trng_ctrl::W`](W) writer structure"]
17047 impl crate::Writable for TrngCtrlSpec {
17048 type Safety = crate::Unsafe;
17049 }
17050 #[doc = "`reset()` method sets TRNG_CTRL to value 0"]
17051 impl crate::Resettable for TrngCtrlSpec {}
17052 }
17053 #[doc = "TRNG_RING_EN (rw) register accessor: TRNG_RING_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_ring_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_ring_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_ring_en`] module"]
17054 #[doc(alias = "TRNG_RING_EN")]
17055 pub type TrngRingEn = crate::Reg<trng_ring_en::TrngRingEnSpec>;
17056 #[doc = "TRNG_RING_EN"]
17057 pub mod trng_ring_en {
17058 #[doc = "Register `TRNG_RING_EN` reader"]
17059 pub type R = crate::R<TrngRingEnSpec>;
17060 #[doc = "Register `TRNG_RING_EN` writer"]
17061 pub type W = crate::W<TrngRingEnSpec>;
17062 #[doc = "Field `ro_en` reader - "]
17063 pub type RoEnR = crate::BitReader;
17064 #[doc = "Field `ro_en` writer - "]
17065 pub type RoEnW<'a, REG> = crate::BitWriter<'a, REG>;
17066 #[doc = "Field `tero_en` reader - "]
17067 pub type TeroEnR = crate::BitReader;
17068 #[doc = "Field `tero_en` writer - "]
17069 pub type TeroEnW<'a, REG> = crate::BitWriter<'a, REG>;
17070 #[doc = "Field `fro_en` reader - "]
17071 pub type FroEnR = crate::BitReader;
17072 #[doc = "Field `fro_en` writer - "]
17073 pub type FroEnW<'a, REG> = crate::BitWriter<'a, REG>;
17074 impl R {
17075 #[doc = "Bit 0"]
17076 #[inline(always)]
17077 pub fn ro_en(&self) -> RoEnR {
17078 RoEnR::new((self.bits & 1) != 0)
17079 }
17080 #[doc = "Bit 1"]
17081 #[inline(always)]
17082 pub fn tero_en(&self) -> TeroEnR {
17083 TeroEnR::new(((self.bits >> 1) & 1) != 0)
17084 }
17085 #[doc = "Bit 2"]
17086 #[inline(always)]
17087 pub fn fro_en(&self) -> FroEnR {
17088 FroEnR::new(((self.bits >> 2) & 1) != 0)
17089 }
17090 }
17091 impl W {
17092 #[doc = "Bit 0"]
17093 #[inline(always)]
17094 pub fn ro_en(&mut self) -> RoEnW<'_, TrngRingEnSpec> {
17095 RoEnW::new(self, 0)
17096 }
17097 #[doc = "Bit 1"]
17098 #[inline(always)]
17099 pub fn tero_en(&mut self) -> TeroEnW<'_, TrngRingEnSpec> {
17100 TeroEnW::new(self, 1)
17101 }
17102 #[doc = "Bit 2"]
17103 #[inline(always)]
17104 pub fn fro_en(&mut self) -> FroEnW<'_, TrngRingEnSpec> {
17105 FroEnW::new(self, 2)
17106 }
17107 }
17108 #[doc = "TRNG_RING_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_ring_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_ring_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17109 pub struct TrngRingEnSpec;
17110 impl crate::RegisterSpec for TrngRingEnSpec {
17111 type Ux = u32;
17112 }
17113 #[doc = "`read()` method returns [`trng_ring_en::R`](R) reader structure"]
17114 impl crate::Readable for TrngRingEnSpec {}
17115 #[doc = "`write(|w| ..)` method takes [`trng_ring_en::W`](W) writer structure"]
17116 impl crate::Writable for TrngRingEnSpec {
17117 type Safety = crate::Unsafe;
17118 }
17119 #[doc = "`reset()` method sets TRNG_RING_EN to value 0"]
17120 impl crate::Resettable for TrngRingEnSpec {}
17121 }
17122 #[doc = "TRNG_FIFO_DATA (rw) register accessor: TRNG FIFO data output register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fifo_data`] module"]
17123 #[doc(alias = "TRNG_FIFO_DATA")]
17124 pub type TrngFifoData = crate::Reg<trng_fifo_data::TrngFifoDataSpec>;
17125 #[doc = "TRNG FIFO data output register"]
17126 pub mod trng_fifo_data {
17127 #[doc = "Register `TRNG_FIFO_DATA` reader"]
17128 pub type R = crate::R<TrngFifoDataSpec>;
17129 #[doc = "Register `TRNG_FIFO_DATA` writer"]
17130 pub type W = crate::W<TrngFifoDataSpec>;
17131 #[doc = "Field `trng_data` reader - Random data (read to get random number)"]
17132 pub type TrngDataR = crate::FieldReader<u32>;
17133 impl R {
17134 #[doc = "Bits 0:31 - Random data (read to get random number)"]
17135 #[inline(always)]
17136 pub fn trng_data(&self) -> TrngDataR {
17137 TrngDataR::new(self.bits)
17138 }
17139 }
17140 impl W {}
17141 #[doc = "TRNG FIFO data output register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17142 pub struct TrngFifoDataSpec;
17143 impl crate::RegisterSpec for TrngFifoDataSpec {
17144 type Ux = u32;
17145 }
17146 #[doc = "`read()` method returns [`trng_fifo_data::R`](R) reader structure"]
17147 impl crate::Readable for TrngFifoDataSpec {}
17148 #[doc = "`write(|w| ..)` method takes [`trng_fifo_data::W`](W) writer structure"]
17149 impl crate::Writable for TrngFifoDataSpec {
17150 type Safety = crate::Unsafe;
17151 }
17152 #[doc = "`reset()` method sets TRNG_FIFO_DATA to value 0"]
17153 impl crate::Resettable for TrngFifoDataSpec {}
17154 }
17155 #[doc = "TRNG_FIFO_READY (rw) register accessor: TRNG FIFO ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_ready::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_ready::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fifo_ready`] module"]
17156 #[doc(alias = "TRNG_FIFO_READY")]
17157 pub type TrngFifoReady = crate::Reg<trng_fifo_ready::TrngFifoReadySpec>;
17158 #[doc = "TRNG FIFO ready status"]
17159 pub mod trng_fifo_ready {
17160 #[doc = "Register `TRNG_FIFO_READY` reader"]
17161 pub type R = crate::R<TrngFifoReadySpec>;
17162 #[doc = "Register `TRNG_FIFO_READY` writer"]
17163 pub type W = crate::W<TrngFifoReadySpec>;
17164 #[doc = "Field `trng_data_ready` reader - Data ready: 1=data available in FIFO"]
17165 pub type TrngDataReadyR = crate::BitReader;
17166 #[doc = "Field `trng_done` reader - TRNG generation done"]
17167 pub type TrngDoneR = crate::BitReader;
17168 impl R {
17169 #[doc = "Bit 0 - Data ready: 1=data available in FIFO"]
17170 #[inline(always)]
17171 pub fn trng_data_ready(&self) -> TrngDataReadyR {
17172 TrngDataReadyR::new((self.bits & 1) != 0)
17173 }
17174 #[doc = "Bit 1 - TRNG generation done"]
17175 #[inline(always)]
17176 pub fn trng_done(&self) -> TrngDoneR {
17177 TrngDoneR::new(((self.bits >> 1) & 1) != 0)
17178 }
17179 }
17180 impl W {}
17181 #[doc = "TRNG FIFO ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_ready::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_ready::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17182 pub struct TrngFifoReadySpec;
17183 impl crate::RegisterSpec for TrngFifoReadySpec {
17184 type Ux = u32;
17185 }
17186 #[doc = "`read()` method returns [`trng_fifo_ready::R`](R) reader structure"]
17187 impl crate::Readable for TrngFifoReadySpec {}
17188 #[doc = "`write(|w| ..)` method takes [`trng_fifo_ready::W`](W) writer structure"]
17189 impl crate::Writable for TrngFifoReadySpec {
17190 type Safety = crate::Unsafe;
17191 }
17192 #[doc = "`reset()` method sets TRNG_FIFO_READY to value 0"]
17193 impl crate::Resettable for TrngFifoReadySpec {}
17194 }
17195 #[doc = "TRNG_DATA_ST (rw) register accessor: TRNG data status register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_data_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_data_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_data_st`] module"]
17196 #[doc(alias = "TRNG_DATA_ST")]
17197 pub type TrngDataSt = crate::Reg<trng_data_st::TrngDataStSpec>;
17198 #[doc = "TRNG data status register"]
17199 pub mod trng_data_st {
17200 #[doc = "Register `TRNG_DATA_ST` reader"]
17201 pub type R = crate::R<TrngDataStSpec>;
17202 #[doc = "Register `TRNG_DATA_ST` writer"]
17203 pub type W = crate::W<TrngDataStSpec>;
17204 #[doc = "Field `data_st` reader - Data status"]
17205 pub type DataStR = crate::FieldReader<u32>;
17206 impl R {
17207 #[doc = "Bits 0:31 - Data status"]
17208 #[inline(always)]
17209 pub fn data_st(&self) -> DataStR {
17210 DataStR::new(self.bits)
17211 }
17212 }
17213 impl W {}
17214 #[doc = "TRNG data status register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_data_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_data_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17215 pub struct TrngDataStSpec;
17216 impl crate::RegisterSpec for TrngDataStSpec {
17217 type Ux = u32;
17218 }
17219 #[doc = "`read()` method returns [`trng_data_st::R`](R) reader structure"]
17220 impl crate::Readable for TrngDataStSpec {}
17221 #[doc = "`write(|w| ..)` method takes [`trng_data_st::W`](W) writer structure"]
17222 impl crate::Writable for TrngDataStSpec {
17223 type Safety = crate::Unsafe;
17224 }
17225 #[doc = "`reset()` method sets TRNG_DATA_ST to value 0"]
17226 impl crate::Resettable for TrngDataStSpec {}
17227 }
17228 #[doc = "TRNG_FRO_SAMPLE_CLK_SEL (rw) register accessor: TRNG FRO sample clock select\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_sample_clk_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_sample_clk_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fro_sample_clk_sel`] module"]
17229 #[doc(alias = "TRNG_FRO_SAMPLE_CLK_SEL")]
17230 pub type TrngFroSampleClkSel = crate::Reg<trng_fro_sample_clk_sel::TrngFroSampleClkSelSpec>;
17231 #[doc = "TRNG FRO sample clock select"]
17232 pub mod trng_fro_sample_clk_sel {
17233 #[doc = "Register `TRNG_FRO_SAMPLE_CLK_SEL` reader"]
17234 pub type R = crate::R<TrngFroSampleClkSelSpec>;
17235 #[doc = "Register `TRNG_FRO_SAMPLE_CLK_SEL` writer"]
17236 pub type W = crate::W<TrngFroSampleClkSelSpec>;
17237 #[doc = "Field `fro_sample_clk_sel` reader - FRO sample clock select: 0=inner; 1=external"]
17238 pub type FroSampleClkSelR = crate::BitReader;
17239 #[doc = "Field `fro_sample_clk_sel` writer - FRO sample clock select: 0=inner; 1=external"]
17240 pub type FroSampleClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
17241 impl R {
17242 #[doc = "Bit 0 - FRO sample clock select: 0=inner; 1=external"]
17243 #[inline(always)]
17244 pub fn fro_sample_clk_sel(&self) -> FroSampleClkSelR {
17245 FroSampleClkSelR::new((self.bits & 1) != 0)
17246 }
17247 }
17248 impl W {
17249 #[doc = "Bit 0 - FRO sample clock select: 0=inner; 1=external"]
17250 #[inline(always)]
17251 pub fn fro_sample_clk_sel(&mut self) -> FroSampleClkSelW<'_, TrngFroSampleClkSelSpec> {
17252 FroSampleClkSelW::new(self, 0)
17253 }
17254 }
17255 #[doc = "TRNG FRO sample clock select\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_sample_clk_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_sample_clk_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17256 pub struct TrngFroSampleClkSelSpec;
17257 impl crate::RegisterSpec for TrngFroSampleClkSelSpec {
17258 type Ux = u32;
17259 }
17260 #[doc = "`read()` method returns [`trng_fro_sample_clk_sel::R`](R) reader structure"]
17261 impl crate::Readable for TrngFroSampleClkSelSpec {}
17262 #[doc = "`write(|w| ..)` method takes [`trng_fro_sample_clk_sel::W`](W) writer structure"]
17263 impl crate::Writable for TrngFroSampleClkSelSpec {
17264 type Safety = crate::Unsafe;
17265 }
17266 #[doc = "`reset()` method sets TRNG_FRO_SAMPLE_CLK_SEL to value 0"]
17267 impl crate::Resettable for TrngFroSampleClkSelSpec {}
17268 }
17269 #[doc = "TRNG_FRO_DIV_CNT (rw) register accessor: TRNG FRO divider count\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_div_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_div_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fro_div_cnt`] module"]
17270 #[doc(alias = "TRNG_FRO_DIV_CNT")]
17271 pub type TrngFroDivCnt = crate::Reg<trng_fro_div_cnt::TrngFroDivCntSpec>;
17272 #[doc = "TRNG FRO divider count"]
17273 pub mod trng_fro_div_cnt {
17274 #[doc = "Register `TRNG_FRO_DIV_CNT` reader"]
17275 pub type R = crate::R<TrngFroDivCntSpec>;
17276 #[doc = "Register `TRNG_FRO_DIV_CNT` writer"]
17277 pub type W = crate::W<TrngFroDivCntSpec>;
17278 #[doc = "Field `fro_div_cnt` reader - FRO divider count (default 0x1b)"]
17279 pub type FroDivCntR = crate::FieldReader;
17280 #[doc = "Field `fro_div_cnt` writer - FRO divider count (default 0x1b)"]
17281 pub type FroDivCntW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17282 impl R {
17283 #[doc = "Bits 0:7 - FRO divider count (default 0x1b)"]
17284 #[inline(always)]
17285 pub fn fro_div_cnt(&self) -> FroDivCntR {
17286 FroDivCntR::new((self.bits & 0xff) as u8)
17287 }
17288 }
17289 impl W {
17290 #[doc = "Bits 0:7 - FRO divider count (default 0x1b)"]
17291 #[inline(always)]
17292 pub fn fro_div_cnt(&mut self) -> FroDivCntW<'_, TrngFroDivCntSpec> {
17293 FroDivCntW::new(self, 0)
17294 }
17295 }
17296 #[doc = "TRNG FRO divider count\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_div_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_div_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
17297 pub struct TrngFroDivCntSpec;
17298 impl crate::RegisterSpec for TrngFroDivCntSpec {
17299 type Ux = u32;
17300 }
17301 #[doc = "`read()` method returns [`trng_fro_div_cnt::R`](R) reader structure"]
17302 impl crate::Readable for TrngFroDivCntSpec {}
17303 #[doc = "`write(|w| ..)` method takes [`trng_fro_div_cnt::W`](W) writer structure"]
17304 impl crate::Writable for TrngFroDivCntSpec {
17305 type Safety = crate::Unsafe;
17306 }
17307 #[doc = "`reset()` method sets TRNG_FRO_DIV_CNT to value 0"]
17308 impl crate::Resettable for TrngFroDivCntSpec {}
17309 }
17310}
17311#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17312pub type Gpio1 = crate::Periph<gpio0::RegisterBlock, 0x5701_4000>;
17313impl core::fmt::Debug for Gpio1 {
17314 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17315 f.debug_struct("Gpio1").finish()
17316 }
17317}
17318#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17319pub use self::gpio0 as gpio1;
17320#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17321pub type Gpio2 = crate::Periph<gpio0::RegisterBlock, 0x5701_8000>;
17322impl core::fmt::Debug for Gpio2 {
17323 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17324 f.debug_struct("Gpio2").finish()
17325 }
17326}
17327#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17328pub use self::gpio0 as gpio2;
17329#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17330pub type Gpio3 = crate::Periph<gpio0::RegisterBlock, 0x5701_c000>;
17331impl core::fmt::Debug for Gpio3 {
17332 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17333 f.debug_struct("Gpio3").finish()
17334 }
17335}
17336#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17337pub use self::gpio0 as gpio3;
17338#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17339pub type Gpio4 = crate::Periph<gpio0::RegisterBlock, 0x5702_0000>;
17340impl core::fmt::Debug for Gpio4 {
17341 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17342 f.debug_struct("Gpio4").finish()
17343 }
17344}
17345#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17346pub use self::gpio0 as gpio4;
17347#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17348pub type UlpGpio = crate::Periph<gpio0::RegisterBlock, 0x5703_0000>;
17349impl core::fmt::Debug for UlpGpio {
17350 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17351 f.debug_struct("UlpGpio").finish()
17352 }
17353}
17354#[doc = "GPIO controller for GPIO\\[7:0\\]"]
17355pub use self::gpio0 as ulp_gpio;
17356#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
17357pub type Uart1 = crate::Periph<uart0::RegisterBlock, 0x5208_0000>;
17358impl core::fmt::Debug for Uart1 {
17359 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17360 f.debug_struct("Uart1").finish()
17361 }
17362}
17363#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
17364pub use self::uart0 as uart1;
17365#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
17366pub type Uart2 = crate::Periph<uart0::RegisterBlock, 0x5208_2000>;
17367impl core::fmt::Debug for Uart2 {
17368 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17369 f.debug_struct("Uart2").finish()
17370 }
17371}
17372#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
17373pub use self::uart0 as uart2;
17374#[doc = "I2C0 master controller (DesignWare SSI, IP v151)"]
17375pub type I2c1 = crate::Periph<i2c0::RegisterBlock, 0x5208_4000>;
17376impl core::fmt::Debug for I2c1 {
17377 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17378 f.debug_struct("I2c1").finish()
17379 }
17380}
17381#[doc = "I2C0 master controller (DesignWare SSI, IP v151)"]
17382pub use self::i2c0 as i2c1;
17383#[doc = "SPI0 master/slave controller (SSI v151)"]
17384pub type Spi1 = crate::Periph<spi0::RegisterBlock, 0x5208_8000>;
17385impl core::fmt::Debug for Spi1 {
17386 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17387 f.debug_struct("Spi1").finish()
17388 }
17389}
17390#[doc = "SPI0 master/slave controller (SSI v151)"]
17391pub use self::spi0 as spi1;
17392#[doc = "SPI0 master/slave controller (SSI v151)"]
17393pub type Spi2 = crate::Periph<spi0::RegisterBlock, 0x5208_9000>;
17394impl core::fmt::Debug for Spi2 {
17395 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17396 f.debug_struct("Spi2").finish()
17397 }
17398}
17399#[doc = "SPI0 master/slave controller (SSI v151)"]
17400pub use self::spi0 as spi2;
17401#[doc = "DMA controller with 4 channels"]
17402pub type Sdma = crate::Periph<dma::RegisterBlock, 0x520a_0000>;
17403impl core::fmt::Debug for Sdma {
17404 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17405 f.debug_struct("Sdma").finish()
17406 }
17407}
17408#[doc = "DMA controller with 4 channels"]
17409pub use self::dma as sdma;
17410#[doc = "13-bit GADC (general ADC, v153)"]
17411pub type Gadc = crate::Periph<gadc::RegisterBlock, 0x5703_6000>;
17412impl core::fmt::Debug for Gadc {
17413 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
17414 f.debug_struct("Gadc").finish()
17415 }
17416}
17417#[doc = "13-bit GADC (general ADC, v153)"]
17418pub mod gadc {
17419 #[repr(C)]
17420 #[doc = "Register block"]
17421 pub struct RegisterBlock {
17422 cfg_rstn: CfgRstn,
17423 cfg_clken: CfgClken,
17424 cfg_prechg_lead: CfgPrechgLead,
17425 cfg_clk_div_0: CfgClkDiv0,
17426 cfg_clk_div_1: CfgClkDiv1,
17427 cfg_manual_clk_0: CfgManualClk0,
17428 cfg_manual_clk_1: CfgManualClk1,
17429 cfg_iso: CfgIso,
17430 _reserved8: [u8; 0x10],
17431 cfg_gadc_ctrl_0: CfgGadcCtrl0,
17432 cfg_gadc_ctrl_1: CfgGadcCtrl1,
17433 cfg_gadc_ctrl_2: CfgGadcCtrl2,
17434 cfg_gadc_ctrl_3: CfgGadcCtrl3,
17435 cfg_gadc_ctrl_4: CfgGadcCtrl4,
17436 rpt_gadc_ctrl_0: RptGadcCtrl0,
17437 cfg_gadc_ctrl_5: CfgGadcCtrl5,
17438 cfg_gadc_ctrl_6: CfgGadcCtrl6,
17439 rpt_gadc_ctrl_1: RptGadcCtrl1,
17440 cfg_gadc_ctrl_7: CfgGadcCtrl7,
17441 rpt_gadc_ctrl_2: RptGadcCtrl2,
17442 cfg_gadc_data_0: CfgGadcData0,
17443 cfg_gadc_data_1: CfgGadcData1,
17444 rpt_gadc_data_0: RptGadcData0,
17445 rpt_gadc_data_1: RptGadcData1,
17446 rpt_gadc_data_2: RptGadcData2,
17447 rpt_gadc_data_3: RptGadcData3,
17448 cfg_gadc_data_3: CfgGadcData3,
17449 cfg_gadc_data_4: CfgGadcData4,
17450 rpt_gadc_data_4: RptGadcData4,
17451 cfg_gadc_data_5: CfgGadcData5,
17452 cfg_gadc_data_6: CfgGadcData6,
17453 cfg_gadc_data_7: CfgGadcData7,
17454 cfg_gadc_data_8: CfgGadcData8,
17455 cfg_gadc_data_9: CfgGadcData9,
17456 cfg_gadc_data_10: CfgGadcData10,
17457 cfg_gadc_data_11: CfgGadcData11,
17458 cfg_gadc_data_12: CfgGadcData12,
17459 cfg_gadc_data_13: CfgGadcData13,
17460 cfg_gadc_data_14: CfgGadcData14,
17461 cfg_gadc_data_15: CfgGadcData15,
17462 cfg_gadc_data_16: CfgGadcData16,
17463 cfg_gadc_data_17: CfgGadcData17,
17464 cfg_gadc_data_18: CfgGadcData18,
17465 cfg_gadc_data_19: CfgGadcData19,
17466 cfg_gadc_data_20: CfgGadcData20,
17467 cfg_gadc_data_21: CfgGadcData21,
17468 cfg_gadc_data_22: CfgGadcData22,
17469 cfg_gadc_data_23: CfgGadcData23,
17470 cfg_gadc_data_24: CfgGadcData24,
17471 cfg_gadc_data_25: CfgGadcData25,
17472 rpt_gadc_data_5: RptGadcData5,
17473 rpt_gadc_data_6: RptGadcData6,
17474 rpt_gadc_data_7: RptGadcData7,
17475 rpt_gadc_data_8: RptGadcData8,
17476 rpt_gadc_data_9: RptGadcData9,
17477 rpt_gadc_data_10: RptGadcData10,
17478 rpt_gadc_data_11: RptGadcData11,
17479 rpt_gadc_data_12: RptGadcData12,
17480 rpt_gadc_data_13: RptGadcData13,
17481 _reserved58: [u8; 0x08],
17482 cfg_cmp_os_0: CfgCmpOs0,
17483 cfg_cmp_os_1: CfgCmpOs1,
17484 cfg_cmp_os_2: CfgCmpOs2,
17485 cfg_cmp_os_3: CfgCmpOs3,
17486 cfg_cmp_os_4: CfgCmpOs4,
17487 cfg_cmp_os_5: CfgCmpOs5,
17488 cfg_cmp_os_6: CfgCmpOs6,
17489 cfg_cmp_os_7: CfgCmpOs7,
17490 cfg_cmp_os_8: CfgCmpOs8,
17491 cfg_cmp_os_9: CfgCmpOs9,
17492 cfg_cmp_os_10: CfgCmpOs10,
17493 rpt_cmp_os_0: RptCmpOs0,
17494 cfg_cmp_os_11: CfgCmpOs11,
17495 cfg_cmp_os_12: CfgCmpOs12,
17496 rpt_cmp_os_2: RptCmpOs2,
17497 _reserved73: [u8; 0x14],
17498 cfg_cdac_fc0_0: CfgCdacFc0_0,
17499 cfg_cdac_fc0_1: CfgCdacFc0_1,
17500 cfg_cdac_fc0_2: CfgCdacFc0_2,
17501 cfg_cdac_fc0_3: CfgCdacFc0_3,
17502 cfg_cdac_fc0_4: CfgCdacFc0_4,
17503 cfg_cdac_fc0_5: CfgCdacFc0_5,
17504 rpt_cdac_fc0_0: RptCdacFc0_0,
17505 cfg_cdac_fc0_6: CfgCdacFc0_6,
17506 cfg_cdac_fc0_7: CfgCdacFc0_7,
17507 cfg_cdac_fc0_8: CfgCdacFc0_8,
17508 cfg_cdac_fc0_9: CfgCdacFc0_9,
17509 cfg_cdac_fc0_10: CfgCdacFc0_10,
17510 cfg_cdac_fc0_11: CfgCdacFc0_11,
17511 cfg_cdac_fc0_12: CfgCdacFc0_12,
17512 cfg_cdac_fc0_13: CfgCdacFc0_13,
17513 cfg_cdac_fc0_14: CfgCdacFc0_14,
17514 cfg_cdac_fc1_0: CfgCdacFc1_0,
17515 cfg_cdac_fc1_1: CfgCdacFc1_1,
17516 cfg_cdac_fc1_2: CfgCdacFc1_2,
17517 cfg_cdac_fc1_3: CfgCdacFc1_3,
17518 rpt_cdac_fc1_0: RptCdacFc1_0,
17519 rpt_cdac_fc1_3: RptCdacFc1_3,
17520 rpt_cdac_fc3_1: RptCdacFc3_1,
17521 rpt_cdac_fc3_2: RptCdacFc3_2,
17522 rpt_cdac_fc3_3: RptCdacFc3_3,
17523 rpt_cdac_fc3_4: RptCdacFc3_4,
17524 rpt_cdac_fc3_5: RptCdacFc3_5,
17525 rpt_cdac_fc3_6: RptCdacFc3_6,
17526 rpt_cdac_fc3_7: RptCdacFc3_7,
17527 rpt_cdac_fc3_8: RptCdacFc3_8,
17528 rpt_cdac_fc3_9: RptCdacFc3_9,
17529 rpt_cdac_fc3_10: RptCdacFc3_10,
17530 rpt_cdac_fc3_11: RptCdacFc3_11,
17531 rpt_cdac_fc3_12: RptCdacFc3_12,
17532 rpt_cdac_fc3_13: RptCdacFc3_13,
17533 rpt_cdac_fc3_14: RptCdacFc3_14,
17534 rpt_cdac_fc3_15: RptCdacFc3_15,
17535 rpt_cdac_fc3_16: RptCdacFc3_16,
17536 rpt_cdac_fc3_17: RptCdacFc3_17,
17537 rpt_cdac_fc3_18: RptCdacFc3_18,
17538 _reserved113: [u8; 0x10],
17539 cfg_dcoc_cal_0: CfgDcocCal0,
17540 cfg_dcoc_cal_1: CfgDcocCal1,
17541 cfg_dcoc_cal_2: CfgDcocCal2,
17542 cfg_dcoc_cal_3: CfgDcocCal3,
17543 cfg_dcoc_cal_4: CfgDcocCal4,
17544 cfg_dcoc_cal_5: CfgDcocCal5,
17545 cfg_dcoc_cal_6: CfgDcocCal6,
17546 cfg_dcoc_cal_7: CfgDcocCal7,
17547 cfg_dcoc_cal_8: CfgDcocCal8,
17548 rpt_dcoc_cal_0: RptDcocCal0,
17549 cfg_dcoc_cal_12: CfgDcocCal12,
17550 cfg_dcoc_cal_13: CfgDcocCal13,
17551 rpt_dcoc_cal_1: RptDcocCal1,
17552 _reserved126: [u8; 0x0c],
17553 cfg_sar_spd_0: CfgSarSpd0,
17554 cfg_sar_spd_1: CfgSarSpd1,
17555 cfg_sar_spd_2: CfgSarSpd2,
17556 cfg_sar_spd_3: CfgSarSpd3,
17557 cfg_sar_spd_4: CfgSarSpd4,
17558 rpt_sar_spd_0: RptSarSpd0,
17559 rpt_sar_spd_1: RptSarSpd1,
17560 cfg_sar_spd_6: CfgSarSpd6,
17561 rpt_sar_spd_2: RptSarSpd2,
17562 _reserved135: [u8; 0x1c],
17563 cfg_rc_cal_0: CfgRcCal0,
17564 cfg_rc_cal_1: CfgRcCal1,
17565 cfg_rc_cal_2: CfgRcCal2,
17566 cfg_rc_cal_3: CfgRcCal3,
17567 cfg_rc_cal_4: CfgRcCal4,
17568 rpt_rc_cal_0: RptRcCal0,
17569 rpt_rc_cal_1: RptRcCal1,
17570 cfg_rc_cal_5: CfgRcCal5,
17571 cfg_rc_cal_6: CfgRcCal6,
17572 cfg_rc_cal_7: CfgRcCal7,
17573 cfg_rc_cal_8: CfgRcCal8,
17574 rpt_rc_cal_2: RptRcCal2,
17575 rpt_rc_cal_3: RptRcCal3,
17576 _reserved148: [u8; 0x0c],
17577 cfg_amux_0: CfgAmux0,
17578 cfg_amux_1: CfgAmux1,
17579 cfg_amux_2: CfgAmux2,
17580 cfg_amux_3: CfgAmux3,
17581 cfg_amux_4: CfgAmux4,
17582 cfg_amux_5: CfgAmux5,
17583 rpt_amux_0: RptAmux0,
17584 _reserved155: [u8; 0x14],
17585 cfg_tst_0: CfgTst0,
17586 cfg_tst_1: CfgTst1,
17587 cfg_cmp_0: CfgCmp0,
17588 cfg_cmp_1: CfgCmp1,
17589 rpt_cmp_0: RptCmp0,
17590 rpt_cmp_1: RptCmp1,
17591 }
17592 impl RegisterBlock {
17593 #[doc = "0x00 - cfg_rstn"]
17594 #[inline(always)]
17595 pub const fn cfg_rstn(&self) -> &CfgRstn {
17596 &self.cfg_rstn
17597 }
17598 #[doc = "0x04 - cfg_clken"]
17599 #[inline(always)]
17600 pub const fn cfg_clken(&self) -> &CfgClken {
17601 &self.cfg_clken
17602 }
17603 #[doc = "0x08 - cfg_prechg_lead"]
17604 #[inline(always)]
17605 pub const fn cfg_prechg_lead(&self) -> &CfgPrechgLead {
17606 &self.cfg_prechg_lead
17607 }
17608 #[doc = "0x0c - cfg_clk_div_0"]
17609 #[inline(always)]
17610 pub const fn cfg_clk_div_0(&self) -> &CfgClkDiv0 {
17611 &self.cfg_clk_div_0
17612 }
17613 #[doc = "0x10 - cfg_clk_div_1"]
17614 #[inline(always)]
17615 pub const fn cfg_clk_div_1(&self) -> &CfgClkDiv1 {
17616 &self.cfg_clk_div_1
17617 }
17618 #[doc = "0x14 - cfg_manual_clk_0"]
17619 #[inline(always)]
17620 pub const fn cfg_manual_clk_0(&self) -> &CfgManualClk0 {
17621 &self.cfg_manual_clk_0
17622 }
17623 #[doc = "0x18 - cfg_manual_clk_1"]
17624 #[inline(always)]
17625 pub const fn cfg_manual_clk_1(&self) -> &CfgManualClk1 {
17626 &self.cfg_manual_clk_1
17627 }
17628 #[doc = "0x1c - cfg_iso"]
17629 #[inline(always)]
17630 pub const fn cfg_iso(&self) -> &CfgIso {
17631 &self.cfg_iso
17632 }
17633 #[doc = "0x30 - cfg_gadc_ctrl_0"]
17634 #[inline(always)]
17635 pub const fn cfg_gadc_ctrl_0(&self) -> &CfgGadcCtrl0 {
17636 &self.cfg_gadc_ctrl_0
17637 }
17638 #[doc = "0x34 - cfg_gadc_ctrl_1"]
17639 #[inline(always)]
17640 pub const fn cfg_gadc_ctrl_1(&self) -> &CfgGadcCtrl1 {
17641 &self.cfg_gadc_ctrl_1
17642 }
17643 #[doc = "0x38 - cfg_gadc_ctrl_2"]
17644 #[inline(always)]
17645 pub const fn cfg_gadc_ctrl_2(&self) -> &CfgGadcCtrl2 {
17646 &self.cfg_gadc_ctrl_2
17647 }
17648 #[doc = "0x3c - cfg_gadc_ctrl_3"]
17649 #[inline(always)]
17650 pub const fn cfg_gadc_ctrl_3(&self) -> &CfgGadcCtrl3 {
17651 &self.cfg_gadc_ctrl_3
17652 }
17653 #[doc = "0x40 - cfg_gadc_ctrl_4"]
17654 #[inline(always)]
17655 pub const fn cfg_gadc_ctrl_4(&self) -> &CfgGadcCtrl4 {
17656 &self.cfg_gadc_ctrl_4
17657 }
17658 #[doc = "0x44 - rpt_gadc_ctrl_0"]
17659 #[inline(always)]
17660 pub const fn rpt_gadc_ctrl_0(&self) -> &RptGadcCtrl0 {
17661 &self.rpt_gadc_ctrl_0
17662 }
17663 #[doc = "0x48 - cfg_gadc_ctrl_5"]
17664 #[inline(always)]
17665 pub const fn cfg_gadc_ctrl_5(&self) -> &CfgGadcCtrl5 {
17666 &self.cfg_gadc_ctrl_5
17667 }
17668 #[doc = "0x4c - cfg_gadc_ctrl_6"]
17669 #[inline(always)]
17670 pub const fn cfg_gadc_ctrl_6(&self) -> &CfgGadcCtrl6 {
17671 &self.cfg_gadc_ctrl_6
17672 }
17673 #[doc = "0x50 - rpt_gadc_ctrl_1"]
17674 #[inline(always)]
17675 pub const fn rpt_gadc_ctrl_1(&self) -> &RptGadcCtrl1 {
17676 &self.rpt_gadc_ctrl_1
17677 }
17678 #[doc = "0x54 - cfg_gadc_ctrl_7"]
17679 #[inline(always)]
17680 pub const fn cfg_gadc_ctrl_7(&self) -> &CfgGadcCtrl7 {
17681 &self.cfg_gadc_ctrl_7
17682 }
17683 #[doc = "0x58 - rpt_gadc_ctrl_2"]
17684 #[inline(always)]
17685 pub const fn rpt_gadc_ctrl_2(&self) -> &RptGadcCtrl2 {
17686 &self.rpt_gadc_ctrl_2
17687 }
17688 #[doc = "0x5c - cfg_gadc_data_0"]
17689 #[inline(always)]
17690 pub const fn cfg_gadc_data_0(&self) -> &CfgGadcData0 {
17691 &self.cfg_gadc_data_0
17692 }
17693 #[doc = "0x60 - cfg_gadc_data_1"]
17694 #[inline(always)]
17695 pub const fn cfg_gadc_data_1(&self) -> &CfgGadcData1 {
17696 &self.cfg_gadc_data_1
17697 }
17698 #[doc = "0x64 - rpt_gadc_data_0"]
17699 #[inline(always)]
17700 pub const fn rpt_gadc_data_0(&self) -> &RptGadcData0 {
17701 &self.rpt_gadc_data_0
17702 }
17703 #[doc = "0x68 - rpt_gadc_data_1"]
17704 #[inline(always)]
17705 pub const fn rpt_gadc_data_1(&self) -> &RptGadcData1 {
17706 &self.rpt_gadc_data_1
17707 }
17708 #[doc = "0x6c - rpt_gadc_data_2"]
17709 #[inline(always)]
17710 pub const fn rpt_gadc_data_2(&self) -> &RptGadcData2 {
17711 &self.rpt_gadc_data_2
17712 }
17713 #[doc = "0x70 - rpt_gadc_data_3"]
17714 #[inline(always)]
17715 pub const fn rpt_gadc_data_3(&self) -> &RptGadcData3 {
17716 &self.rpt_gadc_data_3
17717 }
17718 #[doc = "0x74 - cfg_gadc_data_3"]
17719 #[inline(always)]
17720 pub const fn cfg_gadc_data_3(&self) -> &CfgGadcData3 {
17721 &self.cfg_gadc_data_3
17722 }
17723 #[doc = "0x78 - cfg_gadc_data_4"]
17724 #[inline(always)]
17725 pub const fn cfg_gadc_data_4(&self) -> &CfgGadcData4 {
17726 &self.cfg_gadc_data_4
17727 }
17728 #[doc = "0x7c - rpt_gadc_data_4"]
17729 #[inline(always)]
17730 pub const fn rpt_gadc_data_4(&self) -> &RptGadcData4 {
17731 &self.rpt_gadc_data_4
17732 }
17733 #[doc = "0x80 - cfg_gadc_data_5"]
17734 #[inline(always)]
17735 pub const fn cfg_gadc_data_5(&self) -> &CfgGadcData5 {
17736 &self.cfg_gadc_data_5
17737 }
17738 #[doc = "0x84 - cfg_gadc_data_6"]
17739 #[inline(always)]
17740 pub const fn cfg_gadc_data_6(&self) -> &CfgGadcData6 {
17741 &self.cfg_gadc_data_6
17742 }
17743 #[doc = "0x88 - cfg_gadc_data_7"]
17744 #[inline(always)]
17745 pub const fn cfg_gadc_data_7(&self) -> &CfgGadcData7 {
17746 &self.cfg_gadc_data_7
17747 }
17748 #[doc = "0x8c - cfg_gadc_data_8"]
17749 #[inline(always)]
17750 pub const fn cfg_gadc_data_8(&self) -> &CfgGadcData8 {
17751 &self.cfg_gadc_data_8
17752 }
17753 #[doc = "0x90 - cfg_gadc_data_9"]
17754 #[inline(always)]
17755 pub const fn cfg_gadc_data_9(&self) -> &CfgGadcData9 {
17756 &self.cfg_gadc_data_9
17757 }
17758 #[doc = "0x94 - cfg_gadc_data_10"]
17759 #[inline(always)]
17760 pub const fn cfg_gadc_data_10(&self) -> &CfgGadcData10 {
17761 &self.cfg_gadc_data_10
17762 }
17763 #[doc = "0x98 - cfg_gadc_data_11"]
17764 #[inline(always)]
17765 pub const fn cfg_gadc_data_11(&self) -> &CfgGadcData11 {
17766 &self.cfg_gadc_data_11
17767 }
17768 #[doc = "0x9c - cfg_gadc_data_12"]
17769 #[inline(always)]
17770 pub const fn cfg_gadc_data_12(&self) -> &CfgGadcData12 {
17771 &self.cfg_gadc_data_12
17772 }
17773 #[doc = "0xa0 - cfg_gadc_data_13"]
17774 #[inline(always)]
17775 pub const fn cfg_gadc_data_13(&self) -> &CfgGadcData13 {
17776 &self.cfg_gadc_data_13
17777 }
17778 #[doc = "0xa4 - cfg_gadc_data_14"]
17779 #[inline(always)]
17780 pub const fn cfg_gadc_data_14(&self) -> &CfgGadcData14 {
17781 &self.cfg_gadc_data_14
17782 }
17783 #[doc = "0xa8 - cfg_gadc_data_15"]
17784 #[inline(always)]
17785 pub const fn cfg_gadc_data_15(&self) -> &CfgGadcData15 {
17786 &self.cfg_gadc_data_15
17787 }
17788 #[doc = "0xac - cfg_gadc_data_16"]
17789 #[inline(always)]
17790 pub const fn cfg_gadc_data_16(&self) -> &CfgGadcData16 {
17791 &self.cfg_gadc_data_16
17792 }
17793 #[doc = "0xb0 - cfg_gadc_data_17"]
17794 #[inline(always)]
17795 pub const fn cfg_gadc_data_17(&self) -> &CfgGadcData17 {
17796 &self.cfg_gadc_data_17
17797 }
17798 #[doc = "0xb4 - cfg_gadc_data_18"]
17799 #[inline(always)]
17800 pub const fn cfg_gadc_data_18(&self) -> &CfgGadcData18 {
17801 &self.cfg_gadc_data_18
17802 }
17803 #[doc = "0xb8 - cfg_gadc_data_19"]
17804 #[inline(always)]
17805 pub const fn cfg_gadc_data_19(&self) -> &CfgGadcData19 {
17806 &self.cfg_gadc_data_19
17807 }
17808 #[doc = "0xbc - cfg_gadc_data_20"]
17809 #[inline(always)]
17810 pub const fn cfg_gadc_data_20(&self) -> &CfgGadcData20 {
17811 &self.cfg_gadc_data_20
17812 }
17813 #[doc = "0xc0 - cfg_gadc_data_21"]
17814 #[inline(always)]
17815 pub const fn cfg_gadc_data_21(&self) -> &CfgGadcData21 {
17816 &self.cfg_gadc_data_21
17817 }
17818 #[doc = "0xc4 - cfg_gadc_data_22"]
17819 #[inline(always)]
17820 pub const fn cfg_gadc_data_22(&self) -> &CfgGadcData22 {
17821 &self.cfg_gadc_data_22
17822 }
17823 #[doc = "0xc8 - cfg_gadc_data_23"]
17824 #[inline(always)]
17825 pub const fn cfg_gadc_data_23(&self) -> &CfgGadcData23 {
17826 &self.cfg_gadc_data_23
17827 }
17828 #[doc = "0xcc - cfg_gadc_data_24"]
17829 #[inline(always)]
17830 pub const fn cfg_gadc_data_24(&self) -> &CfgGadcData24 {
17831 &self.cfg_gadc_data_24
17832 }
17833 #[doc = "0xd0 - cfg_gadc_data_25"]
17834 #[inline(always)]
17835 pub const fn cfg_gadc_data_25(&self) -> &CfgGadcData25 {
17836 &self.cfg_gadc_data_25
17837 }
17838 #[doc = "0xd4 - rpt_gadc_data_5"]
17839 #[inline(always)]
17840 pub const fn rpt_gadc_data_5(&self) -> &RptGadcData5 {
17841 &self.rpt_gadc_data_5
17842 }
17843 #[doc = "0xd8 - rpt_gadc_data_6"]
17844 #[inline(always)]
17845 pub const fn rpt_gadc_data_6(&self) -> &RptGadcData6 {
17846 &self.rpt_gadc_data_6
17847 }
17848 #[doc = "0xdc - rpt_gadc_data_7"]
17849 #[inline(always)]
17850 pub const fn rpt_gadc_data_7(&self) -> &RptGadcData7 {
17851 &self.rpt_gadc_data_7
17852 }
17853 #[doc = "0xe0 - rpt_gadc_data_8"]
17854 #[inline(always)]
17855 pub const fn rpt_gadc_data_8(&self) -> &RptGadcData8 {
17856 &self.rpt_gadc_data_8
17857 }
17858 #[doc = "0xe4 - rpt_gadc_data_9"]
17859 #[inline(always)]
17860 pub const fn rpt_gadc_data_9(&self) -> &RptGadcData9 {
17861 &self.rpt_gadc_data_9
17862 }
17863 #[doc = "0xe8 - rpt_gadc_data_10"]
17864 #[inline(always)]
17865 pub const fn rpt_gadc_data_10(&self) -> &RptGadcData10 {
17866 &self.rpt_gadc_data_10
17867 }
17868 #[doc = "0xec - rpt_gadc_data_11"]
17869 #[inline(always)]
17870 pub const fn rpt_gadc_data_11(&self) -> &RptGadcData11 {
17871 &self.rpt_gadc_data_11
17872 }
17873 #[doc = "0xf0 - rpt_gadc_data_12"]
17874 #[inline(always)]
17875 pub const fn rpt_gadc_data_12(&self) -> &RptGadcData12 {
17876 &self.rpt_gadc_data_12
17877 }
17878 #[doc = "0xf4 - rpt_gadc_data_13"]
17879 #[inline(always)]
17880 pub const fn rpt_gadc_data_13(&self) -> &RptGadcData13 {
17881 &self.rpt_gadc_data_13
17882 }
17883 #[doc = "0x100 - cfg_cmp_os_0"]
17884 #[inline(always)]
17885 pub const fn cfg_cmp_os_0(&self) -> &CfgCmpOs0 {
17886 &self.cfg_cmp_os_0
17887 }
17888 #[doc = "0x104 - cfg_cmp_os_1"]
17889 #[inline(always)]
17890 pub const fn cfg_cmp_os_1(&self) -> &CfgCmpOs1 {
17891 &self.cfg_cmp_os_1
17892 }
17893 #[doc = "0x108 - cfg_cmp_os_2"]
17894 #[inline(always)]
17895 pub const fn cfg_cmp_os_2(&self) -> &CfgCmpOs2 {
17896 &self.cfg_cmp_os_2
17897 }
17898 #[doc = "0x10c - cfg_cmp_os_3"]
17899 #[inline(always)]
17900 pub const fn cfg_cmp_os_3(&self) -> &CfgCmpOs3 {
17901 &self.cfg_cmp_os_3
17902 }
17903 #[doc = "0x110 - cfg_cmp_os_4"]
17904 #[inline(always)]
17905 pub const fn cfg_cmp_os_4(&self) -> &CfgCmpOs4 {
17906 &self.cfg_cmp_os_4
17907 }
17908 #[doc = "0x114 - cfg_cmp_os_5"]
17909 #[inline(always)]
17910 pub const fn cfg_cmp_os_5(&self) -> &CfgCmpOs5 {
17911 &self.cfg_cmp_os_5
17912 }
17913 #[doc = "0x118 - cfg_cmp_os_6"]
17914 #[inline(always)]
17915 pub const fn cfg_cmp_os_6(&self) -> &CfgCmpOs6 {
17916 &self.cfg_cmp_os_6
17917 }
17918 #[doc = "0x11c - cfg_cmp_os_7"]
17919 #[inline(always)]
17920 pub const fn cfg_cmp_os_7(&self) -> &CfgCmpOs7 {
17921 &self.cfg_cmp_os_7
17922 }
17923 #[doc = "0x120 - cfg_cmp_os_8"]
17924 #[inline(always)]
17925 pub const fn cfg_cmp_os_8(&self) -> &CfgCmpOs8 {
17926 &self.cfg_cmp_os_8
17927 }
17928 #[doc = "0x124 - cfg_cmp_os_9"]
17929 #[inline(always)]
17930 pub const fn cfg_cmp_os_9(&self) -> &CfgCmpOs9 {
17931 &self.cfg_cmp_os_9
17932 }
17933 #[doc = "0x128 - cfg_cmp_os_10"]
17934 #[inline(always)]
17935 pub const fn cfg_cmp_os_10(&self) -> &CfgCmpOs10 {
17936 &self.cfg_cmp_os_10
17937 }
17938 #[doc = "0x12c - rpt_cmp_os_0"]
17939 #[inline(always)]
17940 pub const fn rpt_cmp_os_0(&self) -> &RptCmpOs0 {
17941 &self.rpt_cmp_os_0
17942 }
17943 #[doc = "0x130 - cfg_cmp_os_11"]
17944 #[inline(always)]
17945 pub const fn cfg_cmp_os_11(&self) -> &CfgCmpOs11 {
17946 &self.cfg_cmp_os_11
17947 }
17948 #[doc = "0x134 - cfg_cmp_os_12"]
17949 #[inline(always)]
17950 pub const fn cfg_cmp_os_12(&self) -> &CfgCmpOs12 {
17951 &self.cfg_cmp_os_12
17952 }
17953 #[doc = "0x138 - rpt_cmp_os_2"]
17954 #[inline(always)]
17955 pub const fn rpt_cmp_os_2(&self) -> &RptCmpOs2 {
17956 &self.rpt_cmp_os_2
17957 }
17958 #[doc = "0x150 - cfg_cdac_fc0_0"]
17959 #[inline(always)]
17960 pub const fn cfg_cdac_fc0_0(&self) -> &CfgCdacFc0_0 {
17961 &self.cfg_cdac_fc0_0
17962 }
17963 #[doc = "0x154 - cfg_cdac_fc0_1"]
17964 #[inline(always)]
17965 pub const fn cfg_cdac_fc0_1(&self) -> &CfgCdacFc0_1 {
17966 &self.cfg_cdac_fc0_1
17967 }
17968 #[doc = "0x158 - cfg_cdac_fc0_2"]
17969 #[inline(always)]
17970 pub const fn cfg_cdac_fc0_2(&self) -> &CfgCdacFc0_2 {
17971 &self.cfg_cdac_fc0_2
17972 }
17973 #[doc = "0x15c - cfg_cdac_fc0_3"]
17974 #[inline(always)]
17975 pub const fn cfg_cdac_fc0_3(&self) -> &CfgCdacFc0_3 {
17976 &self.cfg_cdac_fc0_3
17977 }
17978 #[doc = "0x160 - cfg_cdac_fc0_4"]
17979 #[inline(always)]
17980 pub const fn cfg_cdac_fc0_4(&self) -> &CfgCdacFc0_4 {
17981 &self.cfg_cdac_fc0_4
17982 }
17983 #[doc = "0x164 - cfg_cdac_fc0_5"]
17984 #[inline(always)]
17985 pub const fn cfg_cdac_fc0_5(&self) -> &CfgCdacFc0_5 {
17986 &self.cfg_cdac_fc0_5
17987 }
17988 #[doc = "0x168 - rpt_cdac_fc0_0"]
17989 #[inline(always)]
17990 pub const fn rpt_cdac_fc0_0(&self) -> &RptCdacFc0_0 {
17991 &self.rpt_cdac_fc0_0
17992 }
17993 #[doc = "0x16c - cfg_cdac_fc0_6"]
17994 #[inline(always)]
17995 pub const fn cfg_cdac_fc0_6(&self) -> &CfgCdacFc0_6 {
17996 &self.cfg_cdac_fc0_6
17997 }
17998 #[doc = "0x170 - cfg_cdac_fc0_7"]
17999 #[inline(always)]
18000 pub const fn cfg_cdac_fc0_7(&self) -> &CfgCdacFc0_7 {
18001 &self.cfg_cdac_fc0_7
18002 }
18003 #[doc = "0x174 - cfg_cdac_fc0_8"]
18004 #[inline(always)]
18005 pub const fn cfg_cdac_fc0_8(&self) -> &CfgCdacFc0_8 {
18006 &self.cfg_cdac_fc0_8
18007 }
18008 #[doc = "0x178 - cfg_cdac_fc0_9"]
18009 #[inline(always)]
18010 pub const fn cfg_cdac_fc0_9(&self) -> &CfgCdacFc0_9 {
18011 &self.cfg_cdac_fc0_9
18012 }
18013 #[doc = "0x17c - cfg_cdac_fc0_10"]
18014 #[inline(always)]
18015 pub const fn cfg_cdac_fc0_10(&self) -> &CfgCdacFc0_10 {
18016 &self.cfg_cdac_fc0_10
18017 }
18018 #[doc = "0x180 - cfg_cdac_fc0_11"]
18019 #[inline(always)]
18020 pub const fn cfg_cdac_fc0_11(&self) -> &CfgCdacFc0_11 {
18021 &self.cfg_cdac_fc0_11
18022 }
18023 #[doc = "0x184 - cfg_cdac_fc0_12"]
18024 #[inline(always)]
18025 pub const fn cfg_cdac_fc0_12(&self) -> &CfgCdacFc0_12 {
18026 &self.cfg_cdac_fc0_12
18027 }
18028 #[doc = "0x188 - cfg_cdac_fc0_13"]
18029 #[inline(always)]
18030 pub const fn cfg_cdac_fc0_13(&self) -> &CfgCdacFc0_13 {
18031 &self.cfg_cdac_fc0_13
18032 }
18033 #[doc = "0x18c - cfg_cdac_fc0_14"]
18034 #[inline(always)]
18035 pub const fn cfg_cdac_fc0_14(&self) -> &CfgCdacFc0_14 {
18036 &self.cfg_cdac_fc0_14
18037 }
18038 #[doc = "0x190 - cfg_cdac_fc1_0"]
18039 #[inline(always)]
18040 pub const fn cfg_cdac_fc1_0(&self) -> &CfgCdacFc1_0 {
18041 &self.cfg_cdac_fc1_0
18042 }
18043 #[doc = "0x194 - cfg_cdac_fc1_1"]
18044 #[inline(always)]
18045 pub const fn cfg_cdac_fc1_1(&self) -> &CfgCdacFc1_1 {
18046 &self.cfg_cdac_fc1_1
18047 }
18048 #[doc = "0x198 - cfg_cdac_fc1_2"]
18049 #[inline(always)]
18050 pub const fn cfg_cdac_fc1_2(&self) -> &CfgCdacFc1_2 {
18051 &self.cfg_cdac_fc1_2
18052 }
18053 #[doc = "0x19c - cfg_cdac_fc1_3"]
18054 #[inline(always)]
18055 pub const fn cfg_cdac_fc1_3(&self) -> &CfgCdacFc1_3 {
18056 &self.cfg_cdac_fc1_3
18057 }
18058 #[doc = "0x1a0 - rpt_cdac_fc1_0"]
18059 #[inline(always)]
18060 pub const fn rpt_cdac_fc1_0(&self) -> &RptCdacFc1_0 {
18061 &self.rpt_cdac_fc1_0
18062 }
18063 #[doc = "0x1a4 - rpt_cdac_fc1_3"]
18064 #[inline(always)]
18065 pub const fn rpt_cdac_fc1_3(&self) -> &RptCdacFc1_3 {
18066 &self.rpt_cdac_fc1_3
18067 }
18068 #[doc = "0x1a8 - rpt_cdac_fc3_1"]
18069 #[inline(always)]
18070 pub const fn rpt_cdac_fc3_1(&self) -> &RptCdacFc3_1 {
18071 &self.rpt_cdac_fc3_1
18072 }
18073 #[doc = "0x1ac - rpt_cdac_fc3_2"]
18074 #[inline(always)]
18075 pub const fn rpt_cdac_fc3_2(&self) -> &RptCdacFc3_2 {
18076 &self.rpt_cdac_fc3_2
18077 }
18078 #[doc = "0x1b0 - rpt_cdac_fc3_3"]
18079 #[inline(always)]
18080 pub const fn rpt_cdac_fc3_3(&self) -> &RptCdacFc3_3 {
18081 &self.rpt_cdac_fc3_3
18082 }
18083 #[doc = "0x1b4 - rpt_cdac_fc3_4"]
18084 #[inline(always)]
18085 pub const fn rpt_cdac_fc3_4(&self) -> &RptCdacFc3_4 {
18086 &self.rpt_cdac_fc3_4
18087 }
18088 #[doc = "0x1b8 - rpt_cdac_fc3_5"]
18089 #[inline(always)]
18090 pub const fn rpt_cdac_fc3_5(&self) -> &RptCdacFc3_5 {
18091 &self.rpt_cdac_fc3_5
18092 }
18093 #[doc = "0x1bc - rpt_cdac_fc3_6"]
18094 #[inline(always)]
18095 pub const fn rpt_cdac_fc3_6(&self) -> &RptCdacFc3_6 {
18096 &self.rpt_cdac_fc3_6
18097 }
18098 #[doc = "0x1c0 - rpt_cdac_fc3_7"]
18099 #[inline(always)]
18100 pub const fn rpt_cdac_fc3_7(&self) -> &RptCdacFc3_7 {
18101 &self.rpt_cdac_fc3_7
18102 }
18103 #[doc = "0x1c4 - rpt_cdac_fc3_8"]
18104 #[inline(always)]
18105 pub const fn rpt_cdac_fc3_8(&self) -> &RptCdacFc3_8 {
18106 &self.rpt_cdac_fc3_8
18107 }
18108 #[doc = "0x1c8 - rpt_cdac_fc3_9"]
18109 #[inline(always)]
18110 pub const fn rpt_cdac_fc3_9(&self) -> &RptCdacFc3_9 {
18111 &self.rpt_cdac_fc3_9
18112 }
18113 #[doc = "0x1cc - rpt_cdac_fc3_10"]
18114 #[inline(always)]
18115 pub const fn rpt_cdac_fc3_10(&self) -> &RptCdacFc3_10 {
18116 &self.rpt_cdac_fc3_10
18117 }
18118 #[doc = "0x1d0 - rpt_cdac_fc3_11"]
18119 #[inline(always)]
18120 pub const fn rpt_cdac_fc3_11(&self) -> &RptCdacFc3_11 {
18121 &self.rpt_cdac_fc3_11
18122 }
18123 #[doc = "0x1d4 - rpt_cdac_fc3_12"]
18124 #[inline(always)]
18125 pub const fn rpt_cdac_fc3_12(&self) -> &RptCdacFc3_12 {
18126 &self.rpt_cdac_fc3_12
18127 }
18128 #[doc = "0x1d8 - rpt_cdac_fc3_13"]
18129 #[inline(always)]
18130 pub const fn rpt_cdac_fc3_13(&self) -> &RptCdacFc3_13 {
18131 &self.rpt_cdac_fc3_13
18132 }
18133 #[doc = "0x1dc - rpt_cdac_fc3_14"]
18134 #[inline(always)]
18135 pub const fn rpt_cdac_fc3_14(&self) -> &RptCdacFc3_14 {
18136 &self.rpt_cdac_fc3_14
18137 }
18138 #[doc = "0x1e0 - rpt_cdac_fc3_15"]
18139 #[inline(always)]
18140 pub const fn rpt_cdac_fc3_15(&self) -> &RptCdacFc3_15 {
18141 &self.rpt_cdac_fc3_15
18142 }
18143 #[doc = "0x1e4 - rpt_cdac_fc3_16"]
18144 #[inline(always)]
18145 pub const fn rpt_cdac_fc3_16(&self) -> &RptCdacFc3_16 {
18146 &self.rpt_cdac_fc3_16
18147 }
18148 #[doc = "0x1e8 - rpt_cdac_fc3_17"]
18149 #[inline(always)]
18150 pub const fn rpt_cdac_fc3_17(&self) -> &RptCdacFc3_17 {
18151 &self.rpt_cdac_fc3_17
18152 }
18153 #[doc = "0x1ec - rpt_cdac_fc3_18"]
18154 #[inline(always)]
18155 pub const fn rpt_cdac_fc3_18(&self) -> &RptCdacFc3_18 {
18156 &self.rpt_cdac_fc3_18
18157 }
18158 #[doc = "0x200 - cfg_dcoc_cal_0"]
18159 #[inline(always)]
18160 pub const fn cfg_dcoc_cal_0(&self) -> &CfgDcocCal0 {
18161 &self.cfg_dcoc_cal_0
18162 }
18163 #[doc = "0x204 - cfg_dcoc_cal_1"]
18164 #[inline(always)]
18165 pub const fn cfg_dcoc_cal_1(&self) -> &CfgDcocCal1 {
18166 &self.cfg_dcoc_cal_1
18167 }
18168 #[doc = "0x208 - cfg_dcoc_cal_2"]
18169 #[inline(always)]
18170 pub const fn cfg_dcoc_cal_2(&self) -> &CfgDcocCal2 {
18171 &self.cfg_dcoc_cal_2
18172 }
18173 #[doc = "0x20c - cfg_dcoc_cal_3"]
18174 #[inline(always)]
18175 pub const fn cfg_dcoc_cal_3(&self) -> &CfgDcocCal3 {
18176 &self.cfg_dcoc_cal_3
18177 }
18178 #[doc = "0x210 - cfg_dcoc_cal_4"]
18179 #[inline(always)]
18180 pub const fn cfg_dcoc_cal_4(&self) -> &CfgDcocCal4 {
18181 &self.cfg_dcoc_cal_4
18182 }
18183 #[doc = "0x214 - cfg_dcoc_cal_5"]
18184 #[inline(always)]
18185 pub const fn cfg_dcoc_cal_5(&self) -> &CfgDcocCal5 {
18186 &self.cfg_dcoc_cal_5
18187 }
18188 #[doc = "0x218 - cfg_dcoc_cal_6"]
18189 #[inline(always)]
18190 pub const fn cfg_dcoc_cal_6(&self) -> &CfgDcocCal6 {
18191 &self.cfg_dcoc_cal_6
18192 }
18193 #[doc = "0x21c - cfg_dcoc_cal_7"]
18194 #[inline(always)]
18195 pub const fn cfg_dcoc_cal_7(&self) -> &CfgDcocCal7 {
18196 &self.cfg_dcoc_cal_7
18197 }
18198 #[doc = "0x220 - cfg_dcoc_cal_8"]
18199 #[inline(always)]
18200 pub const fn cfg_dcoc_cal_8(&self) -> &CfgDcocCal8 {
18201 &self.cfg_dcoc_cal_8
18202 }
18203 #[doc = "0x224 - rpt_dcoc_cal_0"]
18204 #[inline(always)]
18205 pub const fn rpt_dcoc_cal_0(&self) -> &RptDcocCal0 {
18206 &self.rpt_dcoc_cal_0
18207 }
18208 #[doc = "0x228 - cfg_dcoc_cal_12"]
18209 #[inline(always)]
18210 pub const fn cfg_dcoc_cal_12(&self) -> &CfgDcocCal12 {
18211 &self.cfg_dcoc_cal_12
18212 }
18213 #[doc = "0x22c - cfg_dcoc_cal_13"]
18214 #[inline(always)]
18215 pub const fn cfg_dcoc_cal_13(&self) -> &CfgDcocCal13 {
18216 &self.cfg_dcoc_cal_13
18217 }
18218 #[doc = "0x230 - rpt_dcoc_cal_1"]
18219 #[inline(always)]
18220 pub const fn rpt_dcoc_cal_1(&self) -> &RptDcocCal1 {
18221 &self.rpt_dcoc_cal_1
18222 }
18223 #[doc = "0x240 - cfg_sar_spd_0"]
18224 #[inline(always)]
18225 pub const fn cfg_sar_spd_0(&self) -> &CfgSarSpd0 {
18226 &self.cfg_sar_spd_0
18227 }
18228 #[doc = "0x244 - cfg_sar_spd_1"]
18229 #[inline(always)]
18230 pub const fn cfg_sar_spd_1(&self) -> &CfgSarSpd1 {
18231 &self.cfg_sar_spd_1
18232 }
18233 #[doc = "0x248 - cfg_sar_spd_2"]
18234 #[inline(always)]
18235 pub const fn cfg_sar_spd_2(&self) -> &CfgSarSpd2 {
18236 &self.cfg_sar_spd_2
18237 }
18238 #[doc = "0x24c - cfg_sar_spd_3"]
18239 #[inline(always)]
18240 pub const fn cfg_sar_spd_3(&self) -> &CfgSarSpd3 {
18241 &self.cfg_sar_spd_3
18242 }
18243 #[doc = "0x250 - cfg_sar_spd_4"]
18244 #[inline(always)]
18245 pub const fn cfg_sar_spd_4(&self) -> &CfgSarSpd4 {
18246 &self.cfg_sar_spd_4
18247 }
18248 #[doc = "0x254 - rpt_sar_spd_0"]
18249 #[inline(always)]
18250 pub const fn rpt_sar_spd_0(&self) -> &RptSarSpd0 {
18251 &self.rpt_sar_spd_0
18252 }
18253 #[doc = "0x258 - rpt_sar_spd_1"]
18254 #[inline(always)]
18255 pub const fn rpt_sar_spd_1(&self) -> &RptSarSpd1 {
18256 &self.rpt_sar_spd_1
18257 }
18258 #[doc = "0x25c - cfg_sar_spd_6"]
18259 #[inline(always)]
18260 pub const fn cfg_sar_spd_6(&self) -> &CfgSarSpd6 {
18261 &self.cfg_sar_spd_6
18262 }
18263 #[doc = "0x260 - rpt_sar_spd_2"]
18264 #[inline(always)]
18265 pub const fn rpt_sar_spd_2(&self) -> &RptSarSpd2 {
18266 &self.rpt_sar_spd_2
18267 }
18268 #[doc = "0x280 - cfg_rc_cal_0"]
18269 #[inline(always)]
18270 pub const fn cfg_rc_cal_0(&self) -> &CfgRcCal0 {
18271 &self.cfg_rc_cal_0
18272 }
18273 #[doc = "0x284 - cfg_rc_cal_1"]
18274 #[inline(always)]
18275 pub const fn cfg_rc_cal_1(&self) -> &CfgRcCal1 {
18276 &self.cfg_rc_cal_1
18277 }
18278 #[doc = "0x288 - cfg_rc_cal_2"]
18279 #[inline(always)]
18280 pub const fn cfg_rc_cal_2(&self) -> &CfgRcCal2 {
18281 &self.cfg_rc_cal_2
18282 }
18283 #[doc = "0x28c - cfg_rc_cal_3"]
18284 #[inline(always)]
18285 pub const fn cfg_rc_cal_3(&self) -> &CfgRcCal3 {
18286 &self.cfg_rc_cal_3
18287 }
18288 #[doc = "0x290 - cfg_rc_cal_4"]
18289 #[inline(always)]
18290 pub const fn cfg_rc_cal_4(&self) -> &CfgRcCal4 {
18291 &self.cfg_rc_cal_4
18292 }
18293 #[doc = "0x294 - rpt_rc_cal_0"]
18294 #[inline(always)]
18295 pub const fn rpt_rc_cal_0(&self) -> &RptRcCal0 {
18296 &self.rpt_rc_cal_0
18297 }
18298 #[doc = "0x298 - rpt_rc_cal_1"]
18299 #[inline(always)]
18300 pub const fn rpt_rc_cal_1(&self) -> &RptRcCal1 {
18301 &self.rpt_rc_cal_1
18302 }
18303 #[doc = "0x29c - cfg_rc_cal_5"]
18304 #[inline(always)]
18305 pub const fn cfg_rc_cal_5(&self) -> &CfgRcCal5 {
18306 &self.cfg_rc_cal_5
18307 }
18308 #[doc = "0x2a0 - cfg_rc_cal_6"]
18309 #[inline(always)]
18310 pub const fn cfg_rc_cal_6(&self) -> &CfgRcCal6 {
18311 &self.cfg_rc_cal_6
18312 }
18313 #[doc = "0x2a4 - cfg_rc_cal_7"]
18314 #[inline(always)]
18315 pub const fn cfg_rc_cal_7(&self) -> &CfgRcCal7 {
18316 &self.cfg_rc_cal_7
18317 }
18318 #[doc = "0x2a8 - cfg_rc_cal_8"]
18319 #[inline(always)]
18320 pub const fn cfg_rc_cal_8(&self) -> &CfgRcCal8 {
18321 &self.cfg_rc_cal_8
18322 }
18323 #[doc = "0x2ac - rpt_rc_cal_2"]
18324 #[inline(always)]
18325 pub const fn rpt_rc_cal_2(&self) -> &RptRcCal2 {
18326 &self.rpt_rc_cal_2
18327 }
18328 #[doc = "0x2b0 - rpt_rc_cal_3"]
18329 #[inline(always)]
18330 pub const fn rpt_rc_cal_3(&self) -> &RptRcCal3 {
18331 &self.rpt_rc_cal_3
18332 }
18333 #[doc = "0x2c0 - cfg_amux_0"]
18334 #[inline(always)]
18335 pub const fn cfg_amux_0(&self) -> &CfgAmux0 {
18336 &self.cfg_amux_0
18337 }
18338 #[doc = "0x2c4 - cfg_amux_1"]
18339 #[inline(always)]
18340 pub const fn cfg_amux_1(&self) -> &CfgAmux1 {
18341 &self.cfg_amux_1
18342 }
18343 #[doc = "0x2c8 - cfg_amux_2"]
18344 #[inline(always)]
18345 pub const fn cfg_amux_2(&self) -> &CfgAmux2 {
18346 &self.cfg_amux_2
18347 }
18348 #[doc = "0x2cc - cfg_amux_3"]
18349 #[inline(always)]
18350 pub const fn cfg_amux_3(&self) -> &CfgAmux3 {
18351 &self.cfg_amux_3
18352 }
18353 #[doc = "0x2d0 - cfg_amux_4"]
18354 #[inline(always)]
18355 pub const fn cfg_amux_4(&self) -> &CfgAmux4 {
18356 &self.cfg_amux_4
18357 }
18358 #[doc = "0x2d4 - cfg_amux_5"]
18359 #[inline(always)]
18360 pub const fn cfg_amux_5(&self) -> &CfgAmux5 {
18361 &self.cfg_amux_5
18362 }
18363 #[doc = "0x2d8 - rpt_amux_0"]
18364 #[inline(always)]
18365 pub const fn rpt_amux_0(&self) -> &RptAmux0 {
18366 &self.rpt_amux_0
18367 }
18368 #[doc = "0x2f0 - cfg_tst_0"]
18369 #[inline(always)]
18370 pub const fn cfg_tst_0(&self) -> &CfgTst0 {
18371 &self.cfg_tst_0
18372 }
18373 #[doc = "0x2f4 - cfg_tst_1"]
18374 #[inline(always)]
18375 pub const fn cfg_tst_1(&self) -> &CfgTst1 {
18376 &self.cfg_tst_1
18377 }
18378 #[doc = "0x2f8 - cfg_cmp_0"]
18379 #[inline(always)]
18380 pub const fn cfg_cmp_0(&self) -> &CfgCmp0 {
18381 &self.cfg_cmp_0
18382 }
18383 #[doc = "0x2fc - cfg_cmp_1"]
18384 #[inline(always)]
18385 pub const fn cfg_cmp_1(&self) -> &CfgCmp1 {
18386 &self.cfg_cmp_1
18387 }
18388 #[doc = "0x300 - rpt_cmp_0"]
18389 #[inline(always)]
18390 pub const fn rpt_cmp_0(&self) -> &RptCmp0 {
18391 &self.rpt_cmp_0
18392 }
18393 #[doc = "0x304 - rpt_cmp_1"]
18394 #[inline(always)]
18395 pub const fn rpt_cmp_1(&self) -> &RptCmp1 {
18396 &self.rpt_cmp_1
18397 }
18398 }
18399 #[doc = "CFG_RSTN (rw) register accessor: cfg_rstn\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rstn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rstn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rstn`] module"]
18400 #[doc(alias = "CFG_RSTN")]
18401 pub type CfgRstn = crate::Reg<cfg_rstn::CfgRstnSpec>;
18402 #[doc = "cfg_rstn"]
18403 pub mod cfg_rstn {
18404 #[doc = "Register `CFG_RSTN` reader"]
18405 pub type R = crate::R<CfgRstnSpec>;
18406 #[doc = "Register `CFG_RSTN` writer"]
18407 pub type W = crate::W<CfgRstnSpec>;
18408 #[doc = "Field `cfg_rstn_tst` reader - "]
18409 pub type CfgRstnTstR = crate::BitReader;
18410 #[doc = "Field `cfg_rstn_tst` writer - "]
18411 pub type CfgRstnTstW<'a, REG> = crate::BitWriter<'a, REG>;
18412 #[doc = "Field `cfg_gadc_rstn_bc` reader - "]
18413 pub type CfgGadcRstnBcR = crate::BitReader;
18414 #[doc = "Field `cfg_gadc_rstn_bc` writer - "]
18415 pub type CfgGadcRstnBcW<'a, REG> = crate::BitWriter<'a, REG>;
18416 #[doc = "Field `cfg_gadc_rstn_fc` reader - "]
18417 pub type CfgGadcRstnFcR = crate::BitReader;
18418 #[doc = "Field `cfg_gadc_rstn_fc` writer - "]
18419 pub type CfgGadcRstnFcW<'a, REG> = crate::BitWriter<'a, REG>;
18420 #[doc = "Field `cfg_gadc_rstn_data` reader - "]
18421 pub type CfgGadcRstnDataR = crate::BitReader;
18422 #[doc = "Field `cfg_gadc_rstn_data` writer - "]
18423 pub type CfgGadcRstnDataW<'a, REG> = crate::BitWriter<'a, REG>;
18424 #[doc = "Field `cfg_gadc_rstn_ana` reader - "]
18425 pub type CfgGadcRstnAnaR = crate::BitReader;
18426 #[doc = "Field `cfg_gadc_rstn_ana` writer - "]
18427 pub type CfgGadcRstnAnaW<'a, REG> = crate::BitWriter<'a, REG>;
18428 impl R {
18429 #[doc = "Bit 0"]
18430 #[inline(always)]
18431 pub fn cfg_rstn_tst(&self) -> CfgRstnTstR {
18432 CfgRstnTstR::new((self.bits & 1) != 0)
18433 }
18434 #[doc = "Bit 4"]
18435 #[inline(always)]
18436 pub fn cfg_gadc_rstn_bc(&self) -> CfgGadcRstnBcR {
18437 CfgGadcRstnBcR::new(((self.bits >> 4) & 1) != 0)
18438 }
18439 #[doc = "Bit 8"]
18440 #[inline(always)]
18441 pub fn cfg_gadc_rstn_fc(&self) -> CfgGadcRstnFcR {
18442 CfgGadcRstnFcR::new(((self.bits >> 8) & 1) != 0)
18443 }
18444 #[doc = "Bit 12"]
18445 #[inline(always)]
18446 pub fn cfg_gadc_rstn_data(&self) -> CfgGadcRstnDataR {
18447 CfgGadcRstnDataR::new(((self.bits >> 12) & 1) != 0)
18448 }
18449 #[doc = "Bit 16"]
18450 #[inline(always)]
18451 pub fn cfg_gadc_rstn_ana(&self) -> CfgGadcRstnAnaR {
18452 CfgGadcRstnAnaR::new(((self.bits >> 16) & 1) != 0)
18453 }
18454 }
18455 impl W {
18456 #[doc = "Bit 0"]
18457 #[inline(always)]
18458 pub fn cfg_rstn_tst(&mut self) -> CfgRstnTstW<'_, CfgRstnSpec> {
18459 CfgRstnTstW::new(self, 0)
18460 }
18461 #[doc = "Bit 4"]
18462 #[inline(always)]
18463 pub fn cfg_gadc_rstn_bc(&mut self) -> CfgGadcRstnBcW<'_, CfgRstnSpec> {
18464 CfgGadcRstnBcW::new(self, 4)
18465 }
18466 #[doc = "Bit 8"]
18467 #[inline(always)]
18468 pub fn cfg_gadc_rstn_fc(&mut self) -> CfgGadcRstnFcW<'_, CfgRstnSpec> {
18469 CfgGadcRstnFcW::new(self, 8)
18470 }
18471 #[doc = "Bit 12"]
18472 #[inline(always)]
18473 pub fn cfg_gadc_rstn_data(&mut self) -> CfgGadcRstnDataW<'_, CfgRstnSpec> {
18474 CfgGadcRstnDataW::new(self, 12)
18475 }
18476 #[doc = "Bit 16"]
18477 #[inline(always)]
18478 pub fn cfg_gadc_rstn_ana(&mut self) -> CfgGadcRstnAnaW<'_, CfgRstnSpec> {
18479 CfgGadcRstnAnaW::new(self, 16)
18480 }
18481 }
18482 #[doc = "cfg_rstn\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rstn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rstn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18483 pub struct CfgRstnSpec;
18484 impl crate::RegisterSpec for CfgRstnSpec {
18485 type Ux = u32;
18486 }
18487 #[doc = "`read()` method returns [`cfg_rstn::R`](R) reader structure"]
18488 impl crate::Readable for CfgRstnSpec {}
18489 #[doc = "`write(|w| ..)` method takes [`cfg_rstn::W`](W) writer structure"]
18490 impl crate::Writable for CfgRstnSpec {
18491 type Safety = crate::Unsafe;
18492 }
18493 #[doc = "`reset()` method sets CFG_RSTN to value 0"]
18494 impl crate::Resettable for CfgRstnSpec {}
18495 }
18496 #[doc = "CFG_CLKEN (rw) register accessor: cfg_clken\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clken::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clken::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_clken`] module"]
18497 #[doc(alias = "CFG_CLKEN")]
18498 pub type CfgClken = crate::Reg<cfg_clken::CfgClkenSpec>;
18499 #[doc = "cfg_clken"]
18500 pub mod cfg_clken {
18501 #[doc = "Register `CFG_CLKEN` reader"]
18502 pub type R = crate::R<CfgClkenSpec>;
18503 #[doc = "Register `CFG_CLKEN` writer"]
18504 pub type W = crate::W<CfgClkenSpec>;
18505 #[doc = "Field `cfg_clken_tst` reader - "]
18506 pub type CfgClkenTstR = crate::BitReader;
18507 #[doc = "Field `cfg_clken_tst` writer - "]
18508 pub type CfgClkenTstW<'a, REG> = crate::BitWriter<'a, REG>;
18509 #[doc = "Field `cfg_gadc_clken_bc` reader - "]
18510 pub type CfgGadcClkenBcR = crate::BitReader;
18511 #[doc = "Field `cfg_gadc_clken_bc` writer - "]
18512 pub type CfgGadcClkenBcW<'a, REG> = crate::BitWriter<'a, REG>;
18513 #[doc = "Field `cfg_gadc_clken_fc` reader - "]
18514 pub type CfgGadcClkenFcR = crate::BitReader;
18515 #[doc = "Field `cfg_gadc_clken_fc` writer - "]
18516 pub type CfgGadcClkenFcW<'a, REG> = crate::BitWriter<'a, REG>;
18517 #[doc = "Field `cfg_gadc_clken_byp` reader - "]
18518 pub type CfgGadcClkenBypR = crate::BitReader;
18519 #[doc = "Field `cfg_gadc_clken_byp` writer - "]
18520 pub type CfgGadcClkenBypW<'a, REG> = crate::BitWriter<'a, REG>;
18521 #[doc = "Field `cfg_gadc_clken_prechg` reader - "]
18522 pub type CfgGadcClkenPrechgR = crate::BitReader;
18523 #[doc = "Field `cfg_gadc_clken_prechg` writer - "]
18524 pub type CfgGadcClkenPrechgW<'a, REG> = crate::BitWriter<'a, REG>;
18525 #[doc = "Field `cfg_gadc_clken_ctrl` reader - "]
18526 pub type CfgGadcClkenCtrlR = crate::BitReader;
18527 #[doc = "Field `cfg_gadc_clken_ctrl` writer - "]
18528 pub type CfgGadcClkenCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
18529 impl R {
18530 #[doc = "Bit 0"]
18531 #[inline(always)]
18532 pub fn cfg_clken_tst(&self) -> CfgClkenTstR {
18533 CfgClkenTstR::new((self.bits & 1) != 0)
18534 }
18535 #[doc = "Bit 4"]
18536 #[inline(always)]
18537 pub fn cfg_gadc_clken_bc(&self) -> CfgGadcClkenBcR {
18538 CfgGadcClkenBcR::new(((self.bits >> 4) & 1) != 0)
18539 }
18540 #[doc = "Bit 8"]
18541 #[inline(always)]
18542 pub fn cfg_gadc_clken_fc(&self) -> CfgGadcClkenFcR {
18543 CfgGadcClkenFcR::new(((self.bits >> 8) & 1) != 0)
18544 }
18545 #[doc = "Bit 12"]
18546 #[inline(always)]
18547 pub fn cfg_gadc_clken_byp(&self) -> CfgGadcClkenBypR {
18548 CfgGadcClkenBypR::new(((self.bits >> 12) & 1) != 0)
18549 }
18550 #[doc = "Bit 16"]
18551 #[inline(always)]
18552 pub fn cfg_gadc_clken_prechg(&self) -> CfgGadcClkenPrechgR {
18553 CfgGadcClkenPrechgR::new(((self.bits >> 16) & 1) != 0)
18554 }
18555 #[doc = "Bit 20"]
18556 #[inline(always)]
18557 pub fn cfg_gadc_clken_ctrl(&self) -> CfgGadcClkenCtrlR {
18558 CfgGadcClkenCtrlR::new(((self.bits >> 20) & 1) != 0)
18559 }
18560 }
18561 impl W {
18562 #[doc = "Bit 0"]
18563 #[inline(always)]
18564 pub fn cfg_clken_tst(&mut self) -> CfgClkenTstW<'_, CfgClkenSpec> {
18565 CfgClkenTstW::new(self, 0)
18566 }
18567 #[doc = "Bit 4"]
18568 #[inline(always)]
18569 pub fn cfg_gadc_clken_bc(&mut self) -> CfgGadcClkenBcW<'_, CfgClkenSpec> {
18570 CfgGadcClkenBcW::new(self, 4)
18571 }
18572 #[doc = "Bit 8"]
18573 #[inline(always)]
18574 pub fn cfg_gadc_clken_fc(&mut self) -> CfgGadcClkenFcW<'_, CfgClkenSpec> {
18575 CfgGadcClkenFcW::new(self, 8)
18576 }
18577 #[doc = "Bit 12"]
18578 #[inline(always)]
18579 pub fn cfg_gadc_clken_byp(&mut self) -> CfgGadcClkenBypW<'_, CfgClkenSpec> {
18580 CfgGadcClkenBypW::new(self, 12)
18581 }
18582 #[doc = "Bit 16"]
18583 #[inline(always)]
18584 pub fn cfg_gadc_clken_prechg(&mut self) -> CfgGadcClkenPrechgW<'_, CfgClkenSpec> {
18585 CfgGadcClkenPrechgW::new(self, 16)
18586 }
18587 #[doc = "Bit 20"]
18588 #[inline(always)]
18589 pub fn cfg_gadc_clken_ctrl(&mut self) -> CfgGadcClkenCtrlW<'_, CfgClkenSpec> {
18590 CfgGadcClkenCtrlW::new(self, 20)
18591 }
18592 }
18593 #[doc = "cfg_clken\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clken::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clken::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18594 pub struct CfgClkenSpec;
18595 impl crate::RegisterSpec for CfgClkenSpec {
18596 type Ux = u32;
18597 }
18598 #[doc = "`read()` method returns [`cfg_clken::R`](R) reader structure"]
18599 impl crate::Readable for CfgClkenSpec {}
18600 #[doc = "`write(|w| ..)` method takes [`cfg_clken::W`](W) writer structure"]
18601 impl crate::Writable for CfgClkenSpec {
18602 type Safety = crate::Unsafe;
18603 }
18604 #[doc = "`reset()` method sets CFG_CLKEN to value 0"]
18605 impl crate::Resettable for CfgClkenSpec {}
18606 }
18607 #[doc = "CFG_PRECHG_LEAD (rw) register accessor: cfg_prechg_lead\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_prechg_lead::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_prechg_lead::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_prechg_lead`] module"]
18608 #[doc(alias = "CFG_PRECHG_LEAD")]
18609 pub type CfgPrechgLead = crate::Reg<cfg_prechg_lead::CfgPrechgLeadSpec>;
18610 #[doc = "cfg_prechg_lead"]
18611 pub mod cfg_prechg_lead {
18612 #[doc = "Register `CFG_PRECHG_LEAD` reader"]
18613 pub type R = crate::R<CfgPrechgLeadSpec>;
18614 #[doc = "Register `CFG_PRECHG_LEAD` writer"]
18615 pub type W = crate::W<CfgPrechgLeadSpec>;
18616 impl core::fmt::Debug for R {
18617 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18618 write!(f, "{}", self.bits())
18619 }
18620 }
18621 impl W {}
18622 #[doc = "cfg_prechg_lead\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_prechg_lead::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_prechg_lead::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18623 pub struct CfgPrechgLeadSpec;
18624 impl crate::RegisterSpec for CfgPrechgLeadSpec {
18625 type Ux = u32;
18626 }
18627 #[doc = "`read()` method returns [`cfg_prechg_lead::R`](R) reader structure"]
18628 impl crate::Readable for CfgPrechgLeadSpec {}
18629 #[doc = "`write(|w| ..)` method takes [`cfg_prechg_lead::W`](W) writer structure"]
18630 impl crate::Writable for CfgPrechgLeadSpec {
18631 type Safety = crate::Unsafe;
18632 }
18633 #[doc = "`reset()` method sets CFG_PRECHG_LEAD to value 0"]
18634 impl crate::Resettable for CfgPrechgLeadSpec {}
18635 }
18636 #[doc = "CFG_CLK_DIV_0 (rw) register accessor: cfg_clk_div_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clk_div_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clk_div_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_clk_div_0`] module"]
18637 #[doc(alias = "CFG_CLK_DIV_0")]
18638 pub type CfgClkDiv0 = crate::Reg<cfg_clk_div_0::CfgClkDiv0Spec>;
18639 #[doc = "cfg_clk_div_0"]
18640 pub mod cfg_clk_div_0 {
18641 #[doc = "Register `CFG_CLK_DIV_0` reader"]
18642 pub type R = crate::R<CfgClkDiv0Spec>;
18643 #[doc = "Register `CFG_CLK_DIV_0` writer"]
18644 pub type W = crate::W<CfgClkDiv0Spec>;
18645 impl core::fmt::Debug for R {
18646 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18647 write!(f, "{}", self.bits())
18648 }
18649 }
18650 impl W {}
18651 #[doc = "cfg_clk_div_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clk_div_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clk_div_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18652 pub struct CfgClkDiv0Spec;
18653 impl crate::RegisterSpec for CfgClkDiv0Spec {
18654 type Ux = u32;
18655 }
18656 #[doc = "`read()` method returns [`cfg_clk_div_0::R`](R) reader structure"]
18657 impl crate::Readable for CfgClkDiv0Spec {}
18658 #[doc = "`write(|w| ..)` method takes [`cfg_clk_div_0::W`](W) writer structure"]
18659 impl crate::Writable for CfgClkDiv0Spec {
18660 type Safety = crate::Unsafe;
18661 }
18662 #[doc = "`reset()` method sets CFG_CLK_DIV_0 to value 0"]
18663 impl crate::Resettable for CfgClkDiv0Spec {}
18664 }
18665 #[doc = "CFG_CLK_DIV_1 (rw) register accessor: cfg_clk_div_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clk_div_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clk_div_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_clk_div_1`] module"]
18666 #[doc(alias = "CFG_CLK_DIV_1")]
18667 pub type CfgClkDiv1 = crate::Reg<cfg_clk_div_1::CfgClkDiv1Spec>;
18668 #[doc = "cfg_clk_div_1"]
18669 pub mod cfg_clk_div_1 {
18670 #[doc = "Register `CFG_CLK_DIV_1` reader"]
18671 pub type R = crate::R<CfgClkDiv1Spec>;
18672 #[doc = "Register `CFG_CLK_DIV_1` writer"]
18673 pub type W = crate::W<CfgClkDiv1Spec>;
18674 #[doc = "Field `ana_div_th` reader - "]
18675 pub type AnaDivThR = crate::FieldReader<u16>;
18676 #[doc = "Field `ana_div_th` writer - "]
18677 pub type AnaDivThW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
18678 #[doc = "Field `prechg_div_th` reader - "]
18679 pub type PrechgDivThR = crate::FieldReader<u16>;
18680 #[doc = "Field `prechg_div_th` writer - "]
18681 pub type PrechgDivThW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
18682 impl R {
18683 #[doc = "Bits 0:11"]
18684 #[inline(always)]
18685 pub fn ana_div_th(&self) -> AnaDivThR {
18686 AnaDivThR::new((self.bits & 0x0fff) as u16)
18687 }
18688 #[doc = "Bits 12:23"]
18689 #[inline(always)]
18690 pub fn prechg_div_th(&self) -> PrechgDivThR {
18691 PrechgDivThR::new(((self.bits >> 12) & 0x0fff) as u16)
18692 }
18693 }
18694 impl W {
18695 #[doc = "Bits 0:11"]
18696 #[inline(always)]
18697 pub fn ana_div_th(&mut self) -> AnaDivThW<'_, CfgClkDiv1Spec> {
18698 AnaDivThW::new(self, 0)
18699 }
18700 #[doc = "Bits 12:23"]
18701 #[inline(always)]
18702 pub fn prechg_div_th(&mut self) -> PrechgDivThW<'_, CfgClkDiv1Spec> {
18703 PrechgDivThW::new(self, 12)
18704 }
18705 }
18706 #[doc = "cfg_clk_div_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clk_div_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clk_div_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18707 pub struct CfgClkDiv1Spec;
18708 impl crate::RegisterSpec for CfgClkDiv1Spec {
18709 type Ux = u32;
18710 }
18711 #[doc = "`read()` method returns [`cfg_clk_div_1::R`](R) reader structure"]
18712 impl crate::Readable for CfgClkDiv1Spec {}
18713 #[doc = "`write(|w| ..)` method takes [`cfg_clk_div_1::W`](W) writer structure"]
18714 impl crate::Writable for CfgClkDiv1Spec {
18715 type Safety = crate::Unsafe;
18716 }
18717 #[doc = "`reset()` method sets CFG_CLK_DIV_1 to value 0"]
18718 impl crate::Resettable for CfgClkDiv1Spec {}
18719 }
18720 #[doc = "CFG_MANUAL_CLK_0 (rw) register accessor: cfg_manual_clk_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_manual_clk_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_manual_clk_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_manual_clk_0`] module"]
18721 #[doc(alias = "CFG_MANUAL_CLK_0")]
18722 pub type CfgManualClk0 = crate::Reg<cfg_manual_clk_0::CfgManualClk0Spec>;
18723 #[doc = "cfg_manual_clk_0"]
18724 pub mod cfg_manual_clk_0 {
18725 #[doc = "Register `CFG_MANUAL_CLK_0` reader"]
18726 pub type R = crate::R<CfgManualClk0Spec>;
18727 #[doc = "Register `CFG_MANUAL_CLK_0` writer"]
18728 pub type W = crate::W<CfgManualClk0Spec>;
18729 impl core::fmt::Debug for R {
18730 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18731 write!(f, "{}", self.bits())
18732 }
18733 }
18734 impl W {}
18735 #[doc = "cfg_manual_clk_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_manual_clk_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_manual_clk_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18736 pub struct CfgManualClk0Spec;
18737 impl crate::RegisterSpec for CfgManualClk0Spec {
18738 type Ux = u32;
18739 }
18740 #[doc = "`read()` method returns [`cfg_manual_clk_0::R`](R) reader structure"]
18741 impl crate::Readable for CfgManualClk0Spec {}
18742 #[doc = "`write(|w| ..)` method takes [`cfg_manual_clk_0::W`](W) writer structure"]
18743 impl crate::Writable for CfgManualClk0Spec {
18744 type Safety = crate::Unsafe;
18745 }
18746 #[doc = "`reset()` method sets CFG_MANUAL_CLK_0 to value 0"]
18747 impl crate::Resettable for CfgManualClk0Spec {}
18748 }
18749 #[doc = "CFG_MANUAL_CLK_1 (rw) register accessor: cfg_manual_clk_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_manual_clk_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_manual_clk_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_manual_clk_1`] module"]
18750 #[doc(alias = "CFG_MANUAL_CLK_1")]
18751 pub type CfgManualClk1 = crate::Reg<cfg_manual_clk_1::CfgManualClk1Spec>;
18752 #[doc = "cfg_manual_clk_1"]
18753 pub mod cfg_manual_clk_1 {
18754 #[doc = "Register `CFG_MANUAL_CLK_1` reader"]
18755 pub type R = crate::R<CfgManualClk1Spec>;
18756 #[doc = "Register `CFG_MANUAL_CLK_1` writer"]
18757 pub type W = crate::W<CfgManualClk1Spec>;
18758 impl core::fmt::Debug for R {
18759 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18760 write!(f, "{}", self.bits())
18761 }
18762 }
18763 impl W {}
18764 #[doc = "cfg_manual_clk_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_manual_clk_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_manual_clk_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18765 pub struct CfgManualClk1Spec;
18766 impl crate::RegisterSpec for CfgManualClk1Spec {
18767 type Ux = u32;
18768 }
18769 #[doc = "`read()` method returns [`cfg_manual_clk_1::R`](R) reader structure"]
18770 impl crate::Readable for CfgManualClk1Spec {}
18771 #[doc = "`write(|w| ..)` method takes [`cfg_manual_clk_1::W`](W) writer structure"]
18772 impl crate::Writable for CfgManualClk1Spec {
18773 type Safety = crate::Unsafe;
18774 }
18775 #[doc = "`reset()` method sets CFG_MANUAL_CLK_1 to value 0"]
18776 impl crate::Resettable for CfgManualClk1Spec {}
18777 }
18778 #[doc = "CFG_ISO (rw) register accessor: cfg_iso\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_iso::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_iso::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_iso`] module"]
18779 #[doc(alias = "CFG_ISO")]
18780 pub type CfgIso = crate::Reg<cfg_iso::CfgIsoSpec>;
18781 #[doc = "cfg_iso"]
18782 pub mod cfg_iso {
18783 #[doc = "Register `CFG_ISO` reader"]
18784 pub type R = crate::R<CfgIsoSpec>;
18785 #[doc = "Register `CFG_ISO` writer"]
18786 pub type W = crate::W<CfgIsoSpec>;
18787 impl core::fmt::Debug for R {
18788 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18789 write!(f, "{}", self.bits())
18790 }
18791 }
18792 impl W {}
18793 #[doc = "cfg_iso\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_iso::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_iso::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18794 pub struct CfgIsoSpec;
18795 impl crate::RegisterSpec for CfgIsoSpec {
18796 type Ux = u32;
18797 }
18798 #[doc = "`read()` method returns [`cfg_iso::R`](R) reader structure"]
18799 impl crate::Readable for CfgIsoSpec {}
18800 #[doc = "`write(|w| ..)` method takes [`cfg_iso::W`](W) writer structure"]
18801 impl crate::Writable for CfgIsoSpec {
18802 type Safety = crate::Unsafe;
18803 }
18804 #[doc = "`reset()` method sets CFG_ISO to value 0"]
18805 impl crate::Resettable for CfgIsoSpec {}
18806 }
18807 #[doc = "CFG_GADC_CTRL_0 (rw) register accessor: cfg_gadc_ctrl_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_0`] module"]
18808 #[doc(alias = "CFG_GADC_CTRL_0")]
18809 pub type CfgGadcCtrl0 = crate::Reg<cfg_gadc_ctrl_0::CfgGadcCtrl0Spec>;
18810 #[doc = "cfg_gadc_ctrl_0"]
18811 pub mod cfg_gadc_ctrl_0 {
18812 #[doc = "Register `CFG_GADC_CTRL_0` reader"]
18813 pub type R = crate::R<CfgGadcCtrl0Spec>;
18814 #[doc = "Register `CFG_GADC_CTRL_0` writer"]
18815 pub type W = crate::W<CfgGadcCtrl0Spec>;
18816 impl core::fmt::Debug for R {
18817 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18818 write!(f, "{}", self.bits())
18819 }
18820 }
18821 impl W {}
18822 #[doc = "cfg_gadc_ctrl_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18823 pub struct CfgGadcCtrl0Spec;
18824 impl crate::RegisterSpec for CfgGadcCtrl0Spec {
18825 type Ux = u32;
18826 }
18827 #[doc = "`read()` method returns [`cfg_gadc_ctrl_0::R`](R) reader structure"]
18828 impl crate::Readable for CfgGadcCtrl0Spec {}
18829 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_0::W`](W) writer structure"]
18830 impl crate::Writable for CfgGadcCtrl0Spec {
18831 type Safety = crate::Unsafe;
18832 }
18833 #[doc = "`reset()` method sets CFG_GADC_CTRL_0 to value 0"]
18834 impl crate::Resettable for CfgGadcCtrl0Spec {}
18835 }
18836 #[doc = "CFG_GADC_CTRL_1 (rw) register accessor: cfg_gadc_ctrl_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_1`] module"]
18837 #[doc(alias = "CFG_GADC_CTRL_1")]
18838 pub type CfgGadcCtrl1 = crate::Reg<cfg_gadc_ctrl_1::CfgGadcCtrl1Spec>;
18839 #[doc = "cfg_gadc_ctrl_1"]
18840 pub mod cfg_gadc_ctrl_1 {
18841 #[doc = "Register `CFG_GADC_CTRL_1` reader"]
18842 pub type R = crate::R<CfgGadcCtrl1Spec>;
18843 #[doc = "Register `CFG_GADC_CTRL_1` writer"]
18844 pub type W = crate::W<CfgGadcCtrl1Spec>;
18845 impl core::fmt::Debug for R {
18846 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18847 write!(f, "{}", self.bits())
18848 }
18849 }
18850 impl W {}
18851 #[doc = "cfg_gadc_ctrl_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18852 pub struct CfgGadcCtrl1Spec;
18853 impl crate::RegisterSpec for CfgGadcCtrl1Spec {
18854 type Ux = u32;
18855 }
18856 #[doc = "`read()` method returns [`cfg_gadc_ctrl_1::R`](R) reader structure"]
18857 impl crate::Readable for CfgGadcCtrl1Spec {}
18858 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_1::W`](W) writer structure"]
18859 impl crate::Writable for CfgGadcCtrl1Spec {
18860 type Safety = crate::Unsafe;
18861 }
18862 #[doc = "`reset()` method sets CFG_GADC_CTRL_1 to value 0"]
18863 impl crate::Resettable for CfgGadcCtrl1Spec {}
18864 }
18865 #[doc = "CFG_GADC_CTRL_2 (rw) register accessor: cfg_gadc_ctrl_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_2`] module"]
18866 #[doc(alias = "CFG_GADC_CTRL_2")]
18867 pub type CfgGadcCtrl2 = crate::Reg<cfg_gadc_ctrl_2::CfgGadcCtrl2Spec>;
18868 #[doc = "cfg_gadc_ctrl_2"]
18869 pub mod cfg_gadc_ctrl_2 {
18870 #[doc = "Register `CFG_GADC_CTRL_2` reader"]
18871 pub type R = crate::R<CfgGadcCtrl2Spec>;
18872 #[doc = "Register `CFG_GADC_CTRL_2` writer"]
18873 pub type W = crate::W<CfgGadcCtrl2Spec>;
18874 impl core::fmt::Debug for R {
18875 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18876 write!(f, "{}", self.bits())
18877 }
18878 }
18879 impl W {}
18880 #[doc = "cfg_gadc_ctrl_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18881 pub struct CfgGadcCtrl2Spec;
18882 impl crate::RegisterSpec for CfgGadcCtrl2Spec {
18883 type Ux = u32;
18884 }
18885 #[doc = "`read()` method returns [`cfg_gadc_ctrl_2::R`](R) reader structure"]
18886 impl crate::Readable for CfgGadcCtrl2Spec {}
18887 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_2::W`](W) writer structure"]
18888 impl crate::Writable for CfgGadcCtrl2Spec {
18889 type Safety = crate::Unsafe;
18890 }
18891 #[doc = "`reset()` method sets CFG_GADC_CTRL_2 to value 0"]
18892 impl crate::Resettable for CfgGadcCtrl2Spec {}
18893 }
18894 #[doc = "CFG_GADC_CTRL_3 (rw) register accessor: cfg_gadc_ctrl_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_3`] module"]
18895 #[doc(alias = "CFG_GADC_CTRL_3")]
18896 pub type CfgGadcCtrl3 = crate::Reg<cfg_gadc_ctrl_3::CfgGadcCtrl3Spec>;
18897 #[doc = "cfg_gadc_ctrl_3"]
18898 pub mod cfg_gadc_ctrl_3 {
18899 #[doc = "Register `CFG_GADC_CTRL_3` reader"]
18900 pub type R = crate::R<CfgGadcCtrl3Spec>;
18901 #[doc = "Register `CFG_GADC_CTRL_3` writer"]
18902 pub type W = crate::W<CfgGadcCtrl3Spec>;
18903 impl core::fmt::Debug for R {
18904 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18905 write!(f, "{}", self.bits())
18906 }
18907 }
18908 impl W {}
18909 #[doc = "cfg_gadc_ctrl_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18910 pub struct CfgGadcCtrl3Spec;
18911 impl crate::RegisterSpec for CfgGadcCtrl3Spec {
18912 type Ux = u32;
18913 }
18914 #[doc = "`read()` method returns [`cfg_gadc_ctrl_3::R`](R) reader structure"]
18915 impl crate::Readable for CfgGadcCtrl3Spec {}
18916 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_3::W`](W) writer structure"]
18917 impl crate::Writable for CfgGadcCtrl3Spec {
18918 type Safety = crate::Unsafe;
18919 }
18920 #[doc = "`reset()` method sets CFG_GADC_CTRL_3 to value 0"]
18921 impl crate::Resettable for CfgGadcCtrl3Spec {}
18922 }
18923 #[doc = "CFG_GADC_CTRL_4 (rw) register accessor: cfg_gadc_ctrl_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_4`] module"]
18924 #[doc(alias = "CFG_GADC_CTRL_4")]
18925 pub type CfgGadcCtrl4 = crate::Reg<cfg_gadc_ctrl_4::CfgGadcCtrl4Spec>;
18926 #[doc = "cfg_gadc_ctrl_4"]
18927 pub mod cfg_gadc_ctrl_4 {
18928 #[doc = "Register `CFG_GADC_CTRL_4` reader"]
18929 pub type R = crate::R<CfgGadcCtrl4Spec>;
18930 #[doc = "Register `CFG_GADC_CTRL_4` writer"]
18931 pub type W = crate::W<CfgGadcCtrl4Spec>;
18932 impl core::fmt::Debug for R {
18933 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18934 write!(f, "{}", self.bits())
18935 }
18936 }
18937 impl W {}
18938 #[doc = "cfg_gadc_ctrl_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18939 pub struct CfgGadcCtrl4Spec;
18940 impl crate::RegisterSpec for CfgGadcCtrl4Spec {
18941 type Ux = u32;
18942 }
18943 #[doc = "`read()` method returns [`cfg_gadc_ctrl_4::R`](R) reader structure"]
18944 impl crate::Readable for CfgGadcCtrl4Spec {}
18945 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_4::W`](W) writer structure"]
18946 impl crate::Writable for CfgGadcCtrl4Spec {
18947 type Safety = crate::Unsafe;
18948 }
18949 #[doc = "`reset()` method sets CFG_GADC_CTRL_4 to value 0"]
18950 impl crate::Resettable for CfgGadcCtrl4Spec {}
18951 }
18952 #[doc = "RPT_GADC_CTRL_0 (rw) register accessor: rpt_gadc_ctrl_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_ctrl_0`] module"]
18953 #[doc(alias = "RPT_GADC_CTRL_0")]
18954 pub type RptGadcCtrl0 = crate::Reg<rpt_gadc_ctrl_0::RptGadcCtrl0Spec>;
18955 #[doc = "rpt_gadc_ctrl_0"]
18956 pub mod rpt_gadc_ctrl_0 {
18957 #[doc = "Register `RPT_GADC_CTRL_0` reader"]
18958 pub type R = crate::R<RptGadcCtrl0Spec>;
18959 #[doc = "Register `RPT_GADC_CTRL_0` writer"]
18960 pub type W = crate::W<RptGadcCtrl0Spec>;
18961 impl core::fmt::Debug for R {
18962 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18963 write!(f, "{}", self.bits())
18964 }
18965 }
18966 impl W {}
18967 #[doc = "rpt_gadc_ctrl_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18968 pub struct RptGadcCtrl0Spec;
18969 impl crate::RegisterSpec for RptGadcCtrl0Spec {
18970 type Ux = u32;
18971 }
18972 #[doc = "`read()` method returns [`rpt_gadc_ctrl_0::R`](R) reader structure"]
18973 impl crate::Readable for RptGadcCtrl0Spec {}
18974 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_ctrl_0::W`](W) writer structure"]
18975 impl crate::Writable for RptGadcCtrl0Spec {
18976 type Safety = crate::Unsafe;
18977 }
18978 #[doc = "`reset()` method sets RPT_GADC_CTRL_0 to value 0"]
18979 impl crate::Resettable for RptGadcCtrl0Spec {}
18980 }
18981 #[doc = "CFG_GADC_CTRL_5 (rw) register accessor: cfg_gadc_ctrl_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_5`] module"]
18982 #[doc(alias = "CFG_GADC_CTRL_5")]
18983 pub type CfgGadcCtrl5 = crate::Reg<cfg_gadc_ctrl_5::CfgGadcCtrl5Spec>;
18984 #[doc = "cfg_gadc_ctrl_5"]
18985 pub mod cfg_gadc_ctrl_5 {
18986 #[doc = "Register `CFG_GADC_CTRL_5` reader"]
18987 pub type R = crate::R<CfgGadcCtrl5Spec>;
18988 #[doc = "Register `CFG_GADC_CTRL_5` writer"]
18989 pub type W = crate::W<CfgGadcCtrl5Spec>;
18990 impl core::fmt::Debug for R {
18991 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18992 write!(f, "{}", self.bits())
18993 }
18994 }
18995 impl W {}
18996 #[doc = "cfg_gadc_ctrl_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
18997 pub struct CfgGadcCtrl5Spec;
18998 impl crate::RegisterSpec for CfgGadcCtrl5Spec {
18999 type Ux = u32;
19000 }
19001 #[doc = "`read()` method returns [`cfg_gadc_ctrl_5::R`](R) reader structure"]
19002 impl crate::Readable for CfgGadcCtrl5Spec {}
19003 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_5::W`](W) writer structure"]
19004 impl crate::Writable for CfgGadcCtrl5Spec {
19005 type Safety = crate::Unsafe;
19006 }
19007 #[doc = "`reset()` method sets CFG_GADC_CTRL_5 to value 0"]
19008 impl crate::Resettable for CfgGadcCtrl5Spec {}
19009 }
19010 #[doc = "CFG_GADC_CTRL_6 (rw) register accessor: cfg_gadc_ctrl_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_6`] module"]
19011 #[doc(alias = "CFG_GADC_CTRL_6")]
19012 pub type CfgGadcCtrl6 = crate::Reg<cfg_gadc_ctrl_6::CfgGadcCtrl6Spec>;
19013 #[doc = "cfg_gadc_ctrl_6"]
19014 pub mod cfg_gadc_ctrl_6 {
19015 #[doc = "Register `CFG_GADC_CTRL_6` reader"]
19016 pub type R = crate::R<CfgGadcCtrl6Spec>;
19017 #[doc = "Register `CFG_GADC_CTRL_6` writer"]
19018 pub type W = crate::W<CfgGadcCtrl6Spec>;
19019 impl core::fmt::Debug for R {
19020 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19021 write!(f, "{}", self.bits())
19022 }
19023 }
19024 impl W {}
19025 #[doc = "cfg_gadc_ctrl_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19026 pub struct CfgGadcCtrl6Spec;
19027 impl crate::RegisterSpec for CfgGadcCtrl6Spec {
19028 type Ux = u32;
19029 }
19030 #[doc = "`read()` method returns [`cfg_gadc_ctrl_6::R`](R) reader structure"]
19031 impl crate::Readable for CfgGadcCtrl6Spec {}
19032 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_6::W`](W) writer structure"]
19033 impl crate::Writable for CfgGadcCtrl6Spec {
19034 type Safety = crate::Unsafe;
19035 }
19036 #[doc = "`reset()` method sets CFG_GADC_CTRL_6 to value 0"]
19037 impl crate::Resettable for CfgGadcCtrl6Spec {}
19038 }
19039 #[doc = "RPT_GADC_CTRL_1 (rw) register accessor: rpt_gadc_ctrl_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_ctrl_1`] module"]
19040 #[doc(alias = "RPT_GADC_CTRL_1")]
19041 pub type RptGadcCtrl1 = crate::Reg<rpt_gadc_ctrl_1::RptGadcCtrl1Spec>;
19042 #[doc = "rpt_gadc_ctrl_1"]
19043 pub mod rpt_gadc_ctrl_1 {
19044 #[doc = "Register `RPT_GADC_CTRL_1` reader"]
19045 pub type R = crate::R<RptGadcCtrl1Spec>;
19046 #[doc = "Register `RPT_GADC_CTRL_1` writer"]
19047 pub type W = crate::W<RptGadcCtrl1Spec>;
19048 impl core::fmt::Debug for R {
19049 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19050 write!(f, "{}", self.bits())
19051 }
19052 }
19053 impl W {}
19054 #[doc = "rpt_gadc_ctrl_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19055 pub struct RptGadcCtrl1Spec;
19056 impl crate::RegisterSpec for RptGadcCtrl1Spec {
19057 type Ux = u32;
19058 }
19059 #[doc = "`read()` method returns [`rpt_gadc_ctrl_1::R`](R) reader structure"]
19060 impl crate::Readable for RptGadcCtrl1Spec {}
19061 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_ctrl_1::W`](W) writer structure"]
19062 impl crate::Writable for RptGadcCtrl1Spec {
19063 type Safety = crate::Unsafe;
19064 }
19065 #[doc = "`reset()` method sets RPT_GADC_CTRL_1 to value 0"]
19066 impl crate::Resettable for RptGadcCtrl1Spec {}
19067 }
19068 #[doc = "CFG_GADC_CTRL_7 (rw) register accessor: cfg_gadc_ctrl_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_7`] module"]
19069 #[doc(alias = "CFG_GADC_CTRL_7")]
19070 pub type CfgGadcCtrl7 = crate::Reg<cfg_gadc_ctrl_7::CfgGadcCtrl7Spec>;
19071 #[doc = "cfg_gadc_ctrl_7"]
19072 pub mod cfg_gadc_ctrl_7 {
19073 #[doc = "Register `CFG_GADC_CTRL_7` reader"]
19074 pub type R = crate::R<CfgGadcCtrl7Spec>;
19075 #[doc = "Register `CFG_GADC_CTRL_7` writer"]
19076 pub type W = crate::W<CfgGadcCtrl7Spec>;
19077 impl core::fmt::Debug for R {
19078 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19079 write!(f, "{}", self.bits())
19080 }
19081 }
19082 impl W {}
19083 #[doc = "cfg_gadc_ctrl_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19084 pub struct CfgGadcCtrl7Spec;
19085 impl crate::RegisterSpec for CfgGadcCtrl7Spec {
19086 type Ux = u32;
19087 }
19088 #[doc = "`read()` method returns [`cfg_gadc_ctrl_7::R`](R) reader structure"]
19089 impl crate::Readable for CfgGadcCtrl7Spec {}
19090 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_7::W`](W) writer structure"]
19091 impl crate::Writable for CfgGadcCtrl7Spec {
19092 type Safety = crate::Unsafe;
19093 }
19094 #[doc = "`reset()` method sets CFG_GADC_CTRL_7 to value 0"]
19095 impl crate::Resettable for CfgGadcCtrl7Spec {}
19096 }
19097 #[doc = "RPT_GADC_CTRL_2 (rw) register accessor: rpt_gadc_ctrl_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_ctrl_2`] module"]
19098 #[doc(alias = "RPT_GADC_CTRL_2")]
19099 pub type RptGadcCtrl2 = crate::Reg<rpt_gadc_ctrl_2::RptGadcCtrl2Spec>;
19100 #[doc = "rpt_gadc_ctrl_2"]
19101 pub mod rpt_gadc_ctrl_2 {
19102 #[doc = "Register `RPT_GADC_CTRL_2` reader"]
19103 pub type R = crate::R<RptGadcCtrl2Spec>;
19104 #[doc = "Register `RPT_GADC_CTRL_2` writer"]
19105 pub type W = crate::W<RptGadcCtrl2Spec>;
19106 impl core::fmt::Debug for R {
19107 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19108 write!(f, "{}", self.bits())
19109 }
19110 }
19111 impl W {}
19112 #[doc = "rpt_gadc_ctrl_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19113 pub struct RptGadcCtrl2Spec;
19114 impl crate::RegisterSpec for RptGadcCtrl2Spec {
19115 type Ux = u32;
19116 }
19117 #[doc = "`read()` method returns [`rpt_gadc_ctrl_2::R`](R) reader structure"]
19118 impl crate::Readable for RptGadcCtrl2Spec {}
19119 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_ctrl_2::W`](W) writer structure"]
19120 impl crate::Writable for RptGadcCtrl2Spec {
19121 type Safety = crate::Unsafe;
19122 }
19123 #[doc = "`reset()` method sets RPT_GADC_CTRL_2 to value 0"]
19124 impl crate::Resettable for RptGadcCtrl2Spec {}
19125 }
19126 #[doc = "CFG_GADC_DATA_0 (rw) register accessor: cfg_gadc_data_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_0`] module"]
19127 #[doc(alias = "CFG_GADC_DATA_0")]
19128 pub type CfgGadcData0 = crate::Reg<cfg_gadc_data_0::CfgGadcData0Spec>;
19129 #[doc = "cfg_gadc_data_0"]
19130 pub mod cfg_gadc_data_0 {
19131 #[doc = "Register `CFG_GADC_DATA_0` reader"]
19132 pub type R = crate::R<CfgGadcData0Spec>;
19133 #[doc = "Register `CFG_GADC_DATA_0` writer"]
19134 pub type W = crate::W<CfgGadcData0Spec>;
19135 #[doc = "Field `data_num` reader - "]
19136 pub type DataNumR = crate::FieldReader<u16>;
19137 #[doc = "Field `data_num` writer - "]
19138 pub type DataNumW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
19139 #[doc = "Field `wait_num` reader - "]
19140 pub type WaitNumR = crate::FieldReader;
19141 #[doc = "Field `wait_num` writer - "]
19142 pub type WaitNumW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
19143 impl R {
19144 #[doc = "Bits 0:9"]
19145 #[inline(always)]
19146 pub fn data_num(&self) -> DataNumR {
19147 DataNumR::new((self.bits & 0x03ff) as u16)
19148 }
19149 #[doc = "Bits 12:14"]
19150 #[inline(always)]
19151 pub fn wait_num(&self) -> WaitNumR {
19152 WaitNumR::new(((self.bits >> 12) & 7) as u8)
19153 }
19154 }
19155 impl W {
19156 #[doc = "Bits 0:9"]
19157 #[inline(always)]
19158 pub fn data_num(&mut self) -> DataNumW<'_, CfgGadcData0Spec> {
19159 DataNumW::new(self, 0)
19160 }
19161 #[doc = "Bits 12:14"]
19162 #[inline(always)]
19163 pub fn wait_num(&mut self) -> WaitNumW<'_, CfgGadcData0Spec> {
19164 WaitNumW::new(self, 12)
19165 }
19166 }
19167 #[doc = "cfg_gadc_data_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19168 pub struct CfgGadcData0Spec;
19169 impl crate::RegisterSpec for CfgGadcData0Spec {
19170 type Ux = u32;
19171 }
19172 #[doc = "`read()` method returns [`cfg_gadc_data_0::R`](R) reader structure"]
19173 impl crate::Readable for CfgGadcData0Spec {}
19174 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_0::W`](W) writer structure"]
19175 impl crate::Writable for CfgGadcData0Spec {
19176 type Safety = crate::Unsafe;
19177 }
19178 #[doc = "`reset()` method sets CFG_GADC_DATA_0 to value 0"]
19179 impl crate::Resettable for CfgGadcData0Spec {}
19180 }
19181 #[doc = "CFG_GADC_DATA_1 (rw) register accessor: cfg_gadc_data_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_1`] module"]
19182 #[doc(alias = "CFG_GADC_DATA_1")]
19183 pub type CfgGadcData1 = crate::Reg<cfg_gadc_data_1::CfgGadcData1Spec>;
19184 #[doc = "cfg_gadc_data_1"]
19185 pub mod cfg_gadc_data_1 {
19186 #[doc = "Register `CFG_GADC_DATA_1` reader"]
19187 pub type R = crate::R<CfgGadcData1Spec>;
19188 #[doc = "Register `CFG_GADC_DATA_1` writer"]
19189 pub type W = crate::W<CfgGadcData1Spec>;
19190 #[doc = "Field `osr_len` reader - "]
19191 pub type OsrLenR = crate::FieldReader;
19192 #[doc = "Field `osr_len` writer - "]
19193 pub type OsrLenW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
19194 #[doc = "Field `osr_sel` reader - "]
19195 pub type OsrSelR = crate::FieldReader;
19196 #[doc = "Field `osr_sel` writer - "]
19197 pub type OsrSelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
19198 #[doc = "Field `osr_wait_num` reader - "]
19199 pub type OsrWaitNumR = crate::FieldReader;
19200 #[doc = "Field `osr_wait_num` writer - "]
19201 pub type OsrWaitNumW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
19202 impl R {
19203 #[doc = "Bits 0:2"]
19204 #[inline(always)]
19205 pub fn osr_len(&self) -> OsrLenR {
19206 OsrLenR::new((self.bits & 7) as u8)
19207 }
19208 #[doc = "Bits 4:6"]
19209 #[inline(always)]
19210 pub fn osr_sel(&self) -> OsrSelR {
19211 OsrSelR::new(((self.bits >> 4) & 7) as u8)
19212 }
19213 #[doc = "Bits 8:13"]
19214 #[inline(always)]
19215 pub fn osr_wait_num(&self) -> OsrWaitNumR {
19216 OsrWaitNumR::new(((self.bits >> 8) & 0x3f) as u8)
19217 }
19218 }
19219 impl W {
19220 #[doc = "Bits 0:2"]
19221 #[inline(always)]
19222 pub fn osr_len(&mut self) -> OsrLenW<'_, CfgGadcData1Spec> {
19223 OsrLenW::new(self, 0)
19224 }
19225 #[doc = "Bits 4:6"]
19226 #[inline(always)]
19227 pub fn osr_sel(&mut self) -> OsrSelW<'_, CfgGadcData1Spec> {
19228 OsrSelW::new(self, 4)
19229 }
19230 #[doc = "Bits 8:13"]
19231 #[inline(always)]
19232 pub fn osr_wait_num(&mut self) -> OsrWaitNumW<'_, CfgGadcData1Spec> {
19233 OsrWaitNumW::new(self, 8)
19234 }
19235 }
19236 #[doc = "cfg_gadc_data_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19237 pub struct CfgGadcData1Spec;
19238 impl crate::RegisterSpec for CfgGadcData1Spec {
19239 type Ux = u32;
19240 }
19241 #[doc = "`read()` method returns [`cfg_gadc_data_1::R`](R) reader structure"]
19242 impl crate::Readable for CfgGadcData1Spec {}
19243 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_1::W`](W) writer structure"]
19244 impl crate::Writable for CfgGadcData1Spec {
19245 type Safety = crate::Unsafe;
19246 }
19247 #[doc = "`reset()` method sets CFG_GADC_DATA_1 to value 0"]
19248 impl crate::Resettable for CfgGadcData1Spec {}
19249 }
19250 #[doc = "RPT_GADC_DATA_0 (rw) register accessor: rpt_gadc_data_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_0`] module"]
19251 #[doc(alias = "RPT_GADC_DATA_0")]
19252 pub type RptGadcData0 = crate::Reg<rpt_gadc_data_0::RptGadcData0Spec>;
19253 #[doc = "rpt_gadc_data_0"]
19254 pub mod rpt_gadc_data_0 {
19255 #[doc = "Register `RPT_GADC_DATA_0` reader"]
19256 pub type R = crate::R<RptGadcData0Spec>;
19257 #[doc = "Register `RPT_GADC_DATA_0` writer"]
19258 pub type W = crate::W<RptGadcData0Spec>;
19259 impl core::fmt::Debug for R {
19260 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19261 write!(f, "{}", self.bits())
19262 }
19263 }
19264 impl W {}
19265 #[doc = "rpt_gadc_data_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19266 pub struct RptGadcData0Spec;
19267 impl crate::RegisterSpec for RptGadcData0Spec {
19268 type Ux = u32;
19269 }
19270 #[doc = "`read()` method returns [`rpt_gadc_data_0::R`](R) reader structure"]
19271 impl crate::Readable for RptGadcData0Spec {}
19272 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_0::W`](W) writer structure"]
19273 impl crate::Writable for RptGadcData0Spec {
19274 type Safety = crate::Unsafe;
19275 }
19276 #[doc = "`reset()` method sets RPT_GADC_DATA_0 to value 0"]
19277 impl crate::Resettable for RptGadcData0Spec {}
19278 }
19279 #[doc = "RPT_GADC_DATA_1 (rw) register accessor: rpt_gadc_data_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_1`] module"]
19280 #[doc(alias = "RPT_GADC_DATA_1")]
19281 pub type RptGadcData1 = crate::Reg<rpt_gadc_data_1::RptGadcData1Spec>;
19282 #[doc = "rpt_gadc_data_1"]
19283 pub mod rpt_gadc_data_1 {
19284 #[doc = "Register `RPT_GADC_DATA_1` reader"]
19285 pub type R = crate::R<RptGadcData1Spec>;
19286 #[doc = "Register `RPT_GADC_DATA_1` writer"]
19287 pub type W = crate::W<RptGadcData1Spec>;
19288 impl core::fmt::Debug for R {
19289 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19290 write!(f, "{}", self.bits())
19291 }
19292 }
19293 impl W {}
19294 #[doc = "rpt_gadc_data_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19295 pub struct RptGadcData1Spec;
19296 impl crate::RegisterSpec for RptGadcData1Spec {
19297 type Ux = u32;
19298 }
19299 #[doc = "`read()` method returns [`rpt_gadc_data_1::R`](R) reader structure"]
19300 impl crate::Readable for RptGadcData1Spec {}
19301 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_1::W`](W) writer structure"]
19302 impl crate::Writable for RptGadcData1Spec {
19303 type Safety = crate::Unsafe;
19304 }
19305 #[doc = "`reset()` method sets RPT_GADC_DATA_1 to value 0"]
19306 impl crate::Resettable for RptGadcData1Spec {}
19307 }
19308 #[doc = "RPT_GADC_DATA_2 (rw) register accessor: rpt_gadc_data_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_2`] module"]
19309 #[doc(alias = "RPT_GADC_DATA_2")]
19310 pub type RptGadcData2 = crate::Reg<rpt_gadc_data_2::RptGadcData2Spec>;
19311 #[doc = "rpt_gadc_data_2"]
19312 pub mod rpt_gadc_data_2 {
19313 #[doc = "Register `RPT_GADC_DATA_2` reader"]
19314 pub type R = crate::R<RptGadcData2Spec>;
19315 #[doc = "Register `RPT_GADC_DATA_2` writer"]
19316 pub type W = crate::W<RptGadcData2Spec>;
19317 impl core::fmt::Debug for R {
19318 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19319 write!(f, "{}", self.bits())
19320 }
19321 }
19322 impl W {}
19323 #[doc = "rpt_gadc_data_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19324 pub struct RptGadcData2Spec;
19325 impl crate::RegisterSpec for RptGadcData2Spec {
19326 type Ux = u32;
19327 }
19328 #[doc = "`read()` method returns [`rpt_gadc_data_2::R`](R) reader structure"]
19329 impl crate::Readable for RptGadcData2Spec {}
19330 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_2::W`](W) writer structure"]
19331 impl crate::Writable for RptGadcData2Spec {
19332 type Safety = crate::Unsafe;
19333 }
19334 #[doc = "`reset()` method sets RPT_GADC_DATA_2 to value 0"]
19335 impl crate::Resettable for RptGadcData2Spec {}
19336 }
19337 #[doc = "RPT_GADC_DATA_3 (rw) register accessor: rpt_gadc_data_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_3`] module"]
19338 #[doc(alias = "RPT_GADC_DATA_3")]
19339 pub type RptGadcData3 = crate::Reg<rpt_gadc_data_3::RptGadcData3Spec>;
19340 #[doc = "rpt_gadc_data_3"]
19341 pub mod rpt_gadc_data_3 {
19342 #[doc = "Register `RPT_GADC_DATA_3` reader"]
19343 pub type R = crate::R<RptGadcData3Spec>;
19344 #[doc = "Register `RPT_GADC_DATA_3` writer"]
19345 pub type W = crate::W<RptGadcData3Spec>;
19346 impl core::fmt::Debug for R {
19347 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19348 write!(f, "{}", self.bits())
19349 }
19350 }
19351 impl W {}
19352 #[doc = "rpt_gadc_data_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19353 pub struct RptGadcData3Spec;
19354 impl crate::RegisterSpec for RptGadcData3Spec {
19355 type Ux = u32;
19356 }
19357 #[doc = "`read()` method returns [`rpt_gadc_data_3::R`](R) reader structure"]
19358 impl crate::Readable for RptGadcData3Spec {}
19359 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_3::W`](W) writer structure"]
19360 impl crate::Writable for RptGadcData3Spec {
19361 type Safety = crate::Unsafe;
19362 }
19363 #[doc = "`reset()` method sets RPT_GADC_DATA_3 to value 0"]
19364 impl crate::Resettable for RptGadcData3Spec {}
19365 }
19366 #[doc = "CFG_GADC_DATA_3 (rw) register accessor: cfg_gadc_data_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_3`] module"]
19367 #[doc(alias = "CFG_GADC_DATA_3")]
19368 pub type CfgGadcData3 = crate::Reg<cfg_gadc_data_3::CfgGadcData3Spec>;
19369 #[doc = "cfg_gadc_data_3"]
19370 pub mod cfg_gadc_data_3 {
19371 #[doc = "Register `CFG_GADC_DATA_3` reader"]
19372 pub type R = crate::R<CfgGadcData3Spec>;
19373 #[doc = "Register `CFG_GADC_DATA_3` writer"]
19374 pub type W = crate::W<CfgGadcData3Spec>;
19375 impl core::fmt::Debug for R {
19376 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19377 write!(f, "{}", self.bits())
19378 }
19379 }
19380 impl W {}
19381 #[doc = "cfg_gadc_data_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19382 pub struct CfgGadcData3Spec;
19383 impl crate::RegisterSpec for CfgGadcData3Spec {
19384 type Ux = u32;
19385 }
19386 #[doc = "`read()` method returns [`cfg_gadc_data_3::R`](R) reader structure"]
19387 impl crate::Readable for CfgGadcData3Spec {}
19388 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_3::W`](W) writer structure"]
19389 impl crate::Writable for CfgGadcData3Spec {
19390 type Safety = crate::Unsafe;
19391 }
19392 #[doc = "`reset()` method sets CFG_GADC_DATA_3 to value 0"]
19393 impl crate::Resettable for CfgGadcData3Spec {}
19394 }
19395 #[doc = "CFG_GADC_DATA_4 (rw) register accessor: cfg_gadc_data_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_4`] module"]
19396 #[doc(alias = "CFG_GADC_DATA_4")]
19397 pub type CfgGadcData4 = crate::Reg<cfg_gadc_data_4::CfgGadcData4Spec>;
19398 #[doc = "cfg_gadc_data_4"]
19399 pub mod cfg_gadc_data_4 {
19400 #[doc = "Register `CFG_GADC_DATA_4` reader"]
19401 pub type R = crate::R<CfgGadcData4Spec>;
19402 #[doc = "Register `CFG_GADC_DATA_4` writer"]
19403 pub type W = crate::W<CfgGadcData4Spec>;
19404 #[doc = "Field `adc_cdac_fc_scale_div` reader - "]
19405 pub type AdcCdacFcScaleDivR = crate::FieldReader<u16>;
19406 #[doc = "Field `adc_cdac_fc_scale_div` writer - "]
19407 pub type AdcCdacFcScaleDivW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
19408 #[doc = "Field `adc_cdac_scale_div_sel` reader - "]
19409 pub type AdcCdacScaleDivSelR = crate::BitReader;
19410 #[doc = "Field `adc_cdac_scale_div_sel` writer - "]
19411 pub type AdcCdacScaleDivSelW<'a, REG> = crate::BitWriter<'a, REG>;
19412 impl R {
19413 #[doc = "Bits 0:8"]
19414 #[inline(always)]
19415 pub fn adc_cdac_fc_scale_div(&self) -> AdcCdacFcScaleDivR {
19416 AdcCdacFcScaleDivR::new((self.bits & 0x01ff) as u16)
19417 }
19418 #[doc = "Bit 12"]
19419 #[inline(always)]
19420 pub fn adc_cdac_scale_div_sel(&self) -> AdcCdacScaleDivSelR {
19421 AdcCdacScaleDivSelR::new(((self.bits >> 12) & 1) != 0)
19422 }
19423 }
19424 impl W {
19425 #[doc = "Bits 0:8"]
19426 #[inline(always)]
19427 pub fn adc_cdac_fc_scale_div(&mut self) -> AdcCdacFcScaleDivW<'_, CfgGadcData4Spec> {
19428 AdcCdacFcScaleDivW::new(self, 0)
19429 }
19430 #[doc = "Bit 12"]
19431 #[inline(always)]
19432 pub fn adc_cdac_scale_div_sel(&mut self) -> AdcCdacScaleDivSelW<'_, CfgGadcData4Spec> {
19433 AdcCdacScaleDivSelW::new(self, 12)
19434 }
19435 }
19436 #[doc = "cfg_gadc_data_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19437 pub struct CfgGadcData4Spec;
19438 impl crate::RegisterSpec for CfgGadcData4Spec {
19439 type Ux = u32;
19440 }
19441 #[doc = "`read()` method returns [`cfg_gadc_data_4::R`](R) reader structure"]
19442 impl crate::Readable for CfgGadcData4Spec {}
19443 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_4::W`](W) writer structure"]
19444 impl crate::Writable for CfgGadcData4Spec {
19445 type Safety = crate::Unsafe;
19446 }
19447 #[doc = "`reset()` method sets CFG_GADC_DATA_4 to value 0"]
19448 impl crate::Resettable for CfgGadcData4Spec {}
19449 }
19450 #[doc = "RPT_GADC_DATA_4 (rw) register accessor: rpt_gadc_data_4\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_4`] module"]
19451 #[doc(alias = "RPT_GADC_DATA_4")]
19452 pub type RptGadcData4 = crate::Reg<rpt_gadc_data_4::RptGadcData4Spec>;
19453 #[doc = "rpt_gadc_data_4"]
19454 pub mod rpt_gadc_data_4 {
19455 #[doc = "Register `RPT_GADC_DATA_4` reader"]
19456 pub type R = crate::R<RptGadcData4Spec>;
19457 #[doc = "Register `RPT_GADC_DATA_4` writer"]
19458 pub type W = crate::W<RptGadcData4Spec>;
19459 impl core::fmt::Debug for R {
19460 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19461 write!(f, "{}", self.bits())
19462 }
19463 }
19464 impl W {}
19465 #[doc = "rpt_gadc_data_4\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19466 pub struct RptGadcData4Spec;
19467 impl crate::RegisterSpec for RptGadcData4Spec {
19468 type Ux = u32;
19469 }
19470 #[doc = "`read()` method returns [`rpt_gadc_data_4::R`](R) reader structure"]
19471 impl crate::Readable for RptGadcData4Spec {}
19472 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_4::W`](W) writer structure"]
19473 impl crate::Writable for RptGadcData4Spec {
19474 type Safety = crate::Unsafe;
19475 }
19476 #[doc = "`reset()` method sets RPT_GADC_DATA_4 to value 0"]
19477 impl crate::Resettable for RptGadcData4Spec {}
19478 }
19479 #[doc = "CFG_GADC_DATA_5 (rw) register accessor: cfg_gadc_data_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_5`] module"]
19480 #[doc(alias = "CFG_GADC_DATA_5")]
19481 pub type CfgGadcData5 = crate::Reg<cfg_gadc_data_5::CfgGadcData5Spec>;
19482 #[doc = "cfg_gadc_data_5"]
19483 pub mod cfg_gadc_data_5 {
19484 #[doc = "Register `CFG_GADC_DATA_5` reader"]
19485 pub type R = crate::R<CfgGadcData5Spec>;
19486 #[doc = "Register `CFG_GADC_DATA_5` writer"]
19487 pub type W = crate::W<CfgGadcData5Spec>;
19488 impl core::fmt::Debug for R {
19489 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19490 write!(f, "{}", self.bits())
19491 }
19492 }
19493 impl W {}
19494 #[doc = "cfg_gadc_data_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19495 pub struct CfgGadcData5Spec;
19496 impl crate::RegisterSpec for CfgGadcData5Spec {
19497 type Ux = u32;
19498 }
19499 #[doc = "`read()` method returns [`cfg_gadc_data_5::R`](R) reader structure"]
19500 impl crate::Readable for CfgGadcData5Spec {}
19501 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_5::W`](W) writer structure"]
19502 impl crate::Writable for CfgGadcData5Spec {
19503 type Safety = crate::Unsafe;
19504 }
19505 #[doc = "`reset()` method sets CFG_GADC_DATA_5 to value 0"]
19506 impl crate::Resettable for CfgGadcData5Spec {}
19507 }
19508 #[doc = "CFG_GADC_DATA_6 (rw) register accessor: cfg_gadc_data_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_6`] module"]
19509 #[doc(alias = "CFG_GADC_DATA_6")]
19510 pub type CfgGadcData6 = crate::Reg<cfg_gadc_data_6::CfgGadcData6Spec>;
19511 #[doc = "cfg_gadc_data_6"]
19512 pub mod cfg_gadc_data_6 {
19513 #[doc = "Register `CFG_GADC_DATA_6` reader"]
19514 pub type R = crate::R<CfgGadcData6Spec>;
19515 #[doc = "Register `CFG_GADC_DATA_6` writer"]
19516 pub type W = crate::W<CfgGadcData6Spec>;
19517 impl core::fmt::Debug for R {
19518 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19519 write!(f, "{}", self.bits())
19520 }
19521 }
19522 impl W {}
19523 #[doc = "cfg_gadc_data_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19524 pub struct CfgGadcData6Spec;
19525 impl crate::RegisterSpec for CfgGadcData6Spec {
19526 type Ux = u32;
19527 }
19528 #[doc = "`read()` method returns [`cfg_gadc_data_6::R`](R) reader structure"]
19529 impl crate::Readable for CfgGadcData6Spec {}
19530 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_6::W`](W) writer structure"]
19531 impl crate::Writable for CfgGadcData6Spec {
19532 type Safety = crate::Unsafe;
19533 }
19534 #[doc = "`reset()` method sets CFG_GADC_DATA_6 to value 0"]
19535 impl crate::Resettable for CfgGadcData6Spec {}
19536 }
19537 #[doc = "CFG_GADC_DATA_7 (rw) register accessor: cfg_gadc_data_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_7`] module"]
19538 #[doc(alias = "CFG_GADC_DATA_7")]
19539 pub type CfgGadcData7 = crate::Reg<cfg_gadc_data_7::CfgGadcData7Spec>;
19540 #[doc = "cfg_gadc_data_7"]
19541 pub mod cfg_gadc_data_7 {
19542 #[doc = "Register `CFG_GADC_DATA_7` reader"]
19543 pub type R = crate::R<CfgGadcData7Spec>;
19544 #[doc = "Register `CFG_GADC_DATA_7` writer"]
19545 pub type W = crate::W<CfgGadcData7Spec>;
19546 impl core::fmt::Debug for R {
19547 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19548 write!(f, "{}", self.bits())
19549 }
19550 }
19551 impl W {}
19552 #[doc = "cfg_gadc_data_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19553 pub struct CfgGadcData7Spec;
19554 impl crate::RegisterSpec for CfgGadcData7Spec {
19555 type Ux = u32;
19556 }
19557 #[doc = "`read()` method returns [`cfg_gadc_data_7::R`](R) reader structure"]
19558 impl crate::Readable for CfgGadcData7Spec {}
19559 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_7::W`](W) writer structure"]
19560 impl crate::Writable for CfgGadcData7Spec {
19561 type Safety = crate::Unsafe;
19562 }
19563 #[doc = "`reset()` method sets CFG_GADC_DATA_7 to value 0"]
19564 impl crate::Resettable for CfgGadcData7Spec {}
19565 }
19566 #[doc = "CFG_GADC_DATA_8 (rw) register accessor: cfg_gadc_data_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_8`] module"]
19567 #[doc(alias = "CFG_GADC_DATA_8")]
19568 pub type CfgGadcData8 = crate::Reg<cfg_gadc_data_8::CfgGadcData8Spec>;
19569 #[doc = "cfg_gadc_data_8"]
19570 pub mod cfg_gadc_data_8 {
19571 #[doc = "Register `CFG_GADC_DATA_8` reader"]
19572 pub type R = crate::R<CfgGadcData8Spec>;
19573 #[doc = "Register `CFG_GADC_DATA_8` writer"]
19574 pub type W = crate::W<CfgGadcData8Spec>;
19575 impl core::fmt::Debug for R {
19576 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19577 write!(f, "{}", self.bits())
19578 }
19579 }
19580 impl W {}
19581 #[doc = "cfg_gadc_data_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19582 pub struct CfgGadcData8Spec;
19583 impl crate::RegisterSpec for CfgGadcData8Spec {
19584 type Ux = u32;
19585 }
19586 #[doc = "`read()` method returns [`cfg_gadc_data_8::R`](R) reader structure"]
19587 impl crate::Readable for CfgGadcData8Spec {}
19588 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_8::W`](W) writer structure"]
19589 impl crate::Writable for CfgGadcData8Spec {
19590 type Safety = crate::Unsafe;
19591 }
19592 #[doc = "`reset()` method sets CFG_GADC_DATA_8 to value 0"]
19593 impl crate::Resettable for CfgGadcData8Spec {}
19594 }
19595 #[doc = "CFG_GADC_DATA_9 (rw) register accessor: cfg_gadc_data_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_9`] module"]
19596 #[doc(alias = "CFG_GADC_DATA_9")]
19597 pub type CfgGadcData9 = crate::Reg<cfg_gadc_data_9::CfgGadcData9Spec>;
19598 #[doc = "cfg_gadc_data_9"]
19599 pub mod cfg_gadc_data_9 {
19600 #[doc = "Register `CFG_GADC_DATA_9` reader"]
19601 pub type R = crate::R<CfgGadcData9Spec>;
19602 #[doc = "Register `CFG_GADC_DATA_9` writer"]
19603 pub type W = crate::W<CfgGadcData9Spec>;
19604 impl core::fmt::Debug for R {
19605 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19606 write!(f, "{}", self.bits())
19607 }
19608 }
19609 impl W {}
19610 #[doc = "cfg_gadc_data_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19611 pub struct CfgGadcData9Spec;
19612 impl crate::RegisterSpec for CfgGadcData9Spec {
19613 type Ux = u32;
19614 }
19615 #[doc = "`read()` method returns [`cfg_gadc_data_9::R`](R) reader structure"]
19616 impl crate::Readable for CfgGadcData9Spec {}
19617 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_9::W`](W) writer structure"]
19618 impl crate::Writable for CfgGadcData9Spec {
19619 type Safety = crate::Unsafe;
19620 }
19621 #[doc = "`reset()` method sets CFG_GADC_DATA_9 to value 0"]
19622 impl crate::Resettable for CfgGadcData9Spec {}
19623 }
19624 #[doc = "CFG_GADC_DATA_10 (rw) register accessor: cfg_gadc_data_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_10`] module"]
19625 #[doc(alias = "CFG_GADC_DATA_10")]
19626 pub type CfgGadcData10 = crate::Reg<cfg_gadc_data_10::CfgGadcData10Spec>;
19627 #[doc = "cfg_gadc_data_10"]
19628 pub mod cfg_gadc_data_10 {
19629 #[doc = "Register `CFG_GADC_DATA_10` reader"]
19630 pub type R = crate::R<CfgGadcData10Spec>;
19631 #[doc = "Register `CFG_GADC_DATA_10` writer"]
19632 pub type W = crate::W<CfgGadcData10Spec>;
19633 impl core::fmt::Debug for R {
19634 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19635 write!(f, "{}", self.bits())
19636 }
19637 }
19638 impl W {}
19639 #[doc = "cfg_gadc_data_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19640 pub struct CfgGadcData10Spec;
19641 impl crate::RegisterSpec for CfgGadcData10Spec {
19642 type Ux = u32;
19643 }
19644 #[doc = "`read()` method returns [`cfg_gadc_data_10::R`](R) reader structure"]
19645 impl crate::Readable for CfgGadcData10Spec {}
19646 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_10::W`](W) writer structure"]
19647 impl crate::Writable for CfgGadcData10Spec {
19648 type Safety = crate::Unsafe;
19649 }
19650 #[doc = "`reset()` method sets CFG_GADC_DATA_10 to value 0"]
19651 impl crate::Resettable for CfgGadcData10Spec {}
19652 }
19653 #[doc = "CFG_GADC_DATA_11 (rw) register accessor: cfg_gadc_data_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_11`] module"]
19654 #[doc(alias = "CFG_GADC_DATA_11")]
19655 pub type CfgGadcData11 = crate::Reg<cfg_gadc_data_11::CfgGadcData11Spec>;
19656 #[doc = "cfg_gadc_data_11"]
19657 pub mod cfg_gadc_data_11 {
19658 #[doc = "Register `CFG_GADC_DATA_11` reader"]
19659 pub type R = crate::R<CfgGadcData11Spec>;
19660 #[doc = "Register `CFG_GADC_DATA_11` writer"]
19661 pub type W = crate::W<CfgGadcData11Spec>;
19662 impl core::fmt::Debug for R {
19663 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19664 write!(f, "{}", self.bits())
19665 }
19666 }
19667 impl W {}
19668 #[doc = "cfg_gadc_data_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19669 pub struct CfgGadcData11Spec;
19670 impl crate::RegisterSpec for CfgGadcData11Spec {
19671 type Ux = u32;
19672 }
19673 #[doc = "`read()` method returns [`cfg_gadc_data_11::R`](R) reader structure"]
19674 impl crate::Readable for CfgGadcData11Spec {}
19675 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_11::W`](W) writer structure"]
19676 impl crate::Writable for CfgGadcData11Spec {
19677 type Safety = crate::Unsafe;
19678 }
19679 #[doc = "`reset()` method sets CFG_GADC_DATA_11 to value 0"]
19680 impl crate::Resettable for CfgGadcData11Spec {}
19681 }
19682 #[doc = "CFG_GADC_DATA_12 (rw) register accessor: cfg_gadc_data_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_12`] module"]
19683 #[doc(alias = "CFG_GADC_DATA_12")]
19684 pub type CfgGadcData12 = crate::Reg<cfg_gadc_data_12::CfgGadcData12Spec>;
19685 #[doc = "cfg_gadc_data_12"]
19686 pub mod cfg_gadc_data_12 {
19687 #[doc = "Register `CFG_GADC_DATA_12` reader"]
19688 pub type R = crate::R<CfgGadcData12Spec>;
19689 #[doc = "Register `CFG_GADC_DATA_12` writer"]
19690 pub type W = crate::W<CfgGadcData12Spec>;
19691 impl core::fmt::Debug for R {
19692 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19693 write!(f, "{}", self.bits())
19694 }
19695 }
19696 impl W {}
19697 #[doc = "cfg_gadc_data_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19698 pub struct CfgGadcData12Spec;
19699 impl crate::RegisterSpec for CfgGadcData12Spec {
19700 type Ux = u32;
19701 }
19702 #[doc = "`read()` method returns [`cfg_gadc_data_12::R`](R) reader structure"]
19703 impl crate::Readable for CfgGadcData12Spec {}
19704 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_12::W`](W) writer structure"]
19705 impl crate::Writable for CfgGadcData12Spec {
19706 type Safety = crate::Unsafe;
19707 }
19708 #[doc = "`reset()` method sets CFG_GADC_DATA_12 to value 0"]
19709 impl crate::Resettable for CfgGadcData12Spec {}
19710 }
19711 #[doc = "CFG_GADC_DATA_13 (rw) register accessor: cfg_gadc_data_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_13`] module"]
19712 #[doc(alias = "CFG_GADC_DATA_13")]
19713 pub type CfgGadcData13 = crate::Reg<cfg_gadc_data_13::CfgGadcData13Spec>;
19714 #[doc = "cfg_gadc_data_13"]
19715 pub mod cfg_gadc_data_13 {
19716 #[doc = "Register `CFG_GADC_DATA_13` reader"]
19717 pub type R = crate::R<CfgGadcData13Spec>;
19718 #[doc = "Register `CFG_GADC_DATA_13` writer"]
19719 pub type W = crate::W<CfgGadcData13Spec>;
19720 impl core::fmt::Debug for R {
19721 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19722 write!(f, "{}", self.bits())
19723 }
19724 }
19725 impl W {}
19726 #[doc = "cfg_gadc_data_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19727 pub struct CfgGadcData13Spec;
19728 impl crate::RegisterSpec for CfgGadcData13Spec {
19729 type Ux = u32;
19730 }
19731 #[doc = "`read()` method returns [`cfg_gadc_data_13::R`](R) reader structure"]
19732 impl crate::Readable for CfgGadcData13Spec {}
19733 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_13::W`](W) writer structure"]
19734 impl crate::Writable for CfgGadcData13Spec {
19735 type Safety = crate::Unsafe;
19736 }
19737 #[doc = "`reset()` method sets CFG_GADC_DATA_13 to value 0"]
19738 impl crate::Resettable for CfgGadcData13Spec {}
19739 }
19740 #[doc = "CFG_GADC_DATA_14 (rw) register accessor: cfg_gadc_data_14\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_14`] module"]
19741 #[doc(alias = "CFG_GADC_DATA_14")]
19742 pub type CfgGadcData14 = crate::Reg<cfg_gadc_data_14::CfgGadcData14Spec>;
19743 #[doc = "cfg_gadc_data_14"]
19744 pub mod cfg_gadc_data_14 {
19745 #[doc = "Register `CFG_GADC_DATA_14` reader"]
19746 pub type R = crate::R<CfgGadcData14Spec>;
19747 #[doc = "Register `CFG_GADC_DATA_14` writer"]
19748 pub type W = crate::W<CfgGadcData14Spec>;
19749 impl core::fmt::Debug for R {
19750 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19751 write!(f, "{}", self.bits())
19752 }
19753 }
19754 impl W {}
19755 #[doc = "cfg_gadc_data_14\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19756 pub struct CfgGadcData14Spec;
19757 impl crate::RegisterSpec for CfgGadcData14Spec {
19758 type Ux = u32;
19759 }
19760 #[doc = "`read()` method returns [`cfg_gadc_data_14::R`](R) reader structure"]
19761 impl crate::Readable for CfgGadcData14Spec {}
19762 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_14::W`](W) writer structure"]
19763 impl crate::Writable for CfgGadcData14Spec {
19764 type Safety = crate::Unsafe;
19765 }
19766 #[doc = "`reset()` method sets CFG_GADC_DATA_14 to value 0"]
19767 impl crate::Resettable for CfgGadcData14Spec {}
19768 }
19769 #[doc = "CFG_GADC_DATA_15 (rw) register accessor: cfg_gadc_data_15\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_15`] module"]
19770 #[doc(alias = "CFG_GADC_DATA_15")]
19771 pub type CfgGadcData15 = crate::Reg<cfg_gadc_data_15::CfgGadcData15Spec>;
19772 #[doc = "cfg_gadc_data_15"]
19773 pub mod cfg_gadc_data_15 {
19774 #[doc = "Register `CFG_GADC_DATA_15` reader"]
19775 pub type R = crate::R<CfgGadcData15Spec>;
19776 #[doc = "Register `CFG_GADC_DATA_15` writer"]
19777 pub type W = crate::W<CfgGadcData15Spec>;
19778 impl core::fmt::Debug for R {
19779 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19780 write!(f, "{}", self.bits())
19781 }
19782 }
19783 impl W {}
19784 #[doc = "cfg_gadc_data_15\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19785 pub struct CfgGadcData15Spec;
19786 impl crate::RegisterSpec for CfgGadcData15Spec {
19787 type Ux = u32;
19788 }
19789 #[doc = "`read()` method returns [`cfg_gadc_data_15::R`](R) reader structure"]
19790 impl crate::Readable for CfgGadcData15Spec {}
19791 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_15::W`](W) writer structure"]
19792 impl crate::Writable for CfgGadcData15Spec {
19793 type Safety = crate::Unsafe;
19794 }
19795 #[doc = "`reset()` method sets CFG_GADC_DATA_15 to value 0"]
19796 impl crate::Resettable for CfgGadcData15Spec {}
19797 }
19798 #[doc = "CFG_GADC_DATA_16 (rw) register accessor: cfg_gadc_data_16\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_16`] module"]
19799 #[doc(alias = "CFG_GADC_DATA_16")]
19800 pub type CfgGadcData16 = crate::Reg<cfg_gadc_data_16::CfgGadcData16Spec>;
19801 #[doc = "cfg_gadc_data_16"]
19802 pub mod cfg_gadc_data_16 {
19803 #[doc = "Register `CFG_GADC_DATA_16` reader"]
19804 pub type R = crate::R<CfgGadcData16Spec>;
19805 #[doc = "Register `CFG_GADC_DATA_16` writer"]
19806 pub type W = crate::W<CfgGadcData16Spec>;
19807 impl core::fmt::Debug for R {
19808 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19809 write!(f, "{}", self.bits())
19810 }
19811 }
19812 impl W {}
19813 #[doc = "cfg_gadc_data_16\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19814 pub struct CfgGadcData16Spec;
19815 impl crate::RegisterSpec for CfgGadcData16Spec {
19816 type Ux = u32;
19817 }
19818 #[doc = "`read()` method returns [`cfg_gadc_data_16::R`](R) reader structure"]
19819 impl crate::Readable for CfgGadcData16Spec {}
19820 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_16::W`](W) writer structure"]
19821 impl crate::Writable for CfgGadcData16Spec {
19822 type Safety = crate::Unsafe;
19823 }
19824 #[doc = "`reset()` method sets CFG_GADC_DATA_16 to value 0"]
19825 impl crate::Resettable for CfgGadcData16Spec {}
19826 }
19827 #[doc = "CFG_GADC_DATA_17 (rw) register accessor: cfg_gadc_data_17\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_17`] module"]
19828 #[doc(alias = "CFG_GADC_DATA_17")]
19829 pub type CfgGadcData17 = crate::Reg<cfg_gadc_data_17::CfgGadcData17Spec>;
19830 #[doc = "cfg_gadc_data_17"]
19831 pub mod cfg_gadc_data_17 {
19832 #[doc = "Register `CFG_GADC_DATA_17` reader"]
19833 pub type R = crate::R<CfgGadcData17Spec>;
19834 #[doc = "Register `CFG_GADC_DATA_17` writer"]
19835 pub type W = crate::W<CfgGadcData17Spec>;
19836 impl core::fmt::Debug for R {
19837 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19838 write!(f, "{}", self.bits())
19839 }
19840 }
19841 impl W {}
19842 #[doc = "cfg_gadc_data_17\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19843 pub struct CfgGadcData17Spec;
19844 impl crate::RegisterSpec for CfgGadcData17Spec {
19845 type Ux = u32;
19846 }
19847 #[doc = "`read()` method returns [`cfg_gadc_data_17::R`](R) reader structure"]
19848 impl crate::Readable for CfgGadcData17Spec {}
19849 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_17::W`](W) writer structure"]
19850 impl crate::Writable for CfgGadcData17Spec {
19851 type Safety = crate::Unsafe;
19852 }
19853 #[doc = "`reset()` method sets CFG_GADC_DATA_17 to value 0"]
19854 impl crate::Resettable for CfgGadcData17Spec {}
19855 }
19856 #[doc = "CFG_GADC_DATA_18 (rw) register accessor: cfg_gadc_data_18\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_18`] module"]
19857 #[doc(alias = "CFG_GADC_DATA_18")]
19858 pub type CfgGadcData18 = crate::Reg<cfg_gadc_data_18::CfgGadcData18Spec>;
19859 #[doc = "cfg_gadc_data_18"]
19860 pub mod cfg_gadc_data_18 {
19861 #[doc = "Register `CFG_GADC_DATA_18` reader"]
19862 pub type R = crate::R<CfgGadcData18Spec>;
19863 #[doc = "Register `CFG_GADC_DATA_18` writer"]
19864 pub type W = crate::W<CfgGadcData18Spec>;
19865 impl core::fmt::Debug for R {
19866 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19867 write!(f, "{}", self.bits())
19868 }
19869 }
19870 impl W {}
19871 #[doc = "cfg_gadc_data_18\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19872 pub struct CfgGadcData18Spec;
19873 impl crate::RegisterSpec for CfgGadcData18Spec {
19874 type Ux = u32;
19875 }
19876 #[doc = "`read()` method returns [`cfg_gadc_data_18::R`](R) reader structure"]
19877 impl crate::Readable for CfgGadcData18Spec {}
19878 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_18::W`](W) writer structure"]
19879 impl crate::Writable for CfgGadcData18Spec {
19880 type Safety = crate::Unsafe;
19881 }
19882 #[doc = "`reset()` method sets CFG_GADC_DATA_18 to value 0"]
19883 impl crate::Resettable for CfgGadcData18Spec {}
19884 }
19885 #[doc = "CFG_GADC_DATA_19 (rw) register accessor: cfg_gadc_data_19\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_19`] module"]
19886 #[doc(alias = "CFG_GADC_DATA_19")]
19887 pub type CfgGadcData19 = crate::Reg<cfg_gadc_data_19::CfgGadcData19Spec>;
19888 #[doc = "cfg_gadc_data_19"]
19889 pub mod cfg_gadc_data_19 {
19890 #[doc = "Register `CFG_GADC_DATA_19` reader"]
19891 pub type R = crate::R<CfgGadcData19Spec>;
19892 #[doc = "Register `CFG_GADC_DATA_19` writer"]
19893 pub type W = crate::W<CfgGadcData19Spec>;
19894 impl core::fmt::Debug for R {
19895 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19896 write!(f, "{}", self.bits())
19897 }
19898 }
19899 impl W {}
19900 #[doc = "cfg_gadc_data_19\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19901 pub struct CfgGadcData19Spec;
19902 impl crate::RegisterSpec for CfgGadcData19Spec {
19903 type Ux = u32;
19904 }
19905 #[doc = "`read()` method returns [`cfg_gadc_data_19::R`](R) reader structure"]
19906 impl crate::Readable for CfgGadcData19Spec {}
19907 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_19::W`](W) writer structure"]
19908 impl crate::Writable for CfgGadcData19Spec {
19909 type Safety = crate::Unsafe;
19910 }
19911 #[doc = "`reset()` method sets CFG_GADC_DATA_19 to value 0"]
19912 impl crate::Resettable for CfgGadcData19Spec {}
19913 }
19914 #[doc = "CFG_GADC_DATA_20 (rw) register accessor: cfg_gadc_data_20\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_20`] module"]
19915 #[doc(alias = "CFG_GADC_DATA_20")]
19916 pub type CfgGadcData20 = crate::Reg<cfg_gadc_data_20::CfgGadcData20Spec>;
19917 #[doc = "cfg_gadc_data_20"]
19918 pub mod cfg_gadc_data_20 {
19919 #[doc = "Register `CFG_GADC_DATA_20` reader"]
19920 pub type R = crate::R<CfgGadcData20Spec>;
19921 #[doc = "Register `CFG_GADC_DATA_20` writer"]
19922 pub type W = crate::W<CfgGadcData20Spec>;
19923 impl core::fmt::Debug for R {
19924 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19925 write!(f, "{}", self.bits())
19926 }
19927 }
19928 impl W {}
19929 #[doc = "cfg_gadc_data_20\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19930 pub struct CfgGadcData20Spec;
19931 impl crate::RegisterSpec for CfgGadcData20Spec {
19932 type Ux = u32;
19933 }
19934 #[doc = "`read()` method returns [`cfg_gadc_data_20::R`](R) reader structure"]
19935 impl crate::Readable for CfgGadcData20Spec {}
19936 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_20::W`](W) writer structure"]
19937 impl crate::Writable for CfgGadcData20Spec {
19938 type Safety = crate::Unsafe;
19939 }
19940 #[doc = "`reset()` method sets CFG_GADC_DATA_20 to value 0"]
19941 impl crate::Resettable for CfgGadcData20Spec {}
19942 }
19943 #[doc = "CFG_GADC_DATA_21 (rw) register accessor: cfg_gadc_data_21\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_21`] module"]
19944 #[doc(alias = "CFG_GADC_DATA_21")]
19945 pub type CfgGadcData21 = crate::Reg<cfg_gadc_data_21::CfgGadcData21Spec>;
19946 #[doc = "cfg_gadc_data_21"]
19947 pub mod cfg_gadc_data_21 {
19948 #[doc = "Register `CFG_GADC_DATA_21` reader"]
19949 pub type R = crate::R<CfgGadcData21Spec>;
19950 #[doc = "Register `CFG_GADC_DATA_21` writer"]
19951 pub type W = crate::W<CfgGadcData21Spec>;
19952 impl core::fmt::Debug for R {
19953 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19954 write!(f, "{}", self.bits())
19955 }
19956 }
19957 impl W {}
19958 #[doc = "cfg_gadc_data_21\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19959 pub struct CfgGadcData21Spec;
19960 impl crate::RegisterSpec for CfgGadcData21Spec {
19961 type Ux = u32;
19962 }
19963 #[doc = "`read()` method returns [`cfg_gadc_data_21::R`](R) reader structure"]
19964 impl crate::Readable for CfgGadcData21Spec {}
19965 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_21::W`](W) writer structure"]
19966 impl crate::Writable for CfgGadcData21Spec {
19967 type Safety = crate::Unsafe;
19968 }
19969 #[doc = "`reset()` method sets CFG_GADC_DATA_21 to value 0"]
19970 impl crate::Resettable for CfgGadcData21Spec {}
19971 }
19972 #[doc = "CFG_GADC_DATA_22 (rw) register accessor: cfg_gadc_data_22\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_22`] module"]
19973 #[doc(alias = "CFG_GADC_DATA_22")]
19974 pub type CfgGadcData22 = crate::Reg<cfg_gadc_data_22::CfgGadcData22Spec>;
19975 #[doc = "cfg_gadc_data_22"]
19976 pub mod cfg_gadc_data_22 {
19977 #[doc = "Register `CFG_GADC_DATA_22` reader"]
19978 pub type R = crate::R<CfgGadcData22Spec>;
19979 #[doc = "Register `CFG_GADC_DATA_22` writer"]
19980 pub type W = crate::W<CfgGadcData22Spec>;
19981 impl core::fmt::Debug for R {
19982 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19983 write!(f, "{}", self.bits())
19984 }
19985 }
19986 impl W {}
19987 #[doc = "cfg_gadc_data_22\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19988 pub struct CfgGadcData22Spec;
19989 impl crate::RegisterSpec for CfgGadcData22Spec {
19990 type Ux = u32;
19991 }
19992 #[doc = "`read()` method returns [`cfg_gadc_data_22::R`](R) reader structure"]
19993 impl crate::Readable for CfgGadcData22Spec {}
19994 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_22::W`](W) writer structure"]
19995 impl crate::Writable for CfgGadcData22Spec {
19996 type Safety = crate::Unsafe;
19997 }
19998 #[doc = "`reset()` method sets CFG_GADC_DATA_22 to value 0"]
19999 impl crate::Resettable for CfgGadcData22Spec {}
20000 }
20001 #[doc = "CFG_GADC_DATA_23 (rw) register accessor: cfg_gadc_data_23\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_23`] module"]
20002 #[doc(alias = "CFG_GADC_DATA_23")]
20003 pub type CfgGadcData23 = crate::Reg<cfg_gadc_data_23::CfgGadcData23Spec>;
20004 #[doc = "cfg_gadc_data_23"]
20005 pub mod cfg_gadc_data_23 {
20006 #[doc = "Register `CFG_GADC_DATA_23` reader"]
20007 pub type R = crate::R<CfgGadcData23Spec>;
20008 #[doc = "Register `CFG_GADC_DATA_23` writer"]
20009 pub type W = crate::W<CfgGadcData23Spec>;
20010 impl core::fmt::Debug for R {
20011 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20012 write!(f, "{}", self.bits())
20013 }
20014 }
20015 impl W {}
20016 #[doc = "cfg_gadc_data_23\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20017 pub struct CfgGadcData23Spec;
20018 impl crate::RegisterSpec for CfgGadcData23Spec {
20019 type Ux = u32;
20020 }
20021 #[doc = "`read()` method returns [`cfg_gadc_data_23::R`](R) reader structure"]
20022 impl crate::Readable for CfgGadcData23Spec {}
20023 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_23::W`](W) writer structure"]
20024 impl crate::Writable for CfgGadcData23Spec {
20025 type Safety = crate::Unsafe;
20026 }
20027 #[doc = "`reset()` method sets CFG_GADC_DATA_23 to value 0"]
20028 impl crate::Resettable for CfgGadcData23Spec {}
20029 }
20030 #[doc = "CFG_GADC_DATA_24 (rw) register accessor: cfg_gadc_data_24\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_24`] module"]
20031 #[doc(alias = "CFG_GADC_DATA_24")]
20032 pub type CfgGadcData24 = crate::Reg<cfg_gadc_data_24::CfgGadcData24Spec>;
20033 #[doc = "cfg_gadc_data_24"]
20034 pub mod cfg_gadc_data_24 {
20035 #[doc = "Register `CFG_GADC_DATA_24` reader"]
20036 pub type R = crate::R<CfgGadcData24Spec>;
20037 #[doc = "Register `CFG_GADC_DATA_24` writer"]
20038 pub type W = crate::W<CfgGadcData24Spec>;
20039 impl core::fmt::Debug for R {
20040 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20041 write!(f, "{}", self.bits())
20042 }
20043 }
20044 impl W {}
20045 #[doc = "cfg_gadc_data_24\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20046 pub struct CfgGadcData24Spec;
20047 impl crate::RegisterSpec for CfgGadcData24Spec {
20048 type Ux = u32;
20049 }
20050 #[doc = "`read()` method returns [`cfg_gadc_data_24::R`](R) reader structure"]
20051 impl crate::Readable for CfgGadcData24Spec {}
20052 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_24::W`](W) writer structure"]
20053 impl crate::Writable for CfgGadcData24Spec {
20054 type Safety = crate::Unsafe;
20055 }
20056 #[doc = "`reset()` method sets CFG_GADC_DATA_24 to value 0"]
20057 impl crate::Resettable for CfgGadcData24Spec {}
20058 }
20059 #[doc = "CFG_GADC_DATA_25 (rw) register accessor: cfg_gadc_data_25\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_25`] module"]
20060 #[doc(alias = "CFG_GADC_DATA_25")]
20061 pub type CfgGadcData25 = crate::Reg<cfg_gadc_data_25::CfgGadcData25Spec>;
20062 #[doc = "cfg_gadc_data_25"]
20063 pub mod cfg_gadc_data_25 {
20064 #[doc = "Register `CFG_GADC_DATA_25` reader"]
20065 pub type R = crate::R<CfgGadcData25Spec>;
20066 #[doc = "Register `CFG_GADC_DATA_25` writer"]
20067 pub type W = crate::W<CfgGadcData25Spec>;
20068 impl core::fmt::Debug for R {
20069 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20070 write!(f, "{}", self.bits())
20071 }
20072 }
20073 impl W {}
20074 #[doc = "cfg_gadc_data_25\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20075 pub struct CfgGadcData25Spec;
20076 impl crate::RegisterSpec for CfgGadcData25Spec {
20077 type Ux = u32;
20078 }
20079 #[doc = "`read()` method returns [`cfg_gadc_data_25::R`](R) reader structure"]
20080 impl crate::Readable for CfgGadcData25Spec {}
20081 #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_25::W`](W) writer structure"]
20082 impl crate::Writable for CfgGadcData25Spec {
20083 type Safety = crate::Unsafe;
20084 }
20085 #[doc = "`reset()` method sets CFG_GADC_DATA_25 to value 0"]
20086 impl crate::Resettable for CfgGadcData25Spec {}
20087 }
20088 #[doc = "RPT_GADC_DATA_5 (rw) register accessor: rpt_gadc_data_5\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_5`] module"]
20089 #[doc(alias = "RPT_GADC_DATA_5")]
20090 pub type RptGadcData5 = crate::Reg<rpt_gadc_data_5::RptGadcData5Spec>;
20091 #[doc = "rpt_gadc_data_5"]
20092 pub mod rpt_gadc_data_5 {
20093 #[doc = "Register `RPT_GADC_DATA_5` reader"]
20094 pub type R = crate::R<RptGadcData5Spec>;
20095 #[doc = "Register `RPT_GADC_DATA_5` writer"]
20096 pub type W = crate::W<RptGadcData5Spec>;
20097 impl core::fmt::Debug for R {
20098 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20099 write!(f, "{}", self.bits())
20100 }
20101 }
20102 impl W {}
20103 #[doc = "rpt_gadc_data_5\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20104 pub struct RptGadcData5Spec;
20105 impl crate::RegisterSpec for RptGadcData5Spec {
20106 type Ux = u32;
20107 }
20108 #[doc = "`read()` method returns [`rpt_gadc_data_5::R`](R) reader structure"]
20109 impl crate::Readable for RptGadcData5Spec {}
20110 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_5::W`](W) writer structure"]
20111 impl crate::Writable for RptGadcData5Spec {
20112 type Safety = crate::Unsafe;
20113 }
20114 #[doc = "`reset()` method sets RPT_GADC_DATA_5 to value 0"]
20115 impl crate::Resettable for RptGadcData5Spec {}
20116 }
20117 #[doc = "RPT_GADC_DATA_6 (rw) register accessor: rpt_gadc_data_6\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_6`] module"]
20118 #[doc(alias = "RPT_GADC_DATA_6")]
20119 pub type RptGadcData6 = crate::Reg<rpt_gadc_data_6::RptGadcData6Spec>;
20120 #[doc = "rpt_gadc_data_6"]
20121 pub mod rpt_gadc_data_6 {
20122 #[doc = "Register `RPT_GADC_DATA_6` reader"]
20123 pub type R = crate::R<RptGadcData6Spec>;
20124 #[doc = "Register `RPT_GADC_DATA_6` writer"]
20125 pub type W = crate::W<RptGadcData6Spec>;
20126 impl core::fmt::Debug for R {
20127 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20128 write!(f, "{}", self.bits())
20129 }
20130 }
20131 impl W {}
20132 #[doc = "rpt_gadc_data_6\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20133 pub struct RptGadcData6Spec;
20134 impl crate::RegisterSpec for RptGadcData6Spec {
20135 type Ux = u32;
20136 }
20137 #[doc = "`read()` method returns [`rpt_gadc_data_6::R`](R) reader structure"]
20138 impl crate::Readable for RptGadcData6Spec {}
20139 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_6::W`](W) writer structure"]
20140 impl crate::Writable for RptGadcData6Spec {
20141 type Safety = crate::Unsafe;
20142 }
20143 #[doc = "`reset()` method sets RPT_GADC_DATA_6 to value 0"]
20144 impl crate::Resettable for RptGadcData6Spec {}
20145 }
20146 #[doc = "RPT_GADC_DATA_7 (rw) register accessor: rpt_gadc_data_7\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_7`] module"]
20147 #[doc(alias = "RPT_GADC_DATA_7")]
20148 pub type RptGadcData7 = crate::Reg<rpt_gadc_data_7::RptGadcData7Spec>;
20149 #[doc = "rpt_gadc_data_7"]
20150 pub mod rpt_gadc_data_7 {
20151 #[doc = "Register `RPT_GADC_DATA_7` reader"]
20152 pub type R = crate::R<RptGadcData7Spec>;
20153 #[doc = "Register `RPT_GADC_DATA_7` writer"]
20154 pub type W = crate::W<RptGadcData7Spec>;
20155 impl core::fmt::Debug for R {
20156 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20157 write!(f, "{}", self.bits())
20158 }
20159 }
20160 impl W {}
20161 #[doc = "rpt_gadc_data_7\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20162 pub struct RptGadcData7Spec;
20163 impl crate::RegisterSpec for RptGadcData7Spec {
20164 type Ux = u32;
20165 }
20166 #[doc = "`read()` method returns [`rpt_gadc_data_7::R`](R) reader structure"]
20167 impl crate::Readable for RptGadcData7Spec {}
20168 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_7::W`](W) writer structure"]
20169 impl crate::Writable for RptGadcData7Spec {
20170 type Safety = crate::Unsafe;
20171 }
20172 #[doc = "`reset()` method sets RPT_GADC_DATA_7 to value 0"]
20173 impl crate::Resettable for RptGadcData7Spec {}
20174 }
20175 #[doc = "RPT_GADC_DATA_8 (rw) register accessor: rpt_gadc_data_8\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_8`] module"]
20176 #[doc(alias = "RPT_GADC_DATA_8")]
20177 pub type RptGadcData8 = crate::Reg<rpt_gadc_data_8::RptGadcData8Spec>;
20178 #[doc = "rpt_gadc_data_8"]
20179 pub mod rpt_gadc_data_8 {
20180 #[doc = "Register `RPT_GADC_DATA_8` reader"]
20181 pub type R = crate::R<RptGadcData8Spec>;
20182 #[doc = "Register `RPT_GADC_DATA_8` writer"]
20183 pub type W = crate::W<RptGadcData8Spec>;
20184 impl core::fmt::Debug for R {
20185 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20186 write!(f, "{}", self.bits())
20187 }
20188 }
20189 impl W {}
20190 #[doc = "rpt_gadc_data_8\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20191 pub struct RptGadcData8Spec;
20192 impl crate::RegisterSpec for RptGadcData8Spec {
20193 type Ux = u32;
20194 }
20195 #[doc = "`read()` method returns [`rpt_gadc_data_8::R`](R) reader structure"]
20196 impl crate::Readable for RptGadcData8Spec {}
20197 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_8::W`](W) writer structure"]
20198 impl crate::Writable for RptGadcData8Spec {
20199 type Safety = crate::Unsafe;
20200 }
20201 #[doc = "`reset()` method sets RPT_GADC_DATA_8 to value 0"]
20202 impl crate::Resettable for RptGadcData8Spec {}
20203 }
20204 #[doc = "RPT_GADC_DATA_9 (rw) register accessor: rpt_gadc_data_9\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_9`] module"]
20205 #[doc(alias = "RPT_GADC_DATA_9")]
20206 pub type RptGadcData9 = crate::Reg<rpt_gadc_data_9::RptGadcData9Spec>;
20207 #[doc = "rpt_gadc_data_9"]
20208 pub mod rpt_gadc_data_9 {
20209 #[doc = "Register `RPT_GADC_DATA_9` reader"]
20210 pub type R = crate::R<RptGadcData9Spec>;
20211 #[doc = "Register `RPT_GADC_DATA_9` writer"]
20212 pub type W = crate::W<RptGadcData9Spec>;
20213 impl core::fmt::Debug for R {
20214 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20215 write!(f, "{}", self.bits())
20216 }
20217 }
20218 impl W {}
20219 #[doc = "rpt_gadc_data_9\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20220 pub struct RptGadcData9Spec;
20221 impl crate::RegisterSpec for RptGadcData9Spec {
20222 type Ux = u32;
20223 }
20224 #[doc = "`read()` method returns [`rpt_gadc_data_9::R`](R) reader structure"]
20225 impl crate::Readable for RptGadcData9Spec {}
20226 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_9::W`](W) writer structure"]
20227 impl crate::Writable for RptGadcData9Spec {
20228 type Safety = crate::Unsafe;
20229 }
20230 #[doc = "`reset()` method sets RPT_GADC_DATA_9 to value 0"]
20231 impl crate::Resettable for RptGadcData9Spec {}
20232 }
20233 #[doc = "RPT_GADC_DATA_10 (rw) register accessor: rpt_gadc_data_10\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_10`] module"]
20234 #[doc(alias = "RPT_GADC_DATA_10")]
20235 pub type RptGadcData10 = crate::Reg<rpt_gadc_data_10::RptGadcData10Spec>;
20236 #[doc = "rpt_gadc_data_10"]
20237 pub mod rpt_gadc_data_10 {
20238 #[doc = "Register `RPT_GADC_DATA_10` reader"]
20239 pub type R = crate::R<RptGadcData10Spec>;
20240 #[doc = "Register `RPT_GADC_DATA_10` writer"]
20241 pub type W = crate::W<RptGadcData10Spec>;
20242 impl core::fmt::Debug for R {
20243 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20244 write!(f, "{}", self.bits())
20245 }
20246 }
20247 impl W {}
20248 #[doc = "rpt_gadc_data_10\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20249 pub struct RptGadcData10Spec;
20250 impl crate::RegisterSpec for RptGadcData10Spec {
20251 type Ux = u32;
20252 }
20253 #[doc = "`read()` method returns [`rpt_gadc_data_10::R`](R) reader structure"]
20254 impl crate::Readable for RptGadcData10Spec {}
20255 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_10::W`](W) writer structure"]
20256 impl crate::Writable for RptGadcData10Spec {
20257 type Safety = crate::Unsafe;
20258 }
20259 #[doc = "`reset()` method sets RPT_GADC_DATA_10 to value 0"]
20260 impl crate::Resettable for RptGadcData10Spec {}
20261 }
20262 #[doc = "RPT_GADC_DATA_11 (rw) register accessor: rpt_gadc_data_11\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_11`] module"]
20263 #[doc(alias = "RPT_GADC_DATA_11")]
20264 pub type RptGadcData11 = crate::Reg<rpt_gadc_data_11::RptGadcData11Spec>;
20265 #[doc = "rpt_gadc_data_11"]
20266 pub mod rpt_gadc_data_11 {
20267 #[doc = "Register `RPT_GADC_DATA_11` reader"]
20268 pub type R = crate::R<RptGadcData11Spec>;
20269 #[doc = "Register `RPT_GADC_DATA_11` writer"]
20270 pub type W = crate::W<RptGadcData11Spec>;
20271 impl core::fmt::Debug for R {
20272 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20273 write!(f, "{}", self.bits())
20274 }
20275 }
20276 impl W {}
20277 #[doc = "rpt_gadc_data_11\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20278 pub struct RptGadcData11Spec;
20279 impl crate::RegisterSpec for RptGadcData11Spec {
20280 type Ux = u32;
20281 }
20282 #[doc = "`read()` method returns [`rpt_gadc_data_11::R`](R) reader structure"]
20283 impl crate::Readable for RptGadcData11Spec {}
20284 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_11::W`](W) writer structure"]
20285 impl crate::Writable for RptGadcData11Spec {
20286 type Safety = crate::Unsafe;
20287 }
20288 #[doc = "`reset()` method sets RPT_GADC_DATA_11 to value 0"]
20289 impl crate::Resettable for RptGadcData11Spec {}
20290 }
20291 #[doc = "RPT_GADC_DATA_12 (rw) register accessor: rpt_gadc_data_12\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_12`] module"]
20292 #[doc(alias = "RPT_GADC_DATA_12")]
20293 pub type RptGadcData12 = crate::Reg<rpt_gadc_data_12::RptGadcData12Spec>;
20294 #[doc = "rpt_gadc_data_12"]
20295 pub mod rpt_gadc_data_12 {
20296 #[doc = "Register `RPT_GADC_DATA_12` reader"]
20297 pub type R = crate::R<RptGadcData12Spec>;
20298 #[doc = "Register `RPT_GADC_DATA_12` writer"]
20299 pub type W = crate::W<RptGadcData12Spec>;
20300 impl core::fmt::Debug for R {
20301 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20302 write!(f, "{}", self.bits())
20303 }
20304 }
20305 impl W {}
20306 #[doc = "rpt_gadc_data_12\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20307 pub struct RptGadcData12Spec;
20308 impl crate::RegisterSpec for RptGadcData12Spec {
20309 type Ux = u32;
20310 }
20311 #[doc = "`read()` method returns [`rpt_gadc_data_12::R`](R) reader structure"]
20312 impl crate::Readable for RptGadcData12Spec {}
20313 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_12::W`](W) writer structure"]
20314 impl crate::Writable for RptGadcData12Spec {
20315 type Safety = crate::Unsafe;
20316 }
20317 #[doc = "`reset()` method sets RPT_GADC_DATA_12 to value 0"]
20318 impl crate::Resettable for RptGadcData12Spec {}
20319 }
20320 #[doc = "RPT_GADC_DATA_13 (rw) register accessor: rpt_gadc_data_13\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_13`] module"]
20321 #[doc(alias = "RPT_GADC_DATA_13")]
20322 pub type RptGadcData13 = crate::Reg<rpt_gadc_data_13::RptGadcData13Spec>;
20323 #[doc = "rpt_gadc_data_13"]
20324 pub mod rpt_gadc_data_13 {
20325 #[doc = "Register `RPT_GADC_DATA_13` reader"]
20326 pub type R = crate::R<RptGadcData13Spec>;
20327 #[doc = "Register `RPT_GADC_DATA_13` writer"]
20328 pub type W = crate::W<RptGadcData13Spec>;
20329 impl core::fmt::Debug for R {
20330 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20331 write!(f, "{}", self.bits())
20332 }
20333 }
20334 impl W {}
20335 #[doc = "rpt_gadc_data_13\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20336 pub struct RptGadcData13Spec;
20337 impl crate::RegisterSpec for RptGadcData13Spec {
20338 type Ux = u32;
20339 }
20340 #[doc = "`read()` method returns [`rpt_gadc_data_13::R`](R) reader structure"]
20341 impl crate::Readable for RptGadcData13Spec {}
20342 #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_13::W`](W) writer structure"]
20343 impl crate::Writable for RptGadcData13Spec {
20344 type Safety = crate::Unsafe;
20345 }
20346 #[doc = "`reset()` method sets RPT_GADC_DATA_13 to value 0"]
20347 impl crate::Resettable for RptGadcData13Spec {}
20348 }
20349 #[doc = "CFG_CMP_OS_0 (rw) register accessor: cfg_cmp_os_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_0`] module"]
20350 #[doc(alias = "CFG_CMP_OS_0")]
20351 pub type CfgCmpOs0 = crate::Reg<cfg_cmp_os_0::CfgCmpOs0Spec>;
20352 #[doc = "cfg_cmp_os_0"]
20353 pub mod cfg_cmp_os_0 {
20354 #[doc = "Register `CFG_CMP_OS_0` reader"]
20355 pub type R = crate::R<CfgCmpOs0Spec>;
20356 #[doc = "Register `CFG_CMP_OS_0` writer"]
20357 pub type W = crate::W<CfgCmpOs0Spec>;
20358 impl core::fmt::Debug for R {
20359 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20360 write!(f, "{}", self.bits())
20361 }
20362 }
20363 impl W {}
20364 #[doc = "cfg_cmp_os_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20365 pub struct CfgCmpOs0Spec;
20366 impl crate::RegisterSpec for CfgCmpOs0Spec {
20367 type Ux = u32;
20368 }
20369 #[doc = "`read()` method returns [`cfg_cmp_os_0::R`](R) reader structure"]
20370 impl crate::Readable for CfgCmpOs0Spec {}
20371 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_0::W`](W) writer structure"]
20372 impl crate::Writable for CfgCmpOs0Spec {
20373 type Safety = crate::Unsafe;
20374 }
20375 #[doc = "`reset()` method sets CFG_CMP_OS_0 to value 0"]
20376 impl crate::Resettable for CfgCmpOs0Spec {}
20377 }
20378 #[doc = "CFG_CMP_OS_1 (rw) register accessor: cfg_cmp_os_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_1`] module"]
20379 #[doc(alias = "CFG_CMP_OS_1")]
20380 pub type CfgCmpOs1 = crate::Reg<cfg_cmp_os_1::CfgCmpOs1Spec>;
20381 #[doc = "cfg_cmp_os_1"]
20382 pub mod cfg_cmp_os_1 {
20383 #[doc = "Register `CFG_CMP_OS_1` reader"]
20384 pub type R = crate::R<CfgCmpOs1Spec>;
20385 #[doc = "Register `CFG_CMP_OS_1` writer"]
20386 pub type W = crate::W<CfgCmpOs1Spec>;
20387 impl core::fmt::Debug for R {
20388 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20389 write!(f, "{}", self.bits())
20390 }
20391 }
20392 impl W {}
20393 #[doc = "cfg_cmp_os_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20394 pub struct CfgCmpOs1Spec;
20395 impl crate::RegisterSpec for CfgCmpOs1Spec {
20396 type Ux = u32;
20397 }
20398 #[doc = "`read()` method returns [`cfg_cmp_os_1::R`](R) reader structure"]
20399 impl crate::Readable for CfgCmpOs1Spec {}
20400 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_1::W`](W) writer structure"]
20401 impl crate::Writable for CfgCmpOs1Spec {
20402 type Safety = crate::Unsafe;
20403 }
20404 #[doc = "`reset()` method sets CFG_CMP_OS_1 to value 0"]
20405 impl crate::Resettable for CfgCmpOs1Spec {}
20406 }
20407 #[doc = "CFG_CMP_OS_2 (rw) register accessor: cfg_cmp_os_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_2`] module"]
20408 #[doc(alias = "CFG_CMP_OS_2")]
20409 pub type CfgCmpOs2 = crate::Reg<cfg_cmp_os_2::CfgCmpOs2Spec>;
20410 #[doc = "cfg_cmp_os_2"]
20411 pub mod cfg_cmp_os_2 {
20412 #[doc = "Register `CFG_CMP_OS_2` reader"]
20413 pub type R = crate::R<CfgCmpOs2Spec>;
20414 #[doc = "Register `CFG_CMP_OS_2` writer"]
20415 pub type W = crate::W<CfgCmpOs2Spec>;
20416 impl core::fmt::Debug for R {
20417 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20418 write!(f, "{}", self.bits())
20419 }
20420 }
20421 impl W {}
20422 #[doc = "cfg_cmp_os_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20423 pub struct CfgCmpOs2Spec;
20424 impl crate::RegisterSpec for CfgCmpOs2Spec {
20425 type Ux = u32;
20426 }
20427 #[doc = "`read()` method returns [`cfg_cmp_os_2::R`](R) reader structure"]
20428 impl crate::Readable for CfgCmpOs2Spec {}
20429 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_2::W`](W) writer structure"]
20430 impl crate::Writable for CfgCmpOs2Spec {
20431 type Safety = crate::Unsafe;
20432 }
20433 #[doc = "`reset()` method sets CFG_CMP_OS_2 to value 0"]
20434 impl crate::Resettable for CfgCmpOs2Spec {}
20435 }
20436 #[doc = "CFG_CMP_OS_3 (rw) register accessor: cfg_cmp_os_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_3`] module"]
20437 #[doc(alias = "CFG_CMP_OS_3")]
20438 pub type CfgCmpOs3 = crate::Reg<cfg_cmp_os_3::CfgCmpOs3Spec>;
20439 #[doc = "cfg_cmp_os_3"]
20440 pub mod cfg_cmp_os_3 {
20441 #[doc = "Register `CFG_CMP_OS_3` reader"]
20442 pub type R = crate::R<CfgCmpOs3Spec>;
20443 #[doc = "Register `CFG_CMP_OS_3` writer"]
20444 pub type W = crate::W<CfgCmpOs3Spec>;
20445 impl core::fmt::Debug for R {
20446 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20447 write!(f, "{}", self.bits())
20448 }
20449 }
20450 impl W {}
20451 #[doc = "cfg_cmp_os_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20452 pub struct CfgCmpOs3Spec;
20453 impl crate::RegisterSpec for CfgCmpOs3Spec {
20454 type Ux = u32;
20455 }
20456 #[doc = "`read()` method returns [`cfg_cmp_os_3::R`](R) reader structure"]
20457 impl crate::Readable for CfgCmpOs3Spec {}
20458 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_3::W`](W) writer structure"]
20459 impl crate::Writable for CfgCmpOs3Spec {
20460 type Safety = crate::Unsafe;
20461 }
20462 #[doc = "`reset()` method sets CFG_CMP_OS_3 to value 0"]
20463 impl crate::Resettable for CfgCmpOs3Spec {}
20464 }
20465 #[doc = "CFG_CMP_OS_4 (rw) register accessor: cfg_cmp_os_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_4`] module"]
20466 #[doc(alias = "CFG_CMP_OS_4")]
20467 pub type CfgCmpOs4 = crate::Reg<cfg_cmp_os_4::CfgCmpOs4Spec>;
20468 #[doc = "cfg_cmp_os_4"]
20469 pub mod cfg_cmp_os_4 {
20470 #[doc = "Register `CFG_CMP_OS_4` reader"]
20471 pub type R = crate::R<CfgCmpOs4Spec>;
20472 #[doc = "Register `CFG_CMP_OS_4` writer"]
20473 pub type W = crate::W<CfgCmpOs4Spec>;
20474 impl core::fmt::Debug for R {
20475 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20476 write!(f, "{}", self.bits())
20477 }
20478 }
20479 impl W {}
20480 #[doc = "cfg_cmp_os_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20481 pub struct CfgCmpOs4Spec;
20482 impl crate::RegisterSpec for CfgCmpOs4Spec {
20483 type Ux = u32;
20484 }
20485 #[doc = "`read()` method returns [`cfg_cmp_os_4::R`](R) reader structure"]
20486 impl crate::Readable for CfgCmpOs4Spec {}
20487 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_4::W`](W) writer structure"]
20488 impl crate::Writable for CfgCmpOs4Spec {
20489 type Safety = crate::Unsafe;
20490 }
20491 #[doc = "`reset()` method sets CFG_CMP_OS_4 to value 0"]
20492 impl crate::Resettable for CfgCmpOs4Spec {}
20493 }
20494 #[doc = "CFG_CMP_OS_5 (rw) register accessor: cfg_cmp_os_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_5`] module"]
20495 #[doc(alias = "CFG_CMP_OS_5")]
20496 pub type CfgCmpOs5 = crate::Reg<cfg_cmp_os_5::CfgCmpOs5Spec>;
20497 #[doc = "cfg_cmp_os_5"]
20498 pub mod cfg_cmp_os_5 {
20499 #[doc = "Register `CFG_CMP_OS_5` reader"]
20500 pub type R = crate::R<CfgCmpOs5Spec>;
20501 #[doc = "Register `CFG_CMP_OS_5` writer"]
20502 pub type W = crate::W<CfgCmpOs5Spec>;
20503 impl core::fmt::Debug for R {
20504 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20505 write!(f, "{}", self.bits())
20506 }
20507 }
20508 impl W {}
20509 #[doc = "cfg_cmp_os_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20510 pub struct CfgCmpOs5Spec;
20511 impl crate::RegisterSpec for CfgCmpOs5Spec {
20512 type Ux = u32;
20513 }
20514 #[doc = "`read()` method returns [`cfg_cmp_os_5::R`](R) reader structure"]
20515 impl crate::Readable for CfgCmpOs5Spec {}
20516 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_5::W`](W) writer structure"]
20517 impl crate::Writable for CfgCmpOs5Spec {
20518 type Safety = crate::Unsafe;
20519 }
20520 #[doc = "`reset()` method sets CFG_CMP_OS_5 to value 0"]
20521 impl crate::Resettable for CfgCmpOs5Spec {}
20522 }
20523 #[doc = "CFG_CMP_OS_6 (rw) register accessor: cfg_cmp_os_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_6`] module"]
20524 #[doc(alias = "CFG_CMP_OS_6")]
20525 pub type CfgCmpOs6 = crate::Reg<cfg_cmp_os_6::CfgCmpOs6Spec>;
20526 #[doc = "cfg_cmp_os_6"]
20527 pub mod cfg_cmp_os_6 {
20528 #[doc = "Register `CFG_CMP_OS_6` reader"]
20529 pub type R = crate::R<CfgCmpOs6Spec>;
20530 #[doc = "Register `CFG_CMP_OS_6` writer"]
20531 pub type W = crate::W<CfgCmpOs6Spec>;
20532 impl core::fmt::Debug for R {
20533 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20534 write!(f, "{}", self.bits())
20535 }
20536 }
20537 impl W {}
20538 #[doc = "cfg_cmp_os_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20539 pub struct CfgCmpOs6Spec;
20540 impl crate::RegisterSpec for CfgCmpOs6Spec {
20541 type Ux = u32;
20542 }
20543 #[doc = "`read()` method returns [`cfg_cmp_os_6::R`](R) reader structure"]
20544 impl crate::Readable for CfgCmpOs6Spec {}
20545 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_6::W`](W) writer structure"]
20546 impl crate::Writable for CfgCmpOs6Spec {
20547 type Safety = crate::Unsafe;
20548 }
20549 #[doc = "`reset()` method sets CFG_CMP_OS_6 to value 0"]
20550 impl crate::Resettable for CfgCmpOs6Spec {}
20551 }
20552 #[doc = "CFG_CMP_OS_7 (rw) register accessor: cfg_cmp_os_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_7`] module"]
20553 #[doc(alias = "CFG_CMP_OS_7")]
20554 pub type CfgCmpOs7 = crate::Reg<cfg_cmp_os_7::CfgCmpOs7Spec>;
20555 #[doc = "cfg_cmp_os_7"]
20556 pub mod cfg_cmp_os_7 {
20557 #[doc = "Register `CFG_CMP_OS_7` reader"]
20558 pub type R = crate::R<CfgCmpOs7Spec>;
20559 #[doc = "Register `CFG_CMP_OS_7` writer"]
20560 pub type W = crate::W<CfgCmpOs7Spec>;
20561 impl core::fmt::Debug for R {
20562 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20563 write!(f, "{}", self.bits())
20564 }
20565 }
20566 impl W {}
20567 #[doc = "cfg_cmp_os_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20568 pub struct CfgCmpOs7Spec;
20569 impl crate::RegisterSpec for CfgCmpOs7Spec {
20570 type Ux = u32;
20571 }
20572 #[doc = "`read()` method returns [`cfg_cmp_os_7::R`](R) reader structure"]
20573 impl crate::Readable for CfgCmpOs7Spec {}
20574 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_7::W`](W) writer structure"]
20575 impl crate::Writable for CfgCmpOs7Spec {
20576 type Safety = crate::Unsafe;
20577 }
20578 #[doc = "`reset()` method sets CFG_CMP_OS_7 to value 0"]
20579 impl crate::Resettable for CfgCmpOs7Spec {}
20580 }
20581 #[doc = "CFG_CMP_OS_8 (rw) register accessor: cfg_cmp_os_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_8`] module"]
20582 #[doc(alias = "CFG_CMP_OS_8")]
20583 pub type CfgCmpOs8 = crate::Reg<cfg_cmp_os_8::CfgCmpOs8Spec>;
20584 #[doc = "cfg_cmp_os_8"]
20585 pub mod cfg_cmp_os_8 {
20586 #[doc = "Register `CFG_CMP_OS_8` reader"]
20587 pub type R = crate::R<CfgCmpOs8Spec>;
20588 #[doc = "Register `CFG_CMP_OS_8` writer"]
20589 pub type W = crate::W<CfgCmpOs8Spec>;
20590 impl core::fmt::Debug for R {
20591 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20592 write!(f, "{}", self.bits())
20593 }
20594 }
20595 impl W {}
20596 #[doc = "cfg_cmp_os_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20597 pub struct CfgCmpOs8Spec;
20598 impl crate::RegisterSpec for CfgCmpOs8Spec {
20599 type Ux = u32;
20600 }
20601 #[doc = "`read()` method returns [`cfg_cmp_os_8::R`](R) reader structure"]
20602 impl crate::Readable for CfgCmpOs8Spec {}
20603 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_8::W`](W) writer structure"]
20604 impl crate::Writable for CfgCmpOs8Spec {
20605 type Safety = crate::Unsafe;
20606 }
20607 #[doc = "`reset()` method sets CFG_CMP_OS_8 to value 0"]
20608 impl crate::Resettable for CfgCmpOs8Spec {}
20609 }
20610 #[doc = "CFG_CMP_OS_9 (rw) register accessor: cfg_cmp_os_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_9`] module"]
20611 #[doc(alias = "CFG_CMP_OS_9")]
20612 pub type CfgCmpOs9 = crate::Reg<cfg_cmp_os_9::CfgCmpOs9Spec>;
20613 #[doc = "cfg_cmp_os_9"]
20614 pub mod cfg_cmp_os_9 {
20615 #[doc = "Register `CFG_CMP_OS_9` reader"]
20616 pub type R = crate::R<CfgCmpOs9Spec>;
20617 #[doc = "Register `CFG_CMP_OS_9` writer"]
20618 pub type W = crate::W<CfgCmpOs9Spec>;
20619 impl core::fmt::Debug for R {
20620 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20621 write!(f, "{}", self.bits())
20622 }
20623 }
20624 impl W {}
20625 #[doc = "cfg_cmp_os_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20626 pub struct CfgCmpOs9Spec;
20627 impl crate::RegisterSpec for CfgCmpOs9Spec {
20628 type Ux = u32;
20629 }
20630 #[doc = "`read()` method returns [`cfg_cmp_os_9::R`](R) reader structure"]
20631 impl crate::Readable for CfgCmpOs9Spec {}
20632 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_9::W`](W) writer structure"]
20633 impl crate::Writable for CfgCmpOs9Spec {
20634 type Safety = crate::Unsafe;
20635 }
20636 #[doc = "`reset()` method sets CFG_CMP_OS_9 to value 0"]
20637 impl crate::Resettable for CfgCmpOs9Spec {}
20638 }
20639 #[doc = "CFG_CMP_OS_10 (rw) register accessor: cfg_cmp_os_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_10`] module"]
20640 #[doc(alias = "CFG_CMP_OS_10")]
20641 pub type CfgCmpOs10 = crate::Reg<cfg_cmp_os_10::CfgCmpOs10Spec>;
20642 #[doc = "cfg_cmp_os_10"]
20643 pub mod cfg_cmp_os_10 {
20644 #[doc = "Register `CFG_CMP_OS_10` reader"]
20645 pub type R = crate::R<CfgCmpOs10Spec>;
20646 #[doc = "Register `CFG_CMP_OS_10` writer"]
20647 pub type W = crate::W<CfgCmpOs10Spec>;
20648 impl core::fmt::Debug for R {
20649 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20650 write!(f, "{}", self.bits())
20651 }
20652 }
20653 impl W {}
20654 #[doc = "cfg_cmp_os_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20655 pub struct CfgCmpOs10Spec;
20656 impl crate::RegisterSpec for CfgCmpOs10Spec {
20657 type Ux = u32;
20658 }
20659 #[doc = "`read()` method returns [`cfg_cmp_os_10::R`](R) reader structure"]
20660 impl crate::Readable for CfgCmpOs10Spec {}
20661 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_10::W`](W) writer structure"]
20662 impl crate::Writable for CfgCmpOs10Spec {
20663 type Safety = crate::Unsafe;
20664 }
20665 #[doc = "`reset()` method sets CFG_CMP_OS_10 to value 0"]
20666 impl crate::Resettable for CfgCmpOs10Spec {}
20667 }
20668 #[doc = "RPT_CMP_OS_0 (rw) register accessor: rpt_cmp_os_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_os_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_os_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cmp_os_0`] module"]
20669 #[doc(alias = "RPT_CMP_OS_0")]
20670 pub type RptCmpOs0 = crate::Reg<rpt_cmp_os_0::RptCmpOs0Spec>;
20671 #[doc = "rpt_cmp_os_0"]
20672 pub mod rpt_cmp_os_0 {
20673 #[doc = "Register `RPT_CMP_OS_0` reader"]
20674 pub type R = crate::R<RptCmpOs0Spec>;
20675 #[doc = "Register `RPT_CMP_OS_0` writer"]
20676 pub type W = crate::W<RptCmpOs0Spec>;
20677 impl core::fmt::Debug for R {
20678 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20679 write!(f, "{}", self.bits())
20680 }
20681 }
20682 impl W {}
20683 #[doc = "rpt_cmp_os_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_os_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_os_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20684 pub struct RptCmpOs0Spec;
20685 impl crate::RegisterSpec for RptCmpOs0Spec {
20686 type Ux = u32;
20687 }
20688 #[doc = "`read()` method returns [`rpt_cmp_os_0::R`](R) reader structure"]
20689 impl crate::Readable for RptCmpOs0Spec {}
20690 #[doc = "`write(|w| ..)` method takes [`rpt_cmp_os_0::W`](W) writer structure"]
20691 impl crate::Writable for RptCmpOs0Spec {
20692 type Safety = crate::Unsafe;
20693 }
20694 #[doc = "`reset()` method sets RPT_CMP_OS_0 to value 0"]
20695 impl crate::Resettable for RptCmpOs0Spec {}
20696 }
20697 #[doc = "CFG_CMP_OS_11 (rw) register accessor: cfg_cmp_os_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_11`] module"]
20698 #[doc(alias = "CFG_CMP_OS_11")]
20699 pub type CfgCmpOs11 = crate::Reg<cfg_cmp_os_11::CfgCmpOs11Spec>;
20700 #[doc = "cfg_cmp_os_11"]
20701 pub mod cfg_cmp_os_11 {
20702 #[doc = "Register `CFG_CMP_OS_11` reader"]
20703 pub type R = crate::R<CfgCmpOs11Spec>;
20704 #[doc = "Register `CFG_CMP_OS_11` writer"]
20705 pub type W = crate::W<CfgCmpOs11Spec>;
20706 impl core::fmt::Debug for R {
20707 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20708 write!(f, "{}", self.bits())
20709 }
20710 }
20711 impl W {}
20712 #[doc = "cfg_cmp_os_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20713 pub struct CfgCmpOs11Spec;
20714 impl crate::RegisterSpec for CfgCmpOs11Spec {
20715 type Ux = u32;
20716 }
20717 #[doc = "`read()` method returns [`cfg_cmp_os_11::R`](R) reader structure"]
20718 impl crate::Readable for CfgCmpOs11Spec {}
20719 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_11::W`](W) writer structure"]
20720 impl crate::Writable for CfgCmpOs11Spec {
20721 type Safety = crate::Unsafe;
20722 }
20723 #[doc = "`reset()` method sets CFG_CMP_OS_11 to value 0"]
20724 impl crate::Resettable for CfgCmpOs11Spec {}
20725 }
20726 #[doc = "CFG_CMP_OS_12 (rw) register accessor: cfg_cmp_os_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_12`] module"]
20727 #[doc(alias = "CFG_CMP_OS_12")]
20728 pub type CfgCmpOs12 = crate::Reg<cfg_cmp_os_12::CfgCmpOs12Spec>;
20729 #[doc = "cfg_cmp_os_12"]
20730 pub mod cfg_cmp_os_12 {
20731 #[doc = "Register `CFG_CMP_OS_12` reader"]
20732 pub type R = crate::R<CfgCmpOs12Spec>;
20733 #[doc = "Register `CFG_CMP_OS_12` writer"]
20734 pub type W = crate::W<CfgCmpOs12Spec>;
20735 #[doc = "Field `cfg_manual_cmp_os_code` reader - "]
20736 pub type CfgManualCmpOsCodeR = crate::FieldReader;
20737 #[doc = "Field `cfg_manual_cmp_os_code` writer - "]
20738 pub type CfgManualCmpOsCodeW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
20739 #[doc = "Field `cfg_manual_cmp_os_update` reader - "]
20740 pub type CfgManualCmpOsUpdateR = crate::BitReader;
20741 #[doc = "Field `cfg_manual_cmp_os_update` writer - "]
20742 pub type CfgManualCmpOsUpdateW<'a, REG> = crate::BitWriter<'a, REG>;
20743 impl R {
20744 #[doc = "Bits 0:6"]
20745 #[inline(always)]
20746 pub fn cfg_manual_cmp_os_code(&self) -> CfgManualCmpOsCodeR {
20747 CfgManualCmpOsCodeR::new((self.bits & 0x7f) as u8)
20748 }
20749 #[doc = "Bit 8"]
20750 #[inline(always)]
20751 pub fn cfg_manual_cmp_os_update(&self) -> CfgManualCmpOsUpdateR {
20752 CfgManualCmpOsUpdateR::new(((self.bits >> 8) & 1) != 0)
20753 }
20754 }
20755 impl W {
20756 #[doc = "Bits 0:6"]
20757 #[inline(always)]
20758 pub fn cfg_manual_cmp_os_code(&mut self) -> CfgManualCmpOsCodeW<'_, CfgCmpOs12Spec> {
20759 CfgManualCmpOsCodeW::new(self, 0)
20760 }
20761 #[doc = "Bit 8"]
20762 #[inline(always)]
20763 pub fn cfg_manual_cmp_os_update(
20764 &mut self,
20765 ) -> CfgManualCmpOsUpdateW<'_, CfgCmpOs12Spec> {
20766 CfgManualCmpOsUpdateW::new(self, 8)
20767 }
20768 }
20769 #[doc = "cfg_cmp_os_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20770 pub struct CfgCmpOs12Spec;
20771 impl crate::RegisterSpec for CfgCmpOs12Spec {
20772 type Ux = u32;
20773 }
20774 #[doc = "`read()` method returns [`cfg_cmp_os_12::R`](R) reader structure"]
20775 impl crate::Readable for CfgCmpOs12Spec {}
20776 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_12::W`](W) writer structure"]
20777 impl crate::Writable for CfgCmpOs12Spec {
20778 type Safety = crate::Unsafe;
20779 }
20780 #[doc = "`reset()` method sets CFG_CMP_OS_12 to value 0"]
20781 impl crate::Resettable for CfgCmpOs12Spec {}
20782 }
20783 #[doc = "RPT_CMP_OS_2 (rw) register accessor: rpt_cmp_os_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_os_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_os_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cmp_os_2`] module"]
20784 #[doc(alias = "RPT_CMP_OS_2")]
20785 pub type RptCmpOs2 = crate::Reg<rpt_cmp_os_2::RptCmpOs2Spec>;
20786 #[doc = "rpt_cmp_os_2"]
20787 pub mod rpt_cmp_os_2 {
20788 #[doc = "Register `RPT_CMP_OS_2` reader"]
20789 pub type R = crate::R<RptCmpOs2Spec>;
20790 #[doc = "Register `RPT_CMP_OS_2` writer"]
20791 pub type W = crate::W<RptCmpOs2Spec>;
20792 impl core::fmt::Debug for R {
20793 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20794 write!(f, "{}", self.bits())
20795 }
20796 }
20797 impl W {}
20798 #[doc = "rpt_cmp_os_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_os_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_os_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20799 pub struct RptCmpOs2Spec;
20800 impl crate::RegisterSpec for RptCmpOs2Spec {
20801 type Ux = u32;
20802 }
20803 #[doc = "`read()` method returns [`rpt_cmp_os_2::R`](R) reader structure"]
20804 impl crate::Readable for RptCmpOs2Spec {}
20805 #[doc = "`write(|w| ..)` method takes [`rpt_cmp_os_2::W`](W) writer structure"]
20806 impl crate::Writable for RptCmpOs2Spec {
20807 type Safety = crate::Unsafe;
20808 }
20809 #[doc = "`reset()` method sets RPT_CMP_OS_2 to value 0"]
20810 impl crate::Resettable for RptCmpOs2Spec {}
20811 }
20812 #[doc = "CFG_CDAC_FC0_0 (rw) register accessor: cfg_cdac_fc0_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_0`] module"]
20813 #[doc(alias = "CFG_CDAC_FC0_0")]
20814 pub type CfgCdacFc0_0 = crate::Reg<cfg_cdac_fc0_0::CfgCdacFc0_0Spec>;
20815 #[doc = "cfg_cdac_fc0_0"]
20816 pub mod cfg_cdac_fc0_0 {
20817 #[doc = "Register `CFG_CDAC_FC0_0` reader"]
20818 pub type R = crate::R<CfgCdacFc0_0Spec>;
20819 #[doc = "Register `CFG_CDAC_FC0_0` writer"]
20820 pub type W = crate::W<CfgCdacFc0_0Spec>;
20821 impl core::fmt::Debug for R {
20822 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20823 write!(f, "{}", self.bits())
20824 }
20825 }
20826 impl W {}
20827 #[doc = "cfg_cdac_fc0_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20828 pub struct CfgCdacFc0_0Spec;
20829 impl crate::RegisterSpec for CfgCdacFc0_0Spec {
20830 type Ux = u32;
20831 }
20832 #[doc = "`read()` method returns [`cfg_cdac_fc0_0::R`](R) reader structure"]
20833 impl crate::Readable for CfgCdacFc0_0Spec {}
20834 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_0::W`](W) writer structure"]
20835 impl crate::Writable for CfgCdacFc0_0Spec {
20836 type Safety = crate::Unsafe;
20837 }
20838 #[doc = "`reset()` method sets CFG_CDAC_FC0_0 to value 0"]
20839 impl crate::Resettable for CfgCdacFc0_0Spec {}
20840 }
20841 #[doc = "CFG_CDAC_FC0_1 (rw) register accessor: cfg_cdac_fc0_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_1`] module"]
20842 #[doc(alias = "CFG_CDAC_FC0_1")]
20843 pub type CfgCdacFc0_1 = crate::Reg<cfg_cdac_fc0_1::CfgCdacFc0_1Spec>;
20844 #[doc = "cfg_cdac_fc0_1"]
20845 pub mod cfg_cdac_fc0_1 {
20846 #[doc = "Register `CFG_CDAC_FC0_1` reader"]
20847 pub type R = crate::R<CfgCdacFc0_1Spec>;
20848 #[doc = "Register `CFG_CDAC_FC0_1` writer"]
20849 pub type W = crate::W<CfgCdacFc0_1Spec>;
20850 impl core::fmt::Debug for R {
20851 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20852 write!(f, "{}", self.bits())
20853 }
20854 }
20855 impl W {}
20856 #[doc = "cfg_cdac_fc0_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20857 pub struct CfgCdacFc0_1Spec;
20858 impl crate::RegisterSpec for CfgCdacFc0_1Spec {
20859 type Ux = u32;
20860 }
20861 #[doc = "`read()` method returns [`cfg_cdac_fc0_1::R`](R) reader structure"]
20862 impl crate::Readable for CfgCdacFc0_1Spec {}
20863 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_1::W`](W) writer structure"]
20864 impl crate::Writable for CfgCdacFc0_1Spec {
20865 type Safety = crate::Unsafe;
20866 }
20867 #[doc = "`reset()` method sets CFG_CDAC_FC0_1 to value 0"]
20868 impl crate::Resettable for CfgCdacFc0_1Spec {}
20869 }
20870 #[doc = "CFG_CDAC_FC0_2 (rw) register accessor: cfg_cdac_fc0_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_2`] module"]
20871 #[doc(alias = "CFG_CDAC_FC0_2")]
20872 pub type CfgCdacFc0_2 = crate::Reg<cfg_cdac_fc0_2::CfgCdacFc0_2Spec>;
20873 #[doc = "cfg_cdac_fc0_2"]
20874 pub mod cfg_cdac_fc0_2 {
20875 #[doc = "Register `CFG_CDAC_FC0_2` reader"]
20876 pub type R = crate::R<CfgCdacFc0_2Spec>;
20877 #[doc = "Register `CFG_CDAC_FC0_2` writer"]
20878 pub type W = crate::W<CfgCdacFc0_2Spec>;
20879 impl core::fmt::Debug for R {
20880 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20881 write!(f, "{}", self.bits())
20882 }
20883 }
20884 impl W {}
20885 #[doc = "cfg_cdac_fc0_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20886 pub struct CfgCdacFc0_2Spec;
20887 impl crate::RegisterSpec for CfgCdacFc0_2Spec {
20888 type Ux = u32;
20889 }
20890 #[doc = "`read()` method returns [`cfg_cdac_fc0_2::R`](R) reader structure"]
20891 impl crate::Readable for CfgCdacFc0_2Spec {}
20892 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_2::W`](W) writer structure"]
20893 impl crate::Writable for CfgCdacFc0_2Spec {
20894 type Safety = crate::Unsafe;
20895 }
20896 #[doc = "`reset()` method sets CFG_CDAC_FC0_2 to value 0"]
20897 impl crate::Resettable for CfgCdacFc0_2Spec {}
20898 }
20899 #[doc = "CFG_CDAC_FC0_3 (rw) register accessor: cfg_cdac_fc0_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_3`] module"]
20900 #[doc(alias = "CFG_CDAC_FC0_3")]
20901 pub type CfgCdacFc0_3 = crate::Reg<cfg_cdac_fc0_3::CfgCdacFc0_3Spec>;
20902 #[doc = "cfg_cdac_fc0_3"]
20903 pub mod cfg_cdac_fc0_3 {
20904 #[doc = "Register `CFG_CDAC_FC0_3` reader"]
20905 pub type R = crate::R<CfgCdacFc0_3Spec>;
20906 #[doc = "Register `CFG_CDAC_FC0_3` writer"]
20907 pub type W = crate::W<CfgCdacFc0_3Spec>;
20908 impl core::fmt::Debug for R {
20909 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20910 write!(f, "{}", self.bits())
20911 }
20912 }
20913 impl W {}
20914 #[doc = "cfg_cdac_fc0_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20915 pub struct CfgCdacFc0_3Spec;
20916 impl crate::RegisterSpec for CfgCdacFc0_3Spec {
20917 type Ux = u32;
20918 }
20919 #[doc = "`read()` method returns [`cfg_cdac_fc0_3::R`](R) reader structure"]
20920 impl crate::Readable for CfgCdacFc0_3Spec {}
20921 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_3::W`](W) writer structure"]
20922 impl crate::Writable for CfgCdacFc0_3Spec {
20923 type Safety = crate::Unsafe;
20924 }
20925 #[doc = "`reset()` method sets CFG_CDAC_FC0_3 to value 0"]
20926 impl crate::Resettable for CfgCdacFc0_3Spec {}
20927 }
20928 #[doc = "CFG_CDAC_FC0_4 (rw) register accessor: cfg_cdac_fc0_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_4`] module"]
20929 #[doc(alias = "CFG_CDAC_FC0_4")]
20930 pub type CfgCdacFc0_4 = crate::Reg<cfg_cdac_fc0_4::CfgCdacFc0_4Spec>;
20931 #[doc = "cfg_cdac_fc0_4"]
20932 pub mod cfg_cdac_fc0_4 {
20933 #[doc = "Register `CFG_CDAC_FC0_4` reader"]
20934 pub type R = crate::R<CfgCdacFc0_4Spec>;
20935 #[doc = "Register `CFG_CDAC_FC0_4` writer"]
20936 pub type W = crate::W<CfgCdacFc0_4Spec>;
20937 impl core::fmt::Debug for R {
20938 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20939 write!(f, "{}", self.bits())
20940 }
20941 }
20942 impl W {}
20943 #[doc = "cfg_cdac_fc0_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20944 pub struct CfgCdacFc0_4Spec;
20945 impl crate::RegisterSpec for CfgCdacFc0_4Spec {
20946 type Ux = u32;
20947 }
20948 #[doc = "`read()` method returns [`cfg_cdac_fc0_4::R`](R) reader structure"]
20949 impl crate::Readable for CfgCdacFc0_4Spec {}
20950 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_4::W`](W) writer structure"]
20951 impl crate::Writable for CfgCdacFc0_4Spec {
20952 type Safety = crate::Unsafe;
20953 }
20954 #[doc = "`reset()` method sets CFG_CDAC_FC0_4 to value 0"]
20955 impl crate::Resettable for CfgCdacFc0_4Spec {}
20956 }
20957 #[doc = "CFG_CDAC_FC0_5 (rw) register accessor: cfg_cdac_fc0_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_5`] module"]
20958 #[doc(alias = "CFG_CDAC_FC0_5")]
20959 pub type CfgCdacFc0_5 = crate::Reg<cfg_cdac_fc0_5::CfgCdacFc0_5Spec>;
20960 #[doc = "cfg_cdac_fc0_5"]
20961 pub mod cfg_cdac_fc0_5 {
20962 #[doc = "Register `CFG_CDAC_FC0_5` reader"]
20963 pub type R = crate::R<CfgCdacFc0_5Spec>;
20964 #[doc = "Register `CFG_CDAC_FC0_5` writer"]
20965 pub type W = crate::W<CfgCdacFc0_5Spec>;
20966 impl core::fmt::Debug for R {
20967 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20968 write!(f, "{}", self.bits())
20969 }
20970 }
20971 impl W {}
20972 #[doc = "cfg_cdac_fc0_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20973 pub struct CfgCdacFc0_5Spec;
20974 impl crate::RegisterSpec for CfgCdacFc0_5Spec {
20975 type Ux = u32;
20976 }
20977 #[doc = "`read()` method returns [`cfg_cdac_fc0_5::R`](R) reader structure"]
20978 impl crate::Readable for CfgCdacFc0_5Spec {}
20979 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_5::W`](W) writer structure"]
20980 impl crate::Writable for CfgCdacFc0_5Spec {
20981 type Safety = crate::Unsafe;
20982 }
20983 #[doc = "`reset()` method sets CFG_CDAC_FC0_5 to value 0"]
20984 impl crate::Resettable for CfgCdacFc0_5Spec {}
20985 }
20986 #[doc = "RPT_CDAC_FC0_0 (rw) register accessor: rpt_cdac_fc0_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc0_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc0_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc0_0`] module"]
20987 #[doc(alias = "RPT_CDAC_FC0_0")]
20988 pub type RptCdacFc0_0 = crate::Reg<rpt_cdac_fc0_0::RptCdacFc0_0Spec>;
20989 #[doc = "rpt_cdac_fc0_0"]
20990 pub mod rpt_cdac_fc0_0 {
20991 #[doc = "Register `RPT_CDAC_FC0_0` reader"]
20992 pub type R = crate::R<RptCdacFc0_0Spec>;
20993 #[doc = "Register `RPT_CDAC_FC0_0` writer"]
20994 pub type W = crate::W<RptCdacFc0_0Spec>;
20995 impl core::fmt::Debug for R {
20996 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
20997 write!(f, "{}", self.bits())
20998 }
20999 }
21000 impl W {}
21001 #[doc = "rpt_cdac_fc0_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc0_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc0_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21002 pub struct RptCdacFc0_0Spec;
21003 impl crate::RegisterSpec for RptCdacFc0_0Spec {
21004 type Ux = u32;
21005 }
21006 #[doc = "`read()` method returns [`rpt_cdac_fc0_0::R`](R) reader structure"]
21007 impl crate::Readable for RptCdacFc0_0Spec {}
21008 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc0_0::W`](W) writer structure"]
21009 impl crate::Writable for RptCdacFc0_0Spec {
21010 type Safety = crate::Unsafe;
21011 }
21012 #[doc = "`reset()` method sets RPT_CDAC_FC0_0 to value 0"]
21013 impl crate::Resettable for RptCdacFc0_0Spec {}
21014 }
21015 #[doc = "CFG_CDAC_FC0_6 (rw) register accessor: cfg_cdac_fc0_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_6`] module"]
21016 #[doc(alias = "CFG_CDAC_FC0_6")]
21017 pub type CfgCdacFc0_6 = crate::Reg<cfg_cdac_fc0_6::CfgCdacFc0_6Spec>;
21018 #[doc = "cfg_cdac_fc0_6"]
21019 pub mod cfg_cdac_fc0_6 {
21020 #[doc = "Register `CFG_CDAC_FC0_6` reader"]
21021 pub type R = crate::R<CfgCdacFc0_6Spec>;
21022 #[doc = "Register `CFG_CDAC_FC0_6` writer"]
21023 pub type W = crate::W<CfgCdacFc0_6Spec>;
21024 impl core::fmt::Debug for R {
21025 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21026 write!(f, "{}", self.bits())
21027 }
21028 }
21029 impl W {}
21030 #[doc = "cfg_cdac_fc0_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21031 pub struct CfgCdacFc0_6Spec;
21032 impl crate::RegisterSpec for CfgCdacFc0_6Spec {
21033 type Ux = u32;
21034 }
21035 #[doc = "`read()` method returns [`cfg_cdac_fc0_6::R`](R) reader structure"]
21036 impl crate::Readable for CfgCdacFc0_6Spec {}
21037 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_6::W`](W) writer structure"]
21038 impl crate::Writable for CfgCdacFc0_6Spec {
21039 type Safety = crate::Unsafe;
21040 }
21041 #[doc = "`reset()` method sets CFG_CDAC_FC0_6 to value 0"]
21042 impl crate::Resettable for CfgCdacFc0_6Spec {}
21043 }
21044 #[doc = "CFG_CDAC_FC0_7 (rw) register accessor: cfg_cdac_fc0_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_7`] module"]
21045 #[doc(alias = "CFG_CDAC_FC0_7")]
21046 pub type CfgCdacFc0_7 = crate::Reg<cfg_cdac_fc0_7::CfgCdacFc0_7Spec>;
21047 #[doc = "cfg_cdac_fc0_7"]
21048 pub mod cfg_cdac_fc0_7 {
21049 #[doc = "Register `CFG_CDAC_FC0_7` reader"]
21050 pub type R = crate::R<CfgCdacFc0_7Spec>;
21051 #[doc = "Register `CFG_CDAC_FC0_7` writer"]
21052 pub type W = crate::W<CfgCdacFc0_7Spec>;
21053 impl core::fmt::Debug for R {
21054 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21055 write!(f, "{}", self.bits())
21056 }
21057 }
21058 impl W {}
21059 #[doc = "cfg_cdac_fc0_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21060 pub struct CfgCdacFc0_7Spec;
21061 impl crate::RegisterSpec for CfgCdacFc0_7Spec {
21062 type Ux = u32;
21063 }
21064 #[doc = "`read()` method returns [`cfg_cdac_fc0_7::R`](R) reader structure"]
21065 impl crate::Readable for CfgCdacFc0_7Spec {}
21066 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_7::W`](W) writer structure"]
21067 impl crate::Writable for CfgCdacFc0_7Spec {
21068 type Safety = crate::Unsafe;
21069 }
21070 #[doc = "`reset()` method sets CFG_CDAC_FC0_7 to value 0"]
21071 impl crate::Resettable for CfgCdacFc0_7Spec {}
21072 }
21073 #[doc = "CFG_CDAC_FC0_8 (rw) register accessor: cfg_cdac_fc0_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_8`] module"]
21074 #[doc(alias = "CFG_CDAC_FC0_8")]
21075 pub type CfgCdacFc0_8 = crate::Reg<cfg_cdac_fc0_8::CfgCdacFc0_8Spec>;
21076 #[doc = "cfg_cdac_fc0_8"]
21077 pub mod cfg_cdac_fc0_8 {
21078 #[doc = "Register `CFG_CDAC_FC0_8` reader"]
21079 pub type R = crate::R<CfgCdacFc0_8Spec>;
21080 #[doc = "Register `CFG_CDAC_FC0_8` writer"]
21081 pub type W = crate::W<CfgCdacFc0_8Spec>;
21082 impl core::fmt::Debug for R {
21083 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21084 write!(f, "{}", self.bits())
21085 }
21086 }
21087 impl W {}
21088 #[doc = "cfg_cdac_fc0_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21089 pub struct CfgCdacFc0_8Spec;
21090 impl crate::RegisterSpec for CfgCdacFc0_8Spec {
21091 type Ux = u32;
21092 }
21093 #[doc = "`read()` method returns [`cfg_cdac_fc0_8::R`](R) reader structure"]
21094 impl crate::Readable for CfgCdacFc0_8Spec {}
21095 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_8::W`](W) writer structure"]
21096 impl crate::Writable for CfgCdacFc0_8Spec {
21097 type Safety = crate::Unsafe;
21098 }
21099 #[doc = "`reset()` method sets CFG_CDAC_FC0_8 to value 0"]
21100 impl crate::Resettable for CfgCdacFc0_8Spec {}
21101 }
21102 #[doc = "CFG_CDAC_FC0_9 (rw) register accessor: cfg_cdac_fc0_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_9`] module"]
21103 #[doc(alias = "CFG_CDAC_FC0_9")]
21104 pub type CfgCdacFc0_9 = crate::Reg<cfg_cdac_fc0_9::CfgCdacFc0_9Spec>;
21105 #[doc = "cfg_cdac_fc0_9"]
21106 pub mod cfg_cdac_fc0_9 {
21107 #[doc = "Register `CFG_CDAC_FC0_9` reader"]
21108 pub type R = crate::R<CfgCdacFc0_9Spec>;
21109 #[doc = "Register `CFG_CDAC_FC0_9` writer"]
21110 pub type W = crate::W<CfgCdacFc0_9Spec>;
21111 impl core::fmt::Debug for R {
21112 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21113 write!(f, "{}", self.bits())
21114 }
21115 }
21116 impl W {}
21117 #[doc = "cfg_cdac_fc0_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21118 pub struct CfgCdacFc0_9Spec;
21119 impl crate::RegisterSpec for CfgCdacFc0_9Spec {
21120 type Ux = u32;
21121 }
21122 #[doc = "`read()` method returns [`cfg_cdac_fc0_9::R`](R) reader structure"]
21123 impl crate::Readable for CfgCdacFc0_9Spec {}
21124 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_9::W`](W) writer structure"]
21125 impl crate::Writable for CfgCdacFc0_9Spec {
21126 type Safety = crate::Unsafe;
21127 }
21128 #[doc = "`reset()` method sets CFG_CDAC_FC0_9 to value 0"]
21129 impl crate::Resettable for CfgCdacFc0_9Spec {}
21130 }
21131 #[doc = "CFG_CDAC_FC0_10 (rw) register accessor: cfg_cdac_fc0_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_10`] module"]
21132 #[doc(alias = "CFG_CDAC_FC0_10")]
21133 pub type CfgCdacFc0_10 = crate::Reg<cfg_cdac_fc0_10::CfgCdacFc0_10Spec>;
21134 #[doc = "cfg_cdac_fc0_10"]
21135 pub mod cfg_cdac_fc0_10 {
21136 #[doc = "Register `CFG_CDAC_FC0_10` reader"]
21137 pub type R = crate::R<CfgCdacFc0_10Spec>;
21138 #[doc = "Register `CFG_CDAC_FC0_10` writer"]
21139 pub type W = crate::W<CfgCdacFc0_10Spec>;
21140 impl core::fmt::Debug for R {
21141 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21142 write!(f, "{}", self.bits())
21143 }
21144 }
21145 impl W {}
21146 #[doc = "cfg_cdac_fc0_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21147 pub struct CfgCdacFc0_10Spec;
21148 impl crate::RegisterSpec for CfgCdacFc0_10Spec {
21149 type Ux = u32;
21150 }
21151 #[doc = "`read()` method returns [`cfg_cdac_fc0_10::R`](R) reader structure"]
21152 impl crate::Readable for CfgCdacFc0_10Spec {}
21153 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_10::W`](W) writer structure"]
21154 impl crate::Writable for CfgCdacFc0_10Spec {
21155 type Safety = crate::Unsafe;
21156 }
21157 #[doc = "`reset()` method sets CFG_CDAC_FC0_10 to value 0"]
21158 impl crate::Resettable for CfgCdacFc0_10Spec {}
21159 }
21160 #[doc = "CFG_CDAC_FC0_11 (rw) register accessor: cfg_cdac_fc0_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_11`] module"]
21161 #[doc(alias = "CFG_CDAC_FC0_11")]
21162 pub type CfgCdacFc0_11 = crate::Reg<cfg_cdac_fc0_11::CfgCdacFc0_11Spec>;
21163 #[doc = "cfg_cdac_fc0_11"]
21164 pub mod cfg_cdac_fc0_11 {
21165 #[doc = "Register `CFG_CDAC_FC0_11` reader"]
21166 pub type R = crate::R<CfgCdacFc0_11Spec>;
21167 #[doc = "Register `CFG_CDAC_FC0_11` writer"]
21168 pub type W = crate::W<CfgCdacFc0_11Spec>;
21169 impl core::fmt::Debug for R {
21170 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21171 write!(f, "{}", self.bits())
21172 }
21173 }
21174 impl W {}
21175 #[doc = "cfg_cdac_fc0_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21176 pub struct CfgCdacFc0_11Spec;
21177 impl crate::RegisterSpec for CfgCdacFc0_11Spec {
21178 type Ux = u32;
21179 }
21180 #[doc = "`read()` method returns [`cfg_cdac_fc0_11::R`](R) reader structure"]
21181 impl crate::Readable for CfgCdacFc0_11Spec {}
21182 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_11::W`](W) writer structure"]
21183 impl crate::Writable for CfgCdacFc0_11Spec {
21184 type Safety = crate::Unsafe;
21185 }
21186 #[doc = "`reset()` method sets CFG_CDAC_FC0_11 to value 0"]
21187 impl crate::Resettable for CfgCdacFc0_11Spec {}
21188 }
21189 #[doc = "CFG_CDAC_FC0_12 (rw) register accessor: cfg_cdac_fc0_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_12`] module"]
21190 #[doc(alias = "CFG_CDAC_FC0_12")]
21191 pub type CfgCdacFc0_12 = crate::Reg<cfg_cdac_fc0_12::CfgCdacFc0_12Spec>;
21192 #[doc = "cfg_cdac_fc0_12"]
21193 pub mod cfg_cdac_fc0_12 {
21194 #[doc = "Register `CFG_CDAC_FC0_12` reader"]
21195 pub type R = crate::R<CfgCdacFc0_12Spec>;
21196 #[doc = "Register `CFG_CDAC_FC0_12` writer"]
21197 pub type W = crate::W<CfgCdacFc0_12Spec>;
21198 impl core::fmt::Debug for R {
21199 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21200 write!(f, "{}", self.bits())
21201 }
21202 }
21203 impl W {}
21204 #[doc = "cfg_cdac_fc0_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21205 pub struct CfgCdacFc0_12Spec;
21206 impl crate::RegisterSpec for CfgCdacFc0_12Spec {
21207 type Ux = u32;
21208 }
21209 #[doc = "`read()` method returns [`cfg_cdac_fc0_12::R`](R) reader structure"]
21210 impl crate::Readable for CfgCdacFc0_12Spec {}
21211 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_12::W`](W) writer structure"]
21212 impl crate::Writable for CfgCdacFc0_12Spec {
21213 type Safety = crate::Unsafe;
21214 }
21215 #[doc = "`reset()` method sets CFG_CDAC_FC0_12 to value 0"]
21216 impl crate::Resettable for CfgCdacFc0_12Spec {}
21217 }
21218 #[doc = "CFG_CDAC_FC0_13 (rw) register accessor: cfg_cdac_fc0_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_13`] module"]
21219 #[doc(alias = "CFG_CDAC_FC0_13")]
21220 pub type CfgCdacFc0_13 = crate::Reg<cfg_cdac_fc0_13::CfgCdacFc0_13Spec>;
21221 #[doc = "cfg_cdac_fc0_13"]
21222 pub mod cfg_cdac_fc0_13 {
21223 #[doc = "Register `CFG_CDAC_FC0_13` reader"]
21224 pub type R = crate::R<CfgCdacFc0_13Spec>;
21225 #[doc = "Register `CFG_CDAC_FC0_13` writer"]
21226 pub type W = crate::W<CfgCdacFc0_13Spec>;
21227 impl core::fmt::Debug for R {
21228 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21229 write!(f, "{}", self.bits())
21230 }
21231 }
21232 impl W {}
21233 #[doc = "cfg_cdac_fc0_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21234 pub struct CfgCdacFc0_13Spec;
21235 impl crate::RegisterSpec for CfgCdacFc0_13Spec {
21236 type Ux = u32;
21237 }
21238 #[doc = "`read()` method returns [`cfg_cdac_fc0_13::R`](R) reader structure"]
21239 impl crate::Readable for CfgCdacFc0_13Spec {}
21240 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_13::W`](W) writer structure"]
21241 impl crate::Writable for CfgCdacFc0_13Spec {
21242 type Safety = crate::Unsafe;
21243 }
21244 #[doc = "`reset()` method sets CFG_CDAC_FC0_13 to value 0"]
21245 impl crate::Resettable for CfgCdacFc0_13Spec {}
21246 }
21247 #[doc = "CFG_CDAC_FC0_14 (rw) register accessor: cfg_cdac_fc0_14\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_14`] module"]
21248 #[doc(alias = "CFG_CDAC_FC0_14")]
21249 pub type CfgCdacFc0_14 = crate::Reg<cfg_cdac_fc0_14::CfgCdacFc0_14Spec>;
21250 #[doc = "cfg_cdac_fc0_14"]
21251 pub mod cfg_cdac_fc0_14 {
21252 #[doc = "Register `CFG_CDAC_FC0_14` reader"]
21253 pub type R = crate::R<CfgCdacFc0_14Spec>;
21254 #[doc = "Register `CFG_CDAC_FC0_14` writer"]
21255 pub type W = crate::W<CfgCdacFc0_14Spec>;
21256 impl core::fmt::Debug for R {
21257 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21258 write!(f, "{}", self.bits())
21259 }
21260 }
21261 impl W {}
21262 #[doc = "cfg_cdac_fc0_14\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21263 pub struct CfgCdacFc0_14Spec;
21264 impl crate::RegisterSpec for CfgCdacFc0_14Spec {
21265 type Ux = u32;
21266 }
21267 #[doc = "`read()` method returns [`cfg_cdac_fc0_14::R`](R) reader structure"]
21268 impl crate::Readable for CfgCdacFc0_14Spec {}
21269 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_14::W`](W) writer structure"]
21270 impl crate::Writable for CfgCdacFc0_14Spec {
21271 type Safety = crate::Unsafe;
21272 }
21273 #[doc = "`reset()` method sets CFG_CDAC_FC0_14 to value 0"]
21274 impl crate::Resettable for CfgCdacFc0_14Spec {}
21275 }
21276 #[doc = "CFG_CDAC_FC1_0 (rw) register accessor: cfg_cdac_fc1_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc1_0`] module"]
21277 #[doc(alias = "CFG_CDAC_FC1_0")]
21278 pub type CfgCdacFc1_0 = crate::Reg<cfg_cdac_fc1_0::CfgCdacFc1_0Spec>;
21279 #[doc = "cfg_cdac_fc1_0"]
21280 pub mod cfg_cdac_fc1_0 {
21281 #[doc = "Register `CFG_CDAC_FC1_0` reader"]
21282 pub type R = crate::R<CfgCdacFc1_0Spec>;
21283 #[doc = "Register `CFG_CDAC_FC1_0` writer"]
21284 pub type W = crate::W<CfgCdacFc1_0Spec>;
21285 impl core::fmt::Debug for R {
21286 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21287 write!(f, "{}", self.bits())
21288 }
21289 }
21290 impl W {}
21291 #[doc = "cfg_cdac_fc1_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21292 pub struct CfgCdacFc1_0Spec;
21293 impl crate::RegisterSpec for CfgCdacFc1_0Spec {
21294 type Ux = u32;
21295 }
21296 #[doc = "`read()` method returns [`cfg_cdac_fc1_0::R`](R) reader structure"]
21297 impl crate::Readable for CfgCdacFc1_0Spec {}
21298 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc1_0::W`](W) writer structure"]
21299 impl crate::Writable for CfgCdacFc1_0Spec {
21300 type Safety = crate::Unsafe;
21301 }
21302 #[doc = "`reset()` method sets CFG_CDAC_FC1_0 to value 0"]
21303 impl crate::Resettable for CfgCdacFc1_0Spec {}
21304 }
21305 #[doc = "CFG_CDAC_FC1_1 (rw) register accessor: cfg_cdac_fc1_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc1_1`] module"]
21306 #[doc(alias = "CFG_CDAC_FC1_1")]
21307 pub type CfgCdacFc1_1 = crate::Reg<cfg_cdac_fc1_1::CfgCdacFc1_1Spec>;
21308 #[doc = "cfg_cdac_fc1_1"]
21309 pub mod cfg_cdac_fc1_1 {
21310 #[doc = "Register `CFG_CDAC_FC1_1` reader"]
21311 pub type R = crate::R<CfgCdacFc1_1Spec>;
21312 #[doc = "Register `CFG_CDAC_FC1_1` writer"]
21313 pub type W = crate::W<CfgCdacFc1_1Spec>;
21314 impl core::fmt::Debug for R {
21315 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21316 write!(f, "{}", self.bits())
21317 }
21318 }
21319 impl W {}
21320 #[doc = "cfg_cdac_fc1_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21321 pub struct CfgCdacFc1_1Spec;
21322 impl crate::RegisterSpec for CfgCdacFc1_1Spec {
21323 type Ux = u32;
21324 }
21325 #[doc = "`read()` method returns [`cfg_cdac_fc1_1::R`](R) reader structure"]
21326 impl crate::Readable for CfgCdacFc1_1Spec {}
21327 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc1_1::W`](W) writer structure"]
21328 impl crate::Writable for CfgCdacFc1_1Spec {
21329 type Safety = crate::Unsafe;
21330 }
21331 #[doc = "`reset()` method sets CFG_CDAC_FC1_1 to value 0"]
21332 impl crate::Resettable for CfgCdacFc1_1Spec {}
21333 }
21334 #[doc = "CFG_CDAC_FC1_2 (rw) register accessor: cfg_cdac_fc1_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc1_2`] module"]
21335 #[doc(alias = "CFG_CDAC_FC1_2")]
21336 pub type CfgCdacFc1_2 = crate::Reg<cfg_cdac_fc1_2::CfgCdacFc1_2Spec>;
21337 #[doc = "cfg_cdac_fc1_2"]
21338 pub mod cfg_cdac_fc1_2 {
21339 #[doc = "Register `CFG_CDAC_FC1_2` reader"]
21340 pub type R = crate::R<CfgCdacFc1_2Spec>;
21341 #[doc = "Register `CFG_CDAC_FC1_2` writer"]
21342 pub type W = crate::W<CfgCdacFc1_2Spec>;
21343 impl core::fmt::Debug for R {
21344 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21345 write!(f, "{}", self.bits())
21346 }
21347 }
21348 impl W {}
21349 #[doc = "cfg_cdac_fc1_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21350 pub struct CfgCdacFc1_2Spec;
21351 impl crate::RegisterSpec for CfgCdacFc1_2Spec {
21352 type Ux = u32;
21353 }
21354 #[doc = "`read()` method returns [`cfg_cdac_fc1_2::R`](R) reader structure"]
21355 impl crate::Readable for CfgCdacFc1_2Spec {}
21356 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc1_2::W`](W) writer structure"]
21357 impl crate::Writable for CfgCdacFc1_2Spec {
21358 type Safety = crate::Unsafe;
21359 }
21360 #[doc = "`reset()` method sets CFG_CDAC_FC1_2 to value 0"]
21361 impl crate::Resettable for CfgCdacFc1_2Spec {}
21362 }
21363 #[doc = "CFG_CDAC_FC1_3 (rw) register accessor: cfg_cdac_fc1_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc1_3`] module"]
21364 #[doc(alias = "CFG_CDAC_FC1_3")]
21365 pub type CfgCdacFc1_3 = crate::Reg<cfg_cdac_fc1_3::CfgCdacFc1_3Spec>;
21366 #[doc = "cfg_cdac_fc1_3"]
21367 pub mod cfg_cdac_fc1_3 {
21368 #[doc = "Register `CFG_CDAC_FC1_3` reader"]
21369 pub type R = crate::R<CfgCdacFc1_3Spec>;
21370 #[doc = "Register `CFG_CDAC_FC1_3` writer"]
21371 pub type W = crate::W<CfgCdacFc1_3Spec>;
21372 impl core::fmt::Debug for R {
21373 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21374 write!(f, "{}", self.bits())
21375 }
21376 }
21377 impl W {}
21378 #[doc = "cfg_cdac_fc1_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21379 pub struct CfgCdacFc1_3Spec;
21380 impl crate::RegisterSpec for CfgCdacFc1_3Spec {
21381 type Ux = u32;
21382 }
21383 #[doc = "`read()` method returns [`cfg_cdac_fc1_3::R`](R) reader structure"]
21384 impl crate::Readable for CfgCdacFc1_3Spec {}
21385 #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc1_3::W`](W) writer structure"]
21386 impl crate::Writable for CfgCdacFc1_3Spec {
21387 type Safety = crate::Unsafe;
21388 }
21389 #[doc = "`reset()` method sets CFG_CDAC_FC1_3 to value 0"]
21390 impl crate::Resettable for CfgCdacFc1_3Spec {}
21391 }
21392 #[doc = "RPT_CDAC_FC1_0 (rw) register accessor: rpt_cdac_fc1_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc1_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc1_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc1_0`] module"]
21393 #[doc(alias = "RPT_CDAC_FC1_0")]
21394 pub type RptCdacFc1_0 = crate::Reg<rpt_cdac_fc1_0::RptCdacFc1_0Spec>;
21395 #[doc = "rpt_cdac_fc1_0"]
21396 pub mod rpt_cdac_fc1_0 {
21397 #[doc = "Register `RPT_CDAC_FC1_0` reader"]
21398 pub type R = crate::R<RptCdacFc1_0Spec>;
21399 #[doc = "Register `RPT_CDAC_FC1_0` writer"]
21400 pub type W = crate::W<RptCdacFc1_0Spec>;
21401 impl core::fmt::Debug for R {
21402 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21403 write!(f, "{}", self.bits())
21404 }
21405 }
21406 impl W {}
21407 #[doc = "rpt_cdac_fc1_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc1_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc1_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21408 pub struct RptCdacFc1_0Spec;
21409 impl crate::RegisterSpec for RptCdacFc1_0Spec {
21410 type Ux = u32;
21411 }
21412 #[doc = "`read()` method returns [`rpt_cdac_fc1_0::R`](R) reader structure"]
21413 impl crate::Readable for RptCdacFc1_0Spec {}
21414 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc1_0::W`](W) writer structure"]
21415 impl crate::Writable for RptCdacFc1_0Spec {
21416 type Safety = crate::Unsafe;
21417 }
21418 #[doc = "`reset()` method sets RPT_CDAC_FC1_0 to value 0"]
21419 impl crate::Resettable for RptCdacFc1_0Spec {}
21420 }
21421 #[doc = "RPT_CDAC_FC1_3 (rw) register accessor: rpt_cdac_fc1_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc1_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc1_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc1_3`] module"]
21422 #[doc(alias = "RPT_CDAC_FC1_3")]
21423 pub type RptCdacFc1_3 = crate::Reg<rpt_cdac_fc1_3::RptCdacFc1_3Spec>;
21424 #[doc = "rpt_cdac_fc1_3"]
21425 pub mod rpt_cdac_fc1_3 {
21426 #[doc = "Register `RPT_CDAC_FC1_3` reader"]
21427 pub type R = crate::R<RptCdacFc1_3Spec>;
21428 #[doc = "Register `RPT_CDAC_FC1_3` writer"]
21429 pub type W = crate::W<RptCdacFc1_3Spec>;
21430 impl core::fmt::Debug for R {
21431 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21432 write!(f, "{}", self.bits())
21433 }
21434 }
21435 impl W {}
21436 #[doc = "rpt_cdac_fc1_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc1_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc1_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21437 pub struct RptCdacFc1_3Spec;
21438 impl crate::RegisterSpec for RptCdacFc1_3Spec {
21439 type Ux = u32;
21440 }
21441 #[doc = "`read()` method returns [`rpt_cdac_fc1_3::R`](R) reader structure"]
21442 impl crate::Readable for RptCdacFc1_3Spec {}
21443 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc1_3::W`](W) writer structure"]
21444 impl crate::Writable for RptCdacFc1_3Spec {
21445 type Safety = crate::Unsafe;
21446 }
21447 #[doc = "`reset()` method sets RPT_CDAC_FC1_3 to value 0"]
21448 impl crate::Resettable for RptCdacFc1_3Spec {}
21449 }
21450 #[doc = "RPT_CDAC_FC3_1 (rw) register accessor: rpt_cdac_fc3_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_1`] module"]
21451 #[doc(alias = "RPT_CDAC_FC3_1")]
21452 pub type RptCdacFc3_1 = crate::Reg<rpt_cdac_fc3_1::RptCdacFc3_1Spec>;
21453 #[doc = "rpt_cdac_fc3_1"]
21454 pub mod rpt_cdac_fc3_1 {
21455 #[doc = "Register `RPT_CDAC_FC3_1` reader"]
21456 pub type R = crate::R<RptCdacFc3_1Spec>;
21457 #[doc = "Register `RPT_CDAC_FC3_1` writer"]
21458 pub type W = crate::W<RptCdacFc3_1Spec>;
21459 impl core::fmt::Debug for R {
21460 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21461 write!(f, "{}", self.bits())
21462 }
21463 }
21464 impl W {}
21465 #[doc = "rpt_cdac_fc3_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21466 pub struct RptCdacFc3_1Spec;
21467 impl crate::RegisterSpec for RptCdacFc3_1Spec {
21468 type Ux = u32;
21469 }
21470 #[doc = "`read()` method returns [`rpt_cdac_fc3_1::R`](R) reader structure"]
21471 impl crate::Readable for RptCdacFc3_1Spec {}
21472 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_1::W`](W) writer structure"]
21473 impl crate::Writable for RptCdacFc3_1Spec {
21474 type Safety = crate::Unsafe;
21475 }
21476 #[doc = "`reset()` method sets RPT_CDAC_FC3_1 to value 0"]
21477 impl crate::Resettable for RptCdacFc3_1Spec {}
21478 }
21479 #[doc = "RPT_CDAC_FC3_2 (rw) register accessor: rpt_cdac_fc3_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_2`] module"]
21480 #[doc(alias = "RPT_CDAC_FC3_2")]
21481 pub type RptCdacFc3_2 = crate::Reg<rpt_cdac_fc3_2::RptCdacFc3_2Spec>;
21482 #[doc = "rpt_cdac_fc3_2"]
21483 pub mod rpt_cdac_fc3_2 {
21484 #[doc = "Register `RPT_CDAC_FC3_2` reader"]
21485 pub type R = crate::R<RptCdacFc3_2Spec>;
21486 #[doc = "Register `RPT_CDAC_FC3_2` writer"]
21487 pub type W = crate::W<RptCdacFc3_2Spec>;
21488 impl core::fmt::Debug for R {
21489 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21490 write!(f, "{}", self.bits())
21491 }
21492 }
21493 impl W {}
21494 #[doc = "rpt_cdac_fc3_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21495 pub struct RptCdacFc3_2Spec;
21496 impl crate::RegisterSpec for RptCdacFc3_2Spec {
21497 type Ux = u32;
21498 }
21499 #[doc = "`read()` method returns [`rpt_cdac_fc3_2::R`](R) reader structure"]
21500 impl crate::Readable for RptCdacFc3_2Spec {}
21501 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_2::W`](W) writer structure"]
21502 impl crate::Writable for RptCdacFc3_2Spec {
21503 type Safety = crate::Unsafe;
21504 }
21505 #[doc = "`reset()` method sets RPT_CDAC_FC3_2 to value 0"]
21506 impl crate::Resettable for RptCdacFc3_2Spec {}
21507 }
21508 #[doc = "RPT_CDAC_FC3_3 (rw) register accessor: rpt_cdac_fc3_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_3`] module"]
21509 #[doc(alias = "RPT_CDAC_FC3_3")]
21510 pub type RptCdacFc3_3 = crate::Reg<rpt_cdac_fc3_3::RptCdacFc3_3Spec>;
21511 #[doc = "rpt_cdac_fc3_3"]
21512 pub mod rpt_cdac_fc3_3 {
21513 #[doc = "Register `RPT_CDAC_FC3_3` reader"]
21514 pub type R = crate::R<RptCdacFc3_3Spec>;
21515 #[doc = "Register `RPT_CDAC_FC3_3` writer"]
21516 pub type W = crate::W<RptCdacFc3_3Spec>;
21517 impl core::fmt::Debug for R {
21518 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21519 write!(f, "{}", self.bits())
21520 }
21521 }
21522 impl W {}
21523 #[doc = "rpt_cdac_fc3_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21524 pub struct RptCdacFc3_3Spec;
21525 impl crate::RegisterSpec for RptCdacFc3_3Spec {
21526 type Ux = u32;
21527 }
21528 #[doc = "`read()` method returns [`rpt_cdac_fc3_3::R`](R) reader structure"]
21529 impl crate::Readable for RptCdacFc3_3Spec {}
21530 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_3::W`](W) writer structure"]
21531 impl crate::Writable for RptCdacFc3_3Spec {
21532 type Safety = crate::Unsafe;
21533 }
21534 #[doc = "`reset()` method sets RPT_CDAC_FC3_3 to value 0"]
21535 impl crate::Resettable for RptCdacFc3_3Spec {}
21536 }
21537 #[doc = "RPT_CDAC_FC3_4 (rw) register accessor: rpt_cdac_fc3_4\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_4`] module"]
21538 #[doc(alias = "RPT_CDAC_FC3_4")]
21539 pub type RptCdacFc3_4 = crate::Reg<rpt_cdac_fc3_4::RptCdacFc3_4Spec>;
21540 #[doc = "rpt_cdac_fc3_4"]
21541 pub mod rpt_cdac_fc3_4 {
21542 #[doc = "Register `RPT_CDAC_FC3_4` reader"]
21543 pub type R = crate::R<RptCdacFc3_4Spec>;
21544 #[doc = "Register `RPT_CDAC_FC3_4` writer"]
21545 pub type W = crate::W<RptCdacFc3_4Spec>;
21546 impl core::fmt::Debug for R {
21547 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21548 write!(f, "{}", self.bits())
21549 }
21550 }
21551 impl W {}
21552 #[doc = "rpt_cdac_fc3_4\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21553 pub struct RptCdacFc3_4Spec;
21554 impl crate::RegisterSpec for RptCdacFc3_4Spec {
21555 type Ux = u32;
21556 }
21557 #[doc = "`read()` method returns [`rpt_cdac_fc3_4::R`](R) reader structure"]
21558 impl crate::Readable for RptCdacFc3_4Spec {}
21559 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_4::W`](W) writer structure"]
21560 impl crate::Writable for RptCdacFc3_4Spec {
21561 type Safety = crate::Unsafe;
21562 }
21563 #[doc = "`reset()` method sets RPT_CDAC_FC3_4 to value 0"]
21564 impl crate::Resettable for RptCdacFc3_4Spec {}
21565 }
21566 #[doc = "RPT_CDAC_FC3_5 (rw) register accessor: rpt_cdac_fc3_5\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_5`] module"]
21567 #[doc(alias = "RPT_CDAC_FC3_5")]
21568 pub type RptCdacFc3_5 = crate::Reg<rpt_cdac_fc3_5::RptCdacFc3_5Spec>;
21569 #[doc = "rpt_cdac_fc3_5"]
21570 pub mod rpt_cdac_fc3_5 {
21571 #[doc = "Register `RPT_CDAC_FC3_5` reader"]
21572 pub type R = crate::R<RptCdacFc3_5Spec>;
21573 #[doc = "Register `RPT_CDAC_FC3_5` writer"]
21574 pub type W = crate::W<RptCdacFc3_5Spec>;
21575 impl core::fmt::Debug for R {
21576 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21577 write!(f, "{}", self.bits())
21578 }
21579 }
21580 impl W {}
21581 #[doc = "rpt_cdac_fc3_5\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21582 pub struct RptCdacFc3_5Spec;
21583 impl crate::RegisterSpec for RptCdacFc3_5Spec {
21584 type Ux = u32;
21585 }
21586 #[doc = "`read()` method returns [`rpt_cdac_fc3_5::R`](R) reader structure"]
21587 impl crate::Readable for RptCdacFc3_5Spec {}
21588 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_5::W`](W) writer structure"]
21589 impl crate::Writable for RptCdacFc3_5Spec {
21590 type Safety = crate::Unsafe;
21591 }
21592 #[doc = "`reset()` method sets RPT_CDAC_FC3_5 to value 0"]
21593 impl crate::Resettable for RptCdacFc3_5Spec {}
21594 }
21595 #[doc = "RPT_CDAC_FC3_6 (rw) register accessor: rpt_cdac_fc3_6\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_6`] module"]
21596 #[doc(alias = "RPT_CDAC_FC3_6")]
21597 pub type RptCdacFc3_6 = crate::Reg<rpt_cdac_fc3_6::RptCdacFc3_6Spec>;
21598 #[doc = "rpt_cdac_fc3_6"]
21599 pub mod rpt_cdac_fc3_6 {
21600 #[doc = "Register `RPT_CDAC_FC3_6` reader"]
21601 pub type R = crate::R<RptCdacFc3_6Spec>;
21602 #[doc = "Register `RPT_CDAC_FC3_6` writer"]
21603 pub type W = crate::W<RptCdacFc3_6Spec>;
21604 impl core::fmt::Debug for R {
21605 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21606 write!(f, "{}", self.bits())
21607 }
21608 }
21609 impl W {}
21610 #[doc = "rpt_cdac_fc3_6\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21611 pub struct RptCdacFc3_6Spec;
21612 impl crate::RegisterSpec for RptCdacFc3_6Spec {
21613 type Ux = u32;
21614 }
21615 #[doc = "`read()` method returns [`rpt_cdac_fc3_6::R`](R) reader structure"]
21616 impl crate::Readable for RptCdacFc3_6Spec {}
21617 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_6::W`](W) writer structure"]
21618 impl crate::Writable for RptCdacFc3_6Spec {
21619 type Safety = crate::Unsafe;
21620 }
21621 #[doc = "`reset()` method sets RPT_CDAC_FC3_6 to value 0"]
21622 impl crate::Resettable for RptCdacFc3_6Spec {}
21623 }
21624 #[doc = "RPT_CDAC_FC3_7 (rw) register accessor: rpt_cdac_fc3_7\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_7`] module"]
21625 #[doc(alias = "RPT_CDAC_FC3_7")]
21626 pub type RptCdacFc3_7 = crate::Reg<rpt_cdac_fc3_7::RptCdacFc3_7Spec>;
21627 #[doc = "rpt_cdac_fc3_7"]
21628 pub mod rpt_cdac_fc3_7 {
21629 #[doc = "Register `RPT_CDAC_FC3_7` reader"]
21630 pub type R = crate::R<RptCdacFc3_7Spec>;
21631 #[doc = "Register `RPT_CDAC_FC3_7` writer"]
21632 pub type W = crate::W<RptCdacFc3_7Spec>;
21633 impl core::fmt::Debug for R {
21634 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21635 write!(f, "{}", self.bits())
21636 }
21637 }
21638 impl W {}
21639 #[doc = "rpt_cdac_fc3_7\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21640 pub struct RptCdacFc3_7Spec;
21641 impl crate::RegisterSpec for RptCdacFc3_7Spec {
21642 type Ux = u32;
21643 }
21644 #[doc = "`read()` method returns [`rpt_cdac_fc3_7::R`](R) reader structure"]
21645 impl crate::Readable for RptCdacFc3_7Spec {}
21646 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_7::W`](W) writer structure"]
21647 impl crate::Writable for RptCdacFc3_7Spec {
21648 type Safety = crate::Unsafe;
21649 }
21650 #[doc = "`reset()` method sets RPT_CDAC_FC3_7 to value 0"]
21651 impl crate::Resettable for RptCdacFc3_7Spec {}
21652 }
21653 #[doc = "RPT_CDAC_FC3_8 (rw) register accessor: rpt_cdac_fc3_8\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_8`] module"]
21654 #[doc(alias = "RPT_CDAC_FC3_8")]
21655 pub type RptCdacFc3_8 = crate::Reg<rpt_cdac_fc3_8::RptCdacFc3_8Spec>;
21656 #[doc = "rpt_cdac_fc3_8"]
21657 pub mod rpt_cdac_fc3_8 {
21658 #[doc = "Register `RPT_CDAC_FC3_8` reader"]
21659 pub type R = crate::R<RptCdacFc3_8Spec>;
21660 #[doc = "Register `RPT_CDAC_FC3_8` writer"]
21661 pub type W = crate::W<RptCdacFc3_8Spec>;
21662 impl core::fmt::Debug for R {
21663 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21664 write!(f, "{}", self.bits())
21665 }
21666 }
21667 impl W {}
21668 #[doc = "rpt_cdac_fc3_8\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21669 pub struct RptCdacFc3_8Spec;
21670 impl crate::RegisterSpec for RptCdacFc3_8Spec {
21671 type Ux = u32;
21672 }
21673 #[doc = "`read()` method returns [`rpt_cdac_fc3_8::R`](R) reader structure"]
21674 impl crate::Readable for RptCdacFc3_8Spec {}
21675 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_8::W`](W) writer structure"]
21676 impl crate::Writable for RptCdacFc3_8Spec {
21677 type Safety = crate::Unsafe;
21678 }
21679 #[doc = "`reset()` method sets RPT_CDAC_FC3_8 to value 0"]
21680 impl crate::Resettable for RptCdacFc3_8Spec {}
21681 }
21682 #[doc = "RPT_CDAC_FC3_9 (rw) register accessor: rpt_cdac_fc3_9\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_9`] module"]
21683 #[doc(alias = "RPT_CDAC_FC3_9")]
21684 pub type RptCdacFc3_9 = crate::Reg<rpt_cdac_fc3_9::RptCdacFc3_9Spec>;
21685 #[doc = "rpt_cdac_fc3_9"]
21686 pub mod rpt_cdac_fc3_9 {
21687 #[doc = "Register `RPT_CDAC_FC3_9` reader"]
21688 pub type R = crate::R<RptCdacFc3_9Spec>;
21689 #[doc = "Register `RPT_CDAC_FC3_9` writer"]
21690 pub type W = crate::W<RptCdacFc3_9Spec>;
21691 impl core::fmt::Debug for R {
21692 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21693 write!(f, "{}", self.bits())
21694 }
21695 }
21696 impl W {}
21697 #[doc = "rpt_cdac_fc3_9\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21698 pub struct RptCdacFc3_9Spec;
21699 impl crate::RegisterSpec for RptCdacFc3_9Spec {
21700 type Ux = u32;
21701 }
21702 #[doc = "`read()` method returns [`rpt_cdac_fc3_9::R`](R) reader structure"]
21703 impl crate::Readable for RptCdacFc3_9Spec {}
21704 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_9::W`](W) writer structure"]
21705 impl crate::Writable for RptCdacFc3_9Spec {
21706 type Safety = crate::Unsafe;
21707 }
21708 #[doc = "`reset()` method sets RPT_CDAC_FC3_9 to value 0"]
21709 impl crate::Resettable for RptCdacFc3_9Spec {}
21710 }
21711 #[doc = "RPT_CDAC_FC3_10 (rw) register accessor: rpt_cdac_fc3_10\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_10`] module"]
21712 #[doc(alias = "RPT_CDAC_FC3_10")]
21713 pub type RptCdacFc3_10 = crate::Reg<rpt_cdac_fc3_10::RptCdacFc3_10Spec>;
21714 #[doc = "rpt_cdac_fc3_10"]
21715 pub mod rpt_cdac_fc3_10 {
21716 #[doc = "Register `RPT_CDAC_FC3_10` reader"]
21717 pub type R = crate::R<RptCdacFc3_10Spec>;
21718 #[doc = "Register `RPT_CDAC_FC3_10` writer"]
21719 pub type W = crate::W<RptCdacFc3_10Spec>;
21720 impl core::fmt::Debug for R {
21721 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21722 write!(f, "{}", self.bits())
21723 }
21724 }
21725 impl W {}
21726 #[doc = "rpt_cdac_fc3_10\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21727 pub struct RptCdacFc3_10Spec;
21728 impl crate::RegisterSpec for RptCdacFc3_10Spec {
21729 type Ux = u32;
21730 }
21731 #[doc = "`read()` method returns [`rpt_cdac_fc3_10::R`](R) reader structure"]
21732 impl crate::Readable for RptCdacFc3_10Spec {}
21733 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_10::W`](W) writer structure"]
21734 impl crate::Writable for RptCdacFc3_10Spec {
21735 type Safety = crate::Unsafe;
21736 }
21737 #[doc = "`reset()` method sets RPT_CDAC_FC3_10 to value 0"]
21738 impl crate::Resettable for RptCdacFc3_10Spec {}
21739 }
21740 #[doc = "RPT_CDAC_FC3_11 (rw) register accessor: rpt_cdac_fc3_11\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_11`] module"]
21741 #[doc(alias = "RPT_CDAC_FC3_11")]
21742 pub type RptCdacFc3_11 = crate::Reg<rpt_cdac_fc3_11::RptCdacFc3_11Spec>;
21743 #[doc = "rpt_cdac_fc3_11"]
21744 pub mod rpt_cdac_fc3_11 {
21745 #[doc = "Register `RPT_CDAC_FC3_11` reader"]
21746 pub type R = crate::R<RptCdacFc3_11Spec>;
21747 #[doc = "Register `RPT_CDAC_FC3_11` writer"]
21748 pub type W = crate::W<RptCdacFc3_11Spec>;
21749 impl core::fmt::Debug for R {
21750 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21751 write!(f, "{}", self.bits())
21752 }
21753 }
21754 impl W {}
21755 #[doc = "rpt_cdac_fc3_11\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21756 pub struct RptCdacFc3_11Spec;
21757 impl crate::RegisterSpec for RptCdacFc3_11Spec {
21758 type Ux = u32;
21759 }
21760 #[doc = "`read()` method returns [`rpt_cdac_fc3_11::R`](R) reader structure"]
21761 impl crate::Readable for RptCdacFc3_11Spec {}
21762 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_11::W`](W) writer structure"]
21763 impl crate::Writable for RptCdacFc3_11Spec {
21764 type Safety = crate::Unsafe;
21765 }
21766 #[doc = "`reset()` method sets RPT_CDAC_FC3_11 to value 0"]
21767 impl crate::Resettable for RptCdacFc3_11Spec {}
21768 }
21769 #[doc = "RPT_CDAC_FC3_12 (rw) register accessor: rpt_cdac_fc3_12\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_12`] module"]
21770 #[doc(alias = "RPT_CDAC_FC3_12")]
21771 pub type RptCdacFc3_12 = crate::Reg<rpt_cdac_fc3_12::RptCdacFc3_12Spec>;
21772 #[doc = "rpt_cdac_fc3_12"]
21773 pub mod rpt_cdac_fc3_12 {
21774 #[doc = "Register `RPT_CDAC_FC3_12` reader"]
21775 pub type R = crate::R<RptCdacFc3_12Spec>;
21776 #[doc = "Register `RPT_CDAC_FC3_12` writer"]
21777 pub type W = crate::W<RptCdacFc3_12Spec>;
21778 impl core::fmt::Debug for R {
21779 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21780 write!(f, "{}", self.bits())
21781 }
21782 }
21783 impl W {}
21784 #[doc = "rpt_cdac_fc3_12\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21785 pub struct RptCdacFc3_12Spec;
21786 impl crate::RegisterSpec for RptCdacFc3_12Spec {
21787 type Ux = u32;
21788 }
21789 #[doc = "`read()` method returns [`rpt_cdac_fc3_12::R`](R) reader structure"]
21790 impl crate::Readable for RptCdacFc3_12Spec {}
21791 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_12::W`](W) writer structure"]
21792 impl crate::Writable for RptCdacFc3_12Spec {
21793 type Safety = crate::Unsafe;
21794 }
21795 #[doc = "`reset()` method sets RPT_CDAC_FC3_12 to value 0"]
21796 impl crate::Resettable for RptCdacFc3_12Spec {}
21797 }
21798 #[doc = "RPT_CDAC_FC3_13 (rw) register accessor: rpt_cdac_fc3_13\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_13`] module"]
21799 #[doc(alias = "RPT_CDAC_FC3_13")]
21800 pub type RptCdacFc3_13 = crate::Reg<rpt_cdac_fc3_13::RptCdacFc3_13Spec>;
21801 #[doc = "rpt_cdac_fc3_13"]
21802 pub mod rpt_cdac_fc3_13 {
21803 #[doc = "Register `RPT_CDAC_FC3_13` reader"]
21804 pub type R = crate::R<RptCdacFc3_13Spec>;
21805 #[doc = "Register `RPT_CDAC_FC3_13` writer"]
21806 pub type W = crate::W<RptCdacFc3_13Spec>;
21807 impl core::fmt::Debug for R {
21808 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21809 write!(f, "{}", self.bits())
21810 }
21811 }
21812 impl W {}
21813 #[doc = "rpt_cdac_fc3_13\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21814 pub struct RptCdacFc3_13Spec;
21815 impl crate::RegisterSpec for RptCdacFc3_13Spec {
21816 type Ux = u32;
21817 }
21818 #[doc = "`read()` method returns [`rpt_cdac_fc3_13::R`](R) reader structure"]
21819 impl crate::Readable for RptCdacFc3_13Spec {}
21820 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_13::W`](W) writer structure"]
21821 impl crate::Writable for RptCdacFc3_13Spec {
21822 type Safety = crate::Unsafe;
21823 }
21824 #[doc = "`reset()` method sets RPT_CDAC_FC3_13 to value 0"]
21825 impl crate::Resettable for RptCdacFc3_13Spec {}
21826 }
21827 #[doc = "RPT_CDAC_FC3_14 (rw) register accessor: rpt_cdac_fc3_14\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_14`] module"]
21828 #[doc(alias = "RPT_CDAC_FC3_14")]
21829 pub type RptCdacFc3_14 = crate::Reg<rpt_cdac_fc3_14::RptCdacFc3_14Spec>;
21830 #[doc = "rpt_cdac_fc3_14"]
21831 pub mod rpt_cdac_fc3_14 {
21832 #[doc = "Register `RPT_CDAC_FC3_14` reader"]
21833 pub type R = crate::R<RptCdacFc3_14Spec>;
21834 #[doc = "Register `RPT_CDAC_FC3_14` writer"]
21835 pub type W = crate::W<RptCdacFc3_14Spec>;
21836 impl core::fmt::Debug for R {
21837 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21838 write!(f, "{}", self.bits())
21839 }
21840 }
21841 impl W {}
21842 #[doc = "rpt_cdac_fc3_14\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21843 pub struct RptCdacFc3_14Spec;
21844 impl crate::RegisterSpec for RptCdacFc3_14Spec {
21845 type Ux = u32;
21846 }
21847 #[doc = "`read()` method returns [`rpt_cdac_fc3_14::R`](R) reader structure"]
21848 impl crate::Readable for RptCdacFc3_14Spec {}
21849 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_14::W`](W) writer structure"]
21850 impl crate::Writable for RptCdacFc3_14Spec {
21851 type Safety = crate::Unsafe;
21852 }
21853 #[doc = "`reset()` method sets RPT_CDAC_FC3_14 to value 0"]
21854 impl crate::Resettable for RptCdacFc3_14Spec {}
21855 }
21856 #[doc = "RPT_CDAC_FC3_15 (rw) register accessor: rpt_cdac_fc3_15\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_15`] module"]
21857 #[doc(alias = "RPT_CDAC_FC3_15")]
21858 pub type RptCdacFc3_15 = crate::Reg<rpt_cdac_fc3_15::RptCdacFc3_15Spec>;
21859 #[doc = "rpt_cdac_fc3_15"]
21860 pub mod rpt_cdac_fc3_15 {
21861 #[doc = "Register `RPT_CDAC_FC3_15` reader"]
21862 pub type R = crate::R<RptCdacFc3_15Spec>;
21863 #[doc = "Register `RPT_CDAC_FC3_15` writer"]
21864 pub type W = crate::W<RptCdacFc3_15Spec>;
21865 impl core::fmt::Debug for R {
21866 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21867 write!(f, "{}", self.bits())
21868 }
21869 }
21870 impl W {}
21871 #[doc = "rpt_cdac_fc3_15\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21872 pub struct RptCdacFc3_15Spec;
21873 impl crate::RegisterSpec for RptCdacFc3_15Spec {
21874 type Ux = u32;
21875 }
21876 #[doc = "`read()` method returns [`rpt_cdac_fc3_15::R`](R) reader structure"]
21877 impl crate::Readable for RptCdacFc3_15Spec {}
21878 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_15::W`](W) writer structure"]
21879 impl crate::Writable for RptCdacFc3_15Spec {
21880 type Safety = crate::Unsafe;
21881 }
21882 #[doc = "`reset()` method sets RPT_CDAC_FC3_15 to value 0"]
21883 impl crate::Resettable for RptCdacFc3_15Spec {}
21884 }
21885 #[doc = "RPT_CDAC_FC3_16 (rw) register accessor: rpt_cdac_fc3_16\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_16`] module"]
21886 #[doc(alias = "RPT_CDAC_FC3_16")]
21887 pub type RptCdacFc3_16 = crate::Reg<rpt_cdac_fc3_16::RptCdacFc3_16Spec>;
21888 #[doc = "rpt_cdac_fc3_16"]
21889 pub mod rpt_cdac_fc3_16 {
21890 #[doc = "Register `RPT_CDAC_FC3_16` reader"]
21891 pub type R = crate::R<RptCdacFc3_16Spec>;
21892 #[doc = "Register `RPT_CDAC_FC3_16` writer"]
21893 pub type W = crate::W<RptCdacFc3_16Spec>;
21894 impl core::fmt::Debug for R {
21895 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21896 write!(f, "{}", self.bits())
21897 }
21898 }
21899 impl W {}
21900 #[doc = "rpt_cdac_fc3_16\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21901 pub struct RptCdacFc3_16Spec;
21902 impl crate::RegisterSpec for RptCdacFc3_16Spec {
21903 type Ux = u32;
21904 }
21905 #[doc = "`read()` method returns [`rpt_cdac_fc3_16::R`](R) reader structure"]
21906 impl crate::Readable for RptCdacFc3_16Spec {}
21907 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_16::W`](W) writer structure"]
21908 impl crate::Writable for RptCdacFc3_16Spec {
21909 type Safety = crate::Unsafe;
21910 }
21911 #[doc = "`reset()` method sets RPT_CDAC_FC3_16 to value 0"]
21912 impl crate::Resettable for RptCdacFc3_16Spec {}
21913 }
21914 #[doc = "RPT_CDAC_FC3_17 (rw) register accessor: rpt_cdac_fc3_17\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_17`] module"]
21915 #[doc(alias = "RPT_CDAC_FC3_17")]
21916 pub type RptCdacFc3_17 = crate::Reg<rpt_cdac_fc3_17::RptCdacFc3_17Spec>;
21917 #[doc = "rpt_cdac_fc3_17"]
21918 pub mod rpt_cdac_fc3_17 {
21919 #[doc = "Register `RPT_CDAC_FC3_17` reader"]
21920 pub type R = crate::R<RptCdacFc3_17Spec>;
21921 #[doc = "Register `RPT_CDAC_FC3_17` writer"]
21922 pub type W = crate::W<RptCdacFc3_17Spec>;
21923 impl core::fmt::Debug for R {
21924 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21925 write!(f, "{}", self.bits())
21926 }
21927 }
21928 impl W {}
21929 #[doc = "rpt_cdac_fc3_17\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21930 pub struct RptCdacFc3_17Spec;
21931 impl crate::RegisterSpec for RptCdacFc3_17Spec {
21932 type Ux = u32;
21933 }
21934 #[doc = "`read()` method returns [`rpt_cdac_fc3_17::R`](R) reader structure"]
21935 impl crate::Readable for RptCdacFc3_17Spec {}
21936 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_17::W`](W) writer structure"]
21937 impl crate::Writable for RptCdacFc3_17Spec {
21938 type Safety = crate::Unsafe;
21939 }
21940 #[doc = "`reset()` method sets RPT_CDAC_FC3_17 to value 0"]
21941 impl crate::Resettable for RptCdacFc3_17Spec {}
21942 }
21943 #[doc = "RPT_CDAC_FC3_18 (rw) register accessor: rpt_cdac_fc3_18\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_18`] module"]
21944 #[doc(alias = "RPT_CDAC_FC3_18")]
21945 pub type RptCdacFc3_18 = crate::Reg<rpt_cdac_fc3_18::RptCdacFc3_18Spec>;
21946 #[doc = "rpt_cdac_fc3_18"]
21947 pub mod rpt_cdac_fc3_18 {
21948 #[doc = "Register `RPT_CDAC_FC3_18` reader"]
21949 pub type R = crate::R<RptCdacFc3_18Spec>;
21950 #[doc = "Register `RPT_CDAC_FC3_18` writer"]
21951 pub type W = crate::W<RptCdacFc3_18Spec>;
21952 impl core::fmt::Debug for R {
21953 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21954 write!(f, "{}", self.bits())
21955 }
21956 }
21957 impl W {}
21958 #[doc = "rpt_cdac_fc3_18\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21959 pub struct RptCdacFc3_18Spec;
21960 impl crate::RegisterSpec for RptCdacFc3_18Spec {
21961 type Ux = u32;
21962 }
21963 #[doc = "`read()` method returns [`rpt_cdac_fc3_18::R`](R) reader structure"]
21964 impl crate::Readable for RptCdacFc3_18Spec {}
21965 #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_18::W`](W) writer structure"]
21966 impl crate::Writable for RptCdacFc3_18Spec {
21967 type Safety = crate::Unsafe;
21968 }
21969 #[doc = "`reset()` method sets RPT_CDAC_FC3_18 to value 0"]
21970 impl crate::Resettable for RptCdacFc3_18Spec {}
21971 }
21972 #[doc = "CFG_DCOC_CAL_0 (rw) register accessor: cfg_dcoc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_0`] module"]
21973 #[doc(alias = "CFG_DCOC_CAL_0")]
21974 pub type CfgDcocCal0 = crate::Reg<cfg_dcoc_cal_0::CfgDcocCal0Spec>;
21975 #[doc = "cfg_dcoc_cal_0"]
21976 pub mod cfg_dcoc_cal_0 {
21977 #[doc = "Register `CFG_DCOC_CAL_0` reader"]
21978 pub type R = crate::R<CfgDcocCal0Spec>;
21979 #[doc = "Register `CFG_DCOC_CAL_0` writer"]
21980 pub type W = crate::W<CfgDcocCal0Spec>;
21981 impl core::fmt::Debug for R {
21982 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21983 write!(f, "{}", self.bits())
21984 }
21985 }
21986 impl W {}
21987 #[doc = "cfg_dcoc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21988 pub struct CfgDcocCal0Spec;
21989 impl crate::RegisterSpec for CfgDcocCal0Spec {
21990 type Ux = u32;
21991 }
21992 #[doc = "`read()` method returns [`cfg_dcoc_cal_0::R`](R) reader structure"]
21993 impl crate::Readable for CfgDcocCal0Spec {}
21994 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_0::W`](W) writer structure"]
21995 impl crate::Writable for CfgDcocCal0Spec {
21996 type Safety = crate::Unsafe;
21997 }
21998 #[doc = "`reset()` method sets CFG_DCOC_CAL_0 to value 0"]
21999 impl crate::Resettable for CfgDcocCal0Spec {}
22000 }
22001 #[doc = "CFG_DCOC_CAL_1 (rw) register accessor: cfg_dcoc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_1`] module"]
22002 #[doc(alias = "CFG_DCOC_CAL_1")]
22003 pub type CfgDcocCal1 = crate::Reg<cfg_dcoc_cal_1::CfgDcocCal1Spec>;
22004 #[doc = "cfg_dcoc_cal_1"]
22005 pub mod cfg_dcoc_cal_1 {
22006 #[doc = "Register `CFG_DCOC_CAL_1` reader"]
22007 pub type R = crate::R<CfgDcocCal1Spec>;
22008 #[doc = "Register `CFG_DCOC_CAL_1` writer"]
22009 pub type W = crate::W<CfgDcocCal1Spec>;
22010 impl core::fmt::Debug for R {
22011 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22012 write!(f, "{}", self.bits())
22013 }
22014 }
22015 impl W {}
22016 #[doc = "cfg_dcoc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22017 pub struct CfgDcocCal1Spec;
22018 impl crate::RegisterSpec for CfgDcocCal1Spec {
22019 type Ux = u32;
22020 }
22021 #[doc = "`read()` method returns [`cfg_dcoc_cal_1::R`](R) reader structure"]
22022 impl crate::Readable for CfgDcocCal1Spec {}
22023 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_1::W`](W) writer structure"]
22024 impl crate::Writable for CfgDcocCal1Spec {
22025 type Safety = crate::Unsafe;
22026 }
22027 #[doc = "`reset()` method sets CFG_DCOC_CAL_1 to value 0"]
22028 impl crate::Resettable for CfgDcocCal1Spec {}
22029 }
22030 #[doc = "CFG_DCOC_CAL_2 (rw) register accessor: cfg_dcoc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_2`] module"]
22031 #[doc(alias = "CFG_DCOC_CAL_2")]
22032 pub type CfgDcocCal2 = crate::Reg<cfg_dcoc_cal_2::CfgDcocCal2Spec>;
22033 #[doc = "cfg_dcoc_cal_2"]
22034 pub mod cfg_dcoc_cal_2 {
22035 #[doc = "Register `CFG_DCOC_CAL_2` reader"]
22036 pub type R = crate::R<CfgDcocCal2Spec>;
22037 #[doc = "Register `CFG_DCOC_CAL_2` writer"]
22038 pub type W = crate::W<CfgDcocCal2Spec>;
22039 impl core::fmt::Debug for R {
22040 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22041 write!(f, "{}", self.bits())
22042 }
22043 }
22044 impl W {}
22045 #[doc = "cfg_dcoc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22046 pub struct CfgDcocCal2Spec;
22047 impl crate::RegisterSpec for CfgDcocCal2Spec {
22048 type Ux = u32;
22049 }
22050 #[doc = "`read()` method returns [`cfg_dcoc_cal_2::R`](R) reader structure"]
22051 impl crate::Readable for CfgDcocCal2Spec {}
22052 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_2::W`](W) writer structure"]
22053 impl crate::Writable for CfgDcocCal2Spec {
22054 type Safety = crate::Unsafe;
22055 }
22056 #[doc = "`reset()` method sets CFG_DCOC_CAL_2 to value 0"]
22057 impl crate::Resettable for CfgDcocCal2Spec {}
22058 }
22059 #[doc = "CFG_DCOC_CAL_3 (rw) register accessor: cfg_dcoc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_3`] module"]
22060 #[doc(alias = "CFG_DCOC_CAL_3")]
22061 pub type CfgDcocCal3 = crate::Reg<cfg_dcoc_cal_3::CfgDcocCal3Spec>;
22062 #[doc = "cfg_dcoc_cal_3"]
22063 pub mod cfg_dcoc_cal_3 {
22064 #[doc = "Register `CFG_DCOC_CAL_3` reader"]
22065 pub type R = crate::R<CfgDcocCal3Spec>;
22066 #[doc = "Register `CFG_DCOC_CAL_3` writer"]
22067 pub type W = crate::W<CfgDcocCal3Spec>;
22068 impl core::fmt::Debug for R {
22069 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22070 write!(f, "{}", self.bits())
22071 }
22072 }
22073 impl W {}
22074 #[doc = "cfg_dcoc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22075 pub struct CfgDcocCal3Spec;
22076 impl crate::RegisterSpec for CfgDcocCal3Spec {
22077 type Ux = u32;
22078 }
22079 #[doc = "`read()` method returns [`cfg_dcoc_cal_3::R`](R) reader structure"]
22080 impl crate::Readable for CfgDcocCal3Spec {}
22081 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_3::W`](W) writer structure"]
22082 impl crate::Writable for CfgDcocCal3Spec {
22083 type Safety = crate::Unsafe;
22084 }
22085 #[doc = "`reset()` method sets CFG_DCOC_CAL_3 to value 0"]
22086 impl crate::Resettable for CfgDcocCal3Spec {}
22087 }
22088 #[doc = "CFG_DCOC_CAL_4 (rw) register accessor: cfg_dcoc_cal_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_4`] module"]
22089 #[doc(alias = "CFG_DCOC_CAL_4")]
22090 pub type CfgDcocCal4 = crate::Reg<cfg_dcoc_cal_4::CfgDcocCal4Spec>;
22091 #[doc = "cfg_dcoc_cal_4"]
22092 pub mod cfg_dcoc_cal_4 {
22093 #[doc = "Register `CFG_DCOC_CAL_4` reader"]
22094 pub type R = crate::R<CfgDcocCal4Spec>;
22095 #[doc = "Register `CFG_DCOC_CAL_4` writer"]
22096 pub type W = crate::W<CfgDcocCal4Spec>;
22097 impl core::fmt::Debug for R {
22098 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22099 write!(f, "{}", self.bits())
22100 }
22101 }
22102 impl W {}
22103 #[doc = "cfg_dcoc_cal_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22104 pub struct CfgDcocCal4Spec;
22105 impl crate::RegisterSpec for CfgDcocCal4Spec {
22106 type Ux = u32;
22107 }
22108 #[doc = "`read()` method returns [`cfg_dcoc_cal_4::R`](R) reader structure"]
22109 impl crate::Readable for CfgDcocCal4Spec {}
22110 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_4::W`](W) writer structure"]
22111 impl crate::Writable for CfgDcocCal4Spec {
22112 type Safety = crate::Unsafe;
22113 }
22114 #[doc = "`reset()` method sets CFG_DCOC_CAL_4 to value 0"]
22115 impl crate::Resettable for CfgDcocCal4Spec {}
22116 }
22117 #[doc = "CFG_DCOC_CAL_5 (rw) register accessor: cfg_dcoc_cal_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_5`] module"]
22118 #[doc(alias = "CFG_DCOC_CAL_5")]
22119 pub type CfgDcocCal5 = crate::Reg<cfg_dcoc_cal_5::CfgDcocCal5Spec>;
22120 #[doc = "cfg_dcoc_cal_5"]
22121 pub mod cfg_dcoc_cal_5 {
22122 #[doc = "Register `CFG_DCOC_CAL_5` reader"]
22123 pub type R = crate::R<CfgDcocCal5Spec>;
22124 #[doc = "Register `CFG_DCOC_CAL_5` writer"]
22125 pub type W = crate::W<CfgDcocCal5Spec>;
22126 impl core::fmt::Debug for R {
22127 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22128 write!(f, "{}", self.bits())
22129 }
22130 }
22131 impl W {}
22132 #[doc = "cfg_dcoc_cal_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22133 pub struct CfgDcocCal5Spec;
22134 impl crate::RegisterSpec for CfgDcocCal5Spec {
22135 type Ux = u32;
22136 }
22137 #[doc = "`read()` method returns [`cfg_dcoc_cal_5::R`](R) reader structure"]
22138 impl crate::Readable for CfgDcocCal5Spec {}
22139 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_5::W`](W) writer structure"]
22140 impl crate::Writable for CfgDcocCal5Spec {
22141 type Safety = crate::Unsafe;
22142 }
22143 #[doc = "`reset()` method sets CFG_DCOC_CAL_5 to value 0"]
22144 impl crate::Resettable for CfgDcocCal5Spec {}
22145 }
22146 #[doc = "CFG_DCOC_CAL_6 (rw) register accessor: cfg_dcoc_cal_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_6`] module"]
22147 #[doc(alias = "CFG_DCOC_CAL_6")]
22148 pub type CfgDcocCal6 = crate::Reg<cfg_dcoc_cal_6::CfgDcocCal6Spec>;
22149 #[doc = "cfg_dcoc_cal_6"]
22150 pub mod cfg_dcoc_cal_6 {
22151 #[doc = "Register `CFG_DCOC_CAL_6` reader"]
22152 pub type R = crate::R<CfgDcocCal6Spec>;
22153 #[doc = "Register `CFG_DCOC_CAL_6` writer"]
22154 pub type W = crate::W<CfgDcocCal6Spec>;
22155 impl core::fmt::Debug for R {
22156 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22157 write!(f, "{}", self.bits())
22158 }
22159 }
22160 impl W {}
22161 #[doc = "cfg_dcoc_cal_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22162 pub struct CfgDcocCal6Spec;
22163 impl crate::RegisterSpec for CfgDcocCal6Spec {
22164 type Ux = u32;
22165 }
22166 #[doc = "`read()` method returns [`cfg_dcoc_cal_6::R`](R) reader structure"]
22167 impl crate::Readable for CfgDcocCal6Spec {}
22168 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_6::W`](W) writer structure"]
22169 impl crate::Writable for CfgDcocCal6Spec {
22170 type Safety = crate::Unsafe;
22171 }
22172 #[doc = "`reset()` method sets CFG_DCOC_CAL_6 to value 0"]
22173 impl crate::Resettable for CfgDcocCal6Spec {}
22174 }
22175 #[doc = "CFG_DCOC_CAL_7 (rw) register accessor: cfg_dcoc_cal_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_7`] module"]
22176 #[doc(alias = "CFG_DCOC_CAL_7")]
22177 pub type CfgDcocCal7 = crate::Reg<cfg_dcoc_cal_7::CfgDcocCal7Spec>;
22178 #[doc = "cfg_dcoc_cal_7"]
22179 pub mod cfg_dcoc_cal_7 {
22180 #[doc = "Register `CFG_DCOC_CAL_7` reader"]
22181 pub type R = crate::R<CfgDcocCal7Spec>;
22182 #[doc = "Register `CFG_DCOC_CAL_7` writer"]
22183 pub type W = crate::W<CfgDcocCal7Spec>;
22184 impl core::fmt::Debug for R {
22185 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22186 write!(f, "{}", self.bits())
22187 }
22188 }
22189 impl W {}
22190 #[doc = "cfg_dcoc_cal_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22191 pub struct CfgDcocCal7Spec;
22192 impl crate::RegisterSpec for CfgDcocCal7Spec {
22193 type Ux = u32;
22194 }
22195 #[doc = "`read()` method returns [`cfg_dcoc_cal_7::R`](R) reader structure"]
22196 impl crate::Readable for CfgDcocCal7Spec {}
22197 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_7::W`](W) writer structure"]
22198 impl crate::Writable for CfgDcocCal7Spec {
22199 type Safety = crate::Unsafe;
22200 }
22201 #[doc = "`reset()` method sets CFG_DCOC_CAL_7 to value 0"]
22202 impl crate::Resettable for CfgDcocCal7Spec {}
22203 }
22204 #[doc = "CFG_DCOC_CAL_8 (rw) register accessor: cfg_dcoc_cal_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_8`] module"]
22205 #[doc(alias = "CFG_DCOC_CAL_8")]
22206 pub type CfgDcocCal8 = crate::Reg<cfg_dcoc_cal_8::CfgDcocCal8Spec>;
22207 #[doc = "cfg_dcoc_cal_8"]
22208 pub mod cfg_dcoc_cal_8 {
22209 #[doc = "Register `CFG_DCOC_CAL_8` reader"]
22210 pub type R = crate::R<CfgDcocCal8Spec>;
22211 #[doc = "Register `CFG_DCOC_CAL_8` writer"]
22212 pub type W = crate::W<CfgDcocCal8Spec>;
22213 impl core::fmt::Debug for R {
22214 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22215 write!(f, "{}", self.bits())
22216 }
22217 }
22218 impl W {}
22219 #[doc = "cfg_dcoc_cal_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22220 pub struct CfgDcocCal8Spec;
22221 impl crate::RegisterSpec for CfgDcocCal8Spec {
22222 type Ux = u32;
22223 }
22224 #[doc = "`read()` method returns [`cfg_dcoc_cal_8::R`](R) reader structure"]
22225 impl crate::Readable for CfgDcocCal8Spec {}
22226 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_8::W`](W) writer structure"]
22227 impl crate::Writable for CfgDcocCal8Spec {
22228 type Safety = crate::Unsafe;
22229 }
22230 #[doc = "`reset()` method sets CFG_DCOC_CAL_8 to value 0"]
22231 impl crate::Resettable for CfgDcocCal8Spec {}
22232 }
22233 #[doc = "RPT_DCOC_CAL_0 (rw) register accessor: rpt_dcoc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_dcoc_cal_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_dcoc_cal_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_dcoc_cal_0`] module"]
22234 #[doc(alias = "RPT_DCOC_CAL_0")]
22235 pub type RptDcocCal0 = crate::Reg<rpt_dcoc_cal_0::RptDcocCal0Spec>;
22236 #[doc = "rpt_dcoc_cal_0"]
22237 pub mod rpt_dcoc_cal_0 {
22238 #[doc = "Register `RPT_DCOC_CAL_0` reader"]
22239 pub type R = crate::R<RptDcocCal0Spec>;
22240 #[doc = "Register `RPT_DCOC_CAL_0` writer"]
22241 pub type W = crate::W<RptDcocCal0Spec>;
22242 impl core::fmt::Debug for R {
22243 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22244 write!(f, "{}", self.bits())
22245 }
22246 }
22247 impl W {}
22248 #[doc = "rpt_dcoc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_dcoc_cal_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_dcoc_cal_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22249 pub struct RptDcocCal0Spec;
22250 impl crate::RegisterSpec for RptDcocCal0Spec {
22251 type Ux = u32;
22252 }
22253 #[doc = "`read()` method returns [`rpt_dcoc_cal_0::R`](R) reader structure"]
22254 impl crate::Readable for RptDcocCal0Spec {}
22255 #[doc = "`write(|w| ..)` method takes [`rpt_dcoc_cal_0::W`](W) writer structure"]
22256 impl crate::Writable for RptDcocCal0Spec {
22257 type Safety = crate::Unsafe;
22258 }
22259 #[doc = "`reset()` method sets RPT_DCOC_CAL_0 to value 0"]
22260 impl crate::Resettable for RptDcocCal0Spec {}
22261 }
22262 #[doc = "CFG_DCOC_CAL_12 (rw) register accessor: cfg_dcoc_cal_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_12`] module"]
22263 #[doc(alias = "CFG_DCOC_CAL_12")]
22264 pub type CfgDcocCal12 = crate::Reg<cfg_dcoc_cal_12::CfgDcocCal12Spec>;
22265 #[doc = "cfg_dcoc_cal_12"]
22266 pub mod cfg_dcoc_cal_12 {
22267 #[doc = "Register `CFG_DCOC_CAL_12` reader"]
22268 pub type R = crate::R<CfgDcocCal12Spec>;
22269 #[doc = "Register `CFG_DCOC_CAL_12` writer"]
22270 pub type W = crate::W<CfgDcocCal12Spec>;
22271 impl core::fmt::Debug for R {
22272 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22273 write!(f, "{}", self.bits())
22274 }
22275 }
22276 impl W {}
22277 #[doc = "cfg_dcoc_cal_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22278 pub struct CfgDcocCal12Spec;
22279 impl crate::RegisterSpec for CfgDcocCal12Spec {
22280 type Ux = u32;
22281 }
22282 #[doc = "`read()` method returns [`cfg_dcoc_cal_12::R`](R) reader structure"]
22283 impl crate::Readable for CfgDcocCal12Spec {}
22284 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_12::W`](W) writer structure"]
22285 impl crate::Writable for CfgDcocCal12Spec {
22286 type Safety = crate::Unsafe;
22287 }
22288 #[doc = "`reset()` method sets CFG_DCOC_CAL_12 to value 0"]
22289 impl crate::Resettable for CfgDcocCal12Spec {}
22290 }
22291 #[doc = "CFG_DCOC_CAL_13 (rw) register accessor: cfg_dcoc_cal_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_13`] module"]
22292 #[doc(alias = "CFG_DCOC_CAL_13")]
22293 pub type CfgDcocCal13 = crate::Reg<cfg_dcoc_cal_13::CfgDcocCal13Spec>;
22294 #[doc = "cfg_dcoc_cal_13"]
22295 pub mod cfg_dcoc_cal_13 {
22296 #[doc = "Register `CFG_DCOC_CAL_13` reader"]
22297 pub type R = crate::R<CfgDcocCal13Spec>;
22298 #[doc = "Register `CFG_DCOC_CAL_13` writer"]
22299 pub type W = crate::W<CfgDcocCal13Spec>;
22300 #[doc = "Field `cfg_manual_preamp_os_code` reader - "]
22301 pub type CfgManualPreampOsCodeR = crate::FieldReader;
22302 #[doc = "Field `cfg_manual_preamp_os_code` writer - "]
22303 pub type CfgManualPreampOsCodeW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
22304 #[doc = "Field `cfg_manual_preamp_os_update` reader - "]
22305 pub type CfgManualPreampOsUpdateR = crate::BitReader;
22306 #[doc = "Field `cfg_manual_preamp_os_update` writer - "]
22307 pub type CfgManualPreampOsUpdateW<'a, REG> = crate::BitWriter<'a, REG>;
22308 impl R {
22309 #[doc = "Bits 0:5"]
22310 #[inline(always)]
22311 pub fn cfg_manual_preamp_os_code(&self) -> CfgManualPreampOsCodeR {
22312 CfgManualPreampOsCodeR::new((self.bits & 0x3f) as u8)
22313 }
22314 #[doc = "Bit 8"]
22315 #[inline(always)]
22316 pub fn cfg_manual_preamp_os_update(&self) -> CfgManualPreampOsUpdateR {
22317 CfgManualPreampOsUpdateR::new(((self.bits >> 8) & 1) != 0)
22318 }
22319 }
22320 impl W {
22321 #[doc = "Bits 0:5"]
22322 #[inline(always)]
22323 pub fn cfg_manual_preamp_os_code(
22324 &mut self,
22325 ) -> CfgManualPreampOsCodeW<'_, CfgDcocCal13Spec> {
22326 CfgManualPreampOsCodeW::new(self, 0)
22327 }
22328 #[doc = "Bit 8"]
22329 #[inline(always)]
22330 pub fn cfg_manual_preamp_os_update(
22331 &mut self,
22332 ) -> CfgManualPreampOsUpdateW<'_, CfgDcocCal13Spec> {
22333 CfgManualPreampOsUpdateW::new(self, 8)
22334 }
22335 }
22336 #[doc = "cfg_dcoc_cal_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22337 pub struct CfgDcocCal13Spec;
22338 impl crate::RegisterSpec for CfgDcocCal13Spec {
22339 type Ux = u32;
22340 }
22341 #[doc = "`read()` method returns [`cfg_dcoc_cal_13::R`](R) reader structure"]
22342 impl crate::Readable for CfgDcocCal13Spec {}
22343 #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_13::W`](W) writer structure"]
22344 impl crate::Writable for CfgDcocCal13Spec {
22345 type Safety = crate::Unsafe;
22346 }
22347 #[doc = "`reset()` method sets CFG_DCOC_CAL_13 to value 0"]
22348 impl crate::Resettable for CfgDcocCal13Spec {}
22349 }
22350 #[doc = "RPT_DCOC_CAL_1 (rw) register accessor: rpt_dcoc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_dcoc_cal_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_dcoc_cal_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_dcoc_cal_1`] module"]
22351 #[doc(alias = "RPT_DCOC_CAL_1")]
22352 pub type RptDcocCal1 = crate::Reg<rpt_dcoc_cal_1::RptDcocCal1Spec>;
22353 #[doc = "rpt_dcoc_cal_1"]
22354 pub mod rpt_dcoc_cal_1 {
22355 #[doc = "Register `RPT_DCOC_CAL_1` reader"]
22356 pub type R = crate::R<RptDcocCal1Spec>;
22357 #[doc = "Register `RPT_DCOC_CAL_1` writer"]
22358 pub type W = crate::W<RptDcocCal1Spec>;
22359 impl core::fmt::Debug for R {
22360 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22361 write!(f, "{}", self.bits())
22362 }
22363 }
22364 impl W {}
22365 #[doc = "rpt_dcoc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_dcoc_cal_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_dcoc_cal_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22366 pub struct RptDcocCal1Spec;
22367 impl crate::RegisterSpec for RptDcocCal1Spec {
22368 type Ux = u32;
22369 }
22370 #[doc = "`read()` method returns [`rpt_dcoc_cal_1::R`](R) reader structure"]
22371 impl crate::Readable for RptDcocCal1Spec {}
22372 #[doc = "`write(|w| ..)` method takes [`rpt_dcoc_cal_1::W`](W) writer structure"]
22373 impl crate::Writable for RptDcocCal1Spec {
22374 type Safety = crate::Unsafe;
22375 }
22376 #[doc = "`reset()` method sets RPT_DCOC_CAL_1 to value 0"]
22377 impl crate::Resettable for RptDcocCal1Spec {}
22378 }
22379 #[doc = "CFG_SAR_SPD_0 (rw) register accessor: cfg_sar_spd_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_0`] module"]
22380 #[doc(alias = "CFG_SAR_SPD_0")]
22381 pub type CfgSarSpd0 = crate::Reg<cfg_sar_spd_0::CfgSarSpd0Spec>;
22382 #[doc = "cfg_sar_spd_0"]
22383 pub mod cfg_sar_spd_0 {
22384 #[doc = "Register `CFG_SAR_SPD_0` reader"]
22385 pub type R = crate::R<CfgSarSpd0Spec>;
22386 #[doc = "Register `CFG_SAR_SPD_0` writer"]
22387 pub type W = crate::W<CfgSarSpd0Spec>;
22388 impl core::fmt::Debug for R {
22389 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22390 write!(f, "{}", self.bits())
22391 }
22392 }
22393 impl W {}
22394 #[doc = "cfg_sar_spd_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22395 pub struct CfgSarSpd0Spec;
22396 impl crate::RegisterSpec for CfgSarSpd0Spec {
22397 type Ux = u32;
22398 }
22399 #[doc = "`read()` method returns [`cfg_sar_spd_0::R`](R) reader structure"]
22400 impl crate::Readable for CfgSarSpd0Spec {}
22401 #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_0::W`](W) writer structure"]
22402 impl crate::Writable for CfgSarSpd0Spec {
22403 type Safety = crate::Unsafe;
22404 }
22405 #[doc = "`reset()` method sets CFG_SAR_SPD_0 to value 0"]
22406 impl crate::Resettable for CfgSarSpd0Spec {}
22407 }
22408 #[doc = "CFG_SAR_SPD_1 (rw) register accessor: cfg_sar_spd_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_1`] module"]
22409 #[doc(alias = "CFG_SAR_SPD_1")]
22410 pub type CfgSarSpd1 = crate::Reg<cfg_sar_spd_1::CfgSarSpd1Spec>;
22411 #[doc = "cfg_sar_spd_1"]
22412 pub mod cfg_sar_spd_1 {
22413 #[doc = "Register `CFG_SAR_SPD_1` reader"]
22414 pub type R = crate::R<CfgSarSpd1Spec>;
22415 #[doc = "Register `CFG_SAR_SPD_1` writer"]
22416 pub type W = crate::W<CfgSarSpd1Spec>;
22417 impl core::fmt::Debug for R {
22418 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22419 write!(f, "{}", self.bits())
22420 }
22421 }
22422 impl W {}
22423 #[doc = "cfg_sar_spd_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22424 pub struct CfgSarSpd1Spec;
22425 impl crate::RegisterSpec for CfgSarSpd1Spec {
22426 type Ux = u32;
22427 }
22428 #[doc = "`read()` method returns [`cfg_sar_spd_1::R`](R) reader structure"]
22429 impl crate::Readable for CfgSarSpd1Spec {}
22430 #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_1::W`](W) writer structure"]
22431 impl crate::Writable for CfgSarSpd1Spec {
22432 type Safety = crate::Unsafe;
22433 }
22434 #[doc = "`reset()` method sets CFG_SAR_SPD_1 to value 0"]
22435 impl crate::Resettable for CfgSarSpd1Spec {}
22436 }
22437 #[doc = "CFG_SAR_SPD_2 (rw) register accessor: cfg_sar_spd_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_2`] module"]
22438 #[doc(alias = "CFG_SAR_SPD_2")]
22439 pub type CfgSarSpd2 = crate::Reg<cfg_sar_spd_2::CfgSarSpd2Spec>;
22440 #[doc = "cfg_sar_spd_2"]
22441 pub mod cfg_sar_spd_2 {
22442 #[doc = "Register `CFG_SAR_SPD_2` reader"]
22443 pub type R = crate::R<CfgSarSpd2Spec>;
22444 #[doc = "Register `CFG_SAR_SPD_2` writer"]
22445 pub type W = crate::W<CfgSarSpd2Spec>;
22446 impl core::fmt::Debug for R {
22447 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22448 write!(f, "{}", self.bits())
22449 }
22450 }
22451 impl W {}
22452 #[doc = "cfg_sar_spd_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22453 pub struct CfgSarSpd2Spec;
22454 impl crate::RegisterSpec for CfgSarSpd2Spec {
22455 type Ux = u32;
22456 }
22457 #[doc = "`read()` method returns [`cfg_sar_spd_2::R`](R) reader structure"]
22458 impl crate::Readable for CfgSarSpd2Spec {}
22459 #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_2::W`](W) writer structure"]
22460 impl crate::Writable for CfgSarSpd2Spec {
22461 type Safety = crate::Unsafe;
22462 }
22463 #[doc = "`reset()` method sets CFG_SAR_SPD_2 to value 0"]
22464 impl crate::Resettable for CfgSarSpd2Spec {}
22465 }
22466 #[doc = "CFG_SAR_SPD_3 (rw) register accessor: cfg_sar_spd_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_3`] module"]
22467 #[doc(alias = "CFG_SAR_SPD_3")]
22468 pub type CfgSarSpd3 = crate::Reg<cfg_sar_spd_3::CfgSarSpd3Spec>;
22469 #[doc = "cfg_sar_spd_3"]
22470 pub mod cfg_sar_spd_3 {
22471 #[doc = "Register `CFG_SAR_SPD_3` reader"]
22472 pub type R = crate::R<CfgSarSpd3Spec>;
22473 #[doc = "Register `CFG_SAR_SPD_3` writer"]
22474 pub type W = crate::W<CfgSarSpd3Spec>;
22475 impl core::fmt::Debug for R {
22476 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22477 write!(f, "{}", self.bits())
22478 }
22479 }
22480 impl W {}
22481 #[doc = "cfg_sar_spd_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22482 pub struct CfgSarSpd3Spec;
22483 impl crate::RegisterSpec for CfgSarSpd3Spec {
22484 type Ux = u32;
22485 }
22486 #[doc = "`read()` method returns [`cfg_sar_spd_3::R`](R) reader structure"]
22487 impl crate::Readable for CfgSarSpd3Spec {}
22488 #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_3::W`](W) writer structure"]
22489 impl crate::Writable for CfgSarSpd3Spec {
22490 type Safety = crate::Unsafe;
22491 }
22492 #[doc = "`reset()` method sets CFG_SAR_SPD_3 to value 0"]
22493 impl crate::Resettable for CfgSarSpd3Spec {}
22494 }
22495 #[doc = "CFG_SAR_SPD_4 (rw) register accessor: cfg_sar_spd_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_4`] module"]
22496 #[doc(alias = "CFG_SAR_SPD_4")]
22497 pub type CfgSarSpd4 = crate::Reg<cfg_sar_spd_4::CfgSarSpd4Spec>;
22498 #[doc = "cfg_sar_spd_4"]
22499 pub mod cfg_sar_spd_4 {
22500 #[doc = "Register `CFG_SAR_SPD_4` reader"]
22501 pub type R = crate::R<CfgSarSpd4Spec>;
22502 #[doc = "Register `CFG_SAR_SPD_4` writer"]
22503 pub type W = crate::W<CfgSarSpd4Spec>;
22504 impl core::fmt::Debug for R {
22505 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22506 write!(f, "{}", self.bits())
22507 }
22508 }
22509 impl W {}
22510 #[doc = "cfg_sar_spd_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22511 pub struct CfgSarSpd4Spec;
22512 impl crate::RegisterSpec for CfgSarSpd4Spec {
22513 type Ux = u32;
22514 }
22515 #[doc = "`read()` method returns [`cfg_sar_spd_4::R`](R) reader structure"]
22516 impl crate::Readable for CfgSarSpd4Spec {}
22517 #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_4::W`](W) writer structure"]
22518 impl crate::Writable for CfgSarSpd4Spec {
22519 type Safety = crate::Unsafe;
22520 }
22521 #[doc = "`reset()` method sets CFG_SAR_SPD_4 to value 0"]
22522 impl crate::Resettable for CfgSarSpd4Spec {}
22523 }
22524 #[doc = "RPT_SAR_SPD_0 (rw) register accessor: rpt_sar_spd_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_sar_spd_0`] module"]
22525 #[doc(alias = "RPT_SAR_SPD_0")]
22526 pub type RptSarSpd0 = crate::Reg<rpt_sar_spd_0::RptSarSpd0Spec>;
22527 #[doc = "rpt_sar_spd_0"]
22528 pub mod rpt_sar_spd_0 {
22529 #[doc = "Register `RPT_SAR_SPD_0` reader"]
22530 pub type R = crate::R<RptSarSpd0Spec>;
22531 #[doc = "Register `RPT_SAR_SPD_0` writer"]
22532 pub type W = crate::W<RptSarSpd0Spec>;
22533 impl core::fmt::Debug for R {
22534 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22535 write!(f, "{}", self.bits())
22536 }
22537 }
22538 impl W {}
22539 #[doc = "rpt_sar_spd_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22540 pub struct RptSarSpd0Spec;
22541 impl crate::RegisterSpec for RptSarSpd0Spec {
22542 type Ux = u32;
22543 }
22544 #[doc = "`read()` method returns [`rpt_sar_spd_0::R`](R) reader structure"]
22545 impl crate::Readable for RptSarSpd0Spec {}
22546 #[doc = "`write(|w| ..)` method takes [`rpt_sar_spd_0::W`](W) writer structure"]
22547 impl crate::Writable for RptSarSpd0Spec {
22548 type Safety = crate::Unsafe;
22549 }
22550 #[doc = "`reset()` method sets RPT_SAR_SPD_0 to value 0"]
22551 impl crate::Resettable for RptSarSpd0Spec {}
22552 }
22553 #[doc = "RPT_SAR_SPD_1 (rw) register accessor: rpt_sar_spd_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_sar_spd_1`] module"]
22554 #[doc(alias = "RPT_SAR_SPD_1")]
22555 pub type RptSarSpd1 = crate::Reg<rpt_sar_spd_1::RptSarSpd1Spec>;
22556 #[doc = "rpt_sar_spd_1"]
22557 pub mod rpt_sar_spd_1 {
22558 #[doc = "Register `RPT_SAR_SPD_1` reader"]
22559 pub type R = crate::R<RptSarSpd1Spec>;
22560 #[doc = "Register `RPT_SAR_SPD_1` writer"]
22561 pub type W = crate::W<RptSarSpd1Spec>;
22562 impl core::fmt::Debug for R {
22563 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22564 write!(f, "{}", self.bits())
22565 }
22566 }
22567 impl W {}
22568 #[doc = "rpt_sar_spd_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22569 pub struct RptSarSpd1Spec;
22570 impl crate::RegisterSpec for RptSarSpd1Spec {
22571 type Ux = u32;
22572 }
22573 #[doc = "`read()` method returns [`rpt_sar_spd_1::R`](R) reader structure"]
22574 impl crate::Readable for RptSarSpd1Spec {}
22575 #[doc = "`write(|w| ..)` method takes [`rpt_sar_spd_1::W`](W) writer structure"]
22576 impl crate::Writable for RptSarSpd1Spec {
22577 type Safety = crate::Unsafe;
22578 }
22579 #[doc = "`reset()` method sets RPT_SAR_SPD_1 to value 0"]
22580 impl crate::Resettable for RptSarSpd1Spec {}
22581 }
22582 #[doc = "CFG_SAR_SPD_6 (rw) register accessor: cfg_sar_spd_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_6`] module"]
22583 #[doc(alias = "CFG_SAR_SPD_6")]
22584 pub type CfgSarSpd6 = crate::Reg<cfg_sar_spd_6::CfgSarSpd6Spec>;
22585 #[doc = "cfg_sar_spd_6"]
22586 pub mod cfg_sar_spd_6 {
22587 #[doc = "Register `CFG_SAR_SPD_6` reader"]
22588 pub type R = crate::R<CfgSarSpd6Spec>;
22589 #[doc = "Register `CFG_SAR_SPD_6` writer"]
22590 pub type W = crate::W<CfgSarSpd6Spec>;
22591 #[doc = "Field `cfg_manual_sar_spd_dly_code` reader - "]
22592 pub type CfgManualSarSpdDlyCodeR = crate::FieldReader;
22593 #[doc = "Field `cfg_manual_sar_spd_dly_code` writer - "]
22594 pub type CfgManualSarSpdDlyCodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
22595 #[doc = "Field `cfg_manual_sar_spd_update` reader - "]
22596 pub type CfgManualSarSpdUpdateR = crate::BitReader;
22597 #[doc = "Field `cfg_manual_sar_spd_update` writer - "]
22598 pub type CfgManualSarSpdUpdateW<'a, REG> = crate::BitWriter<'a, REG>;
22599 impl R {
22600 #[doc = "Bits 0:2"]
22601 #[inline(always)]
22602 pub fn cfg_manual_sar_spd_dly_code(&self) -> CfgManualSarSpdDlyCodeR {
22603 CfgManualSarSpdDlyCodeR::new((self.bits & 7) as u8)
22604 }
22605 #[doc = "Bit 4"]
22606 #[inline(always)]
22607 pub fn cfg_manual_sar_spd_update(&self) -> CfgManualSarSpdUpdateR {
22608 CfgManualSarSpdUpdateR::new(((self.bits >> 4) & 1) != 0)
22609 }
22610 }
22611 impl W {
22612 #[doc = "Bits 0:2"]
22613 #[inline(always)]
22614 pub fn cfg_manual_sar_spd_dly_code(
22615 &mut self,
22616 ) -> CfgManualSarSpdDlyCodeW<'_, CfgSarSpd6Spec> {
22617 CfgManualSarSpdDlyCodeW::new(self, 0)
22618 }
22619 #[doc = "Bit 4"]
22620 #[inline(always)]
22621 pub fn cfg_manual_sar_spd_update(
22622 &mut self,
22623 ) -> CfgManualSarSpdUpdateW<'_, CfgSarSpd6Spec> {
22624 CfgManualSarSpdUpdateW::new(self, 4)
22625 }
22626 }
22627 #[doc = "cfg_sar_spd_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22628 pub struct CfgSarSpd6Spec;
22629 impl crate::RegisterSpec for CfgSarSpd6Spec {
22630 type Ux = u32;
22631 }
22632 #[doc = "`read()` method returns [`cfg_sar_spd_6::R`](R) reader structure"]
22633 impl crate::Readable for CfgSarSpd6Spec {}
22634 #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_6::W`](W) writer structure"]
22635 impl crate::Writable for CfgSarSpd6Spec {
22636 type Safety = crate::Unsafe;
22637 }
22638 #[doc = "`reset()` method sets CFG_SAR_SPD_6 to value 0"]
22639 impl crate::Resettable for CfgSarSpd6Spec {}
22640 }
22641 #[doc = "RPT_SAR_SPD_2 (rw) register accessor: rpt_sar_spd_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_sar_spd_2`] module"]
22642 #[doc(alias = "RPT_SAR_SPD_2")]
22643 pub type RptSarSpd2 = crate::Reg<rpt_sar_spd_2::RptSarSpd2Spec>;
22644 #[doc = "rpt_sar_spd_2"]
22645 pub mod rpt_sar_spd_2 {
22646 #[doc = "Register `RPT_SAR_SPD_2` reader"]
22647 pub type R = crate::R<RptSarSpd2Spec>;
22648 #[doc = "Register `RPT_SAR_SPD_2` writer"]
22649 pub type W = crate::W<RptSarSpd2Spec>;
22650 impl core::fmt::Debug for R {
22651 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22652 write!(f, "{}", self.bits())
22653 }
22654 }
22655 impl W {}
22656 #[doc = "rpt_sar_spd_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22657 pub struct RptSarSpd2Spec;
22658 impl crate::RegisterSpec for RptSarSpd2Spec {
22659 type Ux = u32;
22660 }
22661 #[doc = "`read()` method returns [`rpt_sar_spd_2::R`](R) reader structure"]
22662 impl crate::Readable for RptSarSpd2Spec {}
22663 #[doc = "`write(|w| ..)` method takes [`rpt_sar_spd_2::W`](W) writer structure"]
22664 impl crate::Writable for RptSarSpd2Spec {
22665 type Safety = crate::Unsafe;
22666 }
22667 #[doc = "`reset()` method sets RPT_SAR_SPD_2 to value 0"]
22668 impl crate::Resettable for RptSarSpd2Spec {}
22669 }
22670 #[doc = "CFG_RC_CAL_0 (rw) register accessor: cfg_rc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_0`] module"]
22671 #[doc(alias = "CFG_RC_CAL_0")]
22672 pub type CfgRcCal0 = crate::Reg<cfg_rc_cal_0::CfgRcCal0Spec>;
22673 #[doc = "cfg_rc_cal_0"]
22674 pub mod cfg_rc_cal_0 {
22675 #[doc = "Register `CFG_RC_CAL_0` reader"]
22676 pub type R = crate::R<CfgRcCal0Spec>;
22677 #[doc = "Register `CFG_RC_CAL_0` writer"]
22678 pub type W = crate::W<CfgRcCal0Spec>;
22679 impl core::fmt::Debug for R {
22680 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22681 write!(f, "{}", self.bits())
22682 }
22683 }
22684 impl W {}
22685 #[doc = "cfg_rc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22686 pub struct CfgRcCal0Spec;
22687 impl crate::RegisterSpec for CfgRcCal0Spec {
22688 type Ux = u32;
22689 }
22690 #[doc = "`read()` method returns [`cfg_rc_cal_0::R`](R) reader structure"]
22691 impl crate::Readable for CfgRcCal0Spec {}
22692 #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_0::W`](W) writer structure"]
22693 impl crate::Writable for CfgRcCal0Spec {
22694 type Safety = crate::Unsafe;
22695 }
22696 #[doc = "`reset()` method sets CFG_RC_CAL_0 to value 0"]
22697 impl crate::Resettable for CfgRcCal0Spec {}
22698 }
22699 #[doc = "CFG_RC_CAL_1 (rw) register accessor: cfg_rc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_1`] module"]
22700 #[doc(alias = "CFG_RC_CAL_1")]
22701 pub type CfgRcCal1 = crate::Reg<cfg_rc_cal_1::CfgRcCal1Spec>;
22702 #[doc = "cfg_rc_cal_1"]
22703 pub mod cfg_rc_cal_1 {
22704 #[doc = "Register `CFG_RC_CAL_1` reader"]
22705 pub type R = crate::R<CfgRcCal1Spec>;
22706 #[doc = "Register `CFG_RC_CAL_1` writer"]
22707 pub type W = crate::W<CfgRcCal1Spec>;
22708 impl core::fmt::Debug for R {
22709 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22710 write!(f, "{}", self.bits())
22711 }
22712 }
22713 impl W {}
22714 #[doc = "cfg_rc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22715 pub struct CfgRcCal1Spec;
22716 impl crate::RegisterSpec for CfgRcCal1Spec {
22717 type Ux = u32;
22718 }
22719 #[doc = "`read()` method returns [`cfg_rc_cal_1::R`](R) reader structure"]
22720 impl crate::Readable for CfgRcCal1Spec {}
22721 #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_1::W`](W) writer structure"]
22722 impl crate::Writable for CfgRcCal1Spec {
22723 type Safety = crate::Unsafe;
22724 }
22725 #[doc = "`reset()` method sets CFG_RC_CAL_1 to value 0"]
22726 impl crate::Resettable for CfgRcCal1Spec {}
22727 }
22728 #[doc = "CFG_RC_CAL_2 (rw) register accessor: cfg_rc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_2`] module"]
22729 #[doc(alias = "CFG_RC_CAL_2")]
22730 pub type CfgRcCal2 = crate::Reg<cfg_rc_cal_2::CfgRcCal2Spec>;
22731 #[doc = "cfg_rc_cal_2"]
22732 pub mod cfg_rc_cal_2 {
22733 #[doc = "Register `CFG_RC_CAL_2` reader"]
22734 pub type R = crate::R<CfgRcCal2Spec>;
22735 #[doc = "Register `CFG_RC_CAL_2` writer"]
22736 pub type W = crate::W<CfgRcCal2Spec>;
22737 impl core::fmt::Debug for R {
22738 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22739 write!(f, "{}", self.bits())
22740 }
22741 }
22742 impl W {}
22743 #[doc = "cfg_rc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22744 pub struct CfgRcCal2Spec;
22745 impl crate::RegisterSpec for CfgRcCal2Spec {
22746 type Ux = u32;
22747 }
22748 #[doc = "`read()` method returns [`cfg_rc_cal_2::R`](R) reader structure"]
22749 impl crate::Readable for CfgRcCal2Spec {}
22750 #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_2::W`](W) writer structure"]
22751 impl crate::Writable for CfgRcCal2Spec {
22752 type Safety = crate::Unsafe;
22753 }
22754 #[doc = "`reset()` method sets CFG_RC_CAL_2 to value 0"]
22755 impl crate::Resettable for CfgRcCal2Spec {}
22756 }
22757 #[doc = "CFG_RC_CAL_3 (rw) register accessor: cfg_rc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_3`] module"]
22758 #[doc(alias = "CFG_RC_CAL_3")]
22759 pub type CfgRcCal3 = crate::Reg<cfg_rc_cal_3::CfgRcCal3Spec>;
22760 #[doc = "cfg_rc_cal_3"]
22761 pub mod cfg_rc_cal_3 {
22762 #[doc = "Register `CFG_RC_CAL_3` reader"]
22763 pub type R = crate::R<CfgRcCal3Spec>;
22764 #[doc = "Register `CFG_RC_CAL_3` writer"]
22765 pub type W = crate::W<CfgRcCal3Spec>;
22766 impl core::fmt::Debug for R {
22767 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22768 write!(f, "{}", self.bits())
22769 }
22770 }
22771 impl W {}
22772 #[doc = "cfg_rc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22773 pub struct CfgRcCal3Spec;
22774 impl crate::RegisterSpec for CfgRcCal3Spec {
22775 type Ux = u32;
22776 }
22777 #[doc = "`read()` method returns [`cfg_rc_cal_3::R`](R) reader structure"]
22778 impl crate::Readable for CfgRcCal3Spec {}
22779 #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_3::W`](W) writer structure"]
22780 impl crate::Writable for CfgRcCal3Spec {
22781 type Safety = crate::Unsafe;
22782 }
22783 #[doc = "`reset()` method sets CFG_RC_CAL_3 to value 0"]
22784 impl crate::Resettable for CfgRcCal3Spec {}
22785 }
22786 #[doc = "CFG_RC_CAL_4 (rw) register accessor: cfg_rc_cal_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_4`] module"]
22787 #[doc(alias = "CFG_RC_CAL_4")]
22788 pub type CfgRcCal4 = crate::Reg<cfg_rc_cal_4::CfgRcCal4Spec>;
22789 #[doc = "cfg_rc_cal_4"]
22790 pub mod cfg_rc_cal_4 {
22791 #[doc = "Register `CFG_RC_CAL_4` reader"]
22792 pub type R = crate::R<CfgRcCal4Spec>;
22793 #[doc = "Register `CFG_RC_CAL_4` writer"]
22794 pub type W = crate::W<CfgRcCal4Spec>;
22795 impl core::fmt::Debug for R {
22796 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22797 write!(f, "{}", self.bits())
22798 }
22799 }
22800 impl W {}
22801 #[doc = "cfg_rc_cal_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22802 pub struct CfgRcCal4Spec;
22803 impl crate::RegisterSpec for CfgRcCal4Spec {
22804 type Ux = u32;
22805 }
22806 #[doc = "`read()` method returns [`cfg_rc_cal_4::R`](R) reader structure"]
22807 impl crate::Readable for CfgRcCal4Spec {}
22808 #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_4::W`](W) writer structure"]
22809 impl crate::Writable for CfgRcCal4Spec {
22810 type Safety = crate::Unsafe;
22811 }
22812 #[doc = "`reset()` method sets CFG_RC_CAL_4 to value 0"]
22813 impl crate::Resettable for CfgRcCal4Spec {}
22814 }
22815 #[doc = "RPT_RC_CAL_0 (rw) register accessor: rpt_rc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_rc_cal_0`] module"]
22816 #[doc(alias = "RPT_RC_CAL_0")]
22817 pub type RptRcCal0 = crate::Reg<rpt_rc_cal_0::RptRcCal0Spec>;
22818 #[doc = "rpt_rc_cal_0"]
22819 pub mod rpt_rc_cal_0 {
22820 #[doc = "Register `RPT_RC_CAL_0` reader"]
22821 pub type R = crate::R<RptRcCal0Spec>;
22822 #[doc = "Register `RPT_RC_CAL_0` writer"]
22823 pub type W = crate::W<RptRcCal0Spec>;
22824 impl core::fmt::Debug for R {
22825 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22826 write!(f, "{}", self.bits())
22827 }
22828 }
22829 impl W {}
22830 #[doc = "rpt_rc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22831 pub struct RptRcCal0Spec;
22832 impl crate::RegisterSpec for RptRcCal0Spec {
22833 type Ux = u32;
22834 }
22835 #[doc = "`read()` method returns [`rpt_rc_cal_0::R`](R) reader structure"]
22836 impl crate::Readable for RptRcCal0Spec {}
22837 #[doc = "`write(|w| ..)` method takes [`rpt_rc_cal_0::W`](W) writer structure"]
22838 impl crate::Writable for RptRcCal0Spec {
22839 type Safety = crate::Unsafe;
22840 }
22841 #[doc = "`reset()` method sets RPT_RC_CAL_0 to value 0"]
22842 impl crate::Resettable for RptRcCal0Spec {}
22843 }
22844 #[doc = "RPT_RC_CAL_1 (rw) register accessor: rpt_rc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_rc_cal_1`] module"]
22845 #[doc(alias = "RPT_RC_CAL_1")]
22846 pub type RptRcCal1 = crate::Reg<rpt_rc_cal_1::RptRcCal1Spec>;
22847 #[doc = "rpt_rc_cal_1"]
22848 pub mod rpt_rc_cal_1 {
22849 #[doc = "Register `RPT_RC_CAL_1` reader"]
22850 pub type R = crate::R<RptRcCal1Spec>;
22851 #[doc = "Register `RPT_RC_CAL_1` writer"]
22852 pub type W = crate::W<RptRcCal1Spec>;
22853 impl core::fmt::Debug for R {
22854 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22855 write!(f, "{}", self.bits())
22856 }
22857 }
22858 impl W {}
22859 #[doc = "rpt_rc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22860 pub struct RptRcCal1Spec;
22861 impl crate::RegisterSpec for RptRcCal1Spec {
22862 type Ux = u32;
22863 }
22864 #[doc = "`read()` method returns [`rpt_rc_cal_1::R`](R) reader structure"]
22865 impl crate::Readable for RptRcCal1Spec {}
22866 #[doc = "`write(|w| ..)` method takes [`rpt_rc_cal_1::W`](W) writer structure"]
22867 impl crate::Writable for RptRcCal1Spec {
22868 type Safety = crate::Unsafe;
22869 }
22870 #[doc = "`reset()` method sets RPT_RC_CAL_1 to value 0"]
22871 impl crate::Resettable for RptRcCal1Spec {}
22872 }
22873 #[doc = "CFG_RC_CAL_5 (rw) register accessor: cfg_rc_cal_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_5`] module"]
22874 #[doc(alias = "CFG_RC_CAL_5")]
22875 pub type CfgRcCal5 = crate::Reg<cfg_rc_cal_5::CfgRcCal5Spec>;
22876 #[doc = "cfg_rc_cal_5"]
22877 pub mod cfg_rc_cal_5 {
22878 #[doc = "Register `CFG_RC_CAL_5` reader"]
22879 pub type R = crate::R<CfgRcCal5Spec>;
22880 #[doc = "Register `CFG_RC_CAL_5` writer"]
22881 pub type W = crate::W<CfgRcCal5Spec>;
22882 impl core::fmt::Debug for R {
22883 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22884 write!(f, "{}", self.bits())
22885 }
22886 }
22887 impl W {}
22888 #[doc = "cfg_rc_cal_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22889 pub struct CfgRcCal5Spec;
22890 impl crate::RegisterSpec for CfgRcCal5Spec {
22891 type Ux = u32;
22892 }
22893 #[doc = "`read()` method returns [`cfg_rc_cal_5::R`](R) reader structure"]
22894 impl crate::Readable for CfgRcCal5Spec {}
22895 #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_5::W`](W) writer structure"]
22896 impl crate::Writable for CfgRcCal5Spec {
22897 type Safety = crate::Unsafe;
22898 }
22899 #[doc = "`reset()` method sets CFG_RC_CAL_5 to value 0"]
22900 impl crate::Resettable for CfgRcCal5Spec {}
22901 }
22902 #[doc = "CFG_RC_CAL_6 (rw) register accessor: cfg_rc_cal_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_6`] module"]
22903 #[doc(alias = "CFG_RC_CAL_6")]
22904 pub type CfgRcCal6 = crate::Reg<cfg_rc_cal_6::CfgRcCal6Spec>;
22905 #[doc = "cfg_rc_cal_6"]
22906 pub mod cfg_rc_cal_6 {
22907 #[doc = "Register `CFG_RC_CAL_6` reader"]
22908 pub type R = crate::R<CfgRcCal6Spec>;
22909 #[doc = "Register `CFG_RC_CAL_6` writer"]
22910 pub type W = crate::W<CfgRcCal6Spec>;
22911 impl core::fmt::Debug for R {
22912 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22913 write!(f, "{}", self.bits())
22914 }
22915 }
22916 impl W {}
22917 #[doc = "cfg_rc_cal_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22918 pub struct CfgRcCal6Spec;
22919 impl crate::RegisterSpec for CfgRcCal6Spec {
22920 type Ux = u32;
22921 }
22922 #[doc = "`read()` method returns [`cfg_rc_cal_6::R`](R) reader structure"]
22923 impl crate::Readable for CfgRcCal6Spec {}
22924 #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_6::W`](W) writer structure"]
22925 impl crate::Writable for CfgRcCal6Spec {
22926 type Safety = crate::Unsafe;
22927 }
22928 #[doc = "`reset()` method sets CFG_RC_CAL_6 to value 0"]
22929 impl crate::Resettable for CfgRcCal6Spec {}
22930 }
22931 #[doc = "CFG_RC_CAL_7 (rw) register accessor: cfg_rc_cal_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_7`] module"]
22932 #[doc(alias = "CFG_RC_CAL_7")]
22933 pub type CfgRcCal7 = crate::Reg<cfg_rc_cal_7::CfgRcCal7Spec>;
22934 #[doc = "cfg_rc_cal_7"]
22935 pub mod cfg_rc_cal_7 {
22936 #[doc = "Register `CFG_RC_CAL_7` reader"]
22937 pub type R = crate::R<CfgRcCal7Spec>;
22938 #[doc = "Register `CFG_RC_CAL_7` writer"]
22939 pub type W = crate::W<CfgRcCal7Spec>;
22940 impl core::fmt::Debug for R {
22941 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22942 write!(f, "{}", self.bits())
22943 }
22944 }
22945 impl W {}
22946 #[doc = "cfg_rc_cal_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22947 pub struct CfgRcCal7Spec;
22948 impl crate::RegisterSpec for CfgRcCal7Spec {
22949 type Ux = u32;
22950 }
22951 #[doc = "`read()` method returns [`cfg_rc_cal_7::R`](R) reader structure"]
22952 impl crate::Readable for CfgRcCal7Spec {}
22953 #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_7::W`](W) writer structure"]
22954 impl crate::Writable for CfgRcCal7Spec {
22955 type Safety = crate::Unsafe;
22956 }
22957 #[doc = "`reset()` method sets CFG_RC_CAL_7 to value 0"]
22958 impl crate::Resettable for CfgRcCal7Spec {}
22959 }
22960 #[doc = "CFG_RC_CAL_8 (rw) register accessor: cfg_rc_cal_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_8`] module"]
22961 #[doc(alias = "CFG_RC_CAL_8")]
22962 pub type CfgRcCal8 = crate::Reg<cfg_rc_cal_8::CfgRcCal8Spec>;
22963 #[doc = "cfg_rc_cal_8"]
22964 pub mod cfg_rc_cal_8 {
22965 #[doc = "Register `CFG_RC_CAL_8` reader"]
22966 pub type R = crate::R<CfgRcCal8Spec>;
22967 #[doc = "Register `CFG_RC_CAL_8` writer"]
22968 pub type W = crate::W<CfgRcCal8Spec>;
22969 impl core::fmt::Debug for R {
22970 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22971 write!(f, "{}", self.bits())
22972 }
22973 }
22974 impl W {}
22975 #[doc = "cfg_rc_cal_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
22976 pub struct CfgRcCal8Spec;
22977 impl crate::RegisterSpec for CfgRcCal8Spec {
22978 type Ux = u32;
22979 }
22980 #[doc = "`read()` method returns [`cfg_rc_cal_8::R`](R) reader structure"]
22981 impl crate::Readable for CfgRcCal8Spec {}
22982 #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_8::W`](W) writer structure"]
22983 impl crate::Writable for CfgRcCal8Spec {
22984 type Safety = crate::Unsafe;
22985 }
22986 #[doc = "`reset()` method sets CFG_RC_CAL_8 to value 0"]
22987 impl crate::Resettable for CfgRcCal8Spec {}
22988 }
22989 #[doc = "RPT_RC_CAL_2 (rw) register accessor: rpt_rc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_rc_cal_2`] module"]
22990 #[doc(alias = "RPT_RC_CAL_2")]
22991 pub type RptRcCal2 = crate::Reg<rpt_rc_cal_2::RptRcCal2Spec>;
22992 #[doc = "rpt_rc_cal_2"]
22993 pub mod rpt_rc_cal_2 {
22994 #[doc = "Register `RPT_RC_CAL_2` reader"]
22995 pub type R = crate::R<RptRcCal2Spec>;
22996 #[doc = "Register `RPT_RC_CAL_2` writer"]
22997 pub type W = crate::W<RptRcCal2Spec>;
22998 impl core::fmt::Debug for R {
22999 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23000 write!(f, "{}", self.bits())
23001 }
23002 }
23003 impl W {}
23004 #[doc = "rpt_rc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23005 pub struct RptRcCal2Spec;
23006 impl crate::RegisterSpec for RptRcCal2Spec {
23007 type Ux = u32;
23008 }
23009 #[doc = "`read()` method returns [`rpt_rc_cal_2::R`](R) reader structure"]
23010 impl crate::Readable for RptRcCal2Spec {}
23011 #[doc = "`write(|w| ..)` method takes [`rpt_rc_cal_2::W`](W) writer structure"]
23012 impl crate::Writable for RptRcCal2Spec {
23013 type Safety = crate::Unsafe;
23014 }
23015 #[doc = "`reset()` method sets RPT_RC_CAL_2 to value 0"]
23016 impl crate::Resettable for RptRcCal2Spec {}
23017 }
23018 #[doc = "RPT_RC_CAL_3 (rw) register accessor: rpt_rc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_rc_cal_3`] module"]
23019 #[doc(alias = "RPT_RC_CAL_3")]
23020 pub type RptRcCal3 = crate::Reg<rpt_rc_cal_3::RptRcCal3Spec>;
23021 #[doc = "rpt_rc_cal_3"]
23022 pub mod rpt_rc_cal_3 {
23023 #[doc = "Register `RPT_RC_CAL_3` reader"]
23024 pub type R = crate::R<RptRcCal3Spec>;
23025 #[doc = "Register `RPT_RC_CAL_3` writer"]
23026 pub type W = crate::W<RptRcCal3Spec>;
23027 impl core::fmt::Debug for R {
23028 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23029 write!(f, "{}", self.bits())
23030 }
23031 }
23032 impl W {}
23033 #[doc = "rpt_rc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23034 pub struct RptRcCal3Spec;
23035 impl crate::RegisterSpec for RptRcCal3Spec {
23036 type Ux = u32;
23037 }
23038 #[doc = "`read()` method returns [`rpt_rc_cal_3::R`](R) reader structure"]
23039 impl crate::Readable for RptRcCal3Spec {}
23040 #[doc = "`write(|w| ..)` method takes [`rpt_rc_cal_3::W`](W) writer structure"]
23041 impl crate::Writable for RptRcCal3Spec {
23042 type Safety = crate::Unsafe;
23043 }
23044 #[doc = "`reset()` method sets RPT_RC_CAL_3 to value 0"]
23045 impl crate::Resettable for RptRcCal3Spec {}
23046 }
23047 #[doc = "CFG_AMUX_0 (rw) register accessor: cfg_amux_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_0`] module"]
23048 #[doc(alias = "CFG_AMUX_0")]
23049 pub type CfgAmux0 = crate::Reg<cfg_amux_0::CfgAmux0Spec>;
23050 #[doc = "cfg_amux_0"]
23051 pub mod cfg_amux_0 {
23052 #[doc = "Register `CFG_AMUX_0` reader"]
23053 pub type R = crate::R<CfgAmux0Spec>;
23054 #[doc = "Register `CFG_AMUX_0` writer"]
23055 pub type W = crate::W<CfgAmux0Spec>;
23056 impl core::fmt::Debug for R {
23057 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23058 write!(f, "{}", self.bits())
23059 }
23060 }
23061 impl W {}
23062 #[doc = "cfg_amux_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23063 pub struct CfgAmux0Spec;
23064 impl crate::RegisterSpec for CfgAmux0Spec {
23065 type Ux = u32;
23066 }
23067 #[doc = "`read()` method returns [`cfg_amux_0::R`](R) reader structure"]
23068 impl crate::Readable for CfgAmux0Spec {}
23069 #[doc = "`write(|w| ..)` method takes [`cfg_amux_0::W`](W) writer structure"]
23070 impl crate::Writable for CfgAmux0Spec {
23071 type Safety = crate::Unsafe;
23072 }
23073 #[doc = "`reset()` method sets CFG_AMUX_0 to value 0"]
23074 impl crate::Resettable for CfgAmux0Spec {}
23075 }
23076 #[doc = "CFG_AMUX_1 (rw) register accessor: cfg_amux_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_1`] module"]
23077 #[doc(alias = "CFG_AMUX_1")]
23078 pub type CfgAmux1 = crate::Reg<cfg_amux_1::CfgAmux1Spec>;
23079 #[doc = "cfg_amux_1"]
23080 pub mod cfg_amux_1 {
23081 #[doc = "Register `CFG_AMUX_1` reader"]
23082 pub type R = crate::R<CfgAmux1Spec>;
23083 #[doc = "Register `CFG_AMUX_1` writer"]
23084 pub type W = crate::W<CfgAmux1Spec>;
23085 #[doc = "Field `amuxn_sensor_ch_sel` reader - "]
23086 pub type AmuxnSensorChSelR = crate::FieldReader<u16>;
23087 #[doc = "Field `amuxn_sensor_ch_sel` writer - "]
23088 pub type AmuxnSensorChSelW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
23089 #[doc = "Field `amuxn_devide_disable` reader - "]
23090 pub type AmuxnDevideDisableR = crate::BitReader;
23091 #[doc = "Field `amuxn_devide_disable` writer - "]
23092 pub type AmuxnDevideDisableW<'a, REG> = crate::BitWriter<'a, REG>;
23093 #[doc = "Field `amuxp_sensor_ch_sel` reader - "]
23094 pub type AmuxpSensorChSelR = crate::FieldReader<u16>;
23095 #[doc = "Field `amuxp_sensor_ch_sel` writer - "]
23096 pub type AmuxpSensorChSelW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
23097 #[doc = "Field `amuxp_devide_disable` reader - "]
23098 pub type AmuxpDevideDisableR = crate::BitReader;
23099 #[doc = "Field `amuxp_devide_disable` writer - "]
23100 pub type AmuxpDevideDisableW<'a, REG> = crate::BitWriter<'a, REG>;
23101 impl R {
23102 #[doc = "Bits 0:10"]
23103 #[inline(always)]
23104 pub fn amuxn_sensor_ch_sel(&self) -> AmuxnSensorChSelR {
23105 AmuxnSensorChSelR::new((self.bits & 0x07ff) as u16)
23106 }
23107 #[doc = "Bit 11"]
23108 #[inline(always)]
23109 pub fn amuxn_devide_disable(&self) -> AmuxnDevideDisableR {
23110 AmuxnDevideDisableR::new(((self.bits >> 11) & 1) != 0)
23111 }
23112 #[doc = "Bits 12:22"]
23113 #[inline(always)]
23114 pub fn amuxp_sensor_ch_sel(&self) -> AmuxpSensorChSelR {
23115 AmuxpSensorChSelR::new(((self.bits >> 12) & 0x07ff) as u16)
23116 }
23117 #[doc = "Bit 23"]
23118 #[inline(always)]
23119 pub fn amuxp_devide_disable(&self) -> AmuxpDevideDisableR {
23120 AmuxpDevideDisableR::new(((self.bits >> 23) & 1) != 0)
23121 }
23122 }
23123 impl W {
23124 #[doc = "Bits 0:10"]
23125 #[inline(always)]
23126 pub fn amuxn_sensor_ch_sel(&mut self) -> AmuxnSensorChSelW<'_, CfgAmux1Spec> {
23127 AmuxnSensorChSelW::new(self, 0)
23128 }
23129 #[doc = "Bit 11"]
23130 #[inline(always)]
23131 pub fn amuxn_devide_disable(&mut self) -> AmuxnDevideDisableW<'_, CfgAmux1Spec> {
23132 AmuxnDevideDisableW::new(self, 11)
23133 }
23134 #[doc = "Bits 12:22"]
23135 #[inline(always)]
23136 pub fn amuxp_sensor_ch_sel(&mut self) -> AmuxpSensorChSelW<'_, CfgAmux1Spec> {
23137 AmuxpSensorChSelW::new(self, 12)
23138 }
23139 #[doc = "Bit 23"]
23140 #[inline(always)]
23141 pub fn amuxp_devide_disable(&mut self) -> AmuxpDevideDisableW<'_, CfgAmux1Spec> {
23142 AmuxpDevideDisableW::new(self, 23)
23143 }
23144 }
23145 #[doc = "cfg_amux_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23146 pub struct CfgAmux1Spec;
23147 impl crate::RegisterSpec for CfgAmux1Spec {
23148 type Ux = u32;
23149 }
23150 #[doc = "`read()` method returns [`cfg_amux_1::R`](R) reader structure"]
23151 impl crate::Readable for CfgAmux1Spec {}
23152 #[doc = "`write(|w| ..)` method takes [`cfg_amux_1::W`](W) writer structure"]
23153 impl crate::Writable for CfgAmux1Spec {
23154 type Safety = crate::Unsafe;
23155 }
23156 #[doc = "`reset()` method sets CFG_AMUX_1 to value 0"]
23157 impl crate::Resettable for CfgAmux1Spec {}
23158 }
23159 #[doc = "CFG_AMUX_2 (rw) register accessor: cfg_amux_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_2`] module"]
23160 #[doc(alias = "CFG_AMUX_2")]
23161 pub type CfgAmux2 = crate::Reg<cfg_amux_2::CfgAmux2Spec>;
23162 #[doc = "cfg_amux_2"]
23163 pub mod cfg_amux_2 {
23164 #[doc = "Register `CFG_AMUX_2` reader"]
23165 pub type R = crate::R<CfgAmux2Spec>;
23166 #[doc = "Register `CFG_AMUX_2` writer"]
23167 pub type W = crate::W<CfgAmux2Spec>;
23168 #[doc = "Field `cfg_amuxn_audio_ch_sel` reader - "]
23169 pub type CfgAmuxnAudioChSelR = crate::FieldReader;
23170 #[doc = "Field `cfg_amuxn_audio_ch_sel` writer - "]
23171 pub type CfgAmuxnAudioChSelW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
23172 #[doc = "Field `cfg_amuxp_audio_ch_sel` reader - "]
23173 pub type CfgAmuxpAudioChSelR = crate::FieldReader;
23174 #[doc = "Field `cfg_amuxp_audio_ch_sel` writer - "]
23175 pub type CfgAmuxpAudioChSelW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
23176 impl R {
23177 #[doc = "Bits 0:3"]
23178 #[inline(always)]
23179 pub fn cfg_amuxn_audio_ch_sel(&self) -> CfgAmuxnAudioChSelR {
23180 CfgAmuxnAudioChSelR::new((self.bits & 0x0f) as u8)
23181 }
23182 #[doc = "Bits 4:7"]
23183 #[inline(always)]
23184 pub fn cfg_amuxp_audio_ch_sel(&self) -> CfgAmuxpAudioChSelR {
23185 CfgAmuxpAudioChSelR::new(((self.bits >> 4) & 0x0f) as u8)
23186 }
23187 }
23188 impl W {
23189 #[doc = "Bits 0:3"]
23190 #[inline(always)]
23191 pub fn cfg_amuxn_audio_ch_sel(&mut self) -> CfgAmuxnAudioChSelW<'_, CfgAmux2Spec> {
23192 CfgAmuxnAudioChSelW::new(self, 0)
23193 }
23194 #[doc = "Bits 4:7"]
23195 #[inline(always)]
23196 pub fn cfg_amuxp_audio_ch_sel(&mut self) -> CfgAmuxpAudioChSelW<'_, CfgAmux2Spec> {
23197 CfgAmuxpAudioChSelW::new(self, 4)
23198 }
23199 }
23200 #[doc = "cfg_amux_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23201 pub struct CfgAmux2Spec;
23202 impl crate::RegisterSpec for CfgAmux2Spec {
23203 type Ux = u32;
23204 }
23205 #[doc = "`read()` method returns [`cfg_amux_2::R`](R) reader structure"]
23206 impl crate::Readable for CfgAmux2Spec {}
23207 #[doc = "`write(|w| ..)` method takes [`cfg_amux_2::W`](W) writer structure"]
23208 impl crate::Writable for CfgAmux2Spec {
23209 type Safety = crate::Unsafe;
23210 }
23211 #[doc = "`reset()` method sets CFG_AMUX_2 to value 0"]
23212 impl crate::Resettable for CfgAmux2Spec {}
23213 }
23214 #[doc = "CFG_AMUX_3 (rw) register accessor: cfg_amux_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_3`] module"]
23215 #[doc(alias = "CFG_AMUX_3")]
23216 pub type CfgAmux3 = crate::Reg<cfg_amux_3::CfgAmux3Spec>;
23217 #[doc = "cfg_amux_3"]
23218 pub mod cfg_amux_3 {
23219 #[doc = "Register `CFG_AMUX_3` reader"]
23220 pub type R = crate::R<CfgAmux3Spec>;
23221 #[doc = "Register `CFG_AMUX_3` writer"]
23222 pub type W = crate::W<CfgAmux3Spec>;
23223 impl core::fmt::Debug for R {
23224 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23225 write!(f, "{}", self.bits())
23226 }
23227 }
23228 impl W {}
23229 #[doc = "cfg_amux_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23230 pub struct CfgAmux3Spec;
23231 impl crate::RegisterSpec for CfgAmux3Spec {
23232 type Ux = u32;
23233 }
23234 #[doc = "`read()` method returns [`cfg_amux_3::R`](R) reader structure"]
23235 impl crate::Readable for CfgAmux3Spec {}
23236 #[doc = "`write(|w| ..)` method takes [`cfg_amux_3::W`](W) writer structure"]
23237 impl crate::Writable for CfgAmux3Spec {
23238 type Safety = crate::Unsafe;
23239 }
23240 #[doc = "`reset()` method sets CFG_AMUX_3 to value 0"]
23241 impl crate::Resettable for CfgAmux3Spec {}
23242 }
23243 #[doc = "CFG_AMUX_4 (rw) register accessor: cfg_amux_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_4`] module"]
23244 #[doc(alias = "CFG_AMUX_4")]
23245 pub type CfgAmux4 = crate::Reg<cfg_amux_4::CfgAmux4Spec>;
23246 #[doc = "cfg_amux_4"]
23247 pub mod cfg_amux_4 {
23248 #[doc = "Register `CFG_AMUX_4` reader"]
23249 pub type R = crate::R<CfgAmux4Spec>;
23250 #[doc = "Register `CFG_AMUX_4` writer"]
23251 pub type W = crate::W<CfgAmux4Spec>;
23252 impl core::fmt::Debug for R {
23253 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23254 write!(f, "{}", self.bits())
23255 }
23256 }
23257 impl W {}
23258 #[doc = "cfg_amux_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23259 pub struct CfgAmux4Spec;
23260 impl crate::RegisterSpec for CfgAmux4Spec {
23261 type Ux = u32;
23262 }
23263 #[doc = "`read()` method returns [`cfg_amux_4::R`](R) reader structure"]
23264 impl crate::Readable for CfgAmux4Spec {}
23265 #[doc = "`write(|w| ..)` method takes [`cfg_amux_4::W`](W) writer structure"]
23266 impl crate::Writable for CfgAmux4Spec {
23267 type Safety = crate::Unsafe;
23268 }
23269 #[doc = "`reset()` method sets CFG_AMUX_4 to value 0"]
23270 impl crate::Resettable for CfgAmux4Spec {}
23271 }
23272 #[doc = "CFG_AMUX_5 (rw) register accessor: cfg_amux_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_5`] module"]
23273 #[doc(alias = "CFG_AMUX_5")]
23274 pub type CfgAmux5 = crate::Reg<cfg_amux_5::CfgAmux5Spec>;
23275 #[doc = "cfg_amux_5"]
23276 pub mod cfg_amux_5 {
23277 #[doc = "Register `CFG_AMUX_5` reader"]
23278 pub type R = crate::R<CfgAmux5Spec>;
23279 #[doc = "Register `CFG_AMUX_5` writer"]
23280 pub type W = crate::W<CfgAmux5Spec>;
23281 impl core::fmt::Debug for R {
23282 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23283 write!(f, "{}", self.bits())
23284 }
23285 }
23286 impl W {}
23287 #[doc = "cfg_amux_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23288 pub struct CfgAmux5Spec;
23289 impl crate::RegisterSpec for CfgAmux5Spec {
23290 type Ux = u32;
23291 }
23292 #[doc = "`read()` method returns [`cfg_amux_5::R`](R) reader structure"]
23293 impl crate::Readable for CfgAmux5Spec {}
23294 #[doc = "`write(|w| ..)` method takes [`cfg_amux_5::W`](W) writer structure"]
23295 impl crate::Writable for CfgAmux5Spec {
23296 type Safety = crate::Unsafe;
23297 }
23298 #[doc = "`reset()` method sets CFG_AMUX_5 to value 0"]
23299 impl crate::Resettable for CfgAmux5Spec {}
23300 }
23301 #[doc = "RPT_AMUX_0 (rw) register accessor: rpt_amux_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_amux_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_amux_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_amux_0`] module"]
23302 #[doc(alias = "RPT_AMUX_0")]
23303 pub type RptAmux0 = crate::Reg<rpt_amux_0::RptAmux0Spec>;
23304 #[doc = "rpt_amux_0"]
23305 pub mod rpt_amux_0 {
23306 #[doc = "Register `RPT_AMUX_0` reader"]
23307 pub type R = crate::R<RptAmux0Spec>;
23308 #[doc = "Register `RPT_AMUX_0` writer"]
23309 pub type W = crate::W<RptAmux0Spec>;
23310 impl core::fmt::Debug for R {
23311 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23312 write!(f, "{}", self.bits())
23313 }
23314 }
23315 impl W {}
23316 #[doc = "rpt_amux_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_amux_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_amux_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23317 pub struct RptAmux0Spec;
23318 impl crate::RegisterSpec for RptAmux0Spec {
23319 type Ux = u32;
23320 }
23321 #[doc = "`read()` method returns [`rpt_amux_0::R`](R) reader structure"]
23322 impl crate::Readable for RptAmux0Spec {}
23323 #[doc = "`write(|w| ..)` method takes [`rpt_amux_0::W`](W) writer structure"]
23324 impl crate::Writable for RptAmux0Spec {
23325 type Safety = crate::Unsafe;
23326 }
23327 #[doc = "`reset()` method sets RPT_AMUX_0 to value 0"]
23328 impl crate::Resettable for RptAmux0Spec {}
23329 }
23330 #[doc = "CFG_TST_0 (rw) register accessor: cfg_tst_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tst_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tst_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tst_0`] module"]
23331 #[doc(alias = "CFG_TST_0")]
23332 pub type CfgTst0 = crate::Reg<cfg_tst_0::CfgTst0Spec>;
23333 #[doc = "cfg_tst_0"]
23334 pub mod cfg_tst_0 {
23335 #[doc = "Register `CFG_TST_0` reader"]
23336 pub type R = crate::R<CfgTst0Spec>;
23337 #[doc = "Register `CFG_TST_0` writer"]
23338 pub type W = crate::W<CfgTst0Spec>;
23339 impl core::fmt::Debug for R {
23340 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23341 write!(f, "{}", self.bits())
23342 }
23343 }
23344 impl W {}
23345 #[doc = "cfg_tst_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tst_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tst_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23346 pub struct CfgTst0Spec;
23347 impl crate::RegisterSpec for CfgTst0Spec {
23348 type Ux = u32;
23349 }
23350 #[doc = "`read()` method returns [`cfg_tst_0::R`](R) reader structure"]
23351 impl crate::Readable for CfgTst0Spec {}
23352 #[doc = "`write(|w| ..)` method takes [`cfg_tst_0::W`](W) writer structure"]
23353 impl crate::Writable for CfgTst0Spec {
23354 type Safety = crate::Unsafe;
23355 }
23356 #[doc = "`reset()` method sets CFG_TST_0 to value 0"]
23357 impl crate::Resettable for CfgTst0Spec {}
23358 }
23359 #[doc = "CFG_TST_1 (rw) register accessor: cfg_tst_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tst_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tst_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tst_1`] module"]
23360 #[doc(alias = "CFG_TST_1")]
23361 pub type CfgTst1 = crate::Reg<cfg_tst_1::CfgTst1Spec>;
23362 #[doc = "cfg_tst_1"]
23363 pub mod cfg_tst_1 {
23364 #[doc = "Register `CFG_TST_1` reader"]
23365 pub type R = crate::R<CfgTst1Spec>;
23366 #[doc = "Register `CFG_TST_1` writer"]
23367 pub type W = crate::W<CfgTst1Spec>;
23368 impl core::fmt::Debug for R {
23369 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23370 write!(f, "{}", self.bits())
23371 }
23372 }
23373 impl W {}
23374 #[doc = "cfg_tst_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tst_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tst_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23375 pub struct CfgTst1Spec;
23376 impl crate::RegisterSpec for CfgTst1Spec {
23377 type Ux = u32;
23378 }
23379 #[doc = "`read()` method returns [`cfg_tst_1::R`](R) reader structure"]
23380 impl crate::Readable for CfgTst1Spec {}
23381 #[doc = "`write(|w| ..)` method takes [`cfg_tst_1::W`](W) writer structure"]
23382 impl crate::Writable for CfgTst1Spec {
23383 type Safety = crate::Unsafe;
23384 }
23385 #[doc = "`reset()` method sets CFG_TST_1 to value 0"]
23386 impl crate::Resettable for CfgTst1Spec {}
23387 }
23388 #[doc = "CFG_CMP_0 (rw) register accessor: cfg_cmp_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_0`] module"]
23389 #[doc(alias = "CFG_CMP_0")]
23390 pub type CfgCmp0 = crate::Reg<cfg_cmp_0::CfgCmp0Spec>;
23391 #[doc = "cfg_cmp_0"]
23392 pub mod cfg_cmp_0 {
23393 #[doc = "Register `CFG_CMP_0` reader"]
23394 pub type R = crate::R<CfgCmp0Spec>;
23395 #[doc = "Register `CFG_CMP_0` writer"]
23396 pub type W = crate::W<CfgCmp0Spec>;
23397 impl core::fmt::Debug for R {
23398 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23399 write!(f, "{}", self.bits())
23400 }
23401 }
23402 impl W {}
23403 #[doc = "cfg_cmp_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23404 pub struct CfgCmp0Spec;
23405 impl crate::RegisterSpec for CfgCmp0Spec {
23406 type Ux = u32;
23407 }
23408 #[doc = "`read()` method returns [`cfg_cmp_0::R`](R) reader structure"]
23409 impl crate::Readable for CfgCmp0Spec {}
23410 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_0::W`](W) writer structure"]
23411 impl crate::Writable for CfgCmp0Spec {
23412 type Safety = crate::Unsafe;
23413 }
23414 #[doc = "`reset()` method sets CFG_CMP_0 to value 0"]
23415 impl crate::Resettable for CfgCmp0Spec {}
23416 }
23417 #[doc = "CFG_CMP_1 (rw) register accessor: cfg_cmp_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_1`] module"]
23418 #[doc(alias = "CFG_CMP_1")]
23419 pub type CfgCmp1 = crate::Reg<cfg_cmp_1::CfgCmp1Spec>;
23420 #[doc = "cfg_cmp_1"]
23421 pub mod cfg_cmp_1 {
23422 #[doc = "Register `CFG_CMP_1` reader"]
23423 pub type R = crate::R<CfgCmp1Spec>;
23424 #[doc = "Register `CFG_CMP_1` writer"]
23425 pub type W = crate::W<CfgCmp1Spec>;
23426 impl core::fmt::Debug for R {
23427 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23428 write!(f, "{}", self.bits())
23429 }
23430 }
23431 impl W {}
23432 #[doc = "cfg_cmp_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23433 pub struct CfgCmp1Spec;
23434 impl crate::RegisterSpec for CfgCmp1Spec {
23435 type Ux = u32;
23436 }
23437 #[doc = "`read()` method returns [`cfg_cmp_1::R`](R) reader structure"]
23438 impl crate::Readable for CfgCmp1Spec {}
23439 #[doc = "`write(|w| ..)` method takes [`cfg_cmp_1::W`](W) writer structure"]
23440 impl crate::Writable for CfgCmp1Spec {
23441 type Safety = crate::Unsafe;
23442 }
23443 #[doc = "`reset()` method sets CFG_CMP_1 to value 0"]
23444 impl crate::Resettable for CfgCmp1Spec {}
23445 }
23446 #[doc = "RPT_CMP_0 (rw) register accessor: rpt_cmp_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cmp_0`] module"]
23447 #[doc(alias = "RPT_CMP_0")]
23448 pub type RptCmp0 = crate::Reg<rpt_cmp_0::RptCmp0Spec>;
23449 #[doc = "rpt_cmp_0"]
23450 pub mod rpt_cmp_0 {
23451 #[doc = "Register `RPT_CMP_0` reader"]
23452 pub type R = crate::R<RptCmp0Spec>;
23453 #[doc = "Register `RPT_CMP_0` writer"]
23454 pub type W = crate::W<RptCmp0Spec>;
23455 impl core::fmt::Debug for R {
23456 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23457 write!(f, "{}", self.bits())
23458 }
23459 }
23460 impl W {}
23461 #[doc = "rpt_cmp_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23462 pub struct RptCmp0Spec;
23463 impl crate::RegisterSpec for RptCmp0Spec {
23464 type Ux = u32;
23465 }
23466 #[doc = "`read()` method returns [`rpt_cmp_0::R`](R) reader structure"]
23467 impl crate::Readable for RptCmp0Spec {}
23468 #[doc = "`write(|w| ..)` method takes [`rpt_cmp_0::W`](W) writer structure"]
23469 impl crate::Writable for RptCmp0Spec {
23470 type Safety = crate::Unsafe;
23471 }
23472 #[doc = "`reset()` method sets RPT_CMP_0 to value 0"]
23473 impl crate::Resettable for RptCmp0Spec {}
23474 }
23475 #[doc = "RPT_CMP_1 (rw) register accessor: rpt_cmp_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cmp_1`] module"]
23476 #[doc(alias = "RPT_CMP_1")]
23477 pub type RptCmp1 = crate::Reg<rpt_cmp_1::RptCmp1Spec>;
23478 #[doc = "rpt_cmp_1"]
23479 pub mod rpt_cmp_1 {
23480 #[doc = "Register `RPT_CMP_1` reader"]
23481 pub type R = crate::R<RptCmp1Spec>;
23482 #[doc = "Register `RPT_CMP_1` writer"]
23483 pub type W = crate::W<RptCmp1Spec>;
23484 impl core::fmt::Debug for R {
23485 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23486 write!(f, "{}", self.bits())
23487 }
23488 }
23489 impl W {}
23490 #[doc = "rpt_cmp_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23491 pub struct RptCmp1Spec;
23492 impl crate::RegisterSpec for RptCmp1Spec {
23493 type Ux = u32;
23494 }
23495 #[doc = "`read()` method returns [`rpt_cmp_1::R`](R) reader structure"]
23496 impl crate::Readable for RptCmp1Spec {}
23497 #[doc = "`write(|w| ..)` method takes [`rpt_cmp_1::W`](W) writer structure"]
23498 impl crate::Writable for RptCmp1Spec {
23499 type Safety = crate::Unsafe;
23500 }
23501 #[doc = "`reset()` method sets RPT_CMP_1 to value 0"]
23502 impl crate::Resettable for RptCmp1Spec {}
23503 }
23504}
23505#[doc = "Key-scan matrix controller (v150)"]
23506pub type Keyscan = crate::Periph<keyscan::RegisterBlock, 0x5208_d000>;
23507impl core::fmt::Debug for Keyscan {
23508 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
23509 f.debug_struct("Keyscan").finish()
23510 }
23511}
23512#[doc = "Key-scan matrix controller (v150)"]
23513pub mod keyscan {
23514 #[repr(C)]
23515 #[doc = "Register block"]
23516 pub struct RegisterBlock {
23517 _reserved0: [u8; 0x04],
23518 keyscan_lp_ctl: KeyscanLpCtl,
23519 keyscan_enable: KeyscanEnable,
23520 keyscan_clk_ena: KeyscanClkEna,
23521 keyscan_start: KeyscanStart,
23522 _reserved4: [u8; 0x0c],
23523 keyscan_int_en: KeyscanIntEn,
23524 keyscan_event_clr: KeyscanEventClr,
23525 keyscan_event_sts: KeyscanEventSts,
23526 _reserved7: [u8; 0x04],
23527 keyscan_pin_num: KeyscanPinNum,
23528 keyscan_mode: KeyscanMode,
23529 keyscan_pulse: KeyscanPulse,
23530 _reserved10: [u8; 0x14],
23531 keyscan_de: KeyscanDe,
23532 _reserved11: [u8; 0x40],
23533 key_value_fifo: KeyValueFifo,
23534 }
23535 impl RegisterBlock {
23536 #[doc = "0x04 - keyscan_lp_ctl"]
23537 #[inline(always)]
23538 pub const fn keyscan_lp_ctl(&self) -> &KeyscanLpCtl {
23539 &self.keyscan_lp_ctl
23540 }
23541 #[doc = "0x08 - keyscan_enable"]
23542 #[inline(always)]
23543 pub const fn keyscan_enable(&self) -> &KeyscanEnable {
23544 &self.keyscan_enable
23545 }
23546 #[doc = "0x0c - keyscan_clk_ena"]
23547 #[inline(always)]
23548 pub const fn keyscan_clk_ena(&self) -> &KeyscanClkEna {
23549 &self.keyscan_clk_ena
23550 }
23551 #[doc = "0x10 - keyscan_start"]
23552 #[inline(always)]
23553 pub const fn keyscan_start(&self) -> &KeyscanStart {
23554 &self.keyscan_start
23555 }
23556 #[doc = "0x20 - keyscan_int_en"]
23557 #[inline(always)]
23558 pub const fn keyscan_int_en(&self) -> &KeyscanIntEn {
23559 &self.keyscan_int_en
23560 }
23561 #[doc = "0x24 - keyscan_event_clr"]
23562 #[inline(always)]
23563 pub const fn keyscan_event_clr(&self) -> &KeyscanEventClr {
23564 &self.keyscan_event_clr
23565 }
23566 #[doc = "0x28 - keyscan_event_sts"]
23567 #[inline(always)]
23568 pub const fn keyscan_event_sts(&self) -> &KeyscanEventSts {
23569 &self.keyscan_event_sts
23570 }
23571 #[doc = "0x30 - keyscan_pin_num"]
23572 #[inline(always)]
23573 pub const fn keyscan_pin_num(&self) -> &KeyscanPinNum {
23574 &self.keyscan_pin_num
23575 }
23576 #[doc = "0x34 - keyscan_mode"]
23577 #[inline(always)]
23578 pub const fn keyscan_mode(&self) -> &KeyscanMode {
23579 &self.keyscan_mode
23580 }
23581 #[doc = "0x38 - keyscan_pulse"]
23582 #[inline(always)]
23583 pub const fn keyscan_pulse(&self) -> &KeyscanPulse {
23584 &self.keyscan_pulse
23585 }
23586 #[doc = "0x50 - keyscan_de"]
23587 #[inline(always)]
23588 pub const fn keyscan_de(&self) -> &KeyscanDe {
23589 &self.keyscan_de
23590 }
23591 #[doc = "0x94 - key_value_fifo"]
23592 #[inline(always)]
23593 pub const fn key_value_fifo(&self) -> &KeyValueFifo {
23594 &self.key_value_fifo
23595 }
23596 }
23597 #[doc = "KEYSCAN_LP_CTL (rw) register accessor: keyscan_lp_ctl\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_lp_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_lp_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_lp_ctl`] module"]
23598 #[doc(alias = "KEYSCAN_LP_CTL")]
23599 pub type KeyscanLpCtl = crate::Reg<keyscan_lp_ctl::KeyscanLpCtlSpec>;
23600 #[doc = "keyscan_lp_ctl"]
23601 pub mod keyscan_lp_ctl {
23602 #[doc = "Register `KEYSCAN_LP_CTL` reader"]
23603 pub type R = crate::R<KeyscanLpCtlSpec>;
23604 #[doc = "Register `KEYSCAN_LP_CTL` writer"]
23605 pub type W = crate::W<KeyscanLpCtlSpec>;
23606 #[doc = "Field `alow_slp` reader - "]
23607 pub type AlowSlpR = crate::BitReader;
23608 #[doc = "Field `alow_slp` writer - "]
23609 pub type AlowSlpW<'a, REG> = crate::BitWriter<'a, REG>;
23610 #[doc = "Field `slp_req` reader - "]
23611 pub type SlpReqR = crate::BitReader;
23612 #[doc = "Field `slp_req` writer - "]
23613 pub type SlpReqW<'a, REG> = crate::BitWriter<'a, REG>;
23614 #[doc = "Field `slp_ack` reader - "]
23615 pub type SlpAckR = crate::BitReader;
23616 #[doc = "Field `slp_ack` writer - "]
23617 pub type SlpAckW<'a, REG> = crate::BitWriter<'a, REG>;
23618 impl R {
23619 #[doc = "Bit 0"]
23620 #[inline(always)]
23621 pub fn alow_slp(&self) -> AlowSlpR {
23622 AlowSlpR::new((self.bits & 1) != 0)
23623 }
23624 #[doc = "Bit 4"]
23625 #[inline(always)]
23626 pub fn slp_req(&self) -> SlpReqR {
23627 SlpReqR::new(((self.bits >> 4) & 1) != 0)
23628 }
23629 #[doc = "Bit 8"]
23630 #[inline(always)]
23631 pub fn slp_ack(&self) -> SlpAckR {
23632 SlpAckR::new(((self.bits >> 8) & 1) != 0)
23633 }
23634 }
23635 impl W {
23636 #[doc = "Bit 0"]
23637 #[inline(always)]
23638 pub fn alow_slp(&mut self) -> AlowSlpW<'_, KeyscanLpCtlSpec> {
23639 AlowSlpW::new(self, 0)
23640 }
23641 #[doc = "Bit 4"]
23642 #[inline(always)]
23643 pub fn slp_req(&mut self) -> SlpReqW<'_, KeyscanLpCtlSpec> {
23644 SlpReqW::new(self, 4)
23645 }
23646 #[doc = "Bit 8"]
23647 #[inline(always)]
23648 pub fn slp_ack(&mut self) -> SlpAckW<'_, KeyscanLpCtlSpec> {
23649 SlpAckW::new(self, 8)
23650 }
23651 }
23652 #[doc = "keyscan_lp_ctl\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_lp_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_lp_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23653 pub struct KeyscanLpCtlSpec;
23654 impl crate::RegisterSpec for KeyscanLpCtlSpec {
23655 type Ux = u32;
23656 }
23657 #[doc = "`read()` method returns [`keyscan_lp_ctl::R`](R) reader structure"]
23658 impl crate::Readable for KeyscanLpCtlSpec {}
23659 #[doc = "`write(|w| ..)` method takes [`keyscan_lp_ctl::W`](W) writer structure"]
23660 impl crate::Writable for KeyscanLpCtlSpec {
23661 type Safety = crate::Unsafe;
23662 }
23663 #[doc = "`reset()` method sets KEYSCAN_LP_CTL to value 0"]
23664 impl crate::Resettable for KeyscanLpCtlSpec {}
23665 }
23666 #[doc = "KEYSCAN_ENABLE (rw) register accessor: keyscan_enable\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_enable`] module"]
23667 #[doc(alias = "KEYSCAN_ENABLE")]
23668 pub type KeyscanEnable = crate::Reg<keyscan_enable::KeyscanEnableSpec>;
23669 #[doc = "keyscan_enable"]
23670 pub mod keyscan_enable {
23671 #[doc = "Register `KEYSCAN_ENABLE` reader"]
23672 pub type R = crate::R<KeyscanEnableSpec>;
23673 #[doc = "Register `KEYSCAN_ENABLE` writer"]
23674 pub type W = crate::W<KeyscanEnableSpec>;
23675 #[doc = "Field `ena` reader - "]
23676 pub type EnaR = crate::BitReader;
23677 #[doc = "Field `ena` writer - "]
23678 pub type EnaW<'a, REG> = crate::BitWriter<'a, REG>;
23679 impl R {
23680 #[doc = "Bit 0"]
23681 #[inline(always)]
23682 pub fn ena(&self) -> EnaR {
23683 EnaR::new((self.bits & 1) != 0)
23684 }
23685 }
23686 impl W {
23687 #[doc = "Bit 0"]
23688 #[inline(always)]
23689 pub fn ena(&mut self) -> EnaW<'_, KeyscanEnableSpec> {
23690 EnaW::new(self, 0)
23691 }
23692 }
23693 #[doc = "keyscan_enable\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23694 pub struct KeyscanEnableSpec;
23695 impl crate::RegisterSpec for KeyscanEnableSpec {
23696 type Ux = u32;
23697 }
23698 #[doc = "`read()` method returns [`keyscan_enable::R`](R) reader structure"]
23699 impl crate::Readable for KeyscanEnableSpec {}
23700 #[doc = "`write(|w| ..)` method takes [`keyscan_enable::W`](W) writer structure"]
23701 impl crate::Writable for KeyscanEnableSpec {
23702 type Safety = crate::Unsafe;
23703 }
23704 #[doc = "`reset()` method sets KEYSCAN_ENABLE to value 0"]
23705 impl crate::Resettable for KeyscanEnableSpec {}
23706 }
23707 #[doc = "KEYSCAN_CLK_ENA (rw) register accessor: keyscan_clk_ena\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_clk_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_clk_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_clk_ena`] module"]
23708 #[doc(alias = "KEYSCAN_CLK_ENA")]
23709 pub type KeyscanClkEna = crate::Reg<keyscan_clk_ena::KeyscanClkEnaSpec>;
23710 #[doc = "keyscan_clk_ena"]
23711 pub mod keyscan_clk_ena {
23712 #[doc = "Register `KEYSCAN_CLK_ENA` reader"]
23713 pub type R = crate::R<KeyscanClkEnaSpec>;
23714 #[doc = "Register `KEYSCAN_CLK_ENA` writer"]
23715 pub type W = crate::W<KeyscanClkEnaSpec>;
23716 #[doc = "Field `fifo_rd_clken` reader - "]
23717 pub type FifoRdClkenR = crate::BitReader;
23718 #[doc = "Field `fifo_rd_clken` writer - "]
23719 pub type FifoRdClkenW<'a, REG> = crate::BitWriter<'a, REG>;
23720 impl R {
23721 #[doc = "Bit 0"]
23722 #[inline(always)]
23723 pub fn fifo_rd_clken(&self) -> FifoRdClkenR {
23724 FifoRdClkenR::new((self.bits & 1) != 0)
23725 }
23726 }
23727 impl W {
23728 #[doc = "Bit 0"]
23729 #[inline(always)]
23730 pub fn fifo_rd_clken(&mut self) -> FifoRdClkenW<'_, KeyscanClkEnaSpec> {
23731 FifoRdClkenW::new(self, 0)
23732 }
23733 }
23734 #[doc = "keyscan_clk_ena\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_clk_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_clk_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23735 pub struct KeyscanClkEnaSpec;
23736 impl crate::RegisterSpec for KeyscanClkEnaSpec {
23737 type Ux = u32;
23738 }
23739 #[doc = "`read()` method returns [`keyscan_clk_ena::R`](R) reader structure"]
23740 impl crate::Readable for KeyscanClkEnaSpec {}
23741 #[doc = "`write(|w| ..)` method takes [`keyscan_clk_ena::W`](W) writer structure"]
23742 impl crate::Writable for KeyscanClkEnaSpec {
23743 type Safety = crate::Unsafe;
23744 }
23745 #[doc = "`reset()` method sets KEYSCAN_CLK_ENA to value 0"]
23746 impl crate::Resettable for KeyscanClkEnaSpec {}
23747 }
23748 #[doc = "KEYSCAN_START (rw) register accessor: keyscan_start\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_start`] module"]
23749 #[doc(alias = "KEYSCAN_START")]
23750 pub type KeyscanStart = crate::Reg<keyscan_start::KeyscanStartSpec>;
23751 #[doc = "keyscan_start"]
23752 pub mod keyscan_start {
23753 #[doc = "Register `KEYSCAN_START` reader"]
23754 pub type R = crate::R<KeyscanStartSpec>;
23755 #[doc = "Register `KEYSCAN_START` writer"]
23756 pub type W = crate::W<KeyscanStartSpec>;
23757 #[doc = "Field `task_start` reader - "]
23758 pub type TaskStartR = crate::BitReader;
23759 #[doc = "Field `task_start` writer - "]
23760 pub type TaskStartW<'a, REG> = crate::BitWriter<'a, REG>;
23761 impl R {
23762 #[doc = "Bit 0"]
23763 #[inline(always)]
23764 pub fn task_start(&self) -> TaskStartR {
23765 TaskStartR::new((self.bits & 1) != 0)
23766 }
23767 }
23768 impl W {
23769 #[doc = "Bit 0"]
23770 #[inline(always)]
23771 pub fn task_start(&mut self) -> TaskStartW<'_, KeyscanStartSpec> {
23772 TaskStartW::new(self, 0)
23773 }
23774 }
23775 #[doc = "keyscan_start\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23776 pub struct KeyscanStartSpec;
23777 impl crate::RegisterSpec for KeyscanStartSpec {
23778 type Ux = u32;
23779 }
23780 #[doc = "`read()` method returns [`keyscan_start::R`](R) reader structure"]
23781 impl crate::Readable for KeyscanStartSpec {}
23782 #[doc = "`write(|w| ..)` method takes [`keyscan_start::W`](W) writer structure"]
23783 impl crate::Writable for KeyscanStartSpec {
23784 type Safety = crate::Unsafe;
23785 }
23786 #[doc = "`reset()` method sets KEYSCAN_START to value 0"]
23787 impl crate::Resettable for KeyscanStartSpec {}
23788 }
23789 #[doc = "KEYSCAN_INT_EN (rw) register accessor: keyscan_int_en\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_int_en`] module"]
23790 #[doc(alias = "KEYSCAN_INT_EN")]
23791 pub type KeyscanIntEn = crate::Reg<keyscan_int_en::KeyscanIntEnSpec>;
23792 #[doc = "keyscan_int_en"]
23793 pub mod keyscan_int_en {
23794 #[doc = "Register `KEYSCAN_INT_EN` reader"]
23795 pub type R = crate::R<KeyscanIntEnSpec>;
23796 #[doc = "Register `KEYSCAN_INT_EN` writer"]
23797 pub type W = crate::W<KeyscanIntEnSpec>;
23798 #[doc = "Field `event_fifo_full_int_en` reader - "]
23799 pub type EventFifoFullIntEnR = crate::BitReader;
23800 #[doc = "Field `event_fifo_full_int_en` writer - "]
23801 pub type EventFifoFullIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
23802 #[doc = "Field `event_key_press_int_en` reader - "]
23803 pub type EventKeyPressIntEnR = crate::BitReader;
23804 #[doc = "Field `event_key_press_int_en` writer - "]
23805 pub type EventKeyPressIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
23806 #[doc = "Field `event_key_release_int_en` reader - "]
23807 pub type EventKeyReleaseIntEnR = crate::BitReader;
23808 #[doc = "Field `event_key_release_int_en` writer - "]
23809 pub type EventKeyReleaseIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
23810 #[doc = "Field `event_key_value_rdy_int_en` reader - "]
23811 pub type EventKeyValueRdyIntEnR = crate::BitReader;
23812 #[doc = "Field `event_key_value_rdy_int_en` writer - "]
23813 pub type EventKeyValueRdyIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
23814 #[doc = "Field `event_key_stopped_int_en` reader - "]
23815 pub type EventKeyStoppedIntEnR = crate::BitReader;
23816 #[doc = "Field `event_key_stopped_int_en` writer - "]
23817 pub type EventKeyStoppedIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
23818 #[doc = "Field `event_keyscan_one_int_en` reader - "]
23819 pub type EventKeyscanOneIntEnR = crate::BitReader;
23820 #[doc = "Field `event_keyscan_one_int_en` writer - "]
23821 pub type EventKeyscanOneIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
23822 #[doc = "Field `event_fifo_afull_int_en` reader - "]
23823 pub type EventFifoAfullIntEnR = crate::BitReader;
23824 #[doc = "Field `event_fifo_afull_int_en` writer - "]
23825 pub type EventFifoAfullIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
23826 #[doc = "Field `event_key_press_aon_int_en` reader - "]
23827 pub type EventKeyPressAonIntEnR = crate::BitReader;
23828 #[doc = "Field `event_key_press_aon_int_en` writer - "]
23829 pub type EventKeyPressAonIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
23830 impl R {
23831 #[doc = "Bit 0"]
23832 #[inline(always)]
23833 pub fn event_fifo_full_int_en(&self) -> EventFifoFullIntEnR {
23834 EventFifoFullIntEnR::new((self.bits & 1) != 0)
23835 }
23836 #[doc = "Bit 1"]
23837 #[inline(always)]
23838 pub fn event_key_press_int_en(&self) -> EventKeyPressIntEnR {
23839 EventKeyPressIntEnR::new(((self.bits >> 1) & 1) != 0)
23840 }
23841 #[doc = "Bit 2"]
23842 #[inline(always)]
23843 pub fn event_key_release_int_en(&self) -> EventKeyReleaseIntEnR {
23844 EventKeyReleaseIntEnR::new(((self.bits >> 2) & 1) != 0)
23845 }
23846 #[doc = "Bit 3"]
23847 #[inline(always)]
23848 pub fn event_key_value_rdy_int_en(&self) -> EventKeyValueRdyIntEnR {
23849 EventKeyValueRdyIntEnR::new(((self.bits >> 3) & 1) != 0)
23850 }
23851 #[doc = "Bit 4"]
23852 #[inline(always)]
23853 pub fn event_key_stopped_int_en(&self) -> EventKeyStoppedIntEnR {
23854 EventKeyStoppedIntEnR::new(((self.bits >> 4) & 1) != 0)
23855 }
23856 #[doc = "Bit 5"]
23857 #[inline(always)]
23858 pub fn event_keyscan_one_int_en(&self) -> EventKeyscanOneIntEnR {
23859 EventKeyscanOneIntEnR::new(((self.bits >> 5) & 1) != 0)
23860 }
23861 #[doc = "Bit 6"]
23862 #[inline(always)]
23863 pub fn event_fifo_afull_int_en(&self) -> EventFifoAfullIntEnR {
23864 EventFifoAfullIntEnR::new(((self.bits >> 6) & 1) != 0)
23865 }
23866 #[doc = "Bit 7"]
23867 #[inline(always)]
23868 pub fn event_key_press_aon_int_en(&self) -> EventKeyPressAonIntEnR {
23869 EventKeyPressAonIntEnR::new(((self.bits >> 7) & 1) != 0)
23870 }
23871 }
23872 impl W {
23873 #[doc = "Bit 0"]
23874 #[inline(always)]
23875 pub fn event_fifo_full_int_en(&mut self) -> EventFifoFullIntEnW<'_, KeyscanIntEnSpec> {
23876 EventFifoFullIntEnW::new(self, 0)
23877 }
23878 #[doc = "Bit 1"]
23879 #[inline(always)]
23880 pub fn event_key_press_int_en(&mut self) -> EventKeyPressIntEnW<'_, KeyscanIntEnSpec> {
23881 EventKeyPressIntEnW::new(self, 1)
23882 }
23883 #[doc = "Bit 2"]
23884 #[inline(always)]
23885 pub fn event_key_release_int_en(
23886 &mut self,
23887 ) -> EventKeyReleaseIntEnW<'_, KeyscanIntEnSpec> {
23888 EventKeyReleaseIntEnW::new(self, 2)
23889 }
23890 #[doc = "Bit 3"]
23891 #[inline(always)]
23892 pub fn event_key_value_rdy_int_en(
23893 &mut self,
23894 ) -> EventKeyValueRdyIntEnW<'_, KeyscanIntEnSpec> {
23895 EventKeyValueRdyIntEnW::new(self, 3)
23896 }
23897 #[doc = "Bit 4"]
23898 #[inline(always)]
23899 pub fn event_key_stopped_int_en(
23900 &mut self,
23901 ) -> EventKeyStoppedIntEnW<'_, KeyscanIntEnSpec> {
23902 EventKeyStoppedIntEnW::new(self, 4)
23903 }
23904 #[doc = "Bit 5"]
23905 #[inline(always)]
23906 pub fn event_keyscan_one_int_en(
23907 &mut self,
23908 ) -> EventKeyscanOneIntEnW<'_, KeyscanIntEnSpec> {
23909 EventKeyscanOneIntEnW::new(self, 5)
23910 }
23911 #[doc = "Bit 6"]
23912 #[inline(always)]
23913 pub fn event_fifo_afull_int_en(
23914 &mut self,
23915 ) -> EventFifoAfullIntEnW<'_, KeyscanIntEnSpec> {
23916 EventFifoAfullIntEnW::new(self, 6)
23917 }
23918 #[doc = "Bit 7"]
23919 #[inline(always)]
23920 pub fn event_key_press_aon_int_en(
23921 &mut self,
23922 ) -> EventKeyPressAonIntEnW<'_, KeyscanIntEnSpec> {
23923 EventKeyPressAonIntEnW::new(self, 7)
23924 }
23925 }
23926 #[doc = "keyscan_int_en\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
23927 pub struct KeyscanIntEnSpec;
23928 impl crate::RegisterSpec for KeyscanIntEnSpec {
23929 type Ux = u32;
23930 }
23931 #[doc = "`read()` method returns [`keyscan_int_en::R`](R) reader structure"]
23932 impl crate::Readable for KeyscanIntEnSpec {}
23933 #[doc = "`write(|w| ..)` method takes [`keyscan_int_en::W`](W) writer structure"]
23934 impl crate::Writable for KeyscanIntEnSpec {
23935 type Safety = crate::Unsafe;
23936 }
23937 #[doc = "`reset()` method sets KEYSCAN_INT_EN to value 0"]
23938 impl crate::Resettable for KeyscanIntEnSpec {}
23939 }
23940 #[doc = "KEYSCAN_EVENT_CLR (rw) register accessor: keyscan_event_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_event_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_event_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_event_clr`] module"]
23941 #[doc(alias = "KEYSCAN_EVENT_CLR")]
23942 pub type KeyscanEventClr = crate::Reg<keyscan_event_clr::KeyscanEventClrSpec>;
23943 #[doc = "keyscan_event_clr"]
23944 pub mod keyscan_event_clr {
23945 #[doc = "Register `KEYSCAN_EVENT_CLR` reader"]
23946 pub type R = crate::R<KeyscanEventClrSpec>;
23947 #[doc = "Register `KEYSCAN_EVENT_CLR` writer"]
23948 pub type W = crate::W<KeyscanEventClrSpec>;
23949 #[doc = "Field `event_fifo_full_clr` reader - "]
23950 pub type EventFifoFullClrR = crate::BitReader;
23951 #[doc = "Field `event_fifo_full_clr` writer - "]
23952 pub type EventFifoFullClrW<'a, REG> = crate::BitWriter<'a, REG>;
23953 #[doc = "Field `event_key_press_clr` reader - "]
23954 pub type EventKeyPressClrR = crate::BitReader;
23955 #[doc = "Field `event_key_press_clr` writer - "]
23956 pub type EventKeyPressClrW<'a, REG> = crate::BitWriter<'a, REG>;
23957 #[doc = "Field `event_key_release_clr` reader - "]
23958 pub type EventKeyReleaseClrR = crate::BitReader;
23959 #[doc = "Field `event_key_release_clr` writer - "]
23960 pub type EventKeyReleaseClrW<'a, REG> = crate::BitWriter<'a, REG>;
23961 #[doc = "Field `event_key_value_rdy_clr` reader - "]
23962 pub type EventKeyValueRdyClrR = crate::BitReader;
23963 #[doc = "Field `event_key_value_rdy_clr` writer - "]
23964 pub type EventKeyValueRdyClrW<'a, REG> = crate::BitWriter<'a, REG>;
23965 #[doc = "Field `event_key_stopped_clr` reader - "]
23966 pub type EventKeyStoppedClrR = crate::BitReader;
23967 #[doc = "Field `event_key_stopped_clr` writer - "]
23968 pub type EventKeyStoppedClrW<'a, REG> = crate::BitWriter<'a, REG>;
23969 #[doc = "Field `event_keyscan_one_clr` reader - "]
23970 pub type EventKeyscanOneClrR = crate::BitReader;
23971 #[doc = "Field `event_keyscan_one_clr` writer - "]
23972 pub type EventKeyscanOneClrW<'a, REG> = crate::BitWriter<'a, REG>;
23973 #[doc = "Field `event_fifo_afull_clr` reader - "]
23974 pub type EventFifoAfullClrR = crate::BitReader;
23975 #[doc = "Field `event_fifo_afull_clr` writer - "]
23976 pub type EventFifoAfullClrW<'a, REG> = crate::BitWriter<'a, REG>;
23977 #[doc = "Field `event_key_press_aon_clr` reader - "]
23978 pub type EventKeyPressAonClrR = crate::BitReader;
23979 #[doc = "Field `event_key_press_aon_clr` writer - "]
23980 pub type EventKeyPressAonClrW<'a, REG> = crate::BitWriter<'a, REG>;
23981 impl R {
23982 #[doc = "Bit 0"]
23983 #[inline(always)]
23984 pub fn event_fifo_full_clr(&self) -> EventFifoFullClrR {
23985 EventFifoFullClrR::new((self.bits & 1) != 0)
23986 }
23987 #[doc = "Bit 1"]
23988 #[inline(always)]
23989 pub fn event_key_press_clr(&self) -> EventKeyPressClrR {
23990 EventKeyPressClrR::new(((self.bits >> 1) & 1) != 0)
23991 }
23992 #[doc = "Bit 2"]
23993 #[inline(always)]
23994 pub fn event_key_release_clr(&self) -> EventKeyReleaseClrR {
23995 EventKeyReleaseClrR::new(((self.bits >> 2) & 1) != 0)
23996 }
23997 #[doc = "Bit 3"]
23998 #[inline(always)]
23999 pub fn event_key_value_rdy_clr(&self) -> EventKeyValueRdyClrR {
24000 EventKeyValueRdyClrR::new(((self.bits >> 3) & 1) != 0)
24001 }
24002 #[doc = "Bit 4"]
24003 #[inline(always)]
24004 pub fn event_key_stopped_clr(&self) -> EventKeyStoppedClrR {
24005 EventKeyStoppedClrR::new(((self.bits >> 4) & 1) != 0)
24006 }
24007 #[doc = "Bit 5"]
24008 #[inline(always)]
24009 pub fn event_keyscan_one_clr(&self) -> EventKeyscanOneClrR {
24010 EventKeyscanOneClrR::new(((self.bits >> 5) & 1) != 0)
24011 }
24012 #[doc = "Bit 6"]
24013 #[inline(always)]
24014 pub fn event_fifo_afull_clr(&self) -> EventFifoAfullClrR {
24015 EventFifoAfullClrR::new(((self.bits >> 6) & 1) != 0)
24016 }
24017 #[doc = "Bit 7"]
24018 #[inline(always)]
24019 pub fn event_key_press_aon_clr(&self) -> EventKeyPressAonClrR {
24020 EventKeyPressAonClrR::new(((self.bits >> 7) & 1) != 0)
24021 }
24022 }
24023 impl W {
24024 #[doc = "Bit 0"]
24025 #[inline(always)]
24026 pub fn event_fifo_full_clr(&mut self) -> EventFifoFullClrW<'_, KeyscanEventClrSpec> {
24027 EventFifoFullClrW::new(self, 0)
24028 }
24029 #[doc = "Bit 1"]
24030 #[inline(always)]
24031 pub fn event_key_press_clr(&mut self) -> EventKeyPressClrW<'_, KeyscanEventClrSpec> {
24032 EventKeyPressClrW::new(self, 1)
24033 }
24034 #[doc = "Bit 2"]
24035 #[inline(always)]
24036 pub fn event_key_release_clr(
24037 &mut self,
24038 ) -> EventKeyReleaseClrW<'_, KeyscanEventClrSpec> {
24039 EventKeyReleaseClrW::new(self, 2)
24040 }
24041 #[doc = "Bit 3"]
24042 #[inline(always)]
24043 pub fn event_key_value_rdy_clr(
24044 &mut self,
24045 ) -> EventKeyValueRdyClrW<'_, KeyscanEventClrSpec> {
24046 EventKeyValueRdyClrW::new(self, 3)
24047 }
24048 #[doc = "Bit 4"]
24049 #[inline(always)]
24050 pub fn event_key_stopped_clr(
24051 &mut self,
24052 ) -> EventKeyStoppedClrW<'_, KeyscanEventClrSpec> {
24053 EventKeyStoppedClrW::new(self, 4)
24054 }
24055 #[doc = "Bit 5"]
24056 #[inline(always)]
24057 pub fn event_keyscan_one_clr(
24058 &mut self,
24059 ) -> EventKeyscanOneClrW<'_, KeyscanEventClrSpec> {
24060 EventKeyscanOneClrW::new(self, 5)
24061 }
24062 #[doc = "Bit 6"]
24063 #[inline(always)]
24064 pub fn event_fifo_afull_clr(&mut self) -> EventFifoAfullClrW<'_, KeyscanEventClrSpec> {
24065 EventFifoAfullClrW::new(self, 6)
24066 }
24067 #[doc = "Bit 7"]
24068 #[inline(always)]
24069 pub fn event_key_press_aon_clr(
24070 &mut self,
24071 ) -> EventKeyPressAonClrW<'_, KeyscanEventClrSpec> {
24072 EventKeyPressAonClrW::new(self, 7)
24073 }
24074 }
24075 #[doc = "keyscan_event_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_event_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_event_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24076 pub struct KeyscanEventClrSpec;
24077 impl crate::RegisterSpec for KeyscanEventClrSpec {
24078 type Ux = u32;
24079 }
24080 #[doc = "`read()` method returns [`keyscan_event_clr::R`](R) reader structure"]
24081 impl crate::Readable for KeyscanEventClrSpec {}
24082 #[doc = "`write(|w| ..)` method takes [`keyscan_event_clr::W`](W) writer structure"]
24083 impl crate::Writable for KeyscanEventClrSpec {
24084 type Safety = crate::Unsafe;
24085 }
24086 #[doc = "`reset()` method sets KEYSCAN_EVENT_CLR to value 0"]
24087 impl crate::Resettable for KeyscanEventClrSpec {}
24088 }
24089 #[doc = "KEYSCAN_EVENT_STS (rw) register accessor: keyscan_event_sts\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_event_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_event_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_event_sts`] module"]
24090 #[doc(alias = "KEYSCAN_EVENT_STS")]
24091 pub type KeyscanEventSts = crate::Reg<keyscan_event_sts::KeyscanEventStsSpec>;
24092 #[doc = "keyscan_event_sts"]
24093 pub mod keyscan_event_sts {
24094 #[doc = "Register `KEYSCAN_EVENT_STS` reader"]
24095 pub type R = crate::R<KeyscanEventStsSpec>;
24096 #[doc = "Register `KEYSCAN_EVENT_STS` writer"]
24097 pub type W = crate::W<KeyscanEventStsSpec>;
24098 #[doc = "Field `event_fifo_full` reader - "]
24099 pub type EventFifoFullR = crate::BitReader;
24100 #[doc = "Field `event_fifo_full` writer - "]
24101 pub type EventFifoFullW<'a, REG> = crate::BitWriter<'a, REG>;
24102 #[doc = "Field `event_key_press` reader - "]
24103 pub type EventKeyPressR = crate::BitReader;
24104 #[doc = "Field `event_key_press` writer - "]
24105 pub type EventKeyPressW<'a, REG> = crate::BitWriter<'a, REG>;
24106 #[doc = "Field `event_key_release` reader - "]
24107 pub type EventKeyReleaseR = crate::BitReader;
24108 #[doc = "Field `event_key_release` writer - "]
24109 pub type EventKeyReleaseW<'a, REG> = crate::BitWriter<'a, REG>;
24110 #[doc = "Field `event_key_value_rdy` reader - "]
24111 pub type EventKeyValueRdyR = crate::BitReader;
24112 #[doc = "Field `event_key_value_rdy` writer - "]
24113 pub type EventKeyValueRdyW<'a, REG> = crate::BitWriter<'a, REG>;
24114 #[doc = "Field `event_key_stopped` reader - "]
24115 pub type EventKeyStoppedR = crate::BitReader;
24116 #[doc = "Field `event_key_stopped` writer - "]
24117 pub type EventKeyStoppedW<'a, REG> = crate::BitWriter<'a, REG>;
24118 #[doc = "Field `event_keyscan_one` reader - "]
24119 pub type EventKeyscanOneR = crate::BitReader;
24120 #[doc = "Field `event_keyscan_one` writer - "]
24121 pub type EventKeyscanOneW<'a, REG> = crate::BitWriter<'a, REG>;
24122 #[doc = "Field `event_fifo_afull` reader - "]
24123 pub type EventFifoAfullR = crate::BitReader;
24124 #[doc = "Field `event_fifo_afull` writer - "]
24125 pub type EventFifoAfullW<'a, REG> = crate::BitWriter<'a, REG>;
24126 #[doc = "Field `event_key_press_aon` reader - "]
24127 pub type EventKeyPressAonR = crate::BitReader;
24128 #[doc = "Field `event_key_press_aon` writer - "]
24129 pub type EventKeyPressAonW<'a, REG> = crate::BitWriter<'a, REG>;
24130 impl R {
24131 #[doc = "Bit 0"]
24132 #[inline(always)]
24133 pub fn event_fifo_full(&self) -> EventFifoFullR {
24134 EventFifoFullR::new((self.bits & 1) != 0)
24135 }
24136 #[doc = "Bit 1"]
24137 #[inline(always)]
24138 pub fn event_key_press(&self) -> EventKeyPressR {
24139 EventKeyPressR::new(((self.bits >> 1) & 1) != 0)
24140 }
24141 #[doc = "Bit 2"]
24142 #[inline(always)]
24143 pub fn event_key_release(&self) -> EventKeyReleaseR {
24144 EventKeyReleaseR::new(((self.bits >> 2) & 1) != 0)
24145 }
24146 #[doc = "Bit 3"]
24147 #[inline(always)]
24148 pub fn event_key_value_rdy(&self) -> EventKeyValueRdyR {
24149 EventKeyValueRdyR::new(((self.bits >> 3) & 1) != 0)
24150 }
24151 #[doc = "Bit 4"]
24152 #[inline(always)]
24153 pub fn event_key_stopped(&self) -> EventKeyStoppedR {
24154 EventKeyStoppedR::new(((self.bits >> 4) & 1) != 0)
24155 }
24156 #[doc = "Bit 5"]
24157 #[inline(always)]
24158 pub fn event_keyscan_one(&self) -> EventKeyscanOneR {
24159 EventKeyscanOneR::new(((self.bits >> 5) & 1) != 0)
24160 }
24161 #[doc = "Bit 6"]
24162 #[inline(always)]
24163 pub fn event_fifo_afull(&self) -> EventFifoAfullR {
24164 EventFifoAfullR::new(((self.bits >> 6) & 1) != 0)
24165 }
24166 #[doc = "Bit 7"]
24167 #[inline(always)]
24168 pub fn event_key_press_aon(&self) -> EventKeyPressAonR {
24169 EventKeyPressAonR::new(((self.bits >> 7) & 1) != 0)
24170 }
24171 }
24172 impl W {
24173 #[doc = "Bit 0"]
24174 #[inline(always)]
24175 pub fn event_fifo_full(&mut self) -> EventFifoFullW<'_, KeyscanEventStsSpec> {
24176 EventFifoFullW::new(self, 0)
24177 }
24178 #[doc = "Bit 1"]
24179 #[inline(always)]
24180 pub fn event_key_press(&mut self) -> EventKeyPressW<'_, KeyscanEventStsSpec> {
24181 EventKeyPressW::new(self, 1)
24182 }
24183 #[doc = "Bit 2"]
24184 #[inline(always)]
24185 pub fn event_key_release(&mut self) -> EventKeyReleaseW<'_, KeyscanEventStsSpec> {
24186 EventKeyReleaseW::new(self, 2)
24187 }
24188 #[doc = "Bit 3"]
24189 #[inline(always)]
24190 pub fn event_key_value_rdy(&mut self) -> EventKeyValueRdyW<'_, KeyscanEventStsSpec> {
24191 EventKeyValueRdyW::new(self, 3)
24192 }
24193 #[doc = "Bit 4"]
24194 #[inline(always)]
24195 pub fn event_key_stopped(&mut self) -> EventKeyStoppedW<'_, KeyscanEventStsSpec> {
24196 EventKeyStoppedW::new(self, 4)
24197 }
24198 #[doc = "Bit 5"]
24199 #[inline(always)]
24200 pub fn event_keyscan_one(&mut self) -> EventKeyscanOneW<'_, KeyscanEventStsSpec> {
24201 EventKeyscanOneW::new(self, 5)
24202 }
24203 #[doc = "Bit 6"]
24204 #[inline(always)]
24205 pub fn event_fifo_afull(&mut self) -> EventFifoAfullW<'_, KeyscanEventStsSpec> {
24206 EventFifoAfullW::new(self, 6)
24207 }
24208 #[doc = "Bit 7"]
24209 #[inline(always)]
24210 pub fn event_key_press_aon(&mut self) -> EventKeyPressAonW<'_, KeyscanEventStsSpec> {
24211 EventKeyPressAonW::new(self, 7)
24212 }
24213 }
24214 #[doc = "keyscan_event_sts\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_event_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_event_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24215 pub struct KeyscanEventStsSpec;
24216 impl crate::RegisterSpec for KeyscanEventStsSpec {
24217 type Ux = u32;
24218 }
24219 #[doc = "`read()` method returns [`keyscan_event_sts::R`](R) reader structure"]
24220 impl crate::Readable for KeyscanEventStsSpec {}
24221 #[doc = "`write(|w| ..)` method takes [`keyscan_event_sts::W`](W) writer structure"]
24222 impl crate::Writable for KeyscanEventStsSpec {
24223 type Safety = crate::Unsafe;
24224 }
24225 #[doc = "`reset()` method sets KEYSCAN_EVENT_STS to value 0"]
24226 impl crate::Resettable for KeyscanEventStsSpec {}
24227 }
24228 #[doc = "KEYSCAN_PIN_NUM (rw) register accessor: keyscan_pin_num\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_pin_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_pin_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_pin_num`] module"]
24229 #[doc(alias = "KEYSCAN_PIN_NUM")]
24230 pub type KeyscanPinNum = crate::Reg<keyscan_pin_num::KeyscanPinNumSpec>;
24231 #[doc = "keyscan_pin_num"]
24232 pub mod keyscan_pin_num {
24233 #[doc = "Register `KEYSCAN_PIN_NUM` reader"]
24234 pub type R = crate::R<KeyscanPinNumSpec>;
24235 #[doc = "Register `KEYSCAN_PIN_NUM` writer"]
24236 pub type W = crate::W<KeyscanPinNumSpec>;
24237 #[doc = "Field `clo_pin_en` reader - "]
24238 pub type CloPinEnR = crate::FieldReader;
24239 #[doc = "Field `clo_pin_en` writer - "]
24240 pub type CloPinEnW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
24241 #[doc = "Field `row_pin_en` reader - "]
24242 pub type RowPinEnR = crate::FieldReader;
24243 #[doc = "Field `row_pin_en` writer - "]
24244 pub type RowPinEnW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
24245 impl R {
24246 #[doc = "Bits 0:2"]
24247 #[inline(always)]
24248 pub fn clo_pin_en(&self) -> CloPinEnR {
24249 CloPinEnR::new((self.bits & 7) as u8)
24250 }
24251 #[doc = "Bits 4:8"]
24252 #[inline(always)]
24253 pub fn row_pin_en(&self) -> RowPinEnR {
24254 RowPinEnR::new(((self.bits >> 4) & 0x1f) as u8)
24255 }
24256 }
24257 impl W {
24258 #[doc = "Bits 0:2"]
24259 #[inline(always)]
24260 pub fn clo_pin_en(&mut self) -> CloPinEnW<'_, KeyscanPinNumSpec> {
24261 CloPinEnW::new(self, 0)
24262 }
24263 #[doc = "Bits 4:8"]
24264 #[inline(always)]
24265 pub fn row_pin_en(&mut self) -> RowPinEnW<'_, KeyscanPinNumSpec> {
24266 RowPinEnW::new(self, 4)
24267 }
24268 }
24269 #[doc = "keyscan_pin_num\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_pin_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_pin_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24270 pub struct KeyscanPinNumSpec;
24271 impl crate::RegisterSpec for KeyscanPinNumSpec {
24272 type Ux = u32;
24273 }
24274 #[doc = "`read()` method returns [`keyscan_pin_num::R`](R) reader structure"]
24275 impl crate::Readable for KeyscanPinNumSpec {}
24276 #[doc = "`write(|w| ..)` method takes [`keyscan_pin_num::W`](W) writer structure"]
24277 impl crate::Writable for KeyscanPinNumSpec {
24278 type Safety = crate::Unsafe;
24279 }
24280 #[doc = "`reset()` method sets KEYSCAN_PIN_NUM to value 0"]
24281 impl crate::Resettable for KeyscanPinNumSpec {}
24282 }
24283 #[doc = "KEYSCAN_MODE (rw) register accessor: keyscan_mode\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_mode`] module"]
24284 #[doc(alias = "KEYSCAN_MODE")]
24285 pub type KeyscanMode = crate::Reg<keyscan_mode::KeyscanModeSpec>;
24286 #[doc = "keyscan_mode"]
24287 pub mod keyscan_mode {
24288 #[doc = "Register `KEYSCAN_MODE` reader"]
24289 pub type R = crate::R<KeyscanModeSpec>;
24290 #[doc = "Register `KEYSCAN_MODE` writer"]
24291 pub type W = crate::W<KeyscanModeSpec>;
24292 #[doc = "Field `scan_dir` reader - "]
24293 pub type ScanDirR = crate::BitReader;
24294 #[doc = "Field `scan_dir` writer - "]
24295 pub type ScanDirW<'a, REG> = crate::BitWriter<'a, REG>;
24296 #[doc = "Field `scan_mode` reader - "]
24297 pub type ScanModeR = crate::FieldReader;
24298 #[doc = "Field `scan_mode` writer - "]
24299 pub type ScanModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
24300 impl R {
24301 #[doc = "Bit 0"]
24302 #[inline(always)]
24303 pub fn scan_dir(&self) -> ScanDirR {
24304 ScanDirR::new((self.bits & 1) != 0)
24305 }
24306 #[doc = "Bits 4:5"]
24307 #[inline(always)]
24308 pub fn scan_mode(&self) -> ScanModeR {
24309 ScanModeR::new(((self.bits >> 4) & 3) as u8)
24310 }
24311 }
24312 impl W {
24313 #[doc = "Bit 0"]
24314 #[inline(always)]
24315 pub fn scan_dir(&mut self) -> ScanDirW<'_, KeyscanModeSpec> {
24316 ScanDirW::new(self, 0)
24317 }
24318 #[doc = "Bits 4:5"]
24319 #[inline(always)]
24320 pub fn scan_mode(&mut self) -> ScanModeW<'_, KeyscanModeSpec> {
24321 ScanModeW::new(self, 4)
24322 }
24323 }
24324 #[doc = "keyscan_mode\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24325 pub struct KeyscanModeSpec;
24326 impl crate::RegisterSpec for KeyscanModeSpec {
24327 type Ux = u32;
24328 }
24329 #[doc = "`read()` method returns [`keyscan_mode::R`](R) reader structure"]
24330 impl crate::Readable for KeyscanModeSpec {}
24331 #[doc = "`write(|w| ..)` method takes [`keyscan_mode::W`](W) writer structure"]
24332 impl crate::Writable for KeyscanModeSpec {
24333 type Safety = crate::Unsafe;
24334 }
24335 #[doc = "`reset()` method sets KEYSCAN_MODE to value 0"]
24336 impl crate::Resettable for KeyscanModeSpec {}
24337 }
24338 #[doc = "KEYSCAN_PULSE (rw) register accessor: keyscan_pulse\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_pulse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_pulse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_pulse`] module"]
24339 #[doc(alias = "KEYSCAN_PULSE")]
24340 pub type KeyscanPulse = crate::Reg<keyscan_pulse::KeyscanPulseSpec>;
24341 #[doc = "keyscan_pulse"]
24342 pub mod keyscan_pulse {
24343 #[doc = "Register `KEYSCAN_PULSE` reader"]
24344 pub type R = crate::R<KeyscanPulseSpec>;
24345 #[doc = "Register `KEYSCAN_PULSE` writer"]
24346 pub type W = crate::W<KeyscanPulseSpec>;
24347 #[doc = "Field `tpulse` reader - "]
24348 pub type TpulseR = crate::FieldReader;
24349 #[doc = "Field `tpulse` writer - "]
24350 pub type TpulseW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
24351 #[doc = "Field `ttern` reader - "]
24352 pub type TternR = crate::FieldReader;
24353 #[doc = "Field `ttern` writer - "]
24354 pub type TternW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
24355 #[doc = "Field `tidle` reader - "]
24356 pub type TidleR = crate::FieldReader;
24357 #[doc = "Field `tidle` writer - "]
24358 pub type TidleW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
24359 impl R {
24360 #[doc = "Bits 0:1"]
24361 #[inline(always)]
24362 pub fn tpulse(&self) -> TpulseR {
24363 TpulseR::new((self.bits & 3) as u8)
24364 }
24365 #[doc = "Bits 4:5"]
24366 #[inline(always)]
24367 pub fn ttern(&self) -> TternR {
24368 TternR::new(((self.bits >> 4) & 3) as u8)
24369 }
24370 #[doc = "Bits 8:10"]
24371 #[inline(always)]
24372 pub fn tidle(&self) -> TidleR {
24373 TidleR::new(((self.bits >> 8) & 7) as u8)
24374 }
24375 }
24376 impl W {
24377 #[doc = "Bits 0:1"]
24378 #[inline(always)]
24379 pub fn tpulse(&mut self) -> TpulseW<'_, KeyscanPulseSpec> {
24380 TpulseW::new(self, 0)
24381 }
24382 #[doc = "Bits 4:5"]
24383 #[inline(always)]
24384 pub fn ttern(&mut self) -> TternW<'_, KeyscanPulseSpec> {
24385 TternW::new(self, 4)
24386 }
24387 #[doc = "Bits 8:10"]
24388 #[inline(always)]
24389 pub fn tidle(&mut self) -> TidleW<'_, KeyscanPulseSpec> {
24390 TidleW::new(self, 8)
24391 }
24392 }
24393 #[doc = "keyscan_pulse\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_pulse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_pulse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24394 pub struct KeyscanPulseSpec;
24395 impl crate::RegisterSpec for KeyscanPulseSpec {
24396 type Ux = u32;
24397 }
24398 #[doc = "`read()` method returns [`keyscan_pulse::R`](R) reader structure"]
24399 impl crate::Readable for KeyscanPulseSpec {}
24400 #[doc = "`write(|w| ..)` method takes [`keyscan_pulse::W`](W) writer structure"]
24401 impl crate::Writable for KeyscanPulseSpec {
24402 type Safety = crate::Unsafe;
24403 }
24404 #[doc = "`reset()` method sets KEYSCAN_PULSE to value 0"]
24405 impl crate::Resettable for KeyscanPulseSpec {}
24406 }
24407 #[doc = "KEYSCAN_DE (rw) register accessor: keyscan_de\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_de::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_de::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_de`] module"]
24408 #[doc(alias = "KEYSCAN_DE")]
24409 pub type KeyscanDe = crate::Reg<keyscan_de::KeyscanDeSpec>;
24410 #[doc = "keyscan_de"]
24411 pub mod keyscan_de {
24412 #[doc = "Register `KEYSCAN_DE` reader"]
24413 pub type R = crate::R<KeyscanDeSpec>;
24414 #[doc = "Register `KEYSCAN_DE` writer"]
24415 pub type W = crate::W<KeyscanDeSpec>;
24416 #[doc = "Field `scan_num` reader - "]
24417 pub type ScanNumR = crate::FieldReader;
24418 #[doc = "Field `scan_num` writer - "]
24419 pub type ScanNumW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
24420 #[doc = "Field `ghost` reader - "]
24421 pub type GhostR = crate::BitReader;
24422 #[doc = "Field `ghost` writer - "]
24423 pub type GhostW<'a, REG> = crate::BitWriter<'a, REG>;
24424 #[doc = "Field `io_de` reader - "]
24425 pub type IoDeR = crate::BitReader;
24426 #[doc = "Field `io_de` writer - "]
24427 pub type IoDeW<'a, REG> = crate::BitWriter<'a, REG>;
24428 #[doc = "Field `key_num_sel` reader - "]
24429 pub type KeyNumSelR = crate::FieldReader;
24430 #[doc = "Field `key_num_sel` writer - "]
24431 pub type KeyNumSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
24432 #[doc = "Field `rep_all_key` reader - "]
24433 pub type RepAllKeyR = crate::BitReader;
24434 #[doc = "Field `rep_all_key` writer - "]
24435 pub type RepAllKeyW<'a, REG> = crate::BitWriter<'a, REG>;
24436 impl R {
24437 #[doc = "Bits 0:1"]
24438 #[inline(always)]
24439 pub fn scan_num(&self) -> ScanNumR {
24440 ScanNumR::new((self.bits & 3) as u8)
24441 }
24442 #[doc = "Bit 4"]
24443 #[inline(always)]
24444 pub fn ghost(&self) -> GhostR {
24445 GhostR::new(((self.bits >> 4) & 1) != 0)
24446 }
24447 #[doc = "Bit 8"]
24448 #[inline(always)]
24449 pub fn io_de(&self) -> IoDeR {
24450 IoDeR::new(((self.bits >> 8) & 1) != 0)
24451 }
24452 #[doc = "Bits 12:13"]
24453 #[inline(always)]
24454 pub fn key_num_sel(&self) -> KeyNumSelR {
24455 KeyNumSelR::new(((self.bits >> 12) & 3) as u8)
24456 }
24457 #[doc = "Bit 14"]
24458 #[inline(always)]
24459 pub fn rep_all_key(&self) -> RepAllKeyR {
24460 RepAllKeyR::new(((self.bits >> 14) & 1) != 0)
24461 }
24462 }
24463 impl W {
24464 #[doc = "Bits 0:1"]
24465 #[inline(always)]
24466 pub fn scan_num(&mut self) -> ScanNumW<'_, KeyscanDeSpec> {
24467 ScanNumW::new(self, 0)
24468 }
24469 #[doc = "Bit 4"]
24470 #[inline(always)]
24471 pub fn ghost(&mut self) -> GhostW<'_, KeyscanDeSpec> {
24472 GhostW::new(self, 4)
24473 }
24474 #[doc = "Bit 8"]
24475 #[inline(always)]
24476 pub fn io_de(&mut self) -> IoDeW<'_, KeyscanDeSpec> {
24477 IoDeW::new(self, 8)
24478 }
24479 #[doc = "Bits 12:13"]
24480 #[inline(always)]
24481 pub fn key_num_sel(&mut self) -> KeyNumSelW<'_, KeyscanDeSpec> {
24482 KeyNumSelW::new(self, 12)
24483 }
24484 #[doc = "Bit 14"]
24485 #[inline(always)]
24486 pub fn rep_all_key(&mut self) -> RepAllKeyW<'_, KeyscanDeSpec> {
24487 RepAllKeyW::new(self, 14)
24488 }
24489 }
24490 #[doc = "keyscan_de\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_de::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_de::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24491 pub struct KeyscanDeSpec;
24492 impl crate::RegisterSpec for KeyscanDeSpec {
24493 type Ux = u32;
24494 }
24495 #[doc = "`read()` method returns [`keyscan_de::R`](R) reader structure"]
24496 impl crate::Readable for KeyscanDeSpec {}
24497 #[doc = "`write(|w| ..)` method takes [`keyscan_de::W`](W) writer structure"]
24498 impl crate::Writable for KeyscanDeSpec {
24499 type Safety = crate::Unsafe;
24500 }
24501 #[doc = "`reset()` method sets KEYSCAN_DE to value 0"]
24502 impl crate::Resettable for KeyscanDeSpec {}
24503 }
24504 #[doc = "KEY_VALUE_FIFO (rw) register accessor: key_value_fifo\n\nYou can [`read`](crate::Reg::read) this register and get [`key_value_fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key_value_fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_value_fifo`] module"]
24505 #[doc(alias = "KEY_VALUE_FIFO")]
24506 pub type KeyValueFifo = crate::Reg<key_value_fifo::KeyValueFifoSpec>;
24507 #[doc = "key_value_fifo"]
24508 pub mod key_value_fifo {
24509 #[doc = "Register `KEY_VALUE_FIFO` reader"]
24510 pub type R = crate::R<KeyValueFifoSpec>;
24511 #[doc = "Register `KEY_VALUE_FIFO` writer"]
24512 pub type W = crate::W<KeyValueFifoSpec>;
24513 #[doc = "Field `key_value` reader - "]
24514 pub type KeyValueR = crate::FieldReader<u16>;
24515 #[doc = "Field `key_value` writer - "]
24516 pub type KeyValueW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
24517 impl R {
24518 #[doc = "Bits 0:8"]
24519 #[inline(always)]
24520 pub fn key_value(&self) -> KeyValueR {
24521 KeyValueR::new((self.bits & 0x01ff) as u16)
24522 }
24523 }
24524 impl W {
24525 #[doc = "Bits 0:8"]
24526 #[inline(always)]
24527 pub fn key_value(&mut self) -> KeyValueW<'_, KeyValueFifoSpec> {
24528 KeyValueW::new(self, 0)
24529 }
24530 }
24531 #[doc = "key_value_fifo\n\nYou can [`read`](crate::Reg::read) this register and get [`key_value_fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key_value_fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24532 pub struct KeyValueFifoSpec;
24533 impl crate::RegisterSpec for KeyValueFifoSpec {
24534 type Ux = u32;
24535 }
24536 #[doc = "`read()` method returns [`key_value_fifo::R`](R) reader structure"]
24537 impl crate::Readable for KeyValueFifoSpec {}
24538 #[doc = "`write(|w| ..)` method takes [`key_value_fifo::W`](W) writer structure"]
24539 impl crate::Writable for KeyValueFifoSpec {
24540 type Safety = crate::Unsafe;
24541 }
24542 #[doc = "`reset()` method sets KEY_VALUE_FIFO to value 0"]
24543 impl crate::Resettable for KeyValueFifoSpec {}
24544 }
24545}
24546#[doc = "PDM microphone interface (v150)"]
24547pub type Pdm = crate::Periph<pdm::RegisterBlock, 0x5208_e000>;
24548impl core::fmt::Debug for Pdm {
24549 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
24550 f.debug_struct("Pdm").finish()
24551 }
24552}
24553#[doc = "PDM microphone interface (v150)"]
24554pub mod pdm {
24555 #[repr(C)]
24556 #[doc = "Register block"]
24557 pub struct RegisterBlock {
24558 version: Version,
24559 clk_rst_en: ClkRstEn,
24560 ch_ctrl: ChCtrl,
24561 mic_ctrl: MicCtrl,
24562 cic_ctrl: CicCtrl,
24563 compd_ctrl: CompdCtrl,
24564 _reserved6: [u8; 0x08],
24565 srcdn_ctrl: SrcdnCtrl,
24566 up_fifo_ctrl: UpFifoCtrl,
24567 up_fifo_st_ctrl: UpFifoStCtrl,
24568 up_fifo_st_clr: UpFifoStClr,
24569 }
24570 impl RegisterBlock {
24571 #[doc = "0x00 - version"]
24572 #[inline(always)]
24573 pub const fn version(&self) -> &Version {
24574 &self.version
24575 }
24576 #[doc = "0x04 - clk_rst_en"]
24577 #[inline(always)]
24578 pub const fn clk_rst_en(&self) -> &ClkRstEn {
24579 &self.clk_rst_en
24580 }
24581 #[doc = "0x08 - ch_ctrl"]
24582 #[inline(always)]
24583 pub const fn ch_ctrl(&self) -> &ChCtrl {
24584 &self.ch_ctrl
24585 }
24586 #[doc = "0x0c - mic_ctrl"]
24587 #[inline(always)]
24588 pub const fn mic_ctrl(&self) -> &MicCtrl {
24589 &self.mic_ctrl
24590 }
24591 #[doc = "0x10 - cic_ctrl"]
24592 #[inline(always)]
24593 pub const fn cic_ctrl(&self) -> &CicCtrl {
24594 &self.cic_ctrl
24595 }
24596 #[doc = "0x14 - compd_ctrl"]
24597 #[inline(always)]
24598 pub const fn compd_ctrl(&self) -> &CompdCtrl {
24599 &self.compd_ctrl
24600 }
24601 #[doc = "0x20 - srcdn_ctrl"]
24602 #[inline(always)]
24603 pub const fn srcdn_ctrl(&self) -> &SrcdnCtrl {
24604 &self.srcdn_ctrl
24605 }
24606 #[doc = "0x24 - up_fifo_ctrl"]
24607 #[inline(always)]
24608 pub const fn up_fifo_ctrl(&self) -> &UpFifoCtrl {
24609 &self.up_fifo_ctrl
24610 }
24611 #[doc = "0x28 - up_fifo_st_ctrl"]
24612 #[inline(always)]
24613 pub const fn up_fifo_st_ctrl(&self) -> &UpFifoStCtrl {
24614 &self.up_fifo_st_ctrl
24615 }
24616 #[doc = "0x2c - up_fifo_st_clr"]
24617 #[inline(always)]
24618 pub const fn up_fifo_st_clr(&self) -> &UpFifoStClr {
24619 &self.up_fifo_st_clr
24620 }
24621 }
24622 #[doc = "VERSION (rw) register accessor: version\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"]
24623 #[doc(alias = "VERSION")]
24624 pub type Version = crate::Reg<version::VersionSpec>;
24625 #[doc = "version"]
24626 pub mod version {
24627 #[doc = "Register `VERSION` reader"]
24628 pub type R = crate::R<VersionSpec>;
24629 #[doc = "Register `VERSION` writer"]
24630 pub type W = crate::W<VersionSpec>;
24631 impl core::fmt::Debug for R {
24632 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
24633 write!(f, "{}", self.bits())
24634 }
24635 }
24636 impl W {}
24637 #[doc = "version\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24638 pub struct VersionSpec;
24639 impl crate::RegisterSpec for VersionSpec {
24640 type Ux = u32;
24641 }
24642 #[doc = "`read()` method returns [`version::R`](R) reader structure"]
24643 impl crate::Readable for VersionSpec {}
24644 #[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"]
24645 impl crate::Writable for VersionSpec {
24646 type Safety = crate::Unsafe;
24647 }
24648 #[doc = "`reset()` method sets VERSION to value 0"]
24649 impl crate::Resettable for VersionSpec {}
24650 }
24651 #[doc = "CLK_RST_EN (rw) register accessor: clk_rst_en\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_rst_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_rst_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rst_en`] module"]
24652 #[doc(alias = "CLK_RST_EN")]
24653 pub type ClkRstEn = crate::Reg<clk_rst_en::ClkRstEnSpec>;
24654 #[doc = "clk_rst_en"]
24655 pub mod clk_rst_en {
24656 #[doc = "Register `CLK_RST_EN` reader"]
24657 pub type R = crate::R<ClkRstEnSpec>;
24658 #[doc = "Register `CLK_RST_EN` writer"]
24659 pub type W = crate::W<ClkRstEnSpec>;
24660 #[doc = "Field `pdm_dp_rst_n` reader - "]
24661 pub type PdmDpRstNR = crate::BitReader;
24662 #[doc = "Field `pdm_dp_rst_n` writer - "]
24663 pub type PdmDpRstNW<'a, REG> = crate::BitWriter<'a, REG>;
24664 #[doc = "Field `clk_freq_sel` reader - "]
24665 pub type ClkFreqSelR = crate::BitReader;
24666 #[doc = "Field `clk_freq_sel` writer - "]
24667 pub type ClkFreqSelW<'a, REG> = crate::BitWriter<'a, REG>;
24668 #[doc = "Field `func_up_en` reader - "]
24669 pub type FuncUpEnR = crate::BitReader;
24670 #[doc = "Field `func_up_en` writer - "]
24671 pub type FuncUpEnW<'a, REG> = crate::BitWriter<'a, REG>;
24672 #[doc = "Field `dmic_clken` reader - "]
24673 pub type DmicClkenR = crate::BitReader;
24674 #[doc = "Field `dmic_clken` writer - "]
24675 pub type DmicClkenW<'a, REG> = crate::BitWriter<'a, REG>;
24676 #[doc = "Field `saradc_clken` reader - "]
24677 pub type SaradcClkenR = crate::BitReader;
24678 #[doc = "Field `saradc_clken` writer - "]
24679 pub type SaradcClkenW<'a, REG> = crate::BitWriter<'a, REG>;
24680 #[doc = "Field `ckdiv_6144k_clken` reader - "]
24681 pub type Ckdiv6144kClkenR = crate::BitReader;
24682 #[doc = "Field `ckdiv_6144k_clken` writer - "]
24683 pub type Ckdiv6144kClkenW<'a, REG> = crate::BitWriter<'a, REG>;
24684 #[doc = "Field `up_fifo_clken` reader - "]
24685 pub type UpFifoClkenR = crate::BitReader;
24686 #[doc = "Field `up_fifo_clken` writer - "]
24687 pub type UpFifoClkenW<'a, REG> = crate::BitWriter<'a, REG>;
24688 #[doc = "Field `func_up_ch_en_0` reader - "]
24689 pub type FuncUpChEn0R = crate::BitReader;
24690 #[doc = "Field `func_up_ch_en_0` writer - "]
24691 pub type FuncUpChEn0W<'a, REG> = crate::BitWriter<'a, REG>;
24692 #[doc = "Field `cic_clken_0` reader - "]
24693 pub type CicClken0R = crate::BitReader;
24694 #[doc = "Field `cic_clken_0` writer - "]
24695 pub type CicClken0W<'a, REG> = crate::BitWriter<'a, REG>;
24696 #[doc = "Field `compd_clken_0` reader - "]
24697 pub type CompdClken0R = crate::BitReader;
24698 #[doc = "Field `compd_clken_0` writer - "]
24699 pub type CompdClken0W<'a, REG> = crate::BitWriter<'a, REG>;
24700 #[doc = "Field `hpf_clken_0` reader - "]
24701 pub type HpfClken0R = crate::BitReader;
24702 #[doc = "Field `hpf_clken_0` writer - "]
24703 pub type HpfClken0W<'a, REG> = crate::BitWriter<'a, REG>;
24704 #[doc = "Field `srcdn_clken_0` reader - "]
24705 pub type SrcdnClken0R = crate::BitReader;
24706 #[doc = "Field `srcdn_clken_0` writer - "]
24707 pub type SrcdnClken0W<'a, REG> = crate::BitWriter<'a, REG>;
24708 #[doc = "Field `func_up_ch_en_1` reader - "]
24709 pub type FuncUpChEn1R = crate::BitReader;
24710 #[doc = "Field `func_up_ch_en_1` writer - "]
24711 pub type FuncUpChEn1W<'a, REG> = crate::BitWriter<'a, REG>;
24712 #[doc = "Field `cic_clken_1` reader - "]
24713 pub type CicClken1R = crate::BitReader;
24714 #[doc = "Field `cic_clken_1` writer - "]
24715 pub type CicClken1W<'a, REG> = crate::BitWriter<'a, REG>;
24716 #[doc = "Field `compd_clken_1` reader - "]
24717 pub type CompdClken1R = crate::BitReader;
24718 #[doc = "Field `compd_clken_1` writer - "]
24719 pub type CompdClken1W<'a, REG> = crate::BitWriter<'a, REG>;
24720 #[doc = "Field `hpf_clken_1` reader - "]
24721 pub type HpfClken1R = crate::BitReader;
24722 #[doc = "Field `hpf_clken_1` writer - "]
24723 pub type HpfClken1W<'a, REG> = crate::BitWriter<'a, REG>;
24724 #[doc = "Field `srcdn_clken_1` reader - "]
24725 pub type SrcdnClken1R = crate::BitReader;
24726 #[doc = "Field `srcdn_clken_1` writer - "]
24727 pub type SrcdnClken1W<'a, REG> = crate::BitWriter<'a, REG>;
24728 impl R {
24729 #[doc = "Bit 0"]
24730 #[inline(always)]
24731 pub fn pdm_dp_rst_n(&self) -> PdmDpRstNR {
24732 PdmDpRstNR::new((self.bits & 1) != 0)
24733 }
24734 #[doc = "Bit 1"]
24735 #[inline(always)]
24736 pub fn clk_freq_sel(&self) -> ClkFreqSelR {
24737 ClkFreqSelR::new(((self.bits >> 1) & 1) != 0)
24738 }
24739 #[doc = "Bit 2"]
24740 #[inline(always)]
24741 pub fn func_up_en(&self) -> FuncUpEnR {
24742 FuncUpEnR::new(((self.bits >> 2) & 1) != 0)
24743 }
24744 #[doc = "Bit 3"]
24745 #[inline(always)]
24746 pub fn dmic_clken(&self) -> DmicClkenR {
24747 DmicClkenR::new(((self.bits >> 3) & 1) != 0)
24748 }
24749 #[doc = "Bit 4"]
24750 #[inline(always)]
24751 pub fn saradc_clken(&self) -> SaradcClkenR {
24752 SaradcClkenR::new(((self.bits >> 4) & 1) != 0)
24753 }
24754 #[doc = "Bit 5"]
24755 #[inline(always)]
24756 pub fn ckdiv_6144k_clken(&self) -> Ckdiv6144kClkenR {
24757 Ckdiv6144kClkenR::new(((self.bits >> 5) & 1) != 0)
24758 }
24759 #[doc = "Bit 6"]
24760 #[inline(always)]
24761 pub fn up_fifo_clken(&self) -> UpFifoClkenR {
24762 UpFifoClkenR::new(((self.bits >> 6) & 1) != 0)
24763 }
24764 #[doc = "Bit 8"]
24765 #[inline(always)]
24766 pub fn func_up_ch_en_0(&self) -> FuncUpChEn0R {
24767 FuncUpChEn0R::new(((self.bits >> 8) & 1) != 0)
24768 }
24769 #[doc = "Bit 9"]
24770 #[inline(always)]
24771 pub fn cic_clken_0(&self) -> CicClken0R {
24772 CicClken0R::new(((self.bits >> 9) & 1) != 0)
24773 }
24774 #[doc = "Bit 10"]
24775 #[inline(always)]
24776 pub fn compd_clken_0(&self) -> CompdClken0R {
24777 CompdClken0R::new(((self.bits >> 10) & 1) != 0)
24778 }
24779 #[doc = "Bit 11"]
24780 #[inline(always)]
24781 pub fn hpf_clken_0(&self) -> HpfClken0R {
24782 HpfClken0R::new(((self.bits >> 11) & 1) != 0)
24783 }
24784 #[doc = "Bit 12"]
24785 #[inline(always)]
24786 pub fn srcdn_clken_0(&self) -> SrcdnClken0R {
24787 SrcdnClken0R::new(((self.bits >> 12) & 1) != 0)
24788 }
24789 #[doc = "Bit 16"]
24790 #[inline(always)]
24791 pub fn func_up_ch_en_1(&self) -> FuncUpChEn1R {
24792 FuncUpChEn1R::new(((self.bits >> 16) & 1) != 0)
24793 }
24794 #[doc = "Bit 17"]
24795 #[inline(always)]
24796 pub fn cic_clken_1(&self) -> CicClken1R {
24797 CicClken1R::new(((self.bits >> 17) & 1) != 0)
24798 }
24799 #[doc = "Bit 18"]
24800 #[inline(always)]
24801 pub fn compd_clken_1(&self) -> CompdClken1R {
24802 CompdClken1R::new(((self.bits >> 18) & 1) != 0)
24803 }
24804 #[doc = "Bit 19"]
24805 #[inline(always)]
24806 pub fn hpf_clken_1(&self) -> HpfClken1R {
24807 HpfClken1R::new(((self.bits >> 19) & 1) != 0)
24808 }
24809 #[doc = "Bit 20"]
24810 #[inline(always)]
24811 pub fn srcdn_clken_1(&self) -> SrcdnClken1R {
24812 SrcdnClken1R::new(((self.bits >> 20) & 1) != 0)
24813 }
24814 }
24815 impl W {
24816 #[doc = "Bit 0"]
24817 #[inline(always)]
24818 pub fn pdm_dp_rst_n(&mut self) -> PdmDpRstNW<'_, ClkRstEnSpec> {
24819 PdmDpRstNW::new(self, 0)
24820 }
24821 #[doc = "Bit 1"]
24822 #[inline(always)]
24823 pub fn clk_freq_sel(&mut self) -> ClkFreqSelW<'_, ClkRstEnSpec> {
24824 ClkFreqSelW::new(self, 1)
24825 }
24826 #[doc = "Bit 2"]
24827 #[inline(always)]
24828 pub fn func_up_en(&mut self) -> FuncUpEnW<'_, ClkRstEnSpec> {
24829 FuncUpEnW::new(self, 2)
24830 }
24831 #[doc = "Bit 3"]
24832 #[inline(always)]
24833 pub fn dmic_clken(&mut self) -> DmicClkenW<'_, ClkRstEnSpec> {
24834 DmicClkenW::new(self, 3)
24835 }
24836 #[doc = "Bit 4"]
24837 #[inline(always)]
24838 pub fn saradc_clken(&mut self) -> SaradcClkenW<'_, ClkRstEnSpec> {
24839 SaradcClkenW::new(self, 4)
24840 }
24841 #[doc = "Bit 5"]
24842 #[inline(always)]
24843 pub fn ckdiv_6144k_clken(&mut self) -> Ckdiv6144kClkenW<'_, ClkRstEnSpec> {
24844 Ckdiv6144kClkenW::new(self, 5)
24845 }
24846 #[doc = "Bit 6"]
24847 #[inline(always)]
24848 pub fn up_fifo_clken(&mut self) -> UpFifoClkenW<'_, ClkRstEnSpec> {
24849 UpFifoClkenW::new(self, 6)
24850 }
24851 #[doc = "Bit 8"]
24852 #[inline(always)]
24853 pub fn func_up_ch_en_0(&mut self) -> FuncUpChEn0W<'_, ClkRstEnSpec> {
24854 FuncUpChEn0W::new(self, 8)
24855 }
24856 #[doc = "Bit 9"]
24857 #[inline(always)]
24858 pub fn cic_clken_0(&mut self) -> CicClken0W<'_, ClkRstEnSpec> {
24859 CicClken0W::new(self, 9)
24860 }
24861 #[doc = "Bit 10"]
24862 #[inline(always)]
24863 pub fn compd_clken_0(&mut self) -> CompdClken0W<'_, ClkRstEnSpec> {
24864 CompdClken0W::new(self, 10)
24865 }
24866 #[doc = "Bit 11"]
24867 #[inline(always)]
24868 pub fn hpf_clken_0(&mut self) -> HpfClken0W<'_, ClkRstEnSpec> {
24869 HpfClken0W::new(self, 11)
24870 }
24871 #[doc = "Bit 12"]
24872 #[inline(always)]
24873 pub fn srcdn_clken_0(&mut self) -> SrcdnClken0W<'_, ClkRstEnSpec> {
24874 SrcdnClken0W::new(self, 12)
24875 }
24876 #[doc = "Bit 16"]
24877 #[inline(always)]
24878 pub fn func_up_ch_en_1(&mut self) -> FuncUpChEn1W<'_, ClkRstEnSpec> {
24879 FuncUpChEn1W::new(self, 16)
24880 }
24881 #[doc = "Bit 17"]
24882 #[inline(always)]
24883 pub fn cic_clken_1(&mut self) -> CicClken1W<'_, ClkRstEnSpec> {
24884 CicClken1W::new(self, 17)
24885 }
24886 #[doc = "Bit 18"]
24887 #[inline(always)]
24888 pub fn compd_clken_1(&mut self) -> CompdClken1W<'_, ClkRstEnSpec> {
24889 CompdClken1W::new(self, 18)
24890 }
24891 #[doc = "Bit 19"]
24892 #[inline(always)]
24893 pub fn hpf_clken_1(&mut self) -> HpfClken1W<'_, ClkRstEnSpec> {
24894 HpfClken1W::new(self, 19)
24895 }
24896 #[doc = "Bit 20"]
24897 #[inline(always)]
24898 pub fn srcdn_clken_1(&mut self) -> SrcdnClken1W<'_, ClkRstEnSpec> {
24899 SrcdnClken1W::new(self, 20)
24900 }
24901 }
24902 #[doc = "clk_rst_en\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_rst_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_rst_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24903 pub struct ClkRstEnSpec;
24904 impl crate::RegisterSpec for ClkRstEnSpec {
24905 type Ux = u32;
24906 }
24907 #[doc = "`read()` method returns [`clk_rst_en::R`](R) reader structure"]
24908 impl crate::Readable for ClkRstEnSpec {}
24909 #[doc = "`write(|w| ..)` method takes [`clk_rst_en::W`](W) writer structure"]
24910 impl crate::Writable for ClkRstEnSpec {
24911 type Safety = crate::Unsafe;
24912 }
24913 #[doc = "`reset()` method sets CLK_RST_EN to value 0"]
24914 impl crate::Resettable for ClkRstEnSpec {}
24915 }
24916 #[doc = "CH_CTRL (rw) register accessor: ch_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ctrl`] module"]
24917 #[doc(alias = "CH_CTRL")]
24918 pub type ChCtrl = crate::Reg<ch_ctrl::ChCtrlSpec>;
24919 #[doc = "ch_ctrl"]
24920 pub mod ch_ctrl {
24921 #[doc = "Register `CH_CTRL` reader"]
24922 pub type R = crate::R<ChCtrlSpec>;
24923 #[doc = "Register `CH_CTRL` writer"]
24924 pub type W = crate::W<ChCtrlSpec>;
24925 #[doc = "Field `mic_sel` reader - "]
24926 pub type MicSelR = crate::BitReader;
24927 #[doc = "Field `mic_sel` writer - "]
24928 pub type MicSelW<'a, REG> = crate::BitWriter<'a, REG>;
24929 #[doc = "Field `up_fs_sel_0` reader - "]
24930 pub type UpFsSel0R = crate::BitReader;
24931 #[doc = "Field `up_fs_sel_0` writer - "]
24932 pub type UpFsSel0W<'a, REG> = crate::BitWriter<'a, REG>;
24933 #[doc = "Field `up_fs_sel_1` reader - "]
24934 pub type UpFsSel1R = crate::BitReader;
24935 #[doc = "Field `up_fs_sel_1` writer - "]
24936 pub type UpFsSel1W<'a, REG> = crate::BitWriter<'a, REG>;
24937 impl R {
24938 #[doc = "Bit 0"]
24939 #[inline(always)]
24940 pub fn mic_sel(&self) -> MicSelR {
24941 MicSelR::new((self.bits & 1) != 0)
24942 }
24943 #[doc = "Bit 4"]
24944 #[inline(always)]
24945 pub fn up_fs_sel_0(&self) -> UpFsSel0R {
24946 UpFsSel0R::new(((self.bits >> 4) & 1) != 0)
24947 }
24948 #[doc = "Bit 5"]
24949 #[inline(always)]
24950 pub fn up_fs_sel_1(&self) -> UpFsSel1R {
24951 UpFsSel1R::new(((self.bits >> 5) & 1) != 0)
24952 }
24953 }
24954 impl W {
24955 #[doc = "Bit 0"]
24956 #[inline(always)]
24957 pub fn mic_sel(&mut self) -> MicSelW<'_, ChCtrlSpec> {
24958 MicSelW::new(self, 0)
24959 }
24960 #[doc = "Bit 4"]
24961 #[inline(always)]
24962 pub fn up_fs_sel_0(&mut self) -> UpFsSel0W<'_, ChCtrlSpec> {
24963 UpFsSel0W::new(self, 4)
24964 }
24965 #[doc = "Bit 5"]
24966 #[inline(always)]
24967 pub fn up_fs_sel_1(&mut self) -> UpFsSel1W<'_, ChCtrlSpec> {
24968 UpFsSel1W::new(self, 5)
24969 }
24970 }
24971 #[doc = "ch_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24972 pub struct ChCtrlSpec;
24973 impl crate::RegisterSpec for ChCtrlSpec {
24974 type Ux = u32;
24975 }
24976 #[doc = "`read()` method returns [`ch_ctrl::R`](R) reader structure"]
24977 impl crate::Readable for ChCtrlSpec {}
24978 #[doc = "`write(|w| ..)` method takes [`ch_ctrl::W`](W) writer structure"]
24979 impl crate::Writable for ChCtrlSpec {
24980 type Safety = crate::Unsafe;
24981 }
24982 #[doc = "`reset()` method sets CH_CTRL to value 0"]
24983 impl crate::Resettable for ChCtrlSpec {}
24984 }
24985 #[doc = "MIC_CTRL (rw) register accessor: mic_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`mic_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mic_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mic_ctrl`] module"]
24986 #[doc(alias = "MIC_CTRL")]
24987 pub type MicCtrl = crate::Reg<mic_ctrl::MicCtrlSpec>;
24988 #[doc = "mic_ctrl"]
24989 pub mod mic_ctrl {
24990 #[doc = "Register `MIC_CTRL` reader"]
24991 pub type R = crate::R<MicCtrlSpec>;
24992 #[doc = "Register `MIC_CTRL` writer"]
24993 pub type W = crate::W<MicCtrlSpec>;
24994 #[doc = "Field `dmic_clk_sel` reader - "]
24995 pub type DmicClkSelR = crate::FieldReader;
24996 #[doc = "Field `dmic_clk_sel` writer - "]
24997 pub type DmicClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
24998 #[doc = "Field `dmic_mode` reader - "]
24999 pub type DmicModeR = crate::BitReader;
25000 #[doc = "Field `dmic_mode` writer - "]
25001 pub type DmicModeW<'a, REG> = crate::BitWriter<'a, REG>;
25002 #[doc = "Field `dmic_reverse` reader - "]
25003 pub type DmicReverseR = crate::BitReader;
25004 #[doc = "Field `dmic_reverse` writer - "]
25005 pub type DmicReverseW<'a, REG> = crate::BitWriter<'a, REG>;
25006 #[doc = "Field `saradc_gain` reader - "]
25007 pub type SaradcGainR = crate::FieldReader;
25008 #[doc = "Field `saradc_gain` writer - "]
25009 pub type SaradcGainW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25010 impl R {
25011 #[doc = "Bits 0:1"]
25012 #[inline(always)]
25013 pub fn dmic_clk_sel(&self) -> DmicClkSelR {
25014 DmicClkSelR::new((self.bits & 3) as u8)
25015 }
25016 #[doc = "Bit 2"]
25017 #[inline(always)]
25018 pub fn dmic_mode(&self) -> DmicModeR {
25019 DmicModeR::new(((self.bits >> 2) & 1) != 0)
25020 }
25021 #[doc = "Bit 3"]
25022 #[inline(always)]
25023 pub fn dmic_reverse(&self) -> DmicReverseR {
25024 DmicReverseR::new(((self.bits >> 3) & 1) != 0)
25025 }
25026 #[doc = "Bits 8:15"]
25027 #[inline(always)]
25028 pub fn saradc_gain(&self) -> SaradcGainR {
25029 SaradcGainR::new(((self.bits >> 8) & 0xff) as u8)
25030 }
25031 }
25032 impl W {
25033 #[doc = "Bits 0:1"]
25034 #[inline(always)]
25035 pub fn dmic_clk_sel(&mut self) -> DmicClkSelW<'_, MicCtrlSpec> {
25036 DmicClkSelW::new(self, 0)
25037 }
25038 #[doc = "Bit 2"]
25039 #[inline(always)]
25040 pub fn dmic_mode(&mut self) -> DmicModeW<'_, MicCtrlSpec> {
25041 DmicModeW::new(self, 2)
25042 }
25043 #[doc = "Bit 3"]
25044 #[inline(always)]
25045 pub fn dmic_reverse(&mut self) -> DmicReverseW<'_, MicCtrlSpec> {
25046 DmicReverseW::new(self, 3)
25047 }
25048 #[doc = "Bits 8:15"]
25049 #[inline(always)]
25050 pub fn saradc_gain(&mut self) -> SaradcGainW<'_, MicCtrlSpec> {
25051 SaradcGainW::new(self, 8)
25052 }
25053 }
25054 #[doc = "mic_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`mic_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mic_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25055 pub struct MicCtrlSpec;
25056 impl crate::RegisterSpec for MicCtrlSpec {
25057 type Ux = u32;
25058 }
25059 #[doc = "`read()` method returns [`mic_ctrl::R`](R) reader structure"]
25060 impl crate::Readable for MicCtrlSpec {}
25061 #[doc = "`write(|w| ..)` method takes [`mic_ctrl::W`](W) writer structure"]
25062 impl crate::Writable for MicCtrlSpec {
25063 type Safety = crate::Unsafe;
25064 }
25065 #[doc = "`reset()` method sets MIC_CTRL to value 0"]
25066 impl crate::Resettable for MicCtrlSpec {}
25067 }
25068 #[doc = "CIC_CTRL (rw) register accessor: cic_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`cic_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cic_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cic_ctrl`] module"]
25069 #[doc(alias = "CIC_CTRL")]
25070 pub type CicCtrl = crate::Reg<cic_ctrl::CicCtrlSpec>;
25071 #[doc = "cic_ctrl"]
25072 pub mod cic_ctrl {
25073 #[doc = "Register `CIC_CTRL` reader"]
25074 pub type R = crate::R<CicCtrlSpec>;
25075 #[doc = "Register `CIC_CTRL` writer"]
25076 pub type W = crate::W<CicCtrlSpec>;
25077 #[doc = "Field `cic_en_0` reader - "]
25078 pub type CicEn0R = crate::BitReader;
25079 #[doc = "Field `cic_en_0` writer - "]
25080 pub type CicEn0W<'a, REG> = crate::BitWriter<'a, REG>;
25081 #[doc = "Field `cic_en_1` reader - "]
25082 pub type CicEn1R = crate::BitReader;
25083 #[doc = "Field `cic_en_1` writer - "]
25084 pub type CicEn1W<'a, REG> = crate::BitWriter<'a, REG>;
25085 #[doc = "Field `cic_gain_0` reader - "]
25086 pub type CicGain0R = crate::FieldReader;
25087 #[doc = "Field `cic_gain_0` writer - "]
25088 pub type CicGain0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25089 #[doc = "Field `cic_gain_1` reader - "]
25090 pub type CicGain1R = crate::FieldReader;
25091 #[doc = "Field `cic_gain_1` writer - "]
25092 pub type CicGain1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25093 impl R {
25094 #[doc = "Bit 0"]
25095 #[inline(always)]
25096 pub fn cic_en_0(&self) -> CicEn0R {
25097 CicEn0R::new((self.bits & 1) != 0)
25098 }
25099 #[doc = "Bit 1"]
25100 #[inline(always)]
25101 pub fn cic_en_1(&self) -> CicEn1R {
25102 CicEn1R::new(((self.bits >> 1) & 1) != 0)
25103 }
25104 #[doc = "Bits 8:15"]
25105 #[inline(always)]
25106 pub fn cic_gain_0(&self) -> CicGain0R {
25107 CicGain0R::new(((self.bits >> 8) & 0xff) as u8)
25108 }
25109 #[doc = "Bits 16:23"]
25110 #[inline(always)]
25111 pub fn cic_gain_1(&self) -> CicGain1R {
25112 CicGain1R::new(((self.bits >> 16) & 0xff) as u8)
25113 }
25114 }
25115 impl W {
25116 #[doc = "Bit 0"]
25117 #[inline(always)]
25118 pub fn cic_en_0(&mut self) -> CicEn0W<'_, CicCtrlSpec> {
25119 CicEn0W::new(self, 0)
25120 }
25121 #[doc = "Bit 1"]
25122 #[inline(always)]
25123 pub fn cic_en_1(&mut self) -> CicEn1W<'_, CicCtrlSpec> {
25124 CicEn1W::new(self, 1)
25125 }
25126 #[doc = "Bits 8:15"]
25127 #[inline(always)]
25128 pub fn cic_gain_0(&mut self) -> CicGain0W<'_, CicCtrlSpec> {
25129 CicGain0W::new(self, 8)
25130 }
25131 #[doc = "Bits 16:23"]
25132 #[inline(always)]
25133 pub fn cic_gain_1(&mut self) -> CicGain1W<'_, CicCtrlSpec> {
25134 CicGain1W::new(self, 16)
25135 }
25136 }
25137 #[doc = "cic_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`cic_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cic_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25138 pub struct CicCtrlSpec;
25139 impl crate::RegisterSpec for CicCtrlSpec {
25140 type Ux = u32;
25141 }
25142 #[doc = "`read()` method returns [`cic_ctrl::R`](R) reader structure"]
25143 impl crate::Readable for CicCtrlSpec {}
25144 #[doc = "`write(|w| ..)` method takes [`cic_ctrl::W`](W) writer structure"]
25145 impl crate::Writable for CicCtrlSpec {
25146 type Safety = crate::Unsafe;
25147 }
25148 #[doc = "`reset()` method sets CIC_CTRL to value 0"]
25149 impl crate::Resettable for CicCtrlSpec {}
25150 }
25151 #[doc = "COMPD_CTRL (rw) register accessor: compd_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`compd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`compd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@compd_ctrl`] module"]
25152 #[doc(alias = "COMPD_CTRL")]
25153 pub type CompdCtrl = crate::Reg<compd_ctrl::CompdCtrlSpec>;
25154 #[doc = "compd_ctrl"]
25155 pub mod compd_ctrl {
25156 #[doc = "Register `COMPD_CTRL` reader"]
25157 pub type R = crate::R<CompdCtrlSpec>;
25158 #[doc = "Register `COMPD_CTRL` writer"]
25159 pub type W = crate::W<CompdCtrlSpec>;
25160 #[doc = "Field `compd_bypass_en_0` reader - "]
25161 pub type CompdBypassEn0R = crate::BitReader;
25162 #[doc = "Field `compd_bypass_en_0` writer - "]
25163 pub type CompdBypassEn0W<'a, REG> = crate::BitWriter<'a, REG>;
25164 #[doc = "Field `compd_bypass_en_1` reader - "]
25165 pub type CompdBypassEn1R = crate::BitReader;
25166 #[doc = "Field `compd_bypass_en_1` writer - "]
25167 pub type CompdBypassEn1W<'a, REG> = crate::BitWriter<'a, REG>;
25168 impl R {
25169 #[doc = "Bit 0"]
25170 #[inline(always)]
25171 pub fn compd_bypass_en_0(&self) -> CompdBypassEn0R {
25172 CompdBypassEn0R::new((self.bits & 1) != 0)
25173 }
25174 #[doc = "Bit 1"]
25175 #[inline(always)]
25176 pub fn compd_bypass_en_1(&self) -> CompdBypassEn1R {
25177 CompdBypassEn1R::new(((self.bits >> 1) & 1) != 0)
25178 }
25179 }
25180 impl W {
25181 #[doc = "Bit 0"]
25182 #[inline(always)]
25183 pub fn compd_bypass_en_0(&mut self) -> CompdBypassEn0W<'_, CompdCtrlSpec> {
25184 CompdBypassEn0W::new(self, 0)
25185 }
25186 #[doc = "Bit 1"]
25187 #[inline(always)]
25188 pub fn compd_bypass_en_1(&mut self) -> CompdBypassEn1W<'_, CompdCtrlSpec> {
25189 CompdBypassEn1W::new(self, 1)
25190 }
25191 }
25192 #[doc = "compd_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`compd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`compd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25193 pub struct CompdCtrlSpec;
25194 impl crate::RegisterSpec for CompdCtrlSpec {
25195 type Ux = u32;
25196 }
25197 #[doc = "`read()` method returns [`compd_ctrl::R`](R) reader structure"]
25198 impl crate::Readable for CompdCtrlSpec {}
25199 #[doc = "`write(|w| ..)` method takes [`compd_ctrl::W`](W) writer structure"]
25200 impl crate::Writable for CompdCtrlSpec {
25201 type Safety = crate::Unsafe;
25202 }
25203 #[doc = "`reset()` method sets COMPD_CTRL to value 0"]
25204 impl crate::Resettable for CompdCtrlSpec {}
25205 }
25206 #[doc = "SRCDN_CTRL (rw) register accessor: srcdn_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`srcdn_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srcdn_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srcdn_ctrl`] module"]
25207 #[doc(alias = "SRCDN_CTRL")]
25208 pub type SrcdnCtrl = crate::Reg<srcdn_ctrl::SrcdnCtrlSpec>;
25209 #[doc = "srcdn_ctrl"]
25210 pub mod srcdn_ctrl {
25211 #[doc = "Register `SRCDN_CTRL` reader"]
25212 pub type R = crate::R<SrcdnCtrlSpec>;
25213 #[doc = "Register `SRCDN_CTRL` writer"]
25214 pub type W = crate::W<SrcdnCtrlSpec>;
25215 #[doc = "Field `srcdn_bypass_en_0` reader - "]
25216 pub type SrcdnBypassEn0R = crate::BitReader;
25217 #[doc = "Field `srcdn_bypass_en_0` writer - "]
25218 pub type SrcdnBypassEn0W<'a, REG> = crate::BitWriter<'a, REG>;
25219 #[doc = "Field `srcdn_bypass_en_1` reader - "]
25220 pub type SrcdnBypassEn1R = crate::BitReader;
25221 #[doc = "Field `srcdn_bypass_en_1` writer - "]
25222 pub type SrcdnBypassEn1W<'a, REG> = crate::BitWriter<'a, REG>;
25223 #[doc = "Field `srcdn_mode_0` reader - "]
25224 pub type SrcdnMode0R = crate::FieldReader;
25225 #[doc = "Field `srcdn_mode_0` writer - "]
25226 pub type SrcdnMode0W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25227 #[doc = "Field `srcdn_mode_1` reader - "]
25228 pub type SrcdnMode1R = crate::FieldReader;
25229 #[doc = "Field `srcdn_mode_1` writer - "]
25230 pub type SrcdnMode1W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25231 #[doc = "Field `srcdn_fifo_clr_0` reader - "]
25232 pub type SrcdnFifoClr0R = crate::BitReader;
25233 #[doc = "Field `srcdn_fifo_clr_0` writer - "]
25234 pub type SrcdnFifoClr0W<'a, REG> = crate::BitWriter<'a, REG>;
25235 #[doc = "Field `srcdn_fifo_clr_1` reader - "]
25236 pub type SrcdnFifoClr1R = crate::BitReader;
25237 #[doc = "Field `srcdn_fifo_clr_1` writer - "]
25238 pub type SrcdnFifoClr1W<'a, REG> = crate::BitWriter<'a, REG>;
25239 impl R {
25240 #[doc = "Bit 0"]
25241 #[inline(always)]
25242 pub fn srcdn_bypass_en_0(&self) -> SrcdnBypassEn0R {
25243 SrcdnBypassEn0R::new((self.bits & 1) != 0)
25244 }
25245 #[doc = "Bit 1"]
25246 #[inline(always)]
25247 pub fn srcdn_bypass_en_1(&self) -> SrcdnBypassEn1R {
25248 SrcdnBypassEn1R::new(((self.bits >> 1) & 1) != 0)
25249 }
25250 #[doc = "Bits 4:5"]
25251 #[inline(always)]
25252 pub fn srcdn_mode_0(&self) -> SrcdnMode0R {
25253 SrcdnMode0R::new(((self.bits >> 4) & 3) as u8)
25254 }
25255 #[doc = "Bits 6:7"]
25256 #[inline(always)]
25257 pub fn srcdn_mode_1(&self) -> SrcdnMode1R {
25258 SrcdnMode1R::new(((self.bits >> 6) & 3) as u8)
25259 }
25260 #[doc = "Bit 8"]
25261 #[inline(always)]
25262 pub fn srcdn_fifo_clr_0(&self) -> SrcdnFifoClr0R {
25263 SrcdnFifoClr0R::new(((self.bits >> 8) & 1) != 0)
25264 }
25265 #[doc = "Bit 9"]
25266 #[inline(always)]
25267 pub fn srcdn_fifo_clr_1(&self) -> SrcdnFifoClr1R {
25268 SrcdnFifoClr1R::new(((self.bits >> 9) & 1) != 0)
25269 }
25270 }
25271 impl W {
25272 #[doc = "Bit 0"]
25273 #[inline(always)]
25274 pub fn srcdn_bypass_en_0(&mut self) -> SrcdnBypassEn0W<'_, SrcdnCtrlSpec> {
25275 SrcdnBypassEn0W::new(self, 0)
25276 }
25277 #[doc = "Bit 1"]
25278 #[inline(always)]
25279 pub fn srcdn_bypass_en_1(&mut self) -> SrcdnBypassEn1W<'_, SrcdnCtrlSpec> {
25280 SrcdnBypassEn1W::new(self, 1)
25281 }
25282 #[doc = "Bits 4:5"]
25283 #[inline(always)]
25284 pub fn srcdn_mode_0(&mut self) -> SrcdnMode0W<'_, SrcdnCtrlSpec> {
25285 SrcdnMode0W::new(self, 4)
25286 }
25287 #[doc = "Bits 6:7"]
25288 #[inline(always)]
25289 pub fn srcdn_mode_1(&mut self) -> SrcdnMode1W<'_, SrcdnCtrlSpec> {
25290 SrcdnMode1W::new(self, 6)
25291 }
25292 #[doc = "Bit 8"]
25293 #[inline(always)]
25294 pub fn srcdn_fifo_clr_0(&mut self) -> SrcdnFifoClr0W<'_, SrcdnCtrlSpec> {
25295 SrcdnFifoClr0W::new(self, 8)
25296 }
25297 #[doc = "Bit 9"]
25298 #[inline(always)]
25299 pub fn srcdn_fifo_clr_1(&mut self) -> SrcdnFifoClr1W<'_, SrcdnCtrlSpec> {
25300 SrcdnFifoClr1W::new(self, 9)
25301 }
25302 }
25303 #[doc = "srcdn_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`srcdn_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srcdn_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25304 pub struct SrcdnCtrlSpec;
25305 impl crate::RegisterSpec for SrcdnCtrlSpec {
25306 type Ux = u32;
25307 }
25308 #[doc = "`read()` method returns [`srcdn_ctrl::R`](R) reader structure"]
25309 impl crate::Readable for SrcdnCtrlSpec {}
25310 #[doc = "`write(|w| ..)` method takes [`srcdn_ctrl::W`](W) writer structure"]
25311 impl crate::Writable for SrcdnCtrlSpec {
25312 type Safety = crate::Unsafe;
25313 }
25314 #[doc = "`reset()` method sets SRCDN_CTRL to value 0"]
25315 impl crate::Resettable for SrcdnCtrlSpec {}
25316 }
25317 #[doc = "UP_FIFO_CTRL (rw) register accessor: up_fifo_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@up_fifo_ctrl`] module"]
25318 #[doc(alias = "UP_FIFO_CTRL")]
25319 pub type UpFifoCtrl = crate::Reg<up_fifo_ctrl::UpFifoCtrlSpec>;
25320 #[doc = "up_fifo_ctrl"]
25321 pub mod up_fifo_ctrl {
25322 #[doc = "Register `UP_FIFO_CTRL` reader"]
25323 pub type R = crate::R<UpFifoCtrlSpec>;
25324 #[doc = "Register `UP_FIFO_CTRL` writer"]
25325 pub type W = crate::W<UpFifoCtrlSpec>;
25326 #[doc = "Field `up_fifo_aempty_th` reader - "]
25327 pub type UpFifoAemptyThR = crate::FieldReader;
25328 #[doc = "Field `up_fifo_aempty_th` writer - "]
25329 pub type UpFifoAemptyThW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
25330 #[doc = "Field `up_fifo_afull_th` reader - "]
25331 pub type UpFifoAfullThR = crate::FieldReader;
25332 #[doc = "Field `up_fifo_afull_th` writer - "]
25333 pub type UpFifoAfullThW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
25334 impl R {
25335 #[doc = "Bits 0:4"]
25336 #[inline(always)]
25337 pub fn up_fifo_aempty_th(&self) -> UpFifoAemptyThR {
25338 UpFifoAemptyThR::new((self.bits & 0x1f) as u8)
25339 }
25340 #[doc = "Bits 8:12"]
25341 #[inline(always)]
25342 pub fn up_fifo_afull_th(&self) -> UpFifoAfullThR {
25343 UpFifoAfullThR::new(((self.bits >> 8) & 0x1f) as u8)
25344 }
25345 }
25346 impl W {
25347 #[doc = "Bits 0:4"]
25348 #[inline(always)]
25349 pub fn up_fifo_aempty_th(&mut self) -> UpFifoAemptyThW<'_, UpFifoCtrlSpec> {
25350 UpFifoAemptyThW::new(self, 0)
25351 }
25352 #[doc = "Bits 8:12"]
25353 #[inline(always)]
25354 pub fn up_fifo_afull_th(&mut self) -> UpFifoAfullThW<'_, UpFifoCtrlSpec> {
25355 UpFifoAfullThW::new(self, 8)
25356 }
25357 }
25358 #[doc = "up_fifo_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25359 pub struct UpFifoCtrlSpec;
25360 impl crate::RegisterSpec for UpFifoCtrlSpec {
25361 type Ux = u32;
25362 }
25363 #[doc = "`read()` method returns [`up_fifo_ctrl::R`](R) reader structure"]
25364 impl crate::Readable for UpFifoCtrlSpec {}
25365 #[doc = "`write(|w| ..)` method takes [`up_fifo_ctrl::W`](W) writer structure"]
25366 impl crate::Writable for UpFifoCtrlSpec {
25367 type Safety = crate::Unsafe;
25368 }
25369 #[doc = "`reset()` method sets UP_FIFO_CTRL to value 0"]
25370 impl crate::Resettable for UpFifoCtrlSpec {}
25371 }
25372 #[doc = "UP_FIFO_ST_CTRL (rw) register accessor: up_fifo_st_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_st_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_st_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@up_fifo_st_ctrl`] module"]
25373 #[doc(alias = "UP_FIFO_ST_CTRL")]
25374 pub type UpFifoStCtrl = crate::Reg<up_fifo_st_ctrl::UpFifoStCtrlSpec>;
25375 #[doc = "up_fifo_st_ctrl"]
25376 pub mod up_fifo_st_ctrl {
25377 #[doc = "Register `UP_FIFO_ST_CTRL` reader"]
25378 pub type R = crate::R<UpFifoStCtrlSpec>;
25379 #[doc = "Register `UP_FIFO_ST_CTRL` writer"]
25380 pub type W = crate::W<UpFifoStCtrlSpec>;
25381 #[doc = "Field `up_fifo_full_int_en` reader - "]
25382 pub type UpFifoFullIntEnR = crate::BitReader;
25383 #[doc = "Field `up_fifo_full_int_en` writer - "]
25384 pub type UpFifoFullIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
25385 #[doc = "Field `up_fifo_afull_int_en` reader - "]
25386 pub type UpFifoAfullIntEnR = crate::BitReader;
25387 #[doc = "Field `up_fifo_afull_int_en` writer - "]
25388 pub type UpFifoAfullIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
25389 #[doc = "Field `up_fifo_empty_int_en` reader - "]
25390 pub type UpFifoEmptyIntEnR = crate::BitReader;
25391 #[doc = "Field `up_fifo_empty_int_en` writer - "]
25392 pub type UpFifoEmptyIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
25393 #[doc = "Field `up_fifo_aempty_int_en` reader - "]
25394 pub type UpFifoAemptyIntEnR = crate::BitReader;
25395 #[doc = "Field `up_fifo_aempty_int_en` writer - "]
25396 pub type UpFifoAemptyIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
25397 impl R {
25398 #[doc = "Bit 0"]
25399 #[inline(always)]
25400 pub fn up_fifo_full_int_en(&self) -> UpFifoFullIntEnR {
25401 UpFifoFullIntEnR::new((self.bits & 1) != 0)
25402 }
25403 #[doc = "Bit 1"]
25404 #[inline(always)]
25405 pub fn up_fifo_afull_int_en(&self) -> UpFifoAfullIntEnR {
25406 UpFifoAfullIntEnR::new(((self.bits >> 1) & 1) != 0)
25407 }
25408 #[doc = "Bit 2"]
25409 #[inline(always)]
25410 pub fn up_fifo_empty_int_en(&self) -> UpFifoEmptyIntEnR {
25411 UpFifoEmptyIntEnR::new(((self.bits >> 2) & 1) != 0)
25412 }
25413 #[doc = "Bit 3"]
25414 #[inline(always)]
25415 pub fn up_fifo_aempty_int_en(&self) -> UpFifoAemptyIntEnR {
25416 UpFifoAemptyIntEnR::new(((self.bits >> 3) & 1) != 0)
25417 }
25418 }
25419 impl W {
25420 #[doc = "Bit 0"]
25421 #[inline(always)]
25422 pub fn up_fifo_full_int_en(&mut self) -> UpFifoFullIntEnW<'_, UpFifoStCtrlSpec> {
25423 UpFifoFullIntEnW::new(self, 0)
25424 }
25425 #[doc = "Bit 1"]
25426 #[inline(always)]
25427 pub fn up_fifo_afull_int_en(&mut self) -> UpFifoAfullIntEnW<'_, UpFifoStCtrlSpec> {
25428 UpFifoAfullIntEnW::new(self, 1)
25429 }
25430 #[doc = "Bit 2"]
25431 #[inline(always)]
25432 pub fn up_fifo_empty_int_en(&mut self) -> UpFifoEmptyIntEnW<'_, UpFifoStCtrlSpec> {
25433 UpFifoEmptyIntEnW::new(self, 2)
25434 }
25435 #[doc = "Bit 3"]
25436 #[inline(always)]
25437 pub fn up_fifo_aempty_int_en(&mut self) -> UpFifoAemptyIntEnW<'_, UpFifoStCtrlSpec> {
25438 UpFifoAemptyIntEnW::new(self, 3)
25439 }
25440 }
25441 #[doc = "up_fifo_st_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_st_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_st_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25442 pub struct UpFifoStCtrlSpec;
25443 impl crate::RegisterSpec for UpFifoStCtrlSpec {
25444 type Ux = u32;
25445 }
25446 #[doc = "`read()` method returns [`up_fifo_st_ctrl::R`](R) reader structure"]
25447 impl crate::Readable for UpFifoStCtrlSpec {}
25448 #[doc = "`write(|w| ..)` method takes [`up_fifo_st_ctrl::W`](W) writer structure"]
25449 impl crate::Writable for UpFifoStCtrlSpec {
25450 type Safety = crate::Unsafe;
25451 }
25452 #[doc = "`reset()` method sets UP_FIFO_ST_CTRL to value 0"]
25453 impl crate::Resettable for UpFifoStCtrlSpec {}
25454 }
25455 #[doc = "UP_FIFO_ST_CLR (rw) register accessor: up_fifo_st_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_st_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_st_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@up_fifo_st_clr`] module"]
25456 #[doc(alias = "UP_FIFO_ST_CLR")]
25457 pub type UpFifoStClr = crate::Reg<up_fifo_st_clr::UpFifoStClrSpec>;
25458 #[doc = "up_fifo_st_clr"]
25459 pub mod up_fifo_st_clr {
25460 #[doc = "Register `UP_FIFO_ST_CLR` reader"]
25461 pub type R = crate::R<UpFifoStClrSpec>;
25462 #[doc = "Register `UP_FIFO_ST_CLR` writer"]
25463 pub type W = crate::W<UpFifoStClrSpec>;
25464 #[doc = "Field `up_fifo_full_int_clr` reader - "]
25465 pub type UpFifoFullIntClrR = crate::BitReader;
25466 #[doc = "Field `up_fifo_full_int_clr` writer - "]
25467 pub type UpFifoFullIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
25468 #[doc = "Field `up_fifo_afull_int_clr` reader - "]
25469 pub type UpFifoAfullIntClrR = crate::BitReader;
25470 #[doc = "Field `up_fifo_afull_int_clr` writer - "]
25471 pub type UpFifoAfullIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
25472 #[doc = "Field `up_fifo_empty_int_clr` reader - "]
25473 pub type UpFifoEmptyIntClrR = crate::BitReader;
25474 #[doc = "Field `up_fifo_empty_int_clr` writer - "]
25475 pub type UpFifoEmptyIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
25476 #[doc = "Field `up_fifo_aempty_int_clr` reader - "]
25477 pub type UpFifoAemptyIntClrR = crate::BitReader;
25478 #[doc = "Field `up_fifo_aempty_int_clr` writer - "]
25479 pub type UpFifoAemptyIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
25480 #[doc = "Field `up_fifo_clr` reader - "]
25481 pub type UpFifoClrR = crate::BitReader;
25482 #[doc = "Field `up_fifo_clr` writer - "]
25483 pub type UpFifoClrW<'a, REG> = crate::BitWriter<'a, REG>;
25484 impl R {
25485 #[doc = "Bit 0"]
25486 #[inline(always)]
25487 pub fn up_fifo_full_int_clr(&self) -> UpFifoFullIntClrR {
25488 UpFifoFullIntClrR::new((self.bits & 1) != 0)
25489 }
25490 #[doc = "Bit 1"]
25491 #[inline(always)]
25492 pub fn up_fifo_afull_int_clr(&self) -> UpFifoAfullIntClrR {
25493 UpFifoAfullIntClrR::new(((self.bits >> 1) & 1) != 0)
25494 }
25495 #[doc = "Bit 2"]
25496 #[inline(always)]
25497 pub fn up_fifo_empty_int_clr(&self) -> UpFifoEmptyIntClrR {
25498 UpFifoEmptyIntClrR::new(((self.bits >> 2) & 1) != 0)
25499 }
25500 #[doc = "Bit 3"]
25501 #[inline(always)]
25502 pub fn up_fifo_aempty_int_clr(&self) -> UpFifoAemptyIntClrR {
25503 UpFifoAemptyIntClrR::new(((self.bits >> 3) & 1) != 0)
25504 }
25505 #[doc = "Bit 4"]
25506 #[inline(always)]
25507 pub fn up_fifo_clr(&self) -> UpFifoClrR {
25508 UpFifoClrR::new(((self.bits >> 4) & 1) != 0)
25509 }
25510 }
25511 impl W {
25512 #[doc = "Bit 0"]
25513 #[inline(always)]
25514 pub fn up_fifo_full_int_clr(&mut self) -> UpFifoFullIntClrW<'_, UpFifoStClrSpec> {
25515 UpFifoFullIntClrW::new(self, 0)
25516 }
25517 #[doc = "Bit 1"]
25518 #[inline(always)]
25519 pub fn up_fifo_afull_int_clr(&mut self) -> UpFifoAfullIntClrW<'_, UpFifoStClrSpec> {
25520 UpFifoAfullIntClrW::new(self, 1)
25521 }
25522 #[doc = "Bit 2"]
25523 #[inline(always)]
25524 pub fn up_fifo_empty_int_clr(&mut self) -> UpFifoEmptyIntClrW<'_, UpFifoStClrSpec> {
25525 UpFifoEmptyIntClrW::new(self, 2)
25526 }
25527 #[doc = "Bit 3"]
25528 #[inline(always)]
25529 pub fn up_fifo_aempty_int_clr(&mut self) -> UpFifoAemptyIntClrW<'_, UpFifoStClrSpec> {
25530 UpFifoAemptyIntClrW::new(self, 3)
25531 }
25532 #[doc = "Bit 4"]
25533 #[inline(always)]
25534 pub fn up_fifo_clr(&mut self) -> UpFifoClrW<'_, UpFifoStClrSpec> {
25535 UpFifoClrW::new(self, 4)
25536 }
25537 }
25538 #[doc = "up_fifo_st_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_st_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_st_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25539 pub struct UpFifoStClrSpec;
25540 impl crate::RegisterSpec for UpFifoStClrSpec {
25541 type Ux = u32;
25542 }
25543 #[doc = "`read()` method returns [`up_fifo_st_clr::R`](R) reader structure"]
25544 impl crate::Readable for UpFifoStClrSpec {}
25545 #[doc = "`write(|w| ..)` method takes [`up_fifo_st_clr::W`](W) writer structure"]
25546 impl crate::Writable for UpFifoStClrSpec {
25547 type Safety = crate::Unsafe;
25548 }
25549 #[doc = "`reset()` method sets UP_FIFO_ST_CLR to value 0"]
25550 impl crate::Resettable for UpFifoStClrSpec {}
25551 }
25552}
25553#[doc = "Quadrature decoder (v150)"]
25554pub type Qdec = crate::Periph<qdec::RegisterBlock, 0x5200_0200>;
25555impl core::fmt::Debug for Qdec {
25556 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
25557 f.debug_struct("Qdec").finish()
25558 }
25559}
25560#[doc = "Quadrature decoder (v150)"]
25561pub mod qdec {
25562 #[repr(C)]
25563 #[doc = "Register block"]
25564 pub struct RegisterBlock {
25565 _reserved0: [u8; 0x04],
25566 qdec_task_start: QdecTaskStart,
25567 qdec_task_stop: QdecTaskStop,
25568 qdec_task_readclr_acc: QdecTaskReadclrAcc,
25569 qdec_task_rd_clr_acc: QdecTaskRdClrAcc,
25570 qdec_task_rd_clr_dbl: QdecTaskRdClrDbl,
25571 qdec_enable: QdecEnable,
25572 _reserved6: [u8; 0x04],
25573 qdec_event_int_sts: QdecEventIntSts,
25574 _reserved7: [u8; 0x10],
25575 qdec_int_en: QdecIntEn,
25576 qdec_int_clr: QdecIntClr,
25577 qdec_ledpol_data: QdecLedpolData,
25578 qdec_sampleper_data: QdecSampleperData,
25579 qdec_reporter_data: QdecReporterData,
25580 qdec_defen_data: QdecDefenData,
25581 qdec_ledpre_data: QdecLedpreData,
25582 qdec_sample_data: QdecSampleData,
25583 qdec_acc_data: QdecAccData,
25584 qdec_accdbl_data: QdecAccdblData,
25585 qdec_acc_read: QdecAccRead,
25586 qdec_accdbl_read: QdecAccdblRead,
25587 qdec_acc_event: QdecAccEvent,
25588 qdec_fpga_io_sel: QdecFpgaIoSel,
25589 _reserved21: [u8; 0x04],
25590 qdec_clk_ctl: QdecClkCtl,
25591 qdec_soft_rst: QdecSoftRst,
25592 }
25593 impl RegisterBlock {
25594 #[doc = "0x04 - qdec_task_start"]
25595 #[inline(always)]
25596 pub const fn qdec_task_start(&self) -> &QdecTaskStart {
25597 &self.qdec_task_start
25598 }
25599 #[doc = "0x08 - qdec_task_stop"]
25600 #[inline(always)]
25601 pub const fn qdec_task_stop(&self) -> &QdecTaskStop {
25602 &self.qdec_task_stop
25603 }
25604 #[doc = "0x0c - qdec_task_readclr_acc"]
25605 #[inline(always)]
25606 pub const fn qdec_task_readclr_acc(&self) -> &QdecTaskReadclrAcc {
25607 &self.qdec_task_readclr_acc
25608 }
25609 #[doc = "0x10 - qdec_task_rd_clr_acc"]
25610 #[inline(always)]
25611 pub const fn qdec_task_rd_clr_acc(&self) -> &QdecTaskRdClrAcc {
25612 &self.qdec_task_rd_clr_acc
25613 }
25614 #[doc = "0x14 - qdec_task_rd_clr_dbl"]
25615 #[inline(always)]
25616 pub const fn qdec_task_rd_clr_dbl(&self) -> &QdecTaskRdClrDbl {
25617 &self.qdec_task_rd_clr_dbl
25618 }
25619 #[doc = "0x18 - qdec_enable"]
25620 #[inline(always)]
25621 pub const fn qdec_enable(&self) -> &QdecEnable {
25622 &self.qdec_enable
25623 }
25624 #[doc = "0x20 - qdec_event_int_sts"]
25625 #[inline(always)]
25626 pub const fn qdec_event_int_sts(&self) -> &QdecEventIntSts {
25627 &self.qdec_event_int_sts
25628 }
25629 #[doc = "0x34 - qdec_int_en"]
25630 #[inline(always)]
25631 pub const fn qdec_int_en(&self) -> &QdecIntEn {
25632 &self.qdec_int_en
25633 }
25634 #[doc = "0x38 - qdec_int_clr"]
25635 #[inline(always)]
25636 pub const fn qdec_int_clr(&self) -> &QdecIntClr {
25637 &self.qdec_int_clr
25638 }
25639 #[doc = "0x3c - qdec_ledpol_data"]
25640 #[inline(always)]
25641 pub const fn qdec_ledpol_data(&self) -> &QdecLedpolData {
25642 &self.qdec_ledpol_data
25643 }
25644 #[doc = "0x40 - qdec_sampleper_data"]
25645 #[inline(always)]
25646 pub const fn qdec_sampleper_data(&self) -> &QdecSampleperData {
25647 &self.qdec_sampleper_data
25648 }
25649 #[doc = "0x44 - qdec_reporter_data"]
25650 #[inline(always)]
25651 pub const fn qdec_reporter_data(&self) -> &QdecReporterData {
25652 &self.qdec_reporter_data
25653 }
25654 #[doc = "0x48 - qdec_defen_data"]
25655 #[inline(always)]
25656 pub const fn qdec_defen_data(&self) -> &QdecDefenData {
25657 &self.qdec_defen_data
25658 }
25659 #[doc = "0x4c - qdec_ledpre_data"]
25660 #[inline(always)]
25661 pub const fn qdec_ledpre_data(&self) -> &QdecLedpreData {
25662 &self.qdec_ledpre_data
25663 }
25664 #[doc = "0x50 - qdec_sample_data"]
25665 #[inline(always)]
25666 pub const fn qdec_sample_data(&self) -> &QdecSampleData {
25667 &self.qdec_sample_data
25668 }
25669 #[doc = "0x54 - qdec_acc_data"]
25670 #[inline(always)]
25671 pub const fn qdec_acc_data(&self) -> &QdecAccData {
25672 &self.qdec_acc_data
25673 }
25674 #[doc = "0x58 - qdec_accdbl_data"]
25675 #[inline(always)]
25676 pub const fn qdec_accdbl_data(&self) -> &QdecAccdblData {
25677 &self.qdec_accdbl_data
25678 }
25679 #[doc = "0x5c - qdec_acc_read"]
25680 #[inline(always)]
25681 pub const fn qdec_acc_read(&self) -> &QdecAccRead {
25682 &self.qdec_acc_read
25683 }
25684 #[doc = "0x60 - qdec_accdbl_read"]
25685 #[inline(always)]
25686 pub const fn qdec_accdbl_read(&self) -> &QdecAccdblRead {
25687 &self.qdec_accdbl_read
25688 }
25689 #[doc = "0x64 - qdec_acc_event"]
25690 #[inline(always)]
25691 pub const fn qdec_acc_event(&self) -> &QdecAccEvent {
25692 &self.qdec_acc_event
25693 }
25694 #[doc = "0x68 - qdec_fpga_io_sel"]
25695 #[inline(always)]
25696 pub const fn qdec_fpga_io_sel(&self) -> &QdecFpgaIoSel {
25697 &self.qdec_fpga_io_sel
25698 }
25699 #[doc = "0x70 - qdec_clk_ctl"]
25700 #[inline(always)]
25701 pub const fn qdec_clk_ctl(&self) -> &QdecClkCtl {
25702 &self.qdec_clk_ctl
25703 }
25704 #[doc = "0x74 - qdec_soft_rst"]
25705 #[inline(always)]
25706 pub const fn qdec_soft_rst(&self) -> &QdecSoftRst {
25707 &self.qdec_soft_rst
25708 }
25709 }
25710 #[doc = "QDEC_TASK_START (rw) register accessor: qdec_task_start\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_start`] module"]
25711 #[doc(alias = "QDEC_TASK_START")]
25712 pub type QdecTaskStart = crate::Reg<qdec_task_start::QdecTaskStartSpec>;
25713 #[doc = "qdec_task_start"]
25714 pub mod qdec_task_start {
25715 #[doc = "Register `QDEC_TASK_START` reader"]
25716 pub type R = crate::R<QdecTaskStartSpec>;
25717 #[doc = "Register `QDEC_TASK_START` writer"]
25718 pub type W = crate::W<QdecTaskStartSpec>;
25719 #[doc = "Field `start` reader - "]
25720 pub type StartR = crate::BitReader;
25721 #[doc = "Field `start` writer - "]
25722 pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
25723 impl R {
25724 #[doc = "Bit 0"]
25725 #[inline(always)]
25726 pub fn start(&self) -> StartR {
25727 StartR::new((self.bits & 1) != 0)
25728 }
25729 }
25730 impl W {
25731 #[doc = "Bit 0"]
25732 #[inline(always)]
25733 pub fn start(&mut self) -> StartW<'_, QdecTaskStartSpec> {
25734 StartW::new(self, 0)
25735 }
25736 }
25737 #[doc = "qdec_task_start\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25738 pub struct QdecTaskStartSpec;
25739 impl crate::RegisterSpec for QdecTaskStartSpec {
25740 type Ux = u32;
25741 }
25742 #[doc = "`read()` method returns [`qdec_task_start::R`](R) reader structure"]
25743 impl crate::Readable for QdecTaskStartSpec {}
25744 #[doc = "`write(|w| ..)` method takes [`qdec_task_start::W`](W) writer structure"]
25745 impl crate::Writable for QdecTaskStartSpec {
25746 type Safety = crate::Unsafe;
25747 }
25748 #[doc = "`reset()` method sets QDEC_TASK_START to value 0"]
25749 impl crate::Resettable for QdecTaskStartSpec {}
25750 }
25751 #[doc = "QDEC_TASK_STOP (rw) register accessor: qdec_task_stop\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_stop::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_stop::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_stop`] module"]
25752 #[doc(alias = "QDEC_TASK_STOP")]
25753 pub type QdecTaskStop = crate::Reg<qdec_task_stop::QdecTaskStopSpec>;
25754 #[doc = "qdec_task_stop"]
25755 pub mod qdec_task_stop {
25756 #[doc = "Register `QDEC_TASK_STOP` reader"]
25757 pub type R = crate::R<QdecTaskStopSpec>;
25758 #[doc = "Register `QDEC_TASK_STOP` writer"]
25759 pub type W = crate::W<QdecTaskStopSpec>;
25760 #[doc = "Field `stop` reader - "]
25761 pub type StopR = crate::BitReader;
25762 #[doc = "Field `stop` writer - "]
25763 pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
25764 impl R {
25765 #[doc = "Bit 0"]
25766 #[inline(always)]
25767 pub fn stop(&self) -> StopR {
25768 StopR::new((self.bits & 1) != 0)
25769 }
25770 }
25771 impl W {
25772 #[doc = "Bit 0"]
25773 #[inline(always)]
25774 pub fn stop(&mut self) -> StopW<'_, QdecTaskStopSpec> {
25775 StopW::new(self, 0)
25776 }
25777 }
25778 #[doc = "qdec_task_stop\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_stop::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_stop::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25779 pub struct QdecTaskStopSpec;
25780 impl crate::RegisterSpec for QdecTaskStopSpec {
25781 type Ux = u32;
25782 }
25783 #[doc = "`read()` method returns [`qdec_task_stop::R`](R) reader structure"]
25784 impl crate::Readable for QdecTaskStopSpec {}
25785 #[doc = "`write(|w| ..)` method takes [`qdec_task_stop::W`](W) writer structure"]
25786 impl crate::Writable for QdecTaskStopSpec {
25787 type Safety = crate::Unsafe;
25788 }
25789 #[doc = "`reset()` method sets QDEC_TASK_STOP to value 0"]
25790 impl crate::Resettable for QdecTaskStopSpec {}
25791 }
25792 #[doc = "QDEC_TASK_READCLR_ACC (rw) register accessor: qdec_task_readclr_acc\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_readclr_acc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_readclr_acc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_readclr_acc`] module"]
25793 #[doc(alias = "QDEC_TASK_READCLR_ACC")]
25794 pub type QdecTaskReadclrAcc = crate::Reg<qdec_task_readclr_acc::QdecTaskReadclrAccSpec>;
25795 #[doc = "qdec_task_readclr_acc"]
25796 pub mod qdec_task_readclr_acc {
25797 #[doc = "Register `QDEC_TASK_READCLR_ACC` reader"]
25798 pub type R = crate::R<QdecTaskReadclrAccSpec>;
25799 #[doc = "Register `QDEC_TASK_READCLR_ACC` writer"]
25800 pub type W = crate::W<QdecTaskReadclrAccSpec>;
25801 #[doc = "Field `readclr_acc` reader - "]
25802 pub type ReadclrAccR = crate::BitReader;
25803 #[doc = "Field `readclr_acc` writer - "]
25804 pub type ReadclrAccW<'a, REG> = crate::BitWriter<'a, REG>;
25805 impl R {
25806 #[doc = "Bit 0"]
25807 #[inline(always)]
25808 pub fn readclr_acc(&self) -> ReadclrAccR {
25809 ReadclrAccR::new((self.bits & 1) != 0)
25810 }
25811 }
25812 impl W {
25813 #[doc = "Bit 0"]
25814 #[inline(always)]
25815 pub fn readclr_acc(&mut self) -> ReadclrAccW<'_, QdecTaskReadclrAccSpec> {
25816 ReadclrAccW::new(self, 0)
25817 }
25818 }
25819 #[doc = "qdec_task_readclr_acc\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_readclr_acc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_readclr_acc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25820 pub struct QdecTaskReadclrAccSpec;
25821 impl crate::RegisterSpec for QdecTaskReadclrAccSpec {
25822 type Ux = u32;
25823 }
25824 #[doc = "`read()` method returns [`qdec_task_readclr_acc::R`](R) reader structure"]
25825 impl crate::Readable for QdecTaskReadclrAccSpec {}
25826 #[doc = "`write(|w| ..)` method takes [`qdec_task_readclr_acc::W`](W) writer structure"]
25827 impl crate::Writable for QdecTaskReadclrAccSpec {
25828 type Safety = crate::Unsafe;
25829 }
25830 #[doc = "`reset()` method sets QDEC_TASK_READCLR_ACC to value 0"]
25831 impl crate::Resettable for QdecTaskReadclrAccSpec {}
25832 }
25833 #[doc = "QDEC_TASK_RD_CLR_ACC (rw) register accessor: qdec_task_rd_clr_acc\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_rd_clr_acc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_rd_clr_acc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_rd_clr_acc`] module"]
25834 #[doc(alias = "QDEC_TASK_RD_CLR_ACC")]
25835 pub type QdecTaskRdClrAcc = crate::Reg<qdec_task_rd_clr_acc::QdecTaskRdClrAccSpec>;
25836 #[doc = "qdec_task_rd_clr_acc"]
25837 pub mod qdec_task_rd_clr_acc {
25838 #[doc = "Register `QDEC_TASK_RD_CLR_ACC` reader"]
25839 pub type R = crate::R<QdecTaskRdClrAccSpec>;
25840 #[doc = "Register `QDEC_TASK_RD_CLR_ACC` writer"]
25841 pub type W = crate::W<QdecTaskRdClrAccSpec>;
25842 #[doc = "Field `rd_clr_acc` reader - "]
25843 pub type RdClrAccR = crate::BitReader;
25844 #[doc = "Field `rd_clr_acc` writer - "]
25845 pub type RdClrAccW<'a, REG> = crate::BitWriter<'a, REG>;
25846 impl R {
25847 #[doc = "Bit 0"]
25848 #[inline(always)]
25849 pub fn rd_clr_acc(&self) -> RdClrAccR {
25850 RdClrAccR::new((self.bits & 1) != 0)
25851 }
25852 }
25853 impl W {
25854 #[doc = "Bit 0"]
25855 #[inline(always)]
25856 pub fn rd_clr_acc(&mut self) -> RdClrAccW<'_, QdecTaskRdClrAccSpec> {
25857 RdClrAccW::new(self, 0)
25858 }
25859 }
25860 #[doc = "qdec_task_rd_clr_acc\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_rd_clr_acc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_rd_clr_acc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25861 pub struct QdecTaskRdClrAccSpec;
25862 impl crate::RegisterSpec for QdecTaskRdClrAccSpec {
25863 type Ux = u32;
25864 }
25865 #[doc = "`read()` method returns [`qdec_task_rd_clr_acc::R`](R) reader structure"]
25866 impl crate::Readable for QdecTaskRdClrAccSpec {}
25867 #[doc = "`write(|w| ..)` method takes [`qdec_task_rd_clr_acc::W`](W) writer structure"]
25868 impl crate::Writable for QdecTaskRdClrAccSpec {
25869 type Safety = crate::Unsafe;
25870 }
25871 #[doc = "`reset()` method sets QDEC_TASK_RD_CLR_ACC to value 0"]
25872 impl crate::Resettable for QdecTaskRdClrAccSpec {}
25873 }
25874 #[doc = "QDEC_TASK_RD_CLR_DBL (rw) register accessor: qdec_task_rd_clr_dbl\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_rd_clr_dbl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_rd_clr_dbl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_rd_clr_dbl`] module"]
25875 #[doc(alias = "QDEC_TASK_RD_CLR_DBL")]
25876 pub type QdecTaskRdClrDbl = crate::Reg<qdec_task_rd_clr_dbl::QdecTaskRdClrDblSpec>;
25877 #[doc = "qdec_task_rd_clr_dbl"]
25878 pub mod qdec_task_rd_clr_dbl {
25879 #[doc = "Register `QDEC_TASK_RD_CLR_DBL` reader"]
25880 pub type R = crate::R<QdecTaskRdClrDblSpec>;
25881 #[doc = "Register `QDEC_TASK_RD_CLR_DBL` writer"]
25882 pub type W = crate::W<QdecTaskRdClrDblSpec>;
25883 #[doc = "Field `rd_clr_dbl` reader - "]
25884 pub type RdClrDblR = crate::BitReader;
25885 #[doc = "Field `rd_clr_dbl` writer - "]
25886 pub type RdClrDblW<'a, REG> = crate::BitWriter<'a, REG>;
25887 impl R {
25888 #[doc = "Bit 0"]
25889 #[inline(always)]
25890 pub fn rd_clr_dbl(&self) -> RdClrDblR {
25891 RdClrDblR::new((self.bits & 1) != 0)
25892 }
25893 }
25894 impl W {
25895 #[doc = "Bit 0"]
25896 #[inline(always)]
25897 pub fn rd_clr_dbl(&mut self) -> RdClrDblW<'_, QdecTaskRdClrDblSpec> {
25898 RdClrDblW::new(self, 0)
25899 }
25900 }
25901 #[doc = "qdec_task_rd_clr_dbl\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_rd_clr_dbl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_rd_clr_dbl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25902 pub struct QdecTaskRdClrDblSpec;
25903 impl crate::RegisterSpec for QdecTaskRdClrDblSpec {
25904 type Ux = u32;
25905 }
25906 #[doc = "`read()` method returns [`qdec_task_rd_clr_dbl::R`](R) reader structure"]
25907 impl crate::Readable for QdecTaskRdClrDblSpec {}
25908 #[doc = "`write(|w| ..)` method takes [`qdec_task_rd_clr_dbl::W`](W) writer structure"]
25909 impl crate::Writable for QdecTaskRdClrDblSpec {
25910 type Safety = crate::Unsafe;
25911 }
25912 #[doc = "`reset()` method sets QDEC_TASK_RD_CLR_DBL to value 0"]
25913 impl crate::Resettable for QdecTaskRdClrDblSpec {}
25914 }
25915 #[doc = "QDEC_ENABLE (rw) register accessor: qdec_enable\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_enable`] module"]
25916 #[doc(alias = "QDEC_ENABLE")]
25917 pub type QdecEnable = crate::Reg<qdec_enable::QdecEnableSpec>;
25918 #[doc = "qdec_enable"]
25919 pub mod qdec_enable {
25920 #[doc = "Register `QDEC_ENABLE` reader"]
25921 pub type R = crate::R<QdecEnableSpec>;
25922 #[doc = "Register `QDEC_ENABLE` writer"]
25923 pub type W = crate::W<QdecEnableSpec>;
25924 #[doc = "Field `en` reader - "]
25925 pub type EnR = crate::BitReader;
25926 #[doc = "Field `en` writer - "]
25927 pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
25928 impl R {
25929 #[doc = "Bit 0"]
25930 #[inline(always)]
25931 pub fn en(&self) -> EnR {
25932 EnR::new((self.bits & 1) != 0)
25933 }
25934 }
25935 impl W {
25936 #[doc = "Bit 0"]
25937 #[inline(always)]
25938 pub fn en(&mut self) -> EnW<'_, QdecEnableSpec> {
25939 EnW::new(self, 0)
25940 }
25941 }
25942 #[doc = "qdec_enable\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25943 pub struct QdecEnableSpec;
25944 impl crate::RegisterSpec for QdecEnableSpec {
25945 type Ux = u32;
25946 }
25947 #[doc = "`read()` method returns [`qdec_enable::R`](R) reader structure"]
25948 impl crate::Readable for QdecEnableSpec {}
25949 #[doc = "`write(|w| ..)` method takes [`qdec_enable::W`](W) writer structure"]
25950 impl crate::Writable for QdecEnableSpec {
25951 type Safety = crate::Unsafe;
25952 }
25953 #[doc = "`reset()` method sets QDEC_ENABLE to value 0"]
25954 impl crate::Resettable for QdecEnableSpec {}
25955 }
25956 #[doc = "QDEC_EVENT_INT_STS (rw) register accessor: qdec_event_int_sts\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_event_int_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_event_int_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_event_int_sts`] module"]
25957 #[doc(alias = "QDEC_EVENT_INT_STS")]
25958 pub type QdecEventIntSts = crate::Reg<qdec_event_int_sts::QdecEventIntStsSpec>;
25959 #[doc = "qdec_event_int_sts"]
25960 pub mod qdec_event_int_sts {
25961 #[doc = "Register `QDEC_EVENT_INT_STS` reader"]
25962 pub type R = crate::R<QdecEventIntStsSpec>;
25963 #[doc = "Register `QDEC_EVENT_INT_STS` writer"]
25964 pub type W = crate::W<QdecEventIntStsSpec>;
25965 #[doc = "Field `events_stopped` reader - "]
25966 pub type EventsStoppedR = crate::BitReader;
25967 #[doc = "Field `events_stopped` writer - "]
25968 pub type EventsStoppedW<'a, REG> = crate::BitWriter<'a, REG>;
25969 #[doc = "Field `acc_rdy` reader - "]
25970 pub type AccRdyR = crate::BitReader;
25971 #[doc = "Field `acc_rdy` writer - "]
25972 pub type AccRdyW<'a, REG> = crate::BitWriter<'a, REG>;
25973 #[doc = "Field `dbl_rdy` reader - "]
25974 pub type DblRdyR = crate::BitReader;
25975 #[doc = "Field `dbl_rdy` writer - "]
25976 pub type DblRdyW<'a, REG> = crate::BitWriter<'a, REG>;
25977 #[doc = "Field `report_rdy` reader - "]
25978 pub type ReportRdyR = crate::BitReader;
25979 #[doc = "Field `report_rdy` writer - "]
25980 pub type ReportRdyW<'a, REG> = crate::BitWriter<'a, REG>;
25981 #[doc = "Field `sample_rdy` reader - "]
25982 pub type SampleRdyR = crate::BitReader;
25983 #[doc = "Field `sample_rdy` writer - "]
25984 pub type SampleRdyW<'a, REG> = crate::BitWriter<'a, REG>;
25985 impl R {
25986 #[doc = "Bit 0"]
25987 #[inline(always)]
25988 pub fn events_stopped(&self) -> EventsStoppedR {
25989 EventsStoppedR::new((self.bits & 1) != 0)
25990 }
25991 #[doc = "Bit 1"]
25992 #[inline(always)]
25993 pub fn acc_rdy(&self) -> AccRdyR {
25994 AccRdyR::new(((self.bits >> 1) & 1) != 0)
25995 }
25996 #[doc = "Bit 2"]
25997 #[inline(always)]
25998 pub fn dbl_rdy(&self) -> DblRdyR {
25999 DblRdyR::new(((self.bits >> 2) & 1) != 0)
26000 }
26001 #[doc = "Bit 3"]
26002 #[inline(always)]
26003 pub fn report_rdy(&self) -> ReportRdyR {
26004 ReportRdyR::new(((self.bits >> 3) & 1) != 0)
26005 }
26006 #[doc = "Bit 4"]
26007 #[inline(always)]
26008 pub fn sample_rdy(&self) -> SampleRdyR {
26009 SampleRdyR::new(((self.bits >> 4) & 1) != 0)
26010 }
26011 }
26012 impl W {
26013 #[doc = "Bit 0"]
26014 #[inline(always)]
26015 pub fn events_stopped(&mut self) -> EventsStoppedW<'_, QdecEventIntStsSpec> {
26016 EventsStoppedW::new(self, 0)
26017 }
26018 #[doc = "Bit 1"]
26019 #[inline(always)]
26020 pub fn acc_rdy(&mut self) -> AccRdyW<'_, QdecEventIntStsSpec> {
26021 AccRdyW::new(self, 1)
26022 }
26023 #[doc = "Bit 2"]
26024 #[inline(always)]
26025 pub fn dbl_rdy(&mut self) -> DblRdyW<'_, QdecEventIntStsSpec> {
26026 DblRdyW::new(self, 2)
26027 }
26028 #[doc = "Bit 3"]
26029 #[inline(always)]
26030 pub fn report_rdy(&mut self) -> ReportRdyW<'_, QdecEventIntStsSpec> {
26031 ReportRdyW::new(self, 3)
26032 }
26033 #[doc = "Bit 4"]
26034 #[inline(always)]
26035 pub fn sample_rdy(&mut self) -> SampleRdyW<'_, QdecEventIntStsSpec> {
26036 SampleRdyW::new(self, 4)
26037 }
26038 }
26039 #[doc = "qdec_event_int_sts\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_event_int_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_event_int_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26040 pub struct QdecEventIntStsSpec;
26041 impl crate::RegisterSpec for QdecEventIntStsSpec {
26042 type Ux = u32;
26043 }
26044 #[doc = "`read()` method returns [`qdec_event_int_sts::R`](R) reader structure"]
26045 impl crate::Readable for QdecEventIntStsSpec {}
26046 #[doc = "`write(|w| ..)` method takes [`qdec_event_int_sts::W`](W) writer structure"]
26047 impl crate::Writable for QdecEventIntStsSpec {
26048 type Safety = crate::Unsafe;
26049 }
26050 #[doc = "`reset()` method sets QDEC_EVENT_INT_STS to value 0"]
26051 impl crate::Resettable for QdecEventIntStsSpec {}
26052 }
26053 #[doc = "QDEC_INT_EN (rw) register accessor: qdec_int_en\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_int_en`] module"]
26054 #[doc(alias = "QDEC_INT_EN")]
26055 pub type QdecIntEn = crate::Reg<qdec_int_en::QdecIntEnSpec>;
26056 #[doc = "qdec_int_en"]
26057 pub mod qdec_int_en {
26058 #[doc = "Register `QDEC_INT_EN` reader"]
26059 pub type R = crate::R<QdecIntEnSpec>;
26060 #[doc = "Register `QDEC_INT_EN` writer"]
26061 pub type W = crate::W<QdecIntEnSpec>;
26062 #[doc = "Field `stopped` reader - "]
26063 pub type StoppedR = crate::BitReader;
26064 #[doc = "Field `stopped` writer - "]
26065 pub type StoppedW<'a, REG> = crate::BitWriter<'a, REG>;
26066 #[doc = "Field `acc_en` reader - "]
26067 pub type AccEnR = crate::BitReader;
26068 #[doc = "Field `acc_en` writer - "]
26069 pub type AccEnW<'a, REG> = crate::BitWriter<'a, REG>;
26070 #[doc = "Field `dbl_en` reader - "]
26071 pub type DblEnR = crate::BitReader;
26072 #[doc = "Field `dbl_en` writer - "]
26073 pub type DblEnW<'a, REG> = crate::BitWriter<'a, REG>;
26074 #[doc = "Field `report_en` reader - "]
26075 pub type ReportEnR = crate::BitReader;
26076 #[doc = "Field `report_en` writer - "]
26077 pub type ReportEnW<'a, REG> = crate::BitWriter<'a, REG>;
26078 #[doc = "Field `sample_en` reader - "]
26079 pub type SampleEnR = crate::BitReader;
26080 #[doc = "Field `sample_en` writer - "]
26081 pub type SampleEnW<'a, REG> = crate::BitWriter<'a, REG>;
26082 impl R {
26083 #[doc = "Bit 0"]
26084 #[inline(always)]
26085 pub fn stopped(&self) -> StoppedR {
26086 StoppedR::new((self.bits & 1) != 0)
26087 }
26088 #[doc = "Bit 1"]
26089 #[inline(always)]
26090 pub fn acc_en(&self) -> AccEnR {
26091 AccEnR::new(((self.bits >> 1) & 1) != 0)
26092 }
26093 #[doc = "Bit 2"]
26094 #[inline(always)]
26095 pub fn dbl_en(&self) -> DblEnR {
26096 DblEnR::new(((self.bits >> 2) & 1) != 0)
26097 }
26098 #[doc = "Bit 3"]
26099 #[inline(always)]
26100 pub fn report_en(&self) -> ReportEnR {
26101 ReportEnR::new(((self.bits >> 3) & 1) != 0)
26102 }
26103 #[doc = "Bit 4"]
26104 #[inline(always)]
26105 pub fn sample_en(&self) -> SampleEnR {
26106 SampleEnR::new(((self.bits >> 4) & 1) != 0)
26107 }
26108 }
26109 impl W {
26110 #[doc = "Bit 0"]
26111 #[inline(always)]
26112 pub fn stopped(&mut self) -> StoppedW<'_, QdecIntEnSpec> {
26113 StoppedW::new(self, 0)
26114 }
26115 #[doc = "Bit 1"]
26116 #[inline(always)]
26117 pub fn acc_en(&mut self) -> AccEnW<'_, QdecIntEnSpec> {
26118 AccEnW::new(self, 1)
26119 }
26120 #[doc = "Bit 2"]
26121 #[inline(always)]
26122 pub fn dbl_en(&mut self) -> DblEnW<'_, QdecIntEnSpec> {
26123 DblEnW::new(self, 2)
26124 }
26125 #[doc = "Bit 3"]
26126 #[inline(always)]
26127 pub fn report_en(&mut self) -> ReportEnW<'_, QdecIntEnSpec> {
26128 ReportEnW::new(self, 3)
26129 }
26130 #[doc = "Bit 4"]
26131 #[inline(always)]
26132 pub fn sample_en(&mut self) -> SampleEnW<'_, QdecIntEnSpec> {
26133 SampleEnW::new(self, 4)
26134 }
26135 }
26136 #[doc = "qdec_int_en\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26137 pub struct QdecIntEnSpec;
26138 impl crate::RegisterSpec for QdecIntEnSpec {
26139 type Ux = u32;
26140 }
26141 #[doc = "`read()` method returns [`qdec_int_en::R`](R) reader structure"]
26142 impl crate::Readable for QdecIntEnSpec {}
26143 #[doc = "`write(|w| ..)` method takes [`qdec_int_en::W`](W) writer structure"]
26144 impl crate::Writable for QdecIntEnSpec {
26145 type Safety = crate::Unsafe;
26146 }
26147 #[doc = "`reset()` method sets QDEC_INT_EN to value 0"]
26148 impl crate::Resettable for QdecIntEnSpec {}
26149 }
26150 #[doc = "QDEC_INT_CLR (rw) register accessor: qdec_int_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_int_clr`] module"]
26151 #[doc(alias = "QDEC_INT_CLR")]
26152 pub type QdecIntClr = crate::Reg<qdec_int_clr::QdecIntClrSpec>;
26153 #[doc = "qdec_int_clr"]
26154 pub mod qdec_int_clr {
26155 #[doc = "Register `QDEC_INT_CLR` reader"]
26156 pub type R = crate::R<QdecIntClrSpec>;
26157 #[doc = "Register `QDEC_INT_CLR` writer"]
26158 pub type W = crate::W<QdecIntClrSpec>;
26159 #[doc = "Field `stop_int_clr` reader - "]
26160 pub type StopIntClrR = crate::BitReader;
26161 #[doc = "Field `stop_int_clr` writer - "]
26162 pub type StopIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
26163 #[doc = "Field `acc_clr` reader - "]
26164 pub type AccClrR = crate::BitReader;
26165 #[doc = "Field `acc_clr` writer - "]
26166 pub type AccClrW<'a, REG> = crate::BitWriter<'a, REG>;
26167 #[doc = "Field `dbl_clr` reader - "]
26168 pub type DblClrR = crate::BitReader;
26169 #[doc = "Field `dbl_clr` writer - "]
26170 pub type DblClrW<'a, REG> = crate::BitWriter<'a, REG>;
26171 #[doc = "Field `report_clr` reader - "]
26172 pub type ReportClrR = crate::BitReader;
26173 #[doc = "Field `report_clr` writer - "]
26174 pub type ReportClrW<'a, REG> = crate::BitWriter<'a, REG>;
26175 #[doc = "Field `sample_clr` reader - "]
26176 pub type SampleClrR = crate::BitReader;
26177 #[doc = "Field `sample_clr` writer - "]
26178 pub type SampleClrW<'a, REG> = crate::BitWriter<'a, REG>;
26179 impl R {
26180 #[doc = "Bit 0"]
26181 #[inline(always)]
26182 pub fn stop_int_clr(&self) -> StopIntClrR {
26183 StopIntClrR::new((self.bits & 1) != 0)
26184 }
26185 #[doc = "Bit 1"]
26186 #[inline(always)]
26187 pub fn acc_clr(&self) -> AccClrR {
26188 AccClrR::new(((self.bits >> 1) & 1) != 0)
26189 }
26190 #[doc = "Bit 2"]
26191 #[inline(always)]
26192 pub fn dbl_clr(&self) -> DblClrR {
26193 DblClrR::new(((self.bits >> 2) & 1) != 0)
26194 }
26195 #[doc = "Bit 3"]
26196 #[inline(always)]
26197 pub fn report_clr(&self) -> ReportClrR {
26198 ReportClrR::new(((self.bits >> 3) & 1) != 0)
26199 }
26200 #[doc = "Bit 4"]
26201 #[inline(always)]
26202 pub fn sample_clr(&self) -> SampleClrR {
26203 SampleClrR::new(((self.bits >> 4) & 1) != 0)
26204 }
26205 }
26206 impl W {
26207 #[doc = "Bit 0"]
26208 #[inline(always)]
26209 pub fn stop_int_clr(&mut self) -> StopIntClrW<'_, QdecIntClrSpec> {
26210 StopIntClrW::new(self, 0)
26211 }
26212 #[doc = "Bit 1"]
26213 #[inline(always)]
26214 pub fn acc_clr(&mut self) -> AccClrW<'_, QdecIntClrSpec> {
26215 AccClrW::new(self, 1)
26216 }
26217 #[doc = "Bit 2"]
26218 #[inline(always)]
26219 pub fn dbl_clr(&mut self) -> DblClrW<'_, QdecIntClrSpec> {
26220 DblClrW::new(self, 2)
26221 }
26222 #[doc = "Bit 3"]
26223 #[inline(always)]
26224 pub fn report_clr(&mut self) -> ReportClrW<'_, QdecIntClrSpec> {
26225 ReportClrW::new(self, 3)
26226 }
26227 #[doc = "Bit 4"]
26228 #[inline(always)]
26229 pub fn sample_clr(&mut self) -> SampleClrW<'_, QdecIntClrSpec> {
26230 SampleClrW::new(self, 4)
26231 }
26232 }
26233 #[doc = "qdec_int_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26234 pub struct QdecIntClrSpec;
26235 impl crate::RegisterSpec for QdecIntClrSpec {
26236 type Ux = u32;
26237 }
26238 #[doc = "`read()` method returns [`qdec_int_clr::R`](R) reader structure"]
26239 impl crate::Readable for QdecIntClrSpec {}
26240 #[doc = "`write(|w| ..)` method takes [`qdec_int_clr::W`](W) writer structure"]
26241 impl crate::Writable for QdecIntClrSpec {
26242 type Safety = crate::Unsafe;
26243 }
26244 #[doc = "`reset()` method sets QDEC_INT_CLR to value 0"]
26245 impl crate::Resettable for QdecIntClrSpec {}
26246 }
26247 #[doc = "QDEC_LEDPOL_DATA (rw) register accessor: qdec_ledpol_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_ledpol_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_ledpol_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_ledpol_data`] module"]
26248 #[doc(alias = "QDEC_LEDPOL_DATA")]
26249 pub type QdecLedpolData = crate::Reg<qdec_ledpol_data::QdecLedpolDataSpec>;
26250 #[doc = "qdec_ledpol_data"]
26251 pub mod qdec_ledpol_data {
26252 #[doc = "Register `QDEC_LEDPOL_DATA` reader"]
26253 pub type R = crate::R<QdecLedpolDataSpec>;
26254 #[doc = "Register `QDEC_LEDPOL_DATA` writer"]
26255 pub type W = crate::W<QdecLedpolDataSpec>;
26256 #[doc = "Field `pol` reader - "]
26257 pub type PolR = crate::BitReader;
26258 #[doc = "Field `pol` writer - "]
26259 pub type PolW<'a, REG> = crate::BitWriter<'a, REG>;
26260 #[doc = "Field `en` reader - "]
26261 pub type EnR = crate::BitReader;
26262 #[doc = "Field `en` writer - "]
26263 pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
26264 impl R {
26265 #[doc = "Bit 0"]
26266 #[inline(always)]
26267 pub fn pol(&self) -> PolR {
26268 PolR::new((self.bits & 1) != 0)
26269 }
26270 #[doc = "Bit 1"]
26271 #[inline(always)]
26272 pub fn en(&self) -> EnR {
26273 EnR::new(((self.bits >> 1) & 1) != 0)
26274 }
26275 }
26276 impl W {
26277 #[doc = "Bit 0"]
26278 #[inline(always)]
26279 pub fn pol(&mut self) -> PolW<'_, QdecLedpolDataSpec> {
26280 PolW::new(self, 0)
26281 }
26282 #[doc = "Bit 1"]
26283 #[inline(always)]
26284 pub fn en(&mut self) -> EnW<'_, QdecLedpolDataSpec> {
26285 EnW::new(self, 1)
26286 }
26287 }
26288 #[doc = "qdec_ledpol_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_ledpol_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_ledpol_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26289 pub struct QdecLedpolDataSpec;
26290 impl crate::RegisterSpec for QdecLedpolDataSpec {
26291 type Ux = u32;
26292 }
26293 #[doc = "`read()` method returns [`qdec_ledpol_data::R`](R) reader structure"]
26294 impl crate::Readable for QdecLedpolDataSpec {}
26295 #[doc = "`write(|w| ..)` method takes [`qdec_ledpol_data::W`](W) writer structure"]
26296 impl crate::Writable for QdecLedpolDataSpec {
26297 type Safety = crate::Unsafe;
26298 }
26299 #[doc = "`reset()` method sets QDEC_LEDPOL_DATA to value 0"]
26300 impl crate::Resettable for QdecLedpolDataSpec {}
26301 }
26302 #[doc = "QDEC_SAMPLEPER_DATA (rw) register accessor: qdec_sampleper_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_sampleper_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_sampleper_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_sampleper_data`] module"]
26303 #[doc(alias = "QDEC_SAMPLEPER_DATA")]
26304 pub type QdecSampleperData = crate::Reg<qdec_sampleper_data::QdecSampleperDataSpec>;
26305 #[doc = "qdec_sampleper_data"]
26306 pub mod qdec_sampleper_data {
26307 #[doc = "Register `QDEC_SAMPLEPER_DATA` reader"]
26308 pub type R = crate::R<QdecSampleperDataSpec>;
26309 #[doc = "Register `QDEC_SAMPLEPER_DATA` writer"]
26310 pub type W = crate::W<QdecSampleperDataSpec>;
26311 #[doc = "Field `period` reader - "]
26312 pub type PeriodR = crate::FieldReader;
26313 #[doc = "Field `period` writer - "]
26314 pub type PeriodW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
26315 #[doc = "Field `clk_freq` reader - "]
26316 pub type ClkFreqR = crate::BitReader;
26317 #[doc = "Field `clk_freq` writer - "]
26318 pub type ClkFreqW<'a, REG> = crate::BitWriter<'a, REG>;
26319 impl R {
26320 #[doc = "Bits 0:3"]
26321 #[inline(always)]
26322 pub fn period(&self) -> PeriodR {
26323 PeriodR::new((self.bits & 0x0f) as u8)
26324 }
26325 #[doc = "Bit 4"]
26326 #[inline(always)]
26327 pub fn clk_freq(&self) -> ClkFreqR {
26328 ClkFreqR::new(((self.bits >> 4) & 1) != 0)
26329 }
26330 }
26331 impl W {
26332 #[doc = "Bits 0:3"]
26333 #[inline(always)]
26334 pub fn period(&mut self) -> PeriodW<'_, QdecSampleperDataSpec> {
26335 PeriodW::new(self, 0)
26336 }
26337 #[doc = "Bit 4"]
26338 #[inline(always)]
26339 pub fn clk_freq(&mut self) -> ClkFreqW<'_, QdecSampleperDataSpec> {
26340 ClkFreqW::new(self, 4)
26341 }
26342 }
26343 #[doc = "qdec_sampleper_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_sampleper_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_sampleper_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26344 pub struct QdecSampleperDataSpec;
26345 impl crate::RegisterSpec for QdecSampleperDataSpec {
26346 type Ux = u32;
26347 }
26348 #[doc = "`read()` method returns [`qdec_sampleper_data::R`](R) reader structure"]
26349 impl crate::Readable for QdecSampleperDataSpec {}
26350 #[doc = "`write(|w| ..)` method takes [`qdec_sampleper_data::W`](W) writer structure"]
26351 impl crate::Writable for QdecSampleperDataSpec {
26352 type Safety = crate::Unsafe;
26353 }
26354 #[doc = "`reset()` method sets QDEC_SAMPLEPER_DATA to value 0"]
26355 impl crate::Resettable for QdecSampleperDataSpec {}
26356 }
26357 #[doc = "QDEC_REPORTER_DATA (rw) register accessor: qdec_reporter_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_reporter_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_reporter_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_reporter_data`] module"]
26358 #[doc(alias = "QDEC_REPORTER_DATA")]
26359 pub type QdecReporterData = crate::Reg<qdec_reporter_data::QdecReporterDataSpec>;
26360 #[doc = "qdec_reporter_data"]
26361 pub mod qdec_reporter_data {
26362 #[doc = "Register `QDEC_REPORTER_DATA` reader"]
26363 pub type R = crate::R<QdecReporterDataSpec>;
26364 #[doc = "Register `QDEC_REPORTER_DATA` writer"]
26365 pub type W = crate::W<QdecReporterDataSpec>;
26366 #[doc = "Field `samlple_repo_val` reader - "]
26367 pub type SamlpleRepoValR = crate::FieldReader;
26368 #[doc = "Field `samlple_repo_val` writer - "]
26369 pub type SamlpleRepoValW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
26370 impl R {
26371 #[doc = "Bits 0:2"]
26372 #[inline(always)]
26373 pub fn samlple_repo_val(&self) -> SamlpleRepoValR {
26374 SamlpleRepoValR::new((self.bits & 7) as u8)
26375 }
26376 }
26377 impl W {
26378 #[doc = "Bits 0:2"]
26379 #[inline(always)]
26380 pub fn samlple_repo_val(&mut self) -> SamlpleRepoValW<'_, QdecReporterDataSpec> {
26381 SamlpleRepoValW::new(self, 0)
26382 }
26383 }
26384 #[doc = "qdec_reporter_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_reporter_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_reporter_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26385 pub struct QdecReporterDataSpec;
26386 impl crate::RegisterSpec for QdecReporterDataSpec {
26387 type Ux = u32;
26388 }
26389 #[doc = "`read()` method returns [`qdec_reporter_data::R`](R) reader structure"]
26390 impl crate::Readable for QdecReporterDataSpec {}
26391 #[doc = "`write(|w| ..)` method takes [`qdec_reporter_data::W`](W) writer structure"]
26392 impl crate::Writable for QdecReporterDataSpec {
26393 type Safety = crate::Unsafe;
26394 }
26395 #[doc = "`reset()` method sets QDEC_REPORTER_DATA to value 0"]
26396 impl crate::Resettable for QdecReporterDataSpec {}
26397 }
26398 #[doc = "QDEC_DEFEN_DATA (rw) register accessor: qdec_defen_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_defen_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_defen_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_defen_data`] module"]
26399 #[doc(alias = "QDEC_DEFEN_DATA")]
26400 pub type QdecDefenData = crate::Reg<qdec_defen_data::QdecDefenDataSpec>;
26401 #[doc = "qdec_defen_data"]
26402 pub mod qdec_defen_data {
26403 #[doc = "Register `QDEC_DEFEN_DATA` reader"]
26404 pub type R = crate::R<QdecDefenDataSpec>;
26405 #[doc = "Register `QDEC_DEFEN_DATA` writer"]
26406 pub type W = crate::W<QdecDefenDataSpec>;
26407 #[doc = "Field `en` reader - "]
26408 pub type EnR = crate::BitReader;
26409 #[doc = "Field `en` writer - "]
26410 pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
26411 #[doc = "Field `defen_num` reader - "]
26412 pub type DefenNumR = crate::FieldReader;
26413 #[doc = "Field `defen_num` writer - "]
26414 pub type DefenNumW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
26415 impl R {
26416 #[doc = "Bit 0"]
26417 #[inline(always)]
26418 pub fn en(&self) -> EnR {
26419 EnR::new((self.bits & 1) != 0)
26420 }
26421 #[doc = "Bits 4:6"]
26422 #[inline(always)]
26423 pub fn defen_num(&self) -> DefenNumR {
26424 DefenNumR::new(((self.bits >> 4) & 7) as u8)
26425 }
26426 }
26427 impl W {
26428 #[doc = "Bit 0"]
26429 #[inline(always)]
26430 pub fn en(&mut self) -> EnW<'_, QdecDefenDataSpec> {
26431 EnW::new(self, 0)
26432 }
26433 #[doc = "Bits 4:6"]
26434 #[inline(always)]
26435 pub fn defen_num(&mut self) -> DefenNumW<'_, QdecDefenDataSpec> {
26436 DefenNumW::new(self, 4)
26437 }
26438 }
26439 #[doc = "qdec_defen_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_defen_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_defen_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26440 pub struct QdecDefenDataSpec;
26441 impl crate::RegisterSpec for QdecDefenDataSpec {
26442 type Ux = u32;
26443 }
26444 #[doc = "`read()` method returns [`qdec_defen_data::R`](R) reader structure"]
26445 impl crate::Readable for QdecDefenDataSpec {}
26446 #[doc = "`write(|w| ..)` method takes [`qdec_defen_data::W`](W) writer structure"]
26447 impl crate::Writable for QdecDefenDataSpec {
26448 type Safety = crate::Unsafe;
26449 }
26450 #[doc = "`reset()` method sets QDEC_DEFEN_DATA to value 0"]
26451 impl crate::Resettable for QdecDefenDataSpec {}
26452 }
26453 #[doc = "QDEC_LEDPRE_DATA (rw) register accessor: qdec_ledpre_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_ledpre_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_ledpre_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_ledpre_data`] module"]
26454 #[doc(alias = "QDEC_LEDPRE_DATA")]
26455 pub type QdecLedpreData = crate::Reg<qdec_ledpre_data::QdecLedpreDataSpec>;
26456 #[doc = "qdec_ledpre_data"]
26457 pub mod qdec_ledpre_data {
26458 #[doc = "Register `QDEC_LEDPRE_DATA` reader"]
26459 pub type R = crate::R<QdecLedpreDataSpec>;
26460 #[doc = "Register `QDEC_LEDPRE_DATA` writer"]
26461 pub type W = crate::W<QdecLedpreDataSpec>;
26462 #[doc = "Field `led_pre` reader - "]
26463 pub type LedPreR = crate::FieldReader<u16>;
26464 #[doc = "Field `led_pre` writer - "]
26465 pub type LedPreW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
26466 impl R {
26467 #[doc = "Bits 0:9"]
26468 #[inline(always)]
26469 pub fn led_pre(&self) -> LedPreR {
26470 LedPreR::new((self.bits & 0x03ff) as u16)
26471 }
26472 }
26473 impl W {
26474 #[doc = "Bits 0:9"]
26475 #[inline(always)]
26476 pub fn led_pre(&mut self) -> LedPreW<'_, QdecLedpreDataSpec> {
26477 LedPreW::new(self, 0)
26478 }
26479 }
26480 #[doc = "qdec_ledpre_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_ledpre_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_ledpre_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26481 pub struct QdecLedpreDataSpec;
26482 impl crate::RegisterSpec for QdecLedpreDataSpec {
26483 type Ux = u32;
26484 }
26485 #[doc = "`read()` method returns [`qdec_ledpre_data::R`](R) reader structure"]
26486 impl crate::Readable for QdecLedpreDataSpec {}
26487 #[doc = "`write(|w| ..)` method takes [`qdec_ledpre_data::W`](W) writer structure"]
26488 impl crate::Writable for QdecLedpreDataSpec {
26489 type Safety = crate::Unsafe;
26490 }
26491 #[doc = "`reset()` method sets QDEC_LEDPRE_DATA to value 0"]
26492 impl crate::Resettable for QdecLedpreDataSpec {}
26493 }
26494 #[doc = "QDEC_SAMPLE_DATA (rw) register accessor: qdec_sample_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_sample_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_sample_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_sample_data`] module"]
26495 #[doc(alias = "QDEC_SAMPLE_DATA")]
26496 pub type QdecSampleData = crate::Reg<qdec_sample_data::QdecSampleDataSpec>;
26497 #[doc = "qdec_sample_data"]
26498 pub mod qdec_sample_data {
26499 #[doc = "Register `QDEC_SAMPLE_DATA` reader"]
26500 pub type R = crate::R<QdecSampleDataSpec>;
26501 #[doc = "Register `QDEC_SAMPLE_DATA` writer"]
26502 pub type W = crate::W<QdecSampleDataSpec>;
26503 #[doc = "Field `sample_val` reader - "]
26504 pub type SampleValR = crate::FieldReader;
26505 #[doc = "Field `sample_val` writer - "]
26506 pub type SampleValW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
26507 impl R {
26508 #[doc = "Bits 0:2"]
26509 #[inline(always)]
26510 pub fn sample_val(&self) -> SampleValR {
26511 SampleValR::new((self.bits & 7) as u8)
26512 }
26513 }
26514 impl W {
26515 #[doc = "Bits 0:2"]
26516 #[inline(always)]
26517 pub fn sample_val(&mut self) -> SampleValW<'_, QdecSampleDataSpec> {
26518 SampleValW::new(self, 0)
26519 }
26520 }
26521 #[doc = "qdec_sample_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_sample_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_sample_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26522 pub struct QdecSampleDataSpec;
26523 impl crate::RegisterSpec for QdecSampleDataSpec {
26524 type Ux = u32;
26525 }
26526 #[doc = "`read()` method returns [`qdec_sample_data::R`](R) reader structure"]
26527 impl crate::Readable for QdecSampleDataSpec {}
26528 #[doc = "`write(|w| ..)` method takes [`qdec_sample_data::W`](W) writer structure"]
26529 impl crate::Writable for QdecSampleDataSpec {
26530 type Safety = crate::Unsafe;
26531 }
26532 #[doc = "`reset()` method sets QDEC_SAMPLE_DATA to value 0"]
26533 impl crate::Resettable for QdecSampleDataSpec {}
26534 }
26535 #[doc = "QDEC_ACC_DATA (rw) register accessor: qdec_acc_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_acc_data`] module"]
26536 #[doc(alias = "QDEC_ACC_DATA")]
26537 pub type QdecAccData = crate::Reg<qdec_acc_data::QdecAccDataSpec>;
26538 #[doc = "qdec_acc_data"]
26539 pub mod qdec_acc_data {
26540 #[doc = "Register `QDEC_ACC_DATA` reader"]
26541 pub type R = crate::R<QdecAccDataSpec>;
26542 #[doc = "Register `QDEC_ACC_DATA` writer"]
26543 pub type W = crate::W<QdecAccDataSpec>;
26544 #[doc = "Field `acc_rd_val` reader - "]
26545 pub type AccRdValR = crate::FieldReader<u16>;
26546 #[doc = "Field `acc_rd_val` writer - "]
26547 pub type AccRdValW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
26548 impl R {
26549 #[doc = "Bits 0:15"]
26550 #[inline(always)]
26551 pub fn acc_rd_val(&self) -> AccRdValR {
26552 AccRdValR::new((self.bits & 0xffff) as u16)
26553 }
26554 }
26555 impl W {
26556 #[doc = "Bits 0:15"]
26557 #[inline(always)]
26558 pub fn acc_rd_val(&mut self) -> AccRdValW<'_, QdecAccDataSpec> {
26559 AccRdValW::new(self, 0)
26560 }
26561 }
26562 #[doc = "qdec_acc_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26563 pub struct QdecAccDataSpec;
26564 impl crate::RegisterSpec for QdecAccDataSpec {
26565 type Ux = u32;
26566 }
26567 #[doc = "`read()` method returns [`qdec_acc_data::R`](R) reader structure"]
26568 impl crate::Readable for QdecAccDataSpec {}
26569 #[doc = "`write(|w| ..)` method takes [`qdec_acc_data::W`](W) writer structure"]
26570 impl crate::Writable for QdecAccDataSpec {
26571 type Safety = crate::Unsafe;
26572 }
26573 #[doc = "`reset()` method sets QDEC_ACC_DATA to value 0"]
26574 impl crate::Resettable for QdecAccDataSpec {}
26575 }
26576 #[doc = "QDEC_ACCDBL_DATA (rw) register accessor: qdec_accdbl_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_accdbl_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_accdbl_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_accdbl_data`] module"]
26577 #[doc(alias = "QDEC_ACCDBL_DATA")]
26578 pub type QdecAccdblData = crate::Reg<qdec_accdbl_data::QdecAccdblDataSpec>;
26579 #[doc = "qdec_accdbl_data"]
26580 pub mod qdec_accdbl_data {
26581 #[doc = "Register `QDEC_ACCDBL_DATA` reader"]
26582 pub type R = crate::R<QdecAccdblDataSpec>;
26583 #[doc = "Register `QDEC_ACCDBL_DATA` writer"]
26584 pub type W = crate::W<QdecAccdblDataSpec>;
26585 #[doc = "Field `dbl_rd_val` reader - "]
26586 pub type DblRdValR = crate::FieldReader;
26587 #[doc = "Field `dbl_rd_val` writer - "]
26588 pub type DblRdValW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
26589 impl R {
26590 #[doc = "Bits 0:3"]
26591 #[inline(always)]
26592 pub fn dbl_rd_val(&self) -> DblRdValR {
26593 DblRdValR::new((self.bits & 0x0f) as u8)
26594 }
26595 }
26596 impl W {
26597 #[doc = "Bits 0:3"]
26598 #[inline(always)]
26599 pub fn dbl_rd_val(&mut self) -> DblRdValW<'_, QdecAccdblDataSpec> {
26600 DblRdValW::new(self, 0)
26601 }
26602 }
26603 #[doc = "qdec_accdbl_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_accdbl_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_accdbl_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26604 pub struct QdecAccdblDataSpec;
26605 impl crate::RegisterSpec for QdecAccdblDataSpec {
26606 type Ux = u32;
26607 }
26608 #[doc = "`read()` method returns [`qdec_accdbl_data::R`](R) reader structure"]
26609 impl crate::Readable for QdecAccdblDataSpec {}
26610 #[doc = "`write(|w| ..)` method takes [`qdec_accdbl_data::W`](W) writer structure"]
26611 impl crate::Writable for QdecAccdblDataSpec {
26612 type Safety = crate::Unsafe;
26613 }
26614 #[doc = "`reset()` method sets QDEC_ACCDBL_DATA to value 0"]
26615 impl crate::Resettable for QdecAccdblDataSpec {}
26616 }
26617 #[doc = "QDEC_ACC_READ (rw) register accessor: qdec_acc_read\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_read::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_read::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_acc_read`] module"]
26618 #[doc(alias = "QDEC_ACC_READ")]
26619 pub type QdecAccRead = crate::Reg<qdec_acc_read::QdecAccReadSpec>;
26620 #[doc = "qdec_acc_read"]
26621 pub mod qdec_acc_read {
26622 #[doc = "Register `QDEC_ACC_READ` reader"]
26623 pub type R = crate::R<QdecAccReadSpec>;
26624 #[doc = "Register `QDEC_ACC_READ` writer"]
26625 pub type W = crate::W<QdecAccReadSpec>;
26626 #[doc = "Field `acc_rd_val_shadow` reader - "]
26627 pub type AccRdValShadowR = crate::FieldReader<u16>;
26628 #[doc = "Field `acc_rd_val_shadow` writer - "]
26629 pub type AccRdValShadowW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
26630 impl R {
26631 #[doc = "Bits 0:15"]
26632 #[inline(always)]
26633 pub fn acc_rd_val_shadow(&self) -> AccRdValShadowR {
26634 AccRdValShadowR::new((self.bits & 0xffff) as u16)
26635 }
26636 }
26637 impl W {
26638 #[doc = "Bits 0:15"]
26639 #[inline(always)]
26640 pub fn acc_rd_val_shadow(&mut self) -> AccRdValShadowW<'_, QdecAccReadSpec> {
26641 AccRdValShadowW::new(self, 0)
26642 }
26643 }
26644 #[doc = "qdec_acc_read\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_read::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_read::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26645 pub struct QdecAccReadSpec;
26646 impl crate::RegisterSpec for QdecAccReadSpec {
26647 type Ux = u32;
26648 }
26649 #[doc = "`read()` method returns [`qdec_acc_read::R`](R) reader structure"]
26650 impl crate::Readable for QdecAccReadSpec {}
26651 #[doc = "`write(|w| ..)` method takes [`qdec_acc_read::W`](W) writer structure"]
26652 impl crate::Writable for QdecAccReadSpec {
26653 type Safety = crate::Unsafe;
26654 }
26655 #[doc = "`reset()` method sets QDEC_ACC_READ to value 0"]
26656 impl crate::Resettable for QdecAccReadSpec {}
26657 }
26658 #[doc = "QDEC_ACCDBL_READ (rw) register accessor: qdec_accdbl_read\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_accdbl_read::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_accdbl_read::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_accdbl_read`] module"]
26659 #[doc(alias = "QDEC_ACCDBL_READ")]
26660 pub type QdecAccdblRead = crate::Reg<qdec_accdbl_read::QdecAccdblReadSpec>;
26661 #[doc = "qdec_accdbl_read"]
26662 pub mod qdec_accdbl_read {
26663 #[doc = "Register `QDEC_ACCDBL_READ` reader"]
26664 pub type R = crate::R<QdecAccdblReadSpec>;
26665 #[doc = "Register `QDEC_ACCDBL_READ` writer"]
26666 pub type W = crate::W<QdecAccdblReadSpec>;
26667 #[doc = "Field `dbl_rd_val_shadow` reader - "]
26668 pub type DblRdValShadowR = crate::FieldReader;
26669 #[doc = "Field `dbl_rd_val_shadow` writer - "]
26670 pub type DblRdValShadowW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
26671 impl R {
26672 #[doc = "Bits 0:3"]
26673 #[inline(always)]
26674 pub fn dbl_rd_val_shadow(&self) -> DblRdValShadowR {
26675 DblRdValShadowR::new((self.bits & 0x0f) as u8)
26676 }
26677 }
26678 impl W {
26679 #[doc = "Bits 0:3"]
26680 #[inline(always)]
26681 pub fn dbl_rd_val_shadow(&mut self) -> DblRdValShadowW<'_, QdecAccdblReadSpec> {
26682 DblRdValShadowW::new(self, 0)
26683 }
26684 }
26685 #[doc = "qdec_accdbl_read\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_accdbl_read::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_accdbl_read::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26686 pub struct QdecAccdblReadSpec;
26687 impl crate::RegisterSpec for QdecAccdblReadSpec {
26688 type Ux = u32;
26689 }
26690 #[doc = "`read()` method returns [`qdec_accdbl_read::R`](R) reader structure"]
26691 impl crate::Readable for QdecAccdblReadSpec {}
26692 #[doc = "`write(|w| ..)` method takes [`qdec_accdbl_read::W`](W) writer structure"]
26693 impl crate::Writable for QdecAccdblReadSpec {
26694 type Safety = crate::Unsafe;
26695 }
26696 #[doc = "`reset()` method sets QDEC_ACCDBL_READ to value 0"]
26697 impl crate::Resettable for QdecAccdblReadSpec {}
26698 }
26699 #[doc = "QDEC_ACC_EVENT (rw) register accessor: qdec_acc_event\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_event::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_event::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_acc_event`] module"]
26700 #[doc(alias = "QDEC_ACC_EVENT")]
26701 pub type QdecAccEvent = crate::Reg<qdec_acc_event::QdecAccEventSpec>;
26702 #[doc = "qdec_acc_event"]
26703 pub mod qdec_acc_event {
26704 #[doc = "Register `QDEC_ACC_EVENT` reader"]
26705 pub type R = crate::R<QdecAccEventSpec>;
26706 #[doc = "Register `QDEC_ACC_EVENT` writer"]
26707 pub type W = crate::W<QdecAccEventSpec>;
26708 #[doc = "Field `acc_event_cnt` reader - "]
26709 pub type AccEventCntR = crate::FieldReader<u16>;
26710 #[doc = "Field `acc_event_cnt` writer - "]
26711 pub type AccEventCntW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
26712 impl R {
26713 #[doc = "Bits 0:8"]
26714 #[inline(always)]
26715 pub fn acc_event_cnt(&self) -> AccEventCntR {
26716 AccEventCntR::new((self.bits & 0x01ff) as u16)
26717 }
26718 }
26719 impl W {
26720 #[doc = "Bits 0:8"]
26721 #[inline(always)]
26722 pub fn acc_event_cnt(&mut self) -> AccEventCntW<'_, QdecAccEventSpec> {
26723 AccEventCntW::new(self, 0)
26724 }
26725 }
26726 #[doc = "qdec_acc_event\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_event::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_event::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26727 pub struct QdecAccEventSpec;
26728 impl crate::RegisterSpec for QdecAccEventSpec {
26729 type Ux = u32;
26730 }
26731 #[doc = "`read()` method returns [`qdec_acc_event::R`](R) reader structure"]
26732 impl crate::Readable for QdecAccEventSpec {}
26733 #[doc = "`write(|w| ..)` method takes [`qdec_acc_event::W`](W) writer structure"]
26734 impl crate::Writable for QdecAccEventSpec {
26735 type Safety = crate::Unsafe;
26736 }
26737 #[doc = "`reset()` method sets QDEC_ACC_EVENT to value 0"]
26738 impl crate::Resettable for QdecAccEventSpec {}
26739 }
26740 #[doc = "QDEC_FPGA_IO_SEL (rw) register accessor: qdec_fpga_io_sel\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_fpga_io_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_fpga_io_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_fpga_io_sel`] module"]
26741 #[doc(alias = "QDEC_FPGA_IO_SEL")]
26742 pub type QdecFpgaIoSel = crate::Reg<qdec_fpga_io_sel::QdecFpgaIoSelSpec>;
26743 #[doc = "qdec_fpga_io_sel"]
26744 pub mod qdec_fpga_io_sel {
26745 #[doc = "Register `QDEC_FPGA_IO_SEL` reader"]
26746 pub type R = crate::R<QdecFpgaIoSelSpec>;
26747 #[doc = "Register `QDEC_FPGA_IO_SEL` writer"]
26748 pub type W = crate::W<QdecFpgaIoSelSpec>;
26749 #[doc = "Field `fpga_io_src` reader - "]
26750 pub type FpgaIoSrcR = crate::BitReader;
26751 #[doc = "Field `fpga_io_src` writer - "]
26752 pub type FpgaIoSrcW<'a, REG> = crate::BitWriter<'a, REG>;
26753 impl R {
26754 #[doc = "Bit 0"]
26755 #[inline(always)]
26756 pub fn fpga_io_src(&self) -> FpgaIoSrcR {
26757 FpgaIoSrcR::new((self.bits & 1) != 0)
26758 }
26759 }
26760 impl W {
26761 #[doc = "Bit 0"]
26762 #[inline(always)]
26763 pub fn fpga_io_src(&mut self) -> FpgaIoSrcW<'_, QdecFpgaIoSelSpec> {
26764 FpgaIoSrcW::new(self, 0)
26765 }
26766 }
26767 #[doc = "qdec_fpga_io_sel\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_fpga_io_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_fpga_io_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26768 pub struct QdecFpgaIoSelSpec;
26769 impl crate::RegisterSpec for QdecFpgaIoSelSpec {
26770 type Ux = u32;
26771 }
26772 #[doc = "`read()` method returns [`qdec_fpga_io_sel::R`](R) reader structure"]
26773 impl crate::Readable for QdecFpgaIoSelSpec {}
26774 #[doc = "`write(|w| ..)` method takes [`qdec_fpga_io_sel::W`](W) writer structure"]
26775 impl crate::Writable for QdecFpgaIoSelSpec {
26776 type Safety = crate::Unsafe;
26777 }
26778 #[doc = "`reset()` method sets QDEC_FPGA_IO_SEL to value 0"]
26779 impl crate::Resettable for QdecFpgaIoSelSpec {}
26780 }
26781 #[doc = "QDEC_CLK_CTL (rw) register accessor: qdec_clk_ctl\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_clk_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_clk_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_clk_ctl`] module"]
26782 #[doc(alias = "QDEC_CLK_CTL")]
26783 pub type QdecClkCtl = crate::Reg<qdec_clk_ctl::QdecClkCtlSpec>;
26784 #[doc = "qdec_clk_ctl"]
26785 pub mod qdec_clk_ctl {
26786 #[doc = "Register `QDEC_CLK_CTL` reader"]
26787 pub type R = crate::R<QdecClkCtlSpec>;
26788 #[doc = "Register `QDEC_CLK_CTL` writer"]
26789 pub type W = crate::W<QdecClkCtlSpec>;
26790 #[doc = "Field `sel` reader - "]
26791 pub type SelR = crate::BitReader;
26792 #[doc = "Field `sel` writer - "]
26793 pub type SelW<'a, REG> = crate::BitWriter<'a, REG>;
26794 #[doc = "Field `en` reader - "]
26795 pub type EnR = crate::BitReader;
26796 #[doc = "Field `en` writer - "]
26797 pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
26798 impl R {
26799 #[doc = "Bit 0"]
26800 #[inline(always)]
26801 pub fn sel(&self) -> SelR {
26802 SelR::new((self.bits & 1) != 0)
26803 }
26804 #[doc = "Bit 4"]
26805 #[inline(always)]
26806 pub fn en(&self) -> EnR {
26807 EnR::new(((self.bits >> 4) & 1) != 0)
26808 }
26809 }
26810 impl W {
26811 #[doc = "Bit 0"]
26812 #[inline(always)]
26813 pub fn sel(&mut self) -> SelW<'_, QdecClkCtlSpec> {
26814 SelW::new(self, 0)
26815 }
26816 #[doc = "Bit 4"]
26817 #[inline(always)]
26818 pub fn en(&mut self) -> EnW<'_, QdecClkCtlSpec> {
26819 EnW::new(self, 4)
26820 }
26821 }
26822 #[doc = "qdec_clk_ctl\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_clk_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_clk_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26823 pub struct QdecClkCtlSpec;
26824 impl crate::RegisterSpec for QdecClkCtlSpec {
26825 type Ux = u32;
26826 }
26827 #[doc = "`read()` method returns [`qdec_clk_ctl::R`](R) reader structure"]
26828 impl crate::Readable for QdecClkCtlSpec {}
26829 #[doc = "`write(|w| ..)` method takes [`qdec_clk_ctl::W`](W) writer structure"]
26830 impl crate::Writable for QdecClkCtlSpec {
26831 type Safety = crate::Unsafe;
26832 }
26833 #[doc = "`reset()` method sets QDEC_CLK_CTL to value 0"]
26834 impl crate::Resettable for QdecClkCtlSpec {}
26835 }
26836 #[doc = "QDEC_SOFT_RST (rw) register accessor: qdec_soft_rst\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_soft_rst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_soft_rst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_soft_rst`] module"]
26837 #[doc(alias = "QDEC_SOFT_RST")]
26838 pub type QdecSoftRst = crate::Reg<qdec_soft_rst::QdecSoftRstSpec>;
26839 #[doc = "qdec_soft_rst"]
26840 pub mod qdec_soft_rst {
26841 #[doc = "Register `QDEC_SOFT_RST` reader"]
26842 pub type R = crate::R<QdecSoftRstSpec>;
26843 #[doc = "Register `QDEC_SOFT_RST` writer"]
26844 pub type W = crate::W<QdecSoftRstSpec>;
26845 #[doc = "Field `soft_rst` reader - "]
26846 pub type SoftRstR = crate::BitReader;
26847 #[doc = "Field `soft_rst` writer - "]
26848 pub type SoftRstW<'a, REG> = crate::BitWriter<'a, REG>;
26849 impl R {
26850 #[doc = "Bit 0"]
26851 #[inline(always)]
26852 pub fn soft_rst(&self) -> SoftRstR {
26853 SoftRstR::new((self.bits & 1) != 0)
26854 }
26855 }
26856 impl W {
26857 #[doc = "Bit 0"]
26858 #[inline(always)]
26859 pub fn soft_rst(&mut self) -> SoftRstW<'_, QdecSoftRstSpec> {
26860 SoftRstW::new(self, 0)
26861 }
26862 }
26863 #[doc = "qdec_soft_rst\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_soft_rst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_soft_rst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26864 pub struct QdecSoftRstSpec;
26865 impl crate::RegisterSpec for QdecSoftRstSpec {
26866 type Ux = u32;
26867 }
26868 #[doc = "`read()` method returns [`qdec_soft_rst::R`](R) reader structure"]
26869 impl crate::Readable for QdecSoftRstSpec {}
26870 #[doc = "`write(|w| ..)` method takes [`qdec_soft_rst::W`](W) writer structure"]
26871 impl crate::Writable for QdecSoftRstSpec {
26872 type Safety = crate::Unsafe;
26873 }
26874 #[doc = "`reset()` method sets QDEC_SOFT_RST to value 0"]
26875 impl crate::Resettable for QdecSoftRstSpec {}
26876 }
26877}
26878#[doc = "USB 2.0 OTG controller (Synopsys DWC OTG, device-controller base)"]
26879pub type Usb = crate::Periph<usb::RegisterBlock, 0x5800_0000>;
26880impl core::fmt::Debug for Usb {
26881 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
26882 f.debug_struct("Usb").finish()
26883 }
26884}
26885#[doc = "USB 2.0 OTG controller (Synopsys DWC OTG, device-controller base)"]
26886pub mod usb {
26887 #[repr(C)]
26888 #[doc = "Register block"]
26889 pub struct RegisterBlock {
26890 gotgctl: Gotgctl,
26891 gotgint: Gotgint,
26892 gahbcfg: Gahbcfg,
26893 gusbcfg: Gusbcfg,
26894 grstctl: Grstctl,
26895 gintsts: Gintsts,
26896 gintmsk: Gintmsk,
26897 grxstsrd: Grxstsrd,
26898 grxstspd: Grxstspd,
26899 grxfsiz: Grxfsiz,
26900 gnptxfsiz: Gnptxfsiz,
26901 gnptxsts: Gnptxsts,
26902 gi2cctl: Gi2cctl,
26903 gpvndctl: Gpvndctl,
26904 ggpio: Ggpio,
26905 guid: Guid,
26906 gsnpsid: Gsnpsid,
26907 ghwcfg1: Ghwcfg1,
26908 ghwcfg2: Ghwcfg2,
26909 ghwcfg3: Ghwcfg3,
26910 ghwcfg4: Ghwcfg4,
26911 glpmcfg: Glpmcfg,
26912 gpwrdn: Gpwrdn,
26913 gdfifocfg: Gdfifocfg,
26914 gadpctl: Gadpctl,
26915 _reserved25: [u8; 0x9c],
26916 hptxfsiz: Hptxfsiz,
26917 _reserved26: [u8; 0x02fc],
26918 hcfg: Hcfg,
26919 hfir: Hfir,
26920 hfnum: Hfnum,
26921 _reserved29: [u8; 0x04],
26922 hptxsts: Hptxsts,
26923 haint: Haint,
26924 haintmsk: Haintmsk,
26925 _reserved32: [u8; 0x24],
26926 hprt: Hprt,
26927 _reserved33: [u8; 0x03bc],
26928 dcfg: Dcfg,
26929 dctl: Dctl,
26930 dsts: Dsts,
26931 _reserved36: [u8; 0x04],
26932 diepmsk: Diepmsk,
26933 doepmsk: Doepmsk,
26934 daint: Daint,
26935 daintmsk: Daintmsk,
26936 dtknqr1: Dtknqr1,
26937 dtknqr2: Dtknqr2,
26938 dvbusdis: Dvbusdis,
26939 dvbuspulse: Dvbuspulse,
26940 dthrctl: Dthrctl,
26941 dtknqr4: Dtknqr4,
26942 deachint: Deachint,
26943 deachintmsk: Deachintmsk,
26944 _reserved48: [u8; 0x05c0],
26945 pcgcctl: Pcgcctl,
26946 }
26947 impl RegisterBlock {
26948 #[doc = "0x00 - DOTG_GOTGCTL"]
26949 #[inline(always)]
26950 pub const fn gotgctl(&self) -> &Gotgctl {
26951 &self.gotgctl
26952 }
26953 #[doc = "0x04 - DOTG_GOTGINT"]
26954 #[inline(always)]
26955 pub const fn gotgint(&self) -> &Gotgint {
26956 &self.gotgint
26957 }
26958 #[doc = "0x08 - DOTG_GAHBCFG"]
26959 #[inline(always)]
26960 pub const fn gahbcfg(&self) -> &Gahbcfg {
26961 &self.gahbcfg
26962 }
26963 #[doc = "0x0c - DOTG_GUSBCFG"]
26964 #[inline(always)]
26965 pub const fn gusbcfg(&self) -> &Gusbcfg {
26966 &self.gusbcfg
26967 }
26968 #[doc = "0x10 - DOTG_GRSTCTL"]
26969 #[inline(always)]
26970 pub const fn grstctl(&self) -> &Grstctl {
26971 &self.grstctl
26972 }
26973 #[doc = "0x14 - DOTG_GINTSTS"]
26974 #[inline(always)]
26975 pub const fn gintsts(&self) -> &Gintsts {
26976 &self.gintsts
26977 }
26978 #[doc = "0x18 - DOTG_GINTMSK"]
26979 #[inline(always)]
26980 pub const fn gintmsk(&self) -> &Gintmsk {
26981 &self.gintmsk
26982 }
26983 #[doc = "0x1c - DOTG_GRXSTSRD"]
26984 #[inline(always)]
26985 pub const fn grxstsrd(&self) -> &Grxstsrd {
26986 &self.grxstsrd
26987 }
26988 #[doc = "0x20 - DOTG_GRXSTSPD"]
26989 #[inline(always)]
26990 pub const fn grxstspd(&self) -> &Grxstspd {
26991 &self.grxstspd
26992 }
26993 #[doc = "0x24 - DOTG_GRXFSIZ"]
26994 #[inline(always)]
26995 pub const fn grxfsiz(&self) -> &Grxfsiz {
26996 &self.grxfsiz
26997 }
26998 #[doc = "0x28 - DOTG_GNPTXFSIZ"]
26999 #[inline(always)]
27000 pub const fn gnptxfsiz(&self) -> &Gnptxfsiz {
27001 &self.gnptxfsiz
27002 }
27003 #[doc = "0x2c - DOTG_GNPTXSTS"]
27004 #[inline(always)]
27005 pub const fn gnptxsts(&self) -> &Gnptxsts {
27006 &self.gnptxsts
27007 }
27008 #[doc = "0x30 - DOTG_GI2CCTL"]
27009 #[inline(always)]
27010 pub const fn gi2cctl(&self) -> &Gi2cctl {
27011 &self.gi2cctl
27012 }
27013 #[doc = "0x34 - DOTG_GPVNDCTL"]
27014 #[inline(always)]
27015 pub const fn gpvndctl(&self) -> &Gpvndctl {
27016 &self.gpvndctl
27017 }
27018 #[doc = "0x38 - DOTG_GGPIO"]
27019 #[inline(always)]
27020 pub const fn ggpio(&self) -> &Ggpio {
27021 &self.ggpio
27022 }
27023 #[doc = "0x3c - DOTG_GUID"]
27024 #[inline(always)]
27025 pub const fn guid(&self) -> &Guid {
27026 &self.guid
27027 }
27028 #[doc = "0x40 - DOTG_GSNPSID"]
27029 #[inline(always)]
27030 pub const fn gsnpsid(&self) -> &Gsnpsid {
27031 &self.gsnpsid
27032 }
27033 #[doc = "0x44 - DOTG_GHWCFG1"]
27034 #[inline(always)]
27035 pub const fn ghwcfg1(&self) -> &Ghwcfg1 {
27036 &self.ghwcfg1
27037 }
27038 #[doc = "0x48 - DOTG_GHWCFG2"]
27039 #[inline(always)]
27040 pub const fn ghwcfg2(&self) -> &Ghwcfg2 {
27041 &self.ghwcfg2
27042 }
27043 #[doc = "0x4c - DOTG_GHWCFG3"]
27044 #[inline(always)]
27045 pub const fn ghwcfg3(&self) -> &Ghwcfg3 {
27046 &self.ghwcfg3
27047 }
27048 #[doc = "0x50 - DOTG_GHWCFG4"]
27049 #[inline(always)]
27050 pub const fn ghwcfg4(&self) -> &Ghwcfg4 {
27051 &self.ghwcfg4
27052 }
27053 #[doc = "0x54 - DOTG_GLPMCFG"]
27054 #[inline(always)]
27055 pub const fn glpmcfg(&self) -> &Glpmcfg {
27056 &self.glpmcfg
27057 }
27058 #[doc = "0x58 - DOTG_GPWRDN"]
27059 #[inline(always)]
27060 pub const fn gpwrdn(&self) -> &Gpwrdn {
27061 &self.gpwrdn
27062 }
27063 #[doc = "0x5c - DOTG_GDFIFOCFG"]
27064 #[inline(always)]
27065 pub const fn gdfifocfg(&self) -> &Gdfifocfg {
27066 &self.gdfifocfg
27067 }
27068 #[doc = "0x60 - DOTG_GADPCTL"]
27069 #[inline(always)]
27070 pub const fn gadpctl(&self) -> &Gadpctl {
27071 &self.gadpctl
27072 }
27073 #[doc = "0x100 - DOTG_HPTXFSIZ"]
27074 #[inline(always)]
27075 pub const fn hptxfsiz(&self) -> &Hptxfsiz {
27076 &self.hptxfsiz
27077 }
27078 #[doc = "0x400 - DOTG_HCFG"]
27079 #[inline(always)]
27080 pub const fn hcfg(&self) -> &Hcfg {
27081 &self.hcfg
27082 }
27083 #[doc = "0x404 - DOTG_HFIR"]
27084 #[inline(always)]
27085 pub const fn hfir(&self) -> &Hfir {
27086 &self.hfir
27087 }
27088 #[doc = "0x408 - DOTG_HFNUM"]
27089 #[inline(always)]
27090 pub const fn hfnum(&self) -> &Hfnum {
27091 &self.hfnum
27092 }
27093 #[doc = "0x410 - DOTG_HPTXSTS"]
27094 #[inline(always)]
27095 pub const fn hptxsts(&self) -> &Hptxsts {
27096 &self.hptxsts
27097 }
27098 #[doc = "0x414 - DOTG_HAINT"]
27099 #[inline(always)]
27100 pub const fn haint(&self) -> &Haint {
27101 &self.haint
27102 }
27103 #[doc = "0x418 - DOTG_HAINTMSK"]
27104 #[inline(always)]
27105 pub const fn haintmsk(&self) -> &Haintmsk {
27106 &self.haintmsk
27107 }
27108 #[doc = "0x440 - DOTG_HPRT"]
27109 #[inline(always)]
27110 pub const fn hprt(&self) -> &Hprt {
27111 &self.hprt
27112 }
27113 #[doc = "0x800 - DOTG_DCFG"]
27114 #[inline(always)]
27115 pub const fn dcfg(&self) -> &Dcfg {
27116 &self.dcfg
27117 }
27118 #[doc = "0x804 - DOTG_DCTL"]
27119 #[inline(always)]
27120 pub const fn dctl(&self) -> &Dctl {
27121 &self.dctl
27122 }
27123 #[doc = "0x808 - DOTG_DSTS"]
27124 #[inline(always)]
27125 pub const fn dsts(&self) -> &Dsts {
27126 &self.dsts
27127 }
27128 #[doc = "0x810 - DOTG_DIEPMSK"]
27129 #[inline(always)]
27130 pub const fn diepmsk(&self) -> &Diepmsk {
27131 &self.diepmsk
27132 }
27133 #[doc = "0x814 - DOTG_DOEPMSK"]
27134 #[inline(always)]
27135 pub const fn doepmsk(&self) -> &Doepmsk {
27136 &self.doepmsk
27137 }
27138 #[doc = "0x818 - DOTG_DAINT"]
27139 #[inline(always)]
27140 pub const fn daint(&self) -> &Daint {
27141 &self.daint
27142 }
27143 #[doc = "0x81c - DOTG_DAINTMSK"]
27144 #[inline(always)]
27145 pub const fn daintmsk(&self) -> &Daintmsk {
27146 &self.daintmsk
27147 }
27148 #[doc = "0x820 - DOTG_DTKNQR1"]
27149 #[inline(always)]
27150 pub const fn dtknqr1(&self) -> &Dtknqr1 {
27151 &self.dtknqr1
27152 }
27153 #[doc = "0x824 - DOTG_DTKNQR2"]
27154 #[inline(always)]
27155 pub const fn dtknqr2(&self) -> &Dtknqr2 {
27156 &self.dtknqr2
27157 }
27158 #[doc = "0x828 - DOTG_DVBUSDIS"]
27159 #[inline(always)]
27160 pub const fn dvbusdis(&self) -> &Dvbusdis {
27161 &self.dvbusdis
27162 }
27163 #[doc = "0x82c - DOTG_DVBUSPULSE"]
27164 #[inline(always)]
27165 pub const fn dvbuspulse(&self) -> &Dvbuspulse {
27166 &self.dvbuspulse
27167 }
27168 #[doc = "0x830 - DOTG_DTHRCTL"]
27169 #[inline(always)]
27170 pub const fn dthrctl(&self) -> &Dthrctl {
27171 &self.dthrctl
27172 }
27173 #[doc = "0x834 - DOTG_DTKNQR4"]
27174 #[inline(always)]
27175 pub const fn dtknqr4(&self) -> &Dtknqr4 {
27176 &self.dtknqr4
27177 }
27178 #[doc = "0x838 - DOTG_DEACHINT"]
27179 #[inline(always)]
27180 pub const fn deachint(&self) -> &Deachint {
27181 &self.deachint
27182 }
27183 #[doc = "0x83c - DOTG_DEACHINTMSK"]
27184 #[inline(always)]
27185 pub const fn deachintmsk(&self) -> &Deachintmsk {
27186 &self.deachintmsk
27187 }
27188 #[doc = "0xe00 - DOTG_PCGCCTL"]
27189 #[inline(always)]
27190 pub const fn pcgcctl(&self) -> &Pcgcctl {
27191 &self.pcgcctl
27192 }
27193 }
27194 #[doc = "GOTGCTL (rw) register accessor: DOTG_GOTGCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gotgctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgctl`] module"]
27195 #[doc(alias = "GOTGCTL")]
27196 pub type Gotgctl = crate::Reg<gotgctl::GotgctlSpec>;
27197 #[doc = "DOTG_GOTGCTL"]
27198 pub mod gotgctl {
27199 #[doc = "Register `GOTGCTL` reader"]
27200 pub type R = crate::R<GotgctlSpec>;
27201 #[doc = "Register `GOTGCTL` writer"]
27202 pub type W = crate::W<GotgctlSpec>;
27203 #[doc = "Field `SESREQSCS` reader - "]
27204 pub type SesreqscsR = crate::BitReader;
27205 #[doc = "Field `SESREQSCS` writer - "]
27206 pub type SesreqscsW<'a, REG> = crate::BitWriter<'a, REG>;
27207 #[doc = "Field `SESREQ` reader - "]
27208 pub type SesreqR = crate::BitReader;
27209 #[doc = "Field `SESREQ` writer - "]
27210 pub type SesreqW<'a, REG> = crate::BitWriter<'a, REG>;
27211 #[doc = "Field `SESENDDET` reader - "]
27212 pub type SesenddetR = crate::BitReader;
27213 #[doc = "Field `SESENDDET` writer - "]
27214 pub type SesenddetW<'a, REG> = crate::BitWriter<'a, REG>;
27215 #[doc = "Field `HSTNEGSCS` reader - "]
27216 pub type HstnegscsR = crate::BitReader;
27217 #[doc = "Field `HSTNEGSCS` writer - "]
27218 pub type HstnegscsW<'a, REG> = crate::BitWriter<'a, REG>;
27219 #[doc = "Field `HNPREQ` reader - "]
27220 pub type HnpreqR = crate::BitReader;
27221 #[doc = "Field `HNPREQ` writer - "]
27222 pub type HnpreqW<'a, REG> = crate::BitWriter<'a, REG>;
27223 #[doc = "Field `HSTSETHNPEN` reader - "]
27224 pub type HstsethnpenR = crate::BitReader;
27225 #[doc = "Field `HSTSETHNPEN` writer - "]
27226 pub type HstsethnpenW<'a, REG> = crate::BitWriter<'a, REG>;
27227 #[doc = "Field `DEVHNPEN` reader - "]
27228 pub type DevhnpenR = crate::BitReader;
27229 #[doc = "Field `DEVHNPEN` writer - "]
27230 pub type DevhnpenW<'a, REG> = crate::BitWriter<'a, REG>;
27231 #[doc = "Field `CONIDSTS` reader - "]
27232 pub type ConidstsR = crate::BitReader;
27233 #[doc = "Field `CONIDSTS` writer - "]
27234 pub type ConidstsW<'a, REG> = crate::BitWriter<'a, REG>;
27235 #[doc = "Field `DBNCTIME` reader - "]
27236 pub type DbnctimeR = crate::BitReader;
27237 #[doc = "Field `DBNCTIME` writer - "]
27238 pub type DbnctimeW<'a, REG> = crate::BitWriter<'a, REG>;
27239 #[doc = "Field `ASESVLD` reader - "]
27240 pub type AsesvldR = crate::BitReader;
27241 #[doc = "Field `ASESVLD` writer - "]
27242 pub type AsesvldW<'a, REG> = crate::BitWriter<'a, REG>;
27243 #[doc = "Field `BSESVLD` reader - "]
27244 pub type BsesvldR = crate::BitReader;
27245 #[doc = "Field `BSESVLD` writer - "]
27246 pub type BsesvldW<'a, REG> = crate::BitWriter<'a, REG>;
27247 #[doc = "Field `CHIRP_ON` reader - "]
27248 pub type ChirpOnR = crate::BitReader;
27249 #[doc = "Field `CHIRP_ON` writer - "]
27250 pub type ChirpOnW<'a, REG> = crate::BitWriter<'a, REG>;
27251 impl R {
27252 #[doc = "Bit 0"]
27253 #[inline(always)]
27254 pub fn sesreqscs(&self) -> SesreqscsR {
27255 SesreqscsR::new((self.bits & 1) != 0)
27256 }
27257 #[doc = "Bit 1"]
27258 #[inline(always)]
27259 pub fn sesreq(&self) -> SesreqR {
27260 SesreqR::new(((self.bits >> 1) & 1) != 0)
27261 }
27262 #[doc = "Bit 2"]
27263 #[inline(always)]
27264 pub fn sesenddet(&self) -> SesenddetR {
27265 SesenddetR::new(((self.bits >> 2) & 1) != 0)
27266 }
27267 #[doc = "Bit 8"]
27268 #[inline(always)]
27269 pub fn hstnegscs(&self) -> HstnegscsR {
27270 HstnegscsR::new(((self.bits >> 8) & 1) != 0)
27271 }
27272 #[doc = "Bit 9"]
27273 #[inline(always)]
27274 pub fn hnpreq(&self) -> HnpreqR {
27275 HnpreqR::new(((self.bits >> 9) & 1) != 0)
27276 }
27277 #[doc = "Bit 10"]
27278 #[inline(always)]
27279 pub fn hstsethnpen(&self) -> HstsethnpenR {
27280 HstsethnpenR::new(((self.bits >> 10) & 1) != 0)
27281 }
27282 #[doc = "Bit 11"]
27283 #[inline(always)]
27284 pub fn devhnpen(&self) -> DevhnpenR {
27285 DevhnpenR::new(((self.bits >> 11) & 1) != 0)
27286 }
27287 #[doc = "Bit 16"]
27288 #[inline(always)]
27289 pub fn conidsts(&self) -> ConidstsR {
27290 ConidstsR::new(((self.bits >> 16) & 1) != 0)
27291 }
27292 #[doc = "Bit 17"]
27293 #[inline(always)]
27294 pub fn dbnctime(&self) -> DbnctimeR {
27295 DbnctimeR::new(((self.bits >> 17) & 1) != 0)
27296 }
27297 #[doc = "Bit 18"]
27298 #[inline(always)]
27299 pub fn asesvld(&self) -> AsesvldR {
27300 AsesvldR::new(((self.bits >> 18) & 1) != 0)
27301 }
27302 #[doc = "Bit 19"]
27303 #[inline(always)]
27304 pub fn bsesvld(&self) -> BsesvldR {
27305 BsesvldR::new(((self.bits >> 19) & 1) != 0)
27306 }
27307 #[doc = "Bit 27"]
27308 #[inline(always)]
27309 pub fn chirp_on(&self) -> ChirpOnR {
27310 ChirpOnR::new(((self.bits >> 27) & 1) != 0)
27311 }
27312 }
27313 impl W {
27314 #[doc = "Bit 0"]
27315 #[inline(always)]
27316 pub fn sesreqscs(&mut self) -> SesreqscsW<'_, GotgctlSpec> {
27317 SesreqscsW::new(self, 0)
27318 }
27319 #[doc = "Bit 1"]
27320 #[inline(always)]
27321 pub fn sesreq(&mut self) -> SesreqW<'_, GotgctlSpec> {
27322 SesreqW::new(self, 1)
27323 }
27324 #[doc = "Bit 2"]
27325 #[inline(always)]
27326 pub fn sesenddet(&mut self) -> SesenddetW<'_, GotgctlSpec> {
27327 SesenddetW::new(self, 2)
27328 }
27329 #[doc = "Bit 8"]
27330 #[inline(always)]
27331 pub fn hstnegscs(&mut self) -> HstnegscsW<'_, GotgctlSpec> {
27332 HstnegscsW::new(self, 8)
27333 }
27334 #[doc = "Bit 9"]
27335 #[inline(always)]
27336 pub fn hnpreq(&mut self) -> HnpreqW<'_, GotgctlSpec> {
27337 HnpreqW::new(self, 9)
27338 }
27339 #[doc = "Bit 10"]
27340 #[inline(always)]
27341 pub fn hstsethnpen(&mut self) -> HstsethnpenW<'_, GotgctlSpec> {
27342 HstsethnpenW::new(self, 10)
27343 }
27344 #[doc = "Bit 11"]
27345 #[inline(always)]
27346 pub fn devhnpen(&mut self) -> DevhnpenW<'_, GotgctlSpec> {
27347 DevhnpenW::new(self, 11)
27348 }
27349 #[doc = "Bit 16"]
27350 #[inline(always)]
27351 pub fn conidsts(&mut self) -> ConidstsW<'_, GotgctlSpec> {
27352 ConidstsW::new(self, 16)
27353 }
27354 #[doc = "Bit 17"]
27355 #[inline(always)]
27356 pub fn dbnctime(&mut self) -> DbnctimeW<'_, GotgctlSpec> {
27357 DbnctimeW::new(self, 17)
27358 }
27359 #[doc = "Bit 18"]
27360 #[inline(always)]
27361 pub fn asesvld(&mut self) -> AsesvldW<'_, GotgctlSpec> {
27362 AsesvldW::new(self, 18)
27363 }
27364 #[doc = "Bit 19"]
27365 #[inline(always)]
27366 pub fn bsesvld(&mut self) -> BsesvldW<'_, GotgctlSpec> {
27367 BsesvldW::new(self, 19)
27368 }
27369 #[doc = "Bit 27"]
27370 #[inline(always)]
27371 pub fn chirp_on(&mut self) -> ChirpOnW<'_, GotgctlSpec> {
27372 ChirpOnW::new(self, 27)
27373 }
27374 }
27375 #[doc = "DOTG_GOTGCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gotgctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27376 pub struct GotgctlSpec;
27377 impl crate::RegisterSpec for GotgctlSpec {
27378 type Ux = u32;
27379 }
27380 #[doc = "`read()` method returns [`gotgctl::R`](R) reader structure"]
27381 impl crate::Readable for GotgctlSpec {}
27382 #[doc = "`write(|w| ..)` method takes [`gotgctl::W`](W) writer structure"]
27383 impl crate::Writable for GotgctlSpec {
27384 type Safety = crate::Unsafe;
27385 }
27386 #[doc = "`reset()` method sets GOTGCTL to value 0"]
27387 impl crate::Resettable for GotgctlSpec {}
27388 }
27389 #[doc = "GOTGINT (rw) register accessor: DOTG_GOTGINT\n\nYou can [`read`](crate::Reg::read) this register and get [`gotgint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgint`] module"]
27390 #[doc(alias = "GOTGINT")]
27391 pub type Gotgint = crate::Reg<gotgint::GotgintSpec>;
27392 #[doc = "DOTG_GOTGINT"]
27393 pub mod gotgint {
27394 #[doc = "Register `GOTGINT` reader"]
27395 pub type R = crate::R<GotgintSpec>;
27396 #[doc = "Register `GOTGINT` writer"]
27397 pub type W = crate::W<GotgintSpec>;
27398 impl core::fmt::Debug for R {
27399 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27400 write!(f, "{}", self.bits())
27401 }
27402 }
27403 impl W {}
27404 #[doc = "DOTG_GOTGINT\n\nYou can [`read`](crate::Reg::read) this register and get [`gotgint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27405 pub struct GotgintSpec;
27406 impl crate::RegisterSpec for GotgintSpec {
27407 type Ux = u32;
27408 }
27409 #[doc = "`read()` method returns [`gotgint::R`](R) reader structure"]
27410 impl crate::Readable for GotgintSpec {}
27411 #[doc = "`write(|w| ..)` method takes [`gotgint::W`](W) writer structure"]
27412 impl crate::Writable for GotgintSpec {
27413 type Safety = crate::Unsafe;
27414 }
27415 #[doc = "`reset()` method sets GOTGINT to value 0"]
27416 impl crate::Resettable for GotgintSpec {}
27417 }
27418 #[doc = "GAHBCFG (rw) register accessor: DOTG_GAHBCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gahbcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gahbcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gahbcfg`] module"]
27419 #[doc(alias = "GAHBCFG")]
27420 pub type Gahbcfg = crate::Reg<gahbcfg::GahbcfgSpec>;
27421 #[doc = "DOTG_GAHBCFG"]
27422 pub mod gahbcfg {
27423 #[doc = "Register `GAHBCFG` reader"]
27424 pub type R = crate::R<GahbcfgSpec>;
27425 #[doc = "Register `GAHBCFG` writer"]
27426 pub type W = crate::W<GahbcfgSpec>;
27427 #[doc = "Field `GLBLINTRMSK` reader - "]
27428 pub type GlblintrmskR = crate::BitReader;
27429 #[doc = "Field `GLBLINTRMSK` writer - "]
27430 pub type GlblintrmskW<'a, REG> = crate::BitWriter<'a, REG>;
27431 #[doc = "Field `HBSTLEN` reader - "]
27432 pub type HbstlenR = crate::FieldReader;
27433 #[doc = "Field `HBSTLEN` writer - "]
27434 pub type HbstlenW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
27435 #[doc = "Field `DMAEN` reader - "]
27436 pub type DmaenR = crate::BitReader;
27437 #[doc = "Field `DMAEN` writer - "]
27438 pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
27439 #[doc = "Field `NPTXFEMPLVL` reader - "]
27440 pub type NptxfemplvlR = crate::BitReader;
27441 #[doc = "Field `NPTXFEMPLVL` writer - "]
27442 pub type NptxfemplvlW<'a, REG> = crate::BitWriter<'a, REG>;
27443 #[doc = "Field `PTXFEMPLVL` reader - "]
27444 pub type PtxfemplvlR = crate::BitReader;
27445 #[doc = "Field `PTXFEMPLVL` writer - "]
27446 pub type PtxfemplvlW<'a, REG> = crate::BitWriter<'a, REG>;
27447 impl R {
27448 #[doc = "Bit 0"]
27449 #[inline(always)]
27450 pub fn glblintrmsk(&self) -> GlblintrmskR {
27451 GlblintrmskR::new((self.bits & 1) != 0)
27452 }
27453 #[doc = "Bits 1:4"]
27454 #[inline(always)]
27455 pub fn hbstlen(&self) -> HbstlenR {
27456 HbstlenR::new(((self.bits >> 1) & 0x0f) as u8)
27457 }
27458 #[doc = "Bit 5"]
27459 #[inline(always)]
27460 pub fn dmaen(&self) -> DmaenR {
27461 DmaenR::new(((self.bits >> 5) & 1) != 0)
27462 }
27463 #[doc = "Bit 7"]
27464 #[inline(always)]
27465 pub fn nptxfemplvl(&self) -> NptxfemplvlR {
27466 NptxfemplvlR::new(((self.bits >> 7) & 1) != 0)
27467 }
27468 #[doc = "Bit 8"]
27469 #[inline(always)]
27470 pub fn ptxfemplvl(&self) -> PtxfemplvlR {
27471 PtxfemplvlR::new(((self.bits >> 8) & 1) != 0)
27472 }
27473 }
27474 impl W {
27475 #[doc = "Bit 0"]
27476 #[inline(always)]
27477 pub fn glblintrmsk(&mut self) -> GlblintrmskW<'_, GahbcfgSpec> {
27478 GlblintrmskW::new(self, 0)
27479 }
27480 #[doc = "Bits 1:4"]
27481 #[inline(always)]
27482 pub fn hbstlen(&mut self) -> HbstlenW<'_, GahbcfgSpec> {
27483 HbstlenW::new(self, 1)
27484 }
27485 #[doc = "Bit 5"]
27486 #[inline(always)]
27487 pub fn dmaen(&mut self) -> DmaenW<'_, GahbcfgSpec> {
27488 DmaenW::new(self, 5)
27489 }
27490 #[doc = "Bit 7"]
27491 #[inline(always)]
27492 pub fn nptxfemplvl(&mut self) -> NptxfemplvlW<'_, GahbcfgSpec> {
27493 NptxfemplvlW::new(self, 7)
27494 }
27495 #[doc = "Bit 8"]
27496 #[inline(always)]
27497 pub fn ptxfemplvl(&mut self) -> PtxfemplvlW<'_, GahbcfgSpec> {
27498 PtxfemplvlW::new(self, 8)
27499 }
27500 }
27501 #[doc = "DOTG_GAHBCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gahbcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gahbcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27502 pub struct GahbcfgSpec;
27503 impl crate::RegisterSpec for GahbcfgSpec {
27504 type Ux = u32;
27505 }
27506 #[doc = "`read()` method returns [`gahbcfg::R`](R) reader structure"]
27507 impl crate::Readable for GahbcfgSpec {}
27508 #[doc = "`write(|w| ..)` method takes [`gahbcfg::W`](W) writer structure"]
27509 impl crate::Writable for GahbcfgSpec {
27510 type Safety = crate::Unsafe;
27511 }
27512 #[doc = "`reset()` method sets GAHBCFG to value 0"]
27513 impl crate::Resettable for GahbcfgSpec {}
27514 }
27515 #[doc = "GUSBCFG (rw) register accessor: DOTG_GUSBCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gusbcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gusbcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gusbcfg`] module"]
27516 #[doc(alias = "GUSBCFG")]
27517 pub type Gusbcfg = crate::Reg<gusbcfg::GusbcfgSpec>;
27518 #[doc = "DOTG_GUSBCFG"]
27519 pub mod gusbcfg {
27520 #[doc = "Register `GUSBCFG` reader"]
27521 pub type R = crate::R<GusbcfgSpec>;
27522 #[doc = "Register `GUSBCFG` writer"]
27523 pub type W = crate::W<GusbcfgSpec>;
27524 #[doc = "Field `TOUTCAL` reader - "]
27525 pub type ToutcalR = crate::FieldReader;
27526 #[doc = "Field `TOUTCAL` writer - "]
27527 pub type ToutcalW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
27528 #[doc = "Field `PHYIF` reader - "]
27529 pub type PhyifR = crate::BitReader;
27530 #[doc = "Field `PHYIF` writer - "]
27531 pub type PhyifW<'a, REG> = crate::BitWriter<'a, REG>;
27532 #[doc = "Field `ULPI_UTMI_SEL` reader - "]
27533 pub type UlpiUtmiSelR = crate::BitReader;
27534 #[doc = "Field `ULPI_UTMI_SEL` writer - "]
27535 pub type UlpiUtmiSelW<'a, REG> = crate::BitWriter<'a, REG>;
27536 #[doc = "Field `FSINTF` reader - "]
27537 pub type FsintfR = crate::BitReader;
27538 #[doc = "Field `FSINTF` writer - "]
27539 pub type FsintfW<'a, REG> = crate::BitWriter<'a, REG>;
27540 #[doc = "Field `PHYSEL` reader - "]
27541 pub type PhyselR = crate::BitReader;
27542 #[doc = "Field `PHYSEL` writer - "]
27543 pub type PhyselW<'a, REG> = crate::BitWriter<'a, REG>;
27544 #[doc = "Field `DDRSEL` reader - "]
27545 pub type DdrselR = crate::BitReader;
27546 #[doc = "Field `DDRSEL` writer - "]
27547 pub type DdrselW<'a, REG> = crate::BitWriter<'a, REG>;
27548 #[doc = "Field `SRPCAP` reader - "]
27549 pub type SrpcapR = crate::BitReader;
27550 #[doc = "Field `SRPCAP` writer - "]
27551 pub type SrpcapW<'a, REG> = crate::BitWriter<'a, REG>;
27552 #[doc = "Field `HNPCAP` reader - "]
27553 pub type HnpcapR = crate::BitReader;
27554 #[doc = "Field `HNPCAP` writer - "]
27555 pub type HnpcapW<'a, REG> = crate::BitWriter<'a, REG>;
27556 #[doc = "Field `USBTRDTIM` reader - "]
27557 pub type UsbtrdtimR = crate::FieldReader;
27558 #[doc = "Field `USBTRDTIM` writer - "]
27559 pub type UsbtrdtimW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
27560 #[doc = "Field `PHYLPWRCLKSEL` reader - "]
27561 pub type PhylpwrclkselR = crate::BitReader;
27562 #[doc = "Field `PHYLPWRCLKSEL` writer - "]
27563 pub type PhylpwrclkselW<'a, REG> = crate::BitWriter<'a, REG>;
27564 #[doc = "Field `OTGI2CSEL` reader - "]
27565 pub type Otgi2cselR = crate::BitReader;
27566 #[doc = "Field `OTGI2CSEL` writer - "]
27567 pub type Otgi2cselW<'a, REG> = crate::BitWriter<'a, REG>;
27568 #[doc = "Field `ULPIFSLS` reader - "]
27569 pub type UlpifslsR = crate::BitReader;
27570 #[doc = "Field `ULPIFSLS` writer - "]
27571 pub type UlpifslsW<'a, REG> = crate::BitWriter<'a, REG>;
27572 #[doc = "Field `ULPIAUTORES` reader - "]
27573 pub type UlpiautoresR = crate::BitReader;
27574 #[doc = "Field `ULPIAUTORES` writer - "]
27575 pub type UlpiautoresW<'a, REG> = crate::BitWriter<'a, REG>;
27576 #[doc = "Field `ULPICLKSUSM` reader - "]
27577 pub type UlpiclksusmR = crate::BitReader;
27578 #[doc = "Field `ULPICLKSUSM` writer - "]
27579 pub type UlpiclksusmW<'a, REG> = crate::BitWriter<'a, REG>;
27580 #[doc = "Field `ULPIEXTVBUSDRV` reader - "]
27581 pub type UlpiextvbusdrvR = crate::BitReader;
27582 #[doc = "Field `ULPIEXTVBUSDRV` writer - "]
27583 pub type UlpiextvbusdrvW<'a, REG> = crate::BitWriter<'a, REG>;
27584 #[doc = "Field `ULPIEXTVBUSINDICATOR` reader - "]
27585 pub type UlpiextvbusindicatorR = crate::BitReader;
27586 #[doc = "Field `ULPIEXTVBUSINDICATOR` writer - "]
27587 pub type UlpiextvbusindicatorW<'a, REG> = crate::BitWriter<'a, REG>;
27588 #[doc = "Field `TERMSELDLPULSE` reader - "]
27589 pub type TermseldlpulseR = crate::BitReader;
27590 #[doc = "Field `TERMSELDLPULSE` writer - "]
27591 pub type TermseldlpulseW<'a, REG> = crate::BitWriter<'a, REG>;
27592 #[doc = "Field `IC_USB_CAP` reader - "]
27593 pub type IcUsbCapR = crate::BitReader;
27594 #[doc = "Field `IC_USB_CAP` writer - "]
27595 pub type IcUsbCapW<'a, REG> = crate::BitWriter<'a, REG>;
27596 #[doc = "Field `NO_PULLUP` reader - "]
27597 pub type NoPullupR = crate::BitReader;
27598 #[doc = "Field `NO_PULLUP` writer - "]
27599 pub type NoPullupW<'a, REG> = crate::BitWriter<'a, REG>;
27600 #[doc = "Field `FORCEHOSTMODE` reader - "]
27601 pub type ForcehostmodeR = crate::BitReader;
27602 #[doc = "Field `FORCEHOSTMODE` writer - "]
27603 pub type ForcehostmodeW<'a, REG> = crate::BitWriter<'a, REG>;
27604 #[doc = "Field `FORCEDEVMODE` reader - "]
27605 pub type ForcedevmodeR = crate::BitReader;
27606 #[doc = "Field `FORCEDEVMODE` writer - "]
27607 pub type ForcedevmodeW<'a, REG> = crate::BitWriter<'a, REG>;
27608 #[doc = "Field `CORRUPTTXPACKET` reader - "]
27609 pub type CorrupttxpacketR = crate::BitReader;
27610 #[doc = "Field `CORRUPTTXPACKET` writer - "]
27611 pub type CorrupttxpacketW<'a, REG> = crate::BitWriter<'a, REG>;
27612 impl R {
27613 #[doc = "Bits 0:2"]
27614 #[inline(always)]
27615 pub fn toutcal(&self) -> ToutcalR {
27616 ToutcalR::new((self.bits & 7) as u8)
27617 }
27618 #[doc = "Bit 3"]
27619 #[inline(always)]
27620 pub fn phyif(&self) -> PhyifR {
27621 PhyifR::new(((self.bits >> 3) & 1) != 0)
27622 }
27623 #[doc = "Bit 4"]
27624 #[inline(always)]
27625 pub fn ulpi_utmi_sel(&self) -> UlpiUtmiSelR {
27626 UlpiUtmiSelR::new(((self.bits >> 4) & 1) != 0)
27627 }
27628 #[doc = "Bit 5"]
27629 #[inline(always)]
27630 pub fn fsintf(&self) -> FsintfR {
27631 FsintfR::new(((self.bits >> 5) & 1) != 0)
27632 }
27633 #[doc = "Bit 6"]
27634 #[inline(always)]
27635 pub fn physel(&self) -> PhyselR {
27636 PhyselR::new(((self.bits >> 6) & 1) != 0)
27637 }
27638 #[doc = "Bit 7"]
27639 #[inline(always)]
27640 pub fn ddrsel(&self) -> DdrselR {
27641 DdrselR::new(((self.bits >> 7) & 1) != 0)
27642 }
27643 #[doc = "Bit 8"]
27644 #[inline(always)]
27645 pub fn srpcap(&self) -> SrpcapR {
27646 SrpcapR::new(((self.bits >> 8) & 1) != 0)
27647 }
27648 #[doc = "Bit 9"]
27649 #[inline(always)]
27650 pub fn hnpcap(&self) -> HnpcapR {
27651 HnpcapR::new(((self.bits >> 9) & 1) != 0)
27652 }
27653 #[doc = "Bits 10:13"]
27654 #[inline(always)]
27655 pub fn usbtrdtim(&self) -> UsbtrdtimR {
27656 UsbtrdtimR::new(((self.bits >> 10) & 0x0f) as u8)
27657 }
27658 #[doc = "Bit 15"]
27659 #[inline(always)]
27660 pub fn phylpwrclksel(&self) -> PhylpwrclkselR {
27661 PhylpwrclkselR::new(((self.bits >> 15) & 1) != 0)
27662 }
27663 #[doc = "Bit 16"]
27664 #[inline(always)]
27665 pub fn otgi2csel(&self) -> Otgi2cselR {
27666 Otgi2cselR::new(((self.bits >> 16) & 1) != 0)
27667 }
27668 #[doc = "Bit 17"]
27669 #[inline(always)]
27670 pub fn ulpifsls(&self) -> UlpifslsR {
27671 UlpifslsR::new(((self.bits >> 17) & 1) != 0)
27672 }
27673 #[doc = "Bit 18"]
27674 #[inline(always)]
27675 pub fn ulpiautores(&self) -> UlpiautoresR {
27676 UlpiautoresR::new(((self.bits >> 18) & 1) != 0)
27677 }
27678 #[doc = "Bit 19"]
27679 #[inline(always)]
27680 pub fn ulpiclksusm(&self) -> UlpiclksusmR {
27681 UlpiclksusmR::new(((self.bits >> 19) & 1) != 0)
27682 }
27683 #[doc = "Bit 20"]
27684 #[inline(always)]
27685 pub fn ulpiextvbusdrv(&self) -> UlpiextvbusdrvR {
27686 UlpiextvbusdrvR::new(((self.bits >> 20) & 1) != 0)
27687 }
27688 #[doc = "Bit 21"]
27689 #[inline(always)]
27690 pub fn ulpiextvbusindicator(&self) -> UlpiextvbusindicatorR {
27691 UlpiextvbusindicatorR::new(((self.bits >> 21) & 1) != 0)
27692 }
27693 #[doc = "Bit 22"]
27694 #[inline(always)]
27695 pub fn termseldlpulse(&self) -> TermseldlpulseR {
27696 TermseldlpulseR::new(((self.bits >> 22) & 1) != 0)
27697 }
27698 #[doc = "Bit 26"]
27699 #[inline(always)]
27700 pub fn ic_usb_cap(&self) -> IcUsbCapR {
27701 IcUsbCapR::new(((self.bits >> 26) & 1) != 0)
27702 }
27703 #[doc = "Bit 27"]
27704 #[inline(always)]
27705 pub fn no_pullup(&self) -> NoPullupR {
27706 NoPullupR::new(((self.bits >> 27) & 1) != 0)
27707 }
27708 #[doc = "Bit 29"]
27709 #[inline(always)]
27710 pub fn forcehostmode(&self) -> ForcehostmodeR {
27711 ForcehostmodeR::new(((self.bits >> 29) & 1) != 0)
27712 }
27713 #[doc = "Bit 30"]
27714 #[inline(always)]
27715 pub fn forcedevmode(&self) -> ForcedevmodeR {
27716 ForcedevmodeR::new(((self.bits >> 30) & 1) != 0)
27717 }
27718 #[doc = "Bit 31"]
27719 #[inline(always)]
27720 pub fn corrupttxpacket(&self) -> CorrupttxpacketR {
27721 CorrupttxpacketR::new(((self.bits >> 31) & 1) != 0)
27722 }
27723 }
27724 impl W {
27725 #[doc = "Bits 0:2"]
27726 #[inline(always)]
27727 pub fn toutcal(&mut self) -> ToutcalW<'_, GusbcfgSpec> {
27728 ToutcalW::new(self, 0)
27729 }
27730 #[doc = "Bit 3"]
27731 #[inline(always)]
27732 pub fn phyif(&mut self) -> PhyifW<'_, GusbcfgSpec> {
27733 PhyifW::new(self, 3)
27734 }
27735 #[doc = "Bit 4"]
27736 #[inline(always)]
27737 pub fn ulpi_utmi_sel(&mut self) -> UlpiUtmiSelW<'_, GusbcfgSpec> {
27738 UlpiUtmiSelW::new(self, 4)
27739 }
27740 #[doc = "Bit 5"]
27741 #[inline(always)]
27742 pub fn fsintf(&mut self) -> FsintfW<'_, GusbcfgSpec> {
27743 FsintfW::new(self, 5)
27744 }
27745 #[doc = "Bit 6"]
27746 #[inline(always)]
27747 pub fn physel(&mut self) -> PhyselW<'_, GusbcfgSpec> {
27748 PhyselW::new(self, 6)
27749 }
27750 #[doc = "Bit 7"]
27751 #[inline(always)]
27752 pub fn ddrsel(&mut self) -> DdrselW<'_, GusbcfgSpec> {
27753 DdrselW::new(self, 7)
27754 }
27755 #[doc = "Bit 8"]
27756 #[inline(always)]
27757 pub fn srpcap(&mut self) -> SrpcapW<'_, GusbcfgSpec> {
27758 SrpcapW::new(self, 8)
27759 }
27760 #[doc = "Bit 9"]
27761 #[inline(always)]
27762 pub fn hnpcap(&mut self) -> HnpcapW<'_, GusbcfgSpec> {
27763 HnpcapW::new(self, 9)
27764 }
27765 #[doc = "Bits 10:13"]
27766 #[inline(always)]
27767 pub fn usbtrdtim(&mut self) -> UsbtrdtimW<'_, GusbcfgSpec> {
27768 UsbtrdtimW::new(self, 10)
27769 }
27770 #[doc = "Bit 15"]
27771 #[inline(always)]
27772 pub fn phylpwrclksel(&mut self) -> PhylpwrclkselW<'_, GusbcfgSpec> {
27773 PhylpwrclkselW::new(self, 15)
27774 }
27775 #[doc = "Bit 16"]
27776 #[inline(always)]
27777 pub fn otgi2csel(&mut self) -> Otgi2cselW<'_, GusbcfgSpec> {
27778 Otgi2cselW::new(self, 16)
27779 }
27780 #[doc = "Bit 17"]
27781 #[inline(always)]
27782 pub fn ulpifsls(&mut self) -> UlpifslsW<'_, GusbcfgSpec> {
27783 UlpifslsW::new(self, 17)
27784 }
27785 #[doc = "Bit 18"]
27786 #[inline(always)]
27787 pub fn ulpiautores(&mut self) -> UlpiautoresW<'_, GusbcfgSpec> {
27788 UlpiautoresW::new(self, 18)
27789 }
27790 #[doc = "Bit 19"]
27791 #[inline(always)]
27792 pub fn ulpiclksusm(&mut self) -> UlpiclksusmW<'_, GusbcfgSpec> {
27793 UlpiclksusmW::new(self, 19)
27794 }
27795 #[doc = "Bit 20"]
27796 #[inline(always)]
27797 pub fn ulpiextvbusdrv(&mut self) -> UlpiextvbusdrvW<'_, GusbcfgSpec> {
27798 UlpiextvbusdrvW::new(self, 20)
27799 }
27800 #[doc = "Bit 21"]
27801 #[inline(always)]
27802 pub fn ulpiextvbusindicator(&mut self) -> UlpiextvbusindicatorW<'_, GusbcfgSpec> {
27803 UlpiextvbusindicatorW::new(self, 21)
27804 }
27805 #[doc = "Bit 22"]
27806 #[inline(always)]
27807 pub fn termseldlpulse(&mut self) -> TermseldlpulseW<'_, GusbcfgSpec> {
27808 TermseldlpulseW::new(self, 22)
27809 }
27810 #[doc = "Bit 26"]
27811 #[inline(always)]
27812 pub fn ic_usb_cap(&mut self) -> IcUsbCapW<'_, GusbcfgSpec> {
27813 IcUsbCapW::new(self, 26)
27814 }
27815 #[doc = "Bit 27"]
27816 #[inline(always)]
27817 pub fn no_pullup(&mut self) -> NoPullupW<'_, GusbcfgSpec> {
27818 NoPullupW::new(self, 27)
27819 }
27820 #[doc = "Bit 29"]
27821 #[inline(always)]
27822 pub fn forcehostmode(&mut self) -> ForcehostmodeW<'_, GusbcfgSpec> {
27823 ForcehostmodeW::new(self, 29)
27824 }
27825 #[doc = "Bit 30"]
27826 #[inline(always)]
27827 pub fn forcedevmode(&mut self) -> ForcedevmodeW<'_, GusbcfgSpec> {
27828 ForcedevmodeW::new(self, 30)
27829 }
27830 #[doc = "Bit 31"]
27831 #[inline(always)]
27832 pub fn corrupttxpacket(&mut self) -> CorrupttxpacketW<'_, GusbcfgSpec> {
27833 CorrupttxpacketW::new(self, 31)
27834 }
27835 }
27836 #[doc = "DOTG_GUSBCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gusbcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gusbcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27837 pub struct GusbcfgSpec;
27838 impl crate::RegisterSpec for GusbcfgSpec {
27839 type Ux = u32;
27840 }
27841 #[doc = "`read()` method returns [`gusbcfg::R`](R) reader structure"]
27842 impl crate::Readable for GusbcfgSpec {}
27843 #[doc = "`write(|w| ..)` method takes [`gusbcfg::W`](W) writer structure"]
27844 impl crate::Writable for GusbcfgSpec {
27845 type Safety = crate::Unsafe;
27846 }
27847 #[doc = "`reset()` method sets GUSBCFG to value 0"]
27848 impl crate::Resettable for GusbcfgSpec {}
27849 }
27850 #[doc = "GRSTCTL (rw) register accessor: DOTG_GRSTCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`grstctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grstctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grstctl`] module"]
27851 #[doc(alias = "GRSTCTL")]
27852 pub type Grstctl = crate::Reg<grstctl::GrstctlSpec>;
27853 #[doc = "DOTG_GRSTCTL"]
27854 pub mod grstctl {
27855 #[doc = "Register `GRSTCTL` reader"]
27856 pub type R = crate::R<GrstctlSpec>;
27857 #[doc = "Register `GRSTCTL` writer"]
27858 pub type W = crate::W<GrstctlSpec>;
27859 #[doc = "Field `CSFTRST` reader - "]
27860 pub type CsftrstR = crate::BitReader;
27861 #[doc = "Field `CSFTRST` writer - "]
27862 pub type CsftrstW<'a, REG> = crate::BitWriter<'a, REG>;
27863 #[doc = "Field `HSFTRST` reader - "]
27864 pub type HsftrstR = crate::BitReader;
27865 #[doc = "Field `HSFTRST` writer - "]
27866 pub type HsftrstW<'a, REG> = crate::BitWriter<'a, REG>;
27867 #[doc = "Field `FRMCNTRRST` reader - "]
27868 pub type FrmcntrrstR = crate::BitReader;
27869 #[doc = "Field `FRMCNTRRST` writer - "]
27870 pub type FrmcntrrstW<'a, REG> = crate::BitWriter<'a, REG>;
27871 #[doc = "Field `INTKNQFLSH` reader - "]
27872 pub type IntknqflshR = crate::BitReader;
27873 #[doc = "Field `INTKNQFLSH` writer - "]
27874 pub type IntknqflshW<'a, REG> = crate::BitWriter<'a, REG>;
27875 #[doc = "Field `RXFFLSH` reader - "]
27876 pub type RxfflshR = crate::BitReader;
27877 #[doc = "Field `RXFFLSH` writer - "]
27878 pub type RxfflshW<'a, REG> = crate::BitWriter<'a, REG>;
27879 #[doc = "Field `TXFFLSH` reader - "]
27880 pub type TxfflshR = crate::BitReader;
27881 #[doc = "Field `TXFFLSH` writer - "]
27882 pub type TxfflshW<'a, REG> = crate::BitWriter<'a, REG>;
27883 #[doc = "Field `TXFNUM` reader - "]
27884 pub type TxfnumR = crate::FieldReader;
27885 #[doc = "Field `TXFNUM` writer - "]
27886 pub type TxfnumW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
27887 #[doc = "Field `DMAREQ` reader - "]
27888 pub type DmareqR = crate::BitReader;
27889 #[doc = "Field `DMAREQ` writer - "]
27890 pub type DmareqW<'a, REG> = crate::BitWriter<'a, REG>;
27891 #[doc = "Field `AHBIDLE` reader - "]
27892 pub type AhbidleR = crate::BitReader;
27893 #[doc = "Field `AHBIDLE` writer - "]
27894 pub type AhbidleW<'a, REG> = crate::BitWriter<'a, REG>;
27895 impl R {
27896 #[doc = "Bit 0"]
27897 #[inline(always)]
27898 pub fn csftrst(&self) -> CsftrstR {
27899 CsftrstR::new((self.bits & 1) != 0)
27900 }
27901 #[doc = "Bit 1"]
27902 #[inline(always)]
27903 pub fn hsftrst(&self) -> HsftrstR {
27904 HsftrstR::new(((self.bits >> 1) & 1) != 0)
27905 }
27906 #[doc = "Bit 2"]
27907 #[inline(always)]
27908 pub fn frmcntrrst(&self) -> FrmcntrrstR {
27909 FrmcntrrstR::new(((self.bits >> 2) & 1) != 0)
27910 }
27911 #[doc = "Bit 3"]
27912 #[inline(always)]
27913 pub fn intknqflsh(&self) -> IntknqflshR {
27914 IntknqflshR::new(((self.bits >> 3) & 1) != 0)
27915 }
27916 #[doc = "Bit 4"]
27917 #[inline(always)]
27918 pub fn rxfflsh(&self) -> RxfflshR {
27919 RxfflshR::new(((self.bits >> 4) & 1) != 0)
27920 }
27921 #[doc = "Bit 5"]
27922 #[inline(always)]
27923 pub fn txfflsh(&self) -> TxfflshR {
27924 TxfflshR::new(((self.bits >> 5) & 1) != 0)
27925 }
27926 #[doc = "Bits 6:10"]
27927 #[inline(always)]
27928 pub fn txfnum(&self) -> TxfnumR {
27929 TxfnumR::new(((self.bits >> 6) & 0x1f) as u8)
27930 }
27931 #[doc = "Bit 30"]
27932 #[inline(always)]
27933 pub fn dmareq(&self) -> DmareqR {
27934 DmareqR::new(((self.bits >> 30) & 1) != 0)
27935 }
27936 #[doc = "Bit 31"]
27937 #[inline(always)]
27938 pub fn ahbidle(&self) -> AhbidleR {
27939 AhbidleR::new(((self.bits >> 31) & 1) != 0)
27940 }
27941 }
27942 impl W {
27943 #[doc = "Bit 0"]
27944 #[inline(always)]
27945 pub fn csftrst(&mut self) -> CsftrstW<'_, GrstctlSpec> {
27946 CsftrstW::new(self, 0)
27947 }
27948 #[doc = "Bit 1"]
27949 #[inline(always)]
27950 pub fn hsftrst(&mut self) -> HsftrstW<'_, GrstctlSpec> {
27951 HsftrstW::new(self, 1)
27952 }
27953 #[doc = "Bit 2"]
27954 #[inline(always)]
27955 pub fn frmcntrrst(&mut self) -> FrmcntrrstW<'_, GrstctlSpec> {
27956 FrmcntrrstW::new(self, 2)
27957 }
27958 #[doc = "Bit 3"]
27959 #[inline(always)]
27960 pub fn intknqflsh(&mut self) -> IntknqflshW<'_, GrstctlSpec> {
27961 IntknqflshW::new(self, 3)
27962 }
27963 #[doc = "Bit 4"]
27964 #[inline(always)]
27965 pub fn rxfflsh(&mut self) -> RxfflshW<'_, GrstctlSpec> {
27966 RxfflshW::new(self, 4)
27967 }
27968 #[doc = "Bit 5"]
27969 #[inline(always)]
27970 pub fn txfflsh(&mut self) -> TxfflshW<'_, GrstctlSpec> {
27971 TxfflshW::new(self, 5)
27972 }
27973 #[doc = "Bits 6:10"]
27974 #[inline(always)]
27975 pub fn txfnum(&mut self) -> TxfnumW<'_, GrstctlSpec> {
27976 TxfnumW::new(self, 6)
27977 }
27978 #[doc = "Bit 30"]
27979 #[inline(always)]
27980 pub fn dmareq(&mut self) -> DmareqW<'_, GrstctlSpec> {
27981 DmareqW::new(self, 30)
27982 }
27983 #[doc = "Bit 31"]
27984 #[inline(always)]
27985 pub fn ahbidle(&mut self) -> AhbidleW<'_, GrstctlSpec> {
27986 AhbidleW::new(self, 31)
27987 }
27988 }
27989 #[doc = "DOTG_GRSTCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`grstctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grstctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27990 pub struct GrstctlSpec;
27991 impl crate::RegisterSpec for GrstctlSpec {
27992 type Ux = u32;
27993 }
27994 #[doc = "`read()` method returns [`grstctl::R`](R) reader structure"]
27995 impl crate::Readable for GrstctlSpec {}
27996 #[doc = "`write(|w| ..)` method takes [`grstctl::W`](W) writer structure"]
27997 impl crate::Writable for GrstctlSpec {
27998 type Safety = crate::Unsafe;
27999 }
28000 #[doc = "`reset()` method sets GRSTCTL to value 0"]
28001 impl crate::Resettable for GrstctlSpec {}
28002 }
28003 #[doc = "GINTSTS (rw) register accessor: DOTG_GINTSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`gintsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintsts`] module"]
28004 #[doc(alias = "GINTSTS")]
28005 pub type Gintsts = crate::Reg<gintsts::GintstsSpec>;
28006 #[doc = "DOTG_GINTSTS"]
28007 pub mod gintsts {
28008 #[doc = "Register `GINTSTS` reader"]
28009 pub type R = crate::R<GintstsSpec>;
28010 #[doc = "Register `GINTSTS` writer"]
28011 pub type W = crate::W<GintstsSpec>;
28012 #[doc = "Field `CURMOD` reader - "]
28013 pub type CurmodR = crate::BitReader;
28014 #[doc = "Field `CURMOD` writer - "]
28015 pub type CurmodW<'a, REG> = crate::BitWriter<'a, REG>;
28016 #[doc = "Field `MODEMIS` reader - "]
28017 pub type ModemisR = crate::BitReader;
28018 #[doc = "Field `MODEMIS` writer - "]
28019 pub type ModemisW<'a, REG> = crate::BitWriter<'a, REG>;
28020 #[doc = "Field `OTGINT` reader - "]
28021 pub type OtgintR = crate::BitReader;
28022 #[doc = "Field `OTGINT` writer - "]
28023 pub type OtgintW<'a, REG> = crate::BitWriter<'a, REG>;
28024 #[doc = "Field `SOF` reader - "]
28025 pub type SofR = crate::BitReader;
28026 #[doc = "Field `SOF` writer - "]
28027 pub type SofW<'a, REG> = crate::BitWriter<'a, REG>;
28028 #[doc = "Field `RXFLVL` reader - "]
28029 pub type RxflvlR = crate::BitReader;
28030 #[doc = "Field `RXFLVL` writer - "]
28031 pub type RxflvlW<'a, REG> = crate::BitWriter<'a, REG>;
28032 #[doc = "Field `NPTXFEMP` reader - "]
28033 pub type NptxfempR = crate::BitReader;
28034 #[doc = "Field `NPTXFEMP` writer - "]
28035 pub type NptxfempW<'a, REG> = crate::BitWriter<'a, REG>;
28036 #[doc = "Field `GINNAKEFF` reader - "]
28037 pub type GinnakeffR = crate::BitReader;
28038 #[doc = "Field `GINNAKEFF` writer - "]
28039 pub type GinnakeffW<'a, REG> = crate::BitWriter<'a, REG>;
28040 #[doc = "Field `GOUTNAKEFF` reader - "]
28041 pub type GoutnakeffR = crate::BitReader;
28042 #[doc = "Field `GOUTNAKEFF` writer - "]
28043 pub type GoutnakeffW<'a, REG> = crate::BitWriter<'a, REG>;
28044 #[doc = "Field `ULPICKINT` reader - "]
28045 pub type UlpickintR = crate::BitReader;
28046 #[doc = "Field `ULPICKINT` writer - "]
28047 pub type UlpickintW<'a, REG> = crate::BitWriter<'a, REG>;
28048 #[doc = "Field `I2CINT` reader - "]
28049 pub type I2cintR = crate::BitReader;
28050 #[doc = "Field `I2CINT` writer - "]
28051 pub type I2cintW<'a, REG> = crate::BitWriter<'a, REG>;
28052 #[doc = "Field `ERLYSUSP` reader - "]
28053 pub type ErlysuspR = crate::BitReader;
28054 #[doc = "Field `ERLYSUSP` writer - "]
28055 pub type ErlysuspW<'a, REG> = crate::BitWriter<'a, REG>;
28056 #[doc = "Field `USBSUSP` reader - "]
28057 pub type UsbsuspR = crate::BitReader;
28058 #[doc = "Field `USBSUSP` writer - "]
28059 pub type UsbsuspW<'a, REG> = crate::BitWriter<'a, REG>;
28060 #[doc = "Field `USBRST` reader - "]
28061 pub type UsbrstR = crate::BitReader;
28062 #[doc = "Field `USBRST` writer - "]
28063 pub type UsbrstW<'a, REG> = crate::BitWriter<'a, REG>;
28064 #[doc = "Field `ENUMDONE` reader - "]
28065 pub type EnumdoneR = crate::BitReader;
28066 #[doc = "Field `ENUMDONE` writer - "]
28067 pub type EnumdoneW<'a, REG> = crate::BitWriter<'a, REG>;
28068 #[doc = "Field `ISOOUTDROP` reader - "]
28069 pub type IsooutdropR = crate::BitReader;
28070 #[doc = "Field `ISOOUTDROP` writer - "]
28071 pub type IsooutdropW<'a, REG> = crate::BitWriter<'a, REG>;
28072 #[doc = "Field `EOPF` reader - "]
28073 pub type EopfR = crate::BitReader;
28074 #[doc = "Field `EOPF` writer - "]
28075 pub type EopfW<'a, REG> = crate::BitWriter<'a, REG>;
28076 #[doc = "Field `RESTORE_DONE` reader - "]
28077 pub type RestoreDoneR = crate::BitReader;
28078 #[doc = "Field `RESTORE_DONE` writer - "]
28079 pub type RestoreDoneW<'a, REG> = crate::BitWriter<'a, REG>;
28080 #[doc = "Field `EPMIS` reader - "]
28081 pub type EpmisR = crate::BitReader;
28082 #[doc = "Field `EPMIS` writer - "]
28083 pub type EpmisW<'a, REG> = crate::BitWriter<'a, REG>;
28084 #[doc = "Field `IEPINT` reader - "]
28085 pub type IepintR = crate::BitReader;
28086 #[doc = "Field `IEPINT` writer - "]
28087 pub type IepintW<'a, REG> = crate::BitWriter<'a, REG>;
28088 #[doc = "Field `OEPINT` reader - "]
28089 pub type OepintR = crate::BitReader;
28090 #[doc = "Field `OEPINT` writer - "]
28091 pub type OepintW<'a, REG> = crate::BitWriter<'a, REG>;
28092 #[doc = "Field `INCOMPISOIN` reader - "]
28093 pub type IncompisoinR = crate::BitReader;
28094 #[doc = "Field `INCOMPISOIN` writer - "]
28095 pub type IncompisoinW<'a, REG> = crate::BitWriter<'a, REG>;
28096 #[doc = "Field `INCOMPLP` reader - "]
28097 pub type IncomplpR = crate::BitReader;
28098 #[doc = "Field `INCOMPLP` writer - "]
28099 pub type IncomplpW<'a, REG> = crate::BitWriter<'a, REG>;
28100 #[doc = "Field `FETSUSP` reader - "]
28101 pub type FetsuspR = crate::BitReader;
28102 #[doc = "Field `FETSUSP` writer - "]
28103 pub type FetsuspW<'a, REG> = crate::BitWriter<'a, REG>;
28104 #[doc = "Field `RESETDET` reader - "]
28105 pub type ResetdetR = crate::BitReader;
28106 #[doc = "Field `RESETDET` writer - "]
28107 pub type ResetdetW<'a, REG> = crate::BitWriter<'a, REG>;
28108 #[doc = "Field `PRTINT` reader - "]
28109 pub type PrtintR = crate::BitReader;
28110 #[doc = "Field `PRTINT` writer - "]
28111 pub type PrtintW<'a, REG> = crate::BitWriter<'a, REG>;
28112 #[doc = "Field `HCHINT` reader - "]
28113 pub type HchintR = crate::BitReader;
28114 #[doc = "Field `HCHINT` writer - "]
28115 pub type HchintW<'a, REG> = crate::BitWriter<'a, REG>;
28116 #[doc = "Field `PTXFEMP` reader - "]
28117 pub type PtxfempR = crate::BitReader;
28118 #[doc = "Field `PTXFEMP` writer - "]
28119 pub type PtxfempW<'a, REG> = crate::BitWriter<'a, REG>;
28120 #[doc = "Field `LPM` reader - "]
28121 pub type LpmR = crate::BitReader;
28122 #[doc = "Field `LPM` writer - "]
28123 pub type LpmW<'a, REG> = crate::BitWriter<'a, REG>;
28124 #[doc = "Field `CONIDSTSCHNG` reader - "]
28125 pub type ConidstschngR = crate::BitReader;
28126 #[doc = "Field `CONIDSTSCHNG` writer - "]
28127 pub type ConidstschngW<'a, REG> = crate::BitWriter<'a, REG>;
28128 #[doc = "Field `DISCONNINT` reader - "]
28129 pub type DisconnintR = crate::BitReader;
28130 #[doc = "Field `DISCONNINT` writer - "]
28131 pub type DisconnintW<'a, REG> = crate::BitWriter<'a, REG>;
28132 #[doc = "Field `SESSREQINT` reader - "]
28133 pub type SessreqintR = crate::BitReader;
28134 #[doc = "Field `SESSREQINT` writer - "]
28135 pub type SessreqintW<'a, REG> = crate::BitWriter<'a, REG>;
28136 #[doc = "Field `WKUPINT` reader - "]
28137 pub type WkupintR = crate::BitReader;
28138 #[doc = "Field `WKUPINT` writer - "]
28139 pub type WkupintW<'a, REG> = crate::BitWriter<'a, REG>;
28140 impl R {
28141 #[doc = "Bit 0"]
28142 #[inline(always)]
28143 pub fn curmod(&self) -> CurmodR {
28144 CurmodR::new((self.bits & 1) != 0)
28145 }
28146 #[doc = "Bit 1"]
28147 #[inline(always)]
28148 pub fn modemis(&self) -> ModemisR {
28149 ModemisR::new(((self.bits >> 1) & 1) != 0)
28150 }
28151 #[doc = "Bit 2"]
28152 #[inline(always)]
28153 pub fn otgint(&self) -> OtgintR {
28154 OtgintR::new(((self.bits >> 2) & 1) != 0)
28155 }
28156 #[doc = "Bit 3"]
28157 #[inline(always)]
28158 pub fn sof(&self) -> SofR {
28159 SofR::new(((self.bits >> 3) & 1) != 0)
28160 }
28161 #[doc = "Bit 4"]
28162 #[inline(always)]
28163 pub fn rxflvl(&self) -> RxflvlR {
28164 RxflvlR::new(((self.bits >> 4) & 1) != 0)
28165 }
28166 #[doc = "Bit 5"]
28167 #[inline(always)]
28168 pub fn nptxfemp(&self) -> NptxfempR {
28169 NptxfempR::new(((self.bits >> 5) & 1) != 0)
28170 }
28171 #[doc = "Bit 6"]
28172 #[inline(always)]
28173 pub fn ginnakeff(&self) -> GinnakeffR {
28174 GinnakeffR::new(((self.bits >> 6) & 1) != 0)
28175 }
28176 #[doc = "Bit 7"]
28177 #[inline(always)]
28178 pub fn goutnakeff(&self) -> GoutnakeffR {
28179 GoutnakeffR::new(((self.bits >> 7) & 1) != 0)
28180 }
28181 #[doc = "Bit 8"]
28182 #[inline(always)]
28183 pub fn ulpickint(&self) -> UlpickintR {
28184 UlpickintR::new(((self.bits >> 8) & 1) != 0)
28185 }
28186 #[doc = "Bit 9"]
28187 #[inline(always)]
28188 pub fn i2cint(&self) -> I2cintR {
28189 I2cintR::new(((self.bits >> 9) & 1) != 0)
28190 }
28191 #[doc = "Bit 10"]
28192 #[inline(always)]
28193 pub fn erlysusp(&self) -> ErlysuspR {
28194 ErlysuspR::new(((self.bits >> 10) & 1) != 0)
28195 }
28196 #[doc = "Bit 11"]
28197 #[inline(always)]
28198 pub fn usbsusp(&self) -> UsbsuspR {
28199 UsbsuspR::new(((self.bits >> 11) & 1) != 0)
28200 }
28201 #[doc = "Bit 12"]
28202 #[inline(always)]
28203 pub fn usbrst(&self) -> UsbrstR {
28204 UsbrstR::new(((self.bits >> 12) & 1) != 0)
28205 }
28206 #[doc = "Bit 13"]
28207 #[inline(always)]
28208 pub fn enumdone(&self) -> EnumdoneR {
28209 EnumdoneR::new(((self.bits >> 13) & 1) != 0)
28210 }
28211 #[doc = "Bit 14"]
28212 #[inline(always)]
28213 pub fn isooutdrop(&self) -> IsooutdropR {
28214 IsooutdropR::new(((self.bits >> 14) & 1) != 0)
28215 }
28216 #[doc = "Bit 15"]
28217 #[inline(always)]
28218 pub fn eopf(&self) -> EopfR {
28219 EopfR::new(((self.bits >> 15) & 1) != 0)
28220 }
28221 #[doc = "Bit 16"]
28222 #[inline(always)]
28223 pub fn restore_done(&self) -> RestoreDoneR {
28224 RestoreDoneR::new(((self.bits >> 16) & 1) != 0)
28225 }
28226 #[doc = "Bit 17"]
28227 #[inline(always)]
28228 pub fn epmis(&self) -> EpmisR {
28229 EpmisR::new(((self.bits >> 17) & 1) != 0)
28230 }
28231 #[doc = "Bit 18"]
28232 #[inline(always)]
28233 pub fn iepint(&self) -> IepintR {
28234 IepintR::new(((self.bits >> 18) & 1) != 0)
28235 }
28236 #[doc = "Bit 19"]
28237 #[inline(always)]
28238 pub fn oepint(&self) -> OepintR {
28239 OepintR::new(((self.bits >> 19) & 1) != 0)
28240 }
28241 #[doc = "Bit 20"]
28242 #[inline(always)]
28243 pub fn incompisoin(&self) -> IncompisoinR {
28244 IncompisoinR::new(((self.bits >> 20) & 1) != 0)
28245 }
28246 #[doc = "Bit 21"]
28247 #[inline(always)]
28248 pub fn incomplp(&self) -> IncomplpR {
28249 IncomplpR::new(((self.bits >> 21) & 1) != 0)
28250 }
28251 #[doc = "Bit 22"]
28252 #[inline(always)]
28253 pub fn fetsusp(&self) -> FetsuspR {
28254 FetsuspR::new(((self.bits >> 22) & 1) != 0)
28255 }
28256 #[doc = "Bit 23"]
28257 #[inline(always)]
28258 pub fn resetdet(&self) -> ResetdetR {
28259 ResetdetR::new(((self.bits >> 23) & 1) != 0)
28260 }
28261 #[doc = "Bit 24"]
28262 #[inline(always)]
28263 pub fn prtint(&self) -> PrtintR {
28264 PrtintR::new(((self.bits >> 24) & 1) != 0)
28265 }
28266 #[doc = "Bit 25"]
28267 #[inline(always)]
28268 pub fn hchint(&self) -> HchintR {
28269 HchintR::new(((self.bits >> 25) & 1) != 0)
28270 }
28271 #[doc = "Bit 26"]
28272 #[inline(always)]
28273 pub fn ptxfemp(&self) -> PtxfempR {
28274 PtxfempR::new(((self.bits >> 26) & 1) != 0)
28275 }
28276 #[doc = "Bit 27"]
28277 #[inline(always)]
28278 pub fn lpm(&self) -> LpmR {
28279 LpmR::new(((self.bits >> 27) & 1) != 0)
28280 }
28281 #[doc = "Bit 28"]
28282 #[inline(always)]
28283 pub fn conidstschng(&self) -> ConidstschngR {
28284 ConidstschngR::new(((self.bits >> 28) & 1) != 0)
28285 }
28286 #[doc = "Bit 29"]
28287 #[inline(always)]
28288 pub fn disconnint(&self) -> DisconnintR {
28289 DisconnintR::new(((self.bits >> 29) & 1) != 0)
28290 }
28291 #[doc = "Bit 30"]
28292 #[inline(always)]
28293 pub fn sessreqint(&self) -> SessreqintR {
28294 SessreqintR::new(((self.bits >> 30) & 1) != 0)
28295 }
28296 #[doc = "Bit 31"]
28297 #[inline(always)]
28298 pub fn wkupint(&self) -> WkupintR {
28299 WkupintR::new(((self.bits >> 31) & 1) != 0)
28300 }
28301 }
28302 impl W {
28303 #[doc = "Bit 0"]
28304 #[inline(always)]
28305 pub fn curmod(&mut self) -> CurmodW<'_, GintstsSpec> {
28306 CurmodW::new(self, 0)
28307 }
28308 #[doc = "Bit 1"]
28309 #[inline(always)]
28310 pub fn modemis(&mut self) -> ModemisW<'_, GintstsSpec> {
28311 ModemisW::new(self, 1)
28312 }
28313 #[doc = "Bit 2"]
28314 #[inline(always)]
28315 pub fn otgint(&mut self) -> OtgintW<'_, GintstsSpec> {
28316 OtgintW::new(self, 2)
28317 }
28318 #[doc = "Bit 3"]
28319 #[inline(always)]
28320 pub fn sof(&mut self) -> SofW<'_, GintstsSpec> {
28321 SofW::new(self, 3)
28322 }
28323 #[doc = "Bit 4"]
28324 #[inline(always)]
28325 pub fn rxflvl(&mut self) -> RxflvlW<'_, GintstsSpec> {
28326 RxflvlW::new(self, 4)
28327 }
28328 #[doc = "Bit 5"]
28329 #[inline(always)]
28330 pub fn nptxfemp(&mut self) -> NptxfempW<'_, GintstsSpec> {
28331 NptxfempW::new(self, 5)
28332 }
28333 #[doc = "Bit 6"]
28334 #[inline(always)]
28335 pub fn ginnakeff(&mut self) -> GinnakeffW<'_, GintstsSpec> {
28336 GinnakeffW::new(self, 6)
28337 }
28338 #[doc = "Bit 7"]
28339 #[inline(always)]
28340 pub fn goutnakeff(&mut self) -> GoutnakeffW<'_, GintstsSpec> {
28341 GoutnakeffW::new(self, 7)
28342 }
28343 #[doc = "Bit 8"]
28344 #[inline(always)]
28345 pub fn ulpickint(&mut self) -> UlpickintW<'_, GintstsSpec> {
28346 UlpickintW::new(self, 8)
28347 }
28348 #[doc = "Bit 9"]
28349 #[inline(always)]
28350 pub fn i2cint(&mut self) -> I2cintW<'_, GintstsSpec> {
28351 I2cintW::new(self, 9)
28352 }
28353 #[doc = "Bit 10"]
28354 #[inline(always)]
28355 pub fn erlysusp(&mut self) -> ErlysuspW<'_, GintstsSpec> {
28356 ErlysuspW::new(self, 10)
28357 }
28358 #[doc = "Bit 11"]
28359 #[inline(always)]
28360 pub fn usbsusp(&mut self) -> UsbsuspW<'_, GintstsSpec> {
28361 UsbsuspW::new(self, 11)
28362 }
28363 #[doc = "Bit 12"]
28364 #[inline(always)]
28365 pub fn usbrst(&mut self) -> UsbrstW<'_, GintstsSpec> {
28366 UsbrstW::new(self, 12)
28367 }
28368 #[doc = "Bit 13"]
28369 #[inline(always)]
28370 pub fn enumdone(&mut self) -> EnumdoneW<'_, GintstsSpec> {
28371 EnumdoneW::new(self, 13)
28372 }
28373 #[doc = "Bit 14"]
28374 #[inline(always)]
28375 pub fn isooutdrop(&mut self) -> IsooutdropW<'_, GintstsSpec> {
28376 IsooutdropW::new(self, 14)
28377 }
28378 #[doc = "Bit 15"]
28379 #[inline(always)]
28380 pub fn eopf(&mut self) -> EopfW<'_, GintstsSpec> {
28381 EopfW::new(self, 15)
28382 }
28383 #[doc = "Bit 16"]
28384 #[inline(always)]
28385 pub fn restore_done(&mut self) -> RestoreDoneW<'_, GintstsSpec> {
28386 RestoreDoneW::new(self, 16)
28387 }
28388 #[doc = "Bit 17"]
28389 #[inline(always)]
28390 pub fn epmis(&mut self) -> EpmisW<'_, GintstsSpec> {
28391 EpmisW::new(self, 17)
28392 }
28393 #[doc = "Bit 18"]
28394 #[inline(always)]
28395 pub fn iepint(&mut self) -> IepintW<'_, GintstsSpec> {
28396 IepintW::new(self, 18)
28397 }
28398 #[doc = "Bit 19"]
28399 #[inline(always)]
28400 pub fn oepint(&mut self) -> OepintW<'_, GintstsSpec> {
28401 OepintW::new(self, 19)
28402 }
28403 #[doc = "Bit 20"]
28404 #[inline(always)]
28405 pub fn incompisoin(&mut self) -> IncompisoinW<'_, GintstsSpec> {
28406 IncompisoinW::new(self, 20)
28407 }
28408 #[doc = "Bit 21"]
28409 #[inline(always)]
28410 pub fn incomplp(&mut self) -> IncomplpW<'_, GintstsSpec> {
28411 IncomplpW::new(self, 21)
28412 }
28413 #[doc = "Bit 22"]
28414 #[inline(always)]
28415 pub fn fetsusp(&mut self) -> FetsuspW<'_, GintstsSpec> {
28416 FetsuspW::new(self, 22)
28417 }
28418 #[doc = "Bit 23"]
28419 #[inline(always)]
28420 pub fn resetdet(&mut self) -> ResetdetW<'_, GintstsSpec> {
28421 ResetdetW::new(self, 23)
28422 }
28423 #[doc = "Bit 24"]
28424 #[inline(always)]
28425 pub fn prtint(&mut self) -> PrtintW<'_, GintstsSpec> {
28426 PrtintW::new(self, 24)
28427 }
28428 #[doc = "Bit 25"]
28429 #[inline(always)]
28430 pub fn hchint(&mut self) -> HchintW<'_, GintstsSpec> {
28431 HchintW::new(self, 25)
28432 }
28433 #[doc = "Bit 26"]
28434 #[inline(always)]
28435 pub fn ptxfemp(&mut self) -> PtxfempW<'_, GintstsSpec> {
28436 PtxfempW::new(self, 26)
28437 }
28438 #[doc = "Bit 27"]
28439 #[inline(always)]
28440 pub fn lpm(&mut self) -> LpmW<'_, GintstsSpec> {
28441 LpmW::new(self, 27)
28442 }
28443 #[doc = "Bit 28"]
28444 #[inline(always)]
28445 pub fn conidstschng(&mut self) -> ConidstschngW<'_, GintstsSpec> {
28446 ConidstschngW::new(self, 28)
28447 }
28448 #[doc = "Bit 29"]
28449 #[inline(always)]
28450 pub fn disconnint(&mut self) -> DisconnintW<'_, GintstsSpec> {
28451 DisconnintW::new(self, 29)
28452 }
28453 #[doc = "Bit 30"]
28454 #[inline(always)]
28455 pub fn sessreqint(&mut self) -> SessreqintW<'_, GintstsSpec> {
28456 SessreqintW::new(self, 30)
28457 }
28458 #[doc = "Bit 31"]
28459 #[inline(always)]
28460 pub fn wkupint(&mut self) -> WkupintW<'_, GintstsSpec> {
28461 WkupintW::new(self, 31)
28462 }
28463 }
28464 #[doc = "DOTG_GINTSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`gintsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28465 pub struct GintstsSpec;
28466 impl crate::RegisterSpec for GintstsSpec {
28467 type Ux = u32;
28468 }
28469 #[doc = "`read()` method returns [`gintsts::R`](R) reader structure"]
28470 impl crate::Readable for GintstsSpec {}
28471 #[doc = "`write(|w| ..)` method takes [`gintsts::W`](W) writer structure"]
28472 impl crate::Writable for GintstsSpec {
28473 type Safety = crate::Unsafe;
28474 }
28475 #[doc = "`reset()` method sets GINTSTS to value 0"]
28476 impl crate::Resettable for GintstsSpec {}
28477 }
28478 #[doc = "GINTMSK (rw) register accessor: DOTG_GINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`gintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintmsk`] module"]
28479 #[doc(alias = "GINTMSK")]
28480 pub type Gintmsk = crate::Reg<gintmsk::GintmskSpec>;
28481 #[doc = "DOTG_GINTMSK"]
28482 pub mod gintmsk {
28483 #[doc = "Register `GINTMSK` reader"]
28484 pub type R = crate::R<GintmskSpec>;
28485 #[doc = "Register `GINTMSK` writer"]
28486 pub type W = crate::W<GintmskSpec>;
28487 #[doc = "Field `CURMODMSK` reader - "]
28488 pub type CurmodmskR = crate::BitReader;
28489 #[doc = "Field `CURMODMSK` writer - "]
28490 pub type CurmodmskW<'a, REG> = crate::BitWriter<'a, REG>;
28491 #[doc = "Field `MODEMISMSK` reader - "]
28492 pub type ModemismskR = crate::BitReader;
28493 #[doc = "Field `MODEMISMSK` writer - "]
28494 pub type ModemismskW<'a, REG> = crate::BitWriter<'a, REG>;
28495 #[doc = "Field `OTGINTMSK` reader - "]
28496 pub type OtgintmskR = crate::BitReader;
28497 #[doc = "Field `OTGINTMSK` writer - "]
28498 pub type OtgintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28499 #[doc = "Field `SOFMSK` reader - "]
28500 pub type SofmskR = crate::BitReader;
28501 #[doc = "Field `SOFMSK` writer - "]
28502 pub type SofmskW<'a, REG> = crate::BitWriter<'a, REG>;
28503 #[doc = "Field `RXFLVLMSK` reader - "]
28504 pub type RxflvlmskR = crate::BitReader;
28505 #[doc = "Field `RXFLVLMSK` writer - "]
28506 pub type RxflvlmskW<'a, REG> = crate::BitWriter<'a, REG>;
28507 #[doc = "Field `NPTXFEMPMSK` reader - "]
28508 pub type NptxfempmskR = crate::BitReader;
28509 #[doc = "Field `NPTXFEMPMSK` writer - "]
28510 pub type NptxfempmskW<'a, REG> = crate::BitWriter<'a, REG>;
28511 #[doc = "Field `GINNAKEFFMSK` reader - "]
28512 pub type GinnakeffmskR = crate::BitReader;
28513 #[doc = "Field `GINNAKEFFMSK` writer - "]
28514 pub type GinnakeffmskW<'a, REG> = crate::BitWriter<'a, REG>;
28515 #[doc = "Field `GOUTNAKEFFMSK` reader - "]
28516 pub type GoutnakeffmskR = crate::BitReader;
28517 #[doc = "Field `GOUTNAKEFFMSK` writer - "]
28518 pub type GoutnakeffmskW<'a, REG> = crate::BitWriter<'a, REG>;
28519 #[doc = "Field `ULPICKINTMSK` reader - "]
28520 pub type UlpickintmskR = crate::BitReader;
28521 #[doc = "Field `ULPICKINTMSK` writer - "]
28522 pub type UlpickintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28523 #[doc = "Field `I2CINTMSK` reader - "]
28524 pub type I2cintmskR = crate::BitReader;
28525 #[doc = "Field `I2CINTMSK` writer - "]
28526 pub type I2cintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28527 #[doc = "Field `ERLYSUSPMSK` reader - "]
28528 pub type ErlysuspmskR = crate::BitReader;
28529 #[doc = "Field `ERLYSUSPMSK` writer - "]
28530 pub type ErlysuspmskW<'a, REG> = crate::BitWriter<'a, REG>;
28531 #[doc = "Field `USBSUSPMSK` reader - "]
28532 pub type UsbsuspmskR = crate::BitReader;
28533 #[doc = "Field `USBSUSPMSK` writer - "]
28534 pub type UsbsuspmskW<'a, REG> = crate::BitWriter<'a, REG>;
28535 #[doc = "Field `USBRSTMSK` reader - "]
28536 pub type UsbrstmskR = crate::BitReader;
28537 #[doc = "Field `USBRSTMSK` writer - "]
28538 pub type UsbrstmskW<'a, REG> = crate::BitWriter<'a, REG>;
28539 #[doc = "Field `ENUMDONEMSK` reader - "]
28540 pub type EnumdonemskR = crate::BitReader;
28541 #[doc = "Field `ENUMDONEMSK` writer - "]
28542 pub type EnumdonemskW<'a, REG> = crate::BitWriter<'a, REG>;
28543 #[doc = "Field `ISOOUTDROPMSK` reader - "]
28544 pub type IsooutdropmskR = crate::BitReader;
28545 #[doc = "Field `ISOOUTDROPMSK` writer - "]
28546 pub type IsooutdropmskW<'a, REG> = crate::BitWriter<'a, REG>;
28547 #[doc = "Field `EOPFMSK` reader - "]
28548 pub type EopfmskR = crate::BitReader;
28549 #[doc = "Field `EOPFMSK` writer - "]
28550 pub type EopfmskW<'a, REG> = crate::BitWriter<'a, REG>;
28551 #[doc = "Field `EPMISMSK` reader - "]
28552 pub type EpmismskR = crate::BitReader;
28553 #[doc = "Field `EPMISMSK` writer - "]
28554 pub type EpmismskW<'a, REG> = crate::BitWriter<'a, REG>;
28555 #[doc = "Field `IEPINTMSK` reader - "]
28556 pub type IepintmskR = crate::BitReader;
28557 #[doc = "Field `IEPINTMSK` writer - "]
28558 pub type IepintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28559 #[doc = "Field `OEPINTMSK` reader - "]
28560 pub type OepintmskR = crate::BitReader;
28561 #[doc = "Field `OEPINTMSK` writer - "]
28562 pub type OepintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28563 #[doc = "Field `INCOMPISOINMSK` reader - "]
28564 pub type IncompisoinmskR = crate::BitReader;
28565 #[doc = "Field `INCOMPISOINMSK` writer - "]
28566 pub type IncompisoinmskW<'a, REG> = crate::BitWriter<'a, REG>;
28567 #[doc = "Field `INCOMPLPMSK` reader - "]
28568 pub type IncomplpmskR = crate::BitReader;
28569 #[doc = "Field `INCOMPLPMSK` writer - "]
28570 pub type IncomplpmskW<'a, REG> = crate::BitWriter<'a, REG>;
28571 #[doc = "Field `FETSUSPMSK` reader - "]
28572 pub type FetsuspmskR = crate::BitReader;
28573 #[doc = "Field `FETSUSPMSK` writer - "]
28574 pub type FetsuspmskW<'a, REG> = crate::BitWriter<'a, REG>;
28575 #[doc = "Field `PRTINTMSK` reader - "]
28576 pub type PrtintmskR = crate::BitReader;
28577 #[doc = "Field `PRTINTMSK` writer - "]
28578 pub type PrtintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28579 #[doc = "Field `HCHINTMSK` reader - "]
28580 pub type HchintmskR = crate::BitReader;
28581 #[doc = "Field `HCHINTMSK` writer - "]
28582 pub type HchintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28583 #[doc = "Field `PTXFEMPMSK` reader - "]
28584 pub type PtxfempmskR = crate::BitReader;
28585 #[doc = "Field `PTXFEMPMSK` writer - "]
28586 pub type PtxfempmskW<'a, REG> = crate::BitWriter<'a, REG>;
28587 #[doc = "Field `CONIDSTSCHNGMSK` reader - "]
28588 pub type ConidstschngmskR = crate::BitReader;
28589 #[doc = "Field `CONIDSTSCHNGMSK` writer - "]
28590 pub type ConidstschngmskW<'a, REG> = crate::BitWriter<'a, REG>;
28591 #[doc = "Field `DISCONNINTMSK` reader - "]
28592 pub type DisconnintmskR = crate::BitReader;
28593 #[doc = "Field `DISCONNINTMSK` writer - "]
28594 pub type DisconnintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28595 #[doc = "Field `SESSREQINTMSK` reader - "]
28596 pub type SessreqintmskR = crate::BitReader;
28597 #[doc = "Field `SESSREQINTMSK` writer - "]
28598 pub type SessreqintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28599 #[doc = "Field `WKUPINTMSK` reader - "]
28600 pub type WkupintmskR = crate::BitReader;
28601 #[doc = "Field `WKUPINTMSK` writer - "]
28602 pub type WkupintmskW<'a, REG> = crate::BitWriter<'a, REG>;
28603 impl R {
28604 #[doc = "Bit 0"]
28605 #[inline(always)]
28606 pub fn curmodmsk(&self) -> CurmodmskR {
28607 CurmodmskR::new((self.bits & 1) != 0)
28608 }
28609 #[doc = "Bit 1"]
28610 #[inline(always)]
28611 pub fn modemismsk(&self) -> ModemismskR {
28612 ModemismskR::new(((self.bits >> 1) & 1) != 0)
28613 }
28614 #[doc = "Bit 2"]
28615 #[inline(always)]
28616 pub fn otgintmsk(&self) -> OtgintmskR {
28617 OtgintmskR::new(((self.bits >> 2) & 1) != 0)
28618 }
28619 #[doc = "Bit 3"]
28620 #[inline(always)]
28621 pub fn sofmsk(&self) -> SofmskR {
28622 SofmskR::new(((self.bits >> 3) & 1) != 0)
28623 }
28624 #[doc = "Bit 4"]
28625 #[inline(always)]
28626 pub fn rxflvlmsk(&self) -> RxflvlmskR {
28627 RxflvlmskR::new(((self.bits >> 4) & 1) != 0)
28628 }
28629 #[doc = "Bit 5"]
28630 #[inline(always)]
28631 pub fn nptxfempmsk(&self) -> NptxfempmskR {
28632 NptxfempmskR::new(((self.bits >> 5) & 1) != 0)
28633 }
28634 #[doc = "Bit 6"]
28635 #[inline(always)]
28636 pub fn ginnakeffmsk(&self) -> GinnakeffmskR {
28637 GinnakeffmskR::new(((self.bits >> 6) & 1) != 0)
28638 }
28639 #[doc = "Bit 7"]
28640 #[inline(always)]
28641 pub fn goutnakeffmsk(&self) -> GoutnakeffmskR {
28642 GoutnakeffmskR::new(((self.bits >> 7) & 1) != 0)
28643 }
28644 #[doc = "Bit 8"]
28645 #[inline(always)]
28646 pub fn ulpickintmsk(&self) -> UlpickintmskR {
28647 UlpickintmskR::new(((self.bits >> 8) & 1) != 0)
28648 }
28649 #[doc = "Bit 9"]
28650 #[inline(always)]
28651 pub fn i2cintmsk(&self) -> I2cintmskR {
28652 I2cintmskR::new(((self.bits >> 9) & 1) != 0)
28653 }
28654 #[doc = "Bit 10"]
28655 #[inline(always)]
28656 pub fn erlysuspmsk(&self) -> ErlysuspmskR {
28657 ErlysuspmskR::new(((self.bits >> 10) & 1) != 0)
28658 }
28659 #[doc = "Bit 11"]
28660 #[inline(always)]
28661 pub fn usbsuspmsk(&self) -> UsbsuspmskR {
28662 UsbsuspmskR::new(((self.bits >> 11) & 1) != 0)
28663 }
28664 #[doc = "Bit 12"]
28665 #[inline(always)]
28666 pub fn usbrstmsk(&self) -> UsbrstmskR {
28667 UsbrstmskR::new(((self.bits >> 12) & 1) != 0)
28668 }
28669 #[doc = "Bit 13"]
28670 #[inline(always)]
28671 pub fn enumdonemsk(&self) -> EnumdonemskR {
28672 EnumdonemskR::new(((self.bits >> 13) & 1) != 0)
28673 }
28674 #[doc = "Bit 14"]
28675 #[inline(always)]
28676 pub fn isooutdropmsk(&self) -> IsooutdropmskR {
28677 IsooutdropmskR::new(((self.bits >> 14) & 1) != 0)
28678 }
28679 #[doc = "Bit 15"]
28680 #[inline(always)]
28681 pub fn eopfmsk(&self) -> EopfmskR {
28682 EopfmskR::new(((self.bits >> 15) & 1) != 0)
28683 }
28684 #[doc = "Bit 17"]
28685 #[inline(always)]
28686 pub fn epmismsk(&self) -> EpmismskR {
28687 EpmismskR::new(((self.bits >> 17) & 1) != 0)
28688 }
28689 #[doc = "Bit 18"]
28690 #[inline(always)]
28691 pub fn iepintmsk(&self) -> IepintmskR {
28692 IepintmskR::new(((self.bits >> 18) & 1) != 0)
28693 }
28694 #[doc = "Bit 19"]
28695 #[inline(always)]
28696 pub fn oepintmsk(&self) -> OepintmskR {
28697 OepintmskR::new(((self.bits >> 19) & 1) != 0)
28698 }
28699 #[doc = "Bit 20"]
28700 #[inline(always)]
28701 pub fn incompisoinmsk(&self) -> IncompisoinmskR {
28702 IncompisoinmskR::new(((self.bits >> 20) & 1) != 0)
28703 }
28704 #[doc = "Bit 21"]
28705 #[inline(always)]
28706 pub fn incomplpmsk(&self) -> IncomplpmskR {
28707 IncomplpmskR::new(((self.bits >> 21) & 1) != 0)
28708 }
28709 #[doc = "Bit 22"]
28710 #[inline(always)]
28711 pub fn fetsuspmsk(&self) -> FetsuspmskR {
28712 FetsuspmskR::new(((self.bits >> 22) & 1) != 0)
28713 }
28714 #[doc = "Bit 24"]
28715 #[inline(always)]
28716 pub fn prtintmsk(&self) -> PrtintmskR {
28717 PrtintmskR::new(((self.bits >> 24) & 1) != 0)
28718 }
28719 #[doc = "Bit 25"]
28720 #[inline(always)]
28721 pub fn hchintmsk(&self) -> HchintmskR {
28722 HchintmskR::new(((self.bits >> 25) & 1) != 0)
28723 }
28724 #[doc = "Bit 26"]
28725 #[inline(always)]
28726 pub fn ptxfempmsk(&self) -> PtxfempmskR {
28727 PtxfempmskR::new(((self.bits >> 26) & 1) != 0)
28728 }
28729 #[doc = "Bit 28"]
28730 #[inline(always)]
28731 pub fn conidstschngmsk(&self) -> ConidstschngmskR {
28732 ConidstschngmskR::new(((self.bits >> 28) & 1) != 0)
28733 }
28734 #[doc = "Bit 29"]
28735 #[inline(always)]
28736 pub fn disconnintmsk(&self) -> DisconnintmskR {
28737 DisconnintmskR::new(((self.bits >> 29) & 1) != 0)
28738 }
28739 #[doc = "Bit 30"]
28740 #[inline(always)]
28741 pub fn sessreqintmsk(&self) -> SessreqintmskR {
28742 SessreqintmskR::new(((self.bits >> 30) & 1) != 0)
28743 }
28744 #[doc = "Bit 31"]
28745 #[inline(always)]
28746 pub fn wkupintmsk(&self) -> WkupintmskR {
28747 WkupintmskR::new(((self.bits >> 31) & 1) != 0)
28748 }
28749 }
28750 impl W {
28751 #[doc = "Bit 0"]
28752 #[inline(always)]
28753 pub fn curmodmsk(&mut self) -> CurmodmskW<'_, GintmskSpec> {
28754 CurmodmskW::new(self, 0)
28755 }
28756 #[doc = "Bit 1"]
28757 #[inline(always)]
28758 pub fn modemismsk(&mut self) -> ModemismskW<'_, GintmskSpec> {
28759 ModemismskW::new(self, 1)
28760 }
28761 #[doc = "Bit 2"]
28762 #[inline(always)]
28763 pub fn otgintmsk(&mut self) -> OtgintmskW<'_, GintmskSpec> {
28764 OtgintmskW::new(self, 2)
28765 }
28766 #[doc = "Bit 3"]
28767 #[inline(always)]
28768 pub fn sofmsk(&mut self) -> SofmskW<'_, GintmskSpec> {
28769 SofmskW::new(self, 3)
28770 }
28771 #[doc = "Bit 4"]
28772 #[inline(always)]
28773 pub fn rxflvlmsk(&mut self) -> RxflvlmskW<'_, GintmskSpec> {
28774 RxflvlmskW::new(self, 4)
28775 }
28776 #[doc = "Bit 5"]
28777 #[inline(always)]
28778 pub fn nptxfempmsk(&mut self) -> NptxfempmskW<'_, GintmskSpec> {
28779 NptxfempmskW::new(self, 5)
28780 }
28781 #[doc = "Bit 6"]
28782 #[inline(always)]
28783 pub fn ginnakeffmsk(&mut self) -> GinnakeffmskW<'_, GintmskSpec> {
28784 GinnakeffmskW::new(self, 6)
28785 }
28786 #[doc = "Bit 7"]
28787 #[inline(always)]
28788 pub fn goutnakeffmsk(&mut self) -> GoutnakeffmskW<'_, GintmskSpec> {
28789 GoutnakeffmskW::new(self, 7)
28790 }
28791 #[doc = "Bit 8"]
28792 #[inline(always)]
28793 pub fn ulpickintmsk(&mut self) -> UlpickintmskW<'_, GintmskSpec> {
28794 UlpickintmskW::new(self, 8)
28795 }
28796 #[doc = "Bit 9"]
28797 #[inline(always)]
28798 pub fn i2cintmsk(&mut self) -> I2cintmskW<'_, GintmskSpec> {
28799 I2cintmskW::new(self, 9)
28800 }
28801 #[doc = "Bit 10"]
28802 #[inline(always)]
28803 pub fn erlysuspmsk(&mut self) -> ErlysuspmskW<'_, GintmskSpec> {
28804 ErlysuspmskW::new(self, 10)
28805 }
28806 #[doc = "Bit 11"]
28807 #[inline(always)]
28808 pub fn usbsuspmsk(&mut self) -> UsbsuspmskW<'_, GintmskSpec> {
28809 UsbsuspmskW::new(self, 11)
28810 }
28811 #[doc = "Bit 12"]
28812 #[inline(always)]
28813 pub fn usbrstmsk(&mut self) -> UsbrstmskW<'_, GintmskSpec> {
28814 UsbrstmskW::new(self, 12)
28815 }
28816 #[doc = "Bit 13"]
28817 #[inline(always)]
28818 pub fn enumdonemsk(&mut self) -> EnumdonemskW<'_, GintmskSpec> {
28819 EnumdonemskW::new(self, 13)
28820 }
28821 #[doc = "Bit 14"]
28822 #[inline(always)]
28823 pub fn isooutdropmsk(&mut self) -> IsooutdropmskW<'_, GintmskSpec> {
28824 IsooutdropmskW::new(self, 14)
28825 }
28826 #[doc = "Bit 15"]
28827 #[inline(always)]
28828 pub fn eopfmsk(&mut self) -> EopfmskW<'_, GintmskSpec> {
28829 EopfmskW::new(self, 15)
28830 }
28831 #[doc = "Bit 17"]
28832 #[inline(always)]
28833 pub fn epmismsk(&mut self) -> EpmismskW<'_, GintmskSpec> {
28834 EpmismskW::new(self, 17)
28835 }
28836 #[doc = "Bit 18"]
28837 #[inline(always)]
28838 pub fn iepintmsk(&mut self) -> IepintmskW<'_, GintmskSpec> {
28839 IepintmskW::new(self, 18)
28840 }
28841 #[doc = "Bit 19"]
28842 #[inline(always)]
28843 pub fn oepintmsk(&mut self) -> OepintmskW<'_, GintmskSpec> {
28844 OepintmskW::new(self, 19)
28845 }
28846 #[doc = "Bit 20"]
28847 #[inline(always)]
28848 pub fn incompisoinmsk(&mut self) -> IncompisoinmskW<'_, GintmskSpec> {
28849 IncompisoinmskW::new(self, 20)
28850 }
28851 #[doc = "Bit 21"]
28852 #[inline(always)]
28853 pub fn incomplpmsk(&mut self) -> IncomplpmskW<'_, GintmskSpec> {
28854 IncomplpmskW::new(self, 21)
28855 }
28856 #[doc = "Bit 22"]
28857 #[inline(always)]
28858 pub fn fetsuspmsk(&mut self) -> FetsuspmskW<'_, GintmskSpec> {
28859 FetsuspmskW::new(self, 22)
28860 }
28861 #[doc = "Bit 24"]
28862 #[inline(always)]
28863 pub fn prtintmsk(&mut self) -> PrtintmskW<'_, GintmskSpec> {
28864 PrtintmskW::new(self, 24)
28865 }
28866 #[doc = "Bit 25"]
28867 #[inline(always)]
28868 pub fn hchintmsk(&mut self) -> HchintmskW<'_, GintmskSpec> {
28869 HchintmskW::new(self, 25)
28870 }
28871 #[doc = "Bit 26"]
28872 #[inline(always)]
28873 pub fn ptxfempmsk(&mut self) -> PtxfempmskW<'_, GintmskSpec> {
28874 PtxfempmskW::new(self, 26)
28875 }
28876 #[doc = "Bit 28"]
28877 #[inline(always)]
28878 pub fn conidstschngmsk(&mut self) -> ConidstschngmskW<'_, GintmskSpec> {
28879 ConidstschngmskW::new(self, 28)
28880 }
28881 #[doc = "Bit 29"]
28882 #[inline(always)]
28883 pub fn disconnintmsk(&mut self) -> DisconnintmskW<'_, GintmskSpec> {
28884 DisconnintmskW::new(self, 29)
28885 }
28886 #[doc = "Bit 30"]
28887 #[inline(always)]
28888 pub fn sessreqintmsk(&mut self) -> SessreqintmskW<'_, GintmskSpec> {
28889 SessreqintmskW::new(self, 30)
28890 }
28891 #[doc = "Bit 31"]
28892 #[inline(always)]
28893 pub fn wkupintmsk(&mut self) -> WkupintmskW<'_, GintmskSpec> {
28894 WkupintmskW::new(self, 31)
28895 }
28896 }
28897 #[doc = "DOTG_GINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`gintmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28898 pub struct GintmskSpec;
28899 impl crate::RegisterSpec for GintmskSpec {
28900 type Ux = u32;
28901 }
28902 #[doc = "`read()` method returns [`gintmsk::R`](R) reader structure"]
28903 impl crate::Readable for GintmskSpec {}
28904 #[doc = "`write(|w| ..)` method takes [`gintmsk::W`](W) writer structure"]
28905 impl crate::Writable for GintmskSpec {
28906 type Safety = crate::Unsafe;
28907 }
28908 #[doc = "`reset()` method sets GINTMSK to value 0"]
28909 impl crate::Resettable for GintmskSpec {}
28910 }
28911 #[doc = "GRXSTSRD (rw) register accessor: DOTG_GRXSTSRD\n\nYou can [`read`](crate::Reg::read) this register and get [`grxstsrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxstsrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsrd`] module"]
28912 #[doc(alias = "GRXSTSRD")]
28913 pub type Grxstsrd = crate::Reg<grxstsrd::GrxstsrdSpec>;
28914 #[doc = "DOTG_GRXSTSRD"]
28915 pub mod grxstsrd {
28916 #[doc = "Register `GRXSTSRD` reader"]
28917 pub type R = crate::R<GrxstsrdSpec>;
28918 #[doc = "Register `GRXSTSRD` writer"]
28919 pub type W = crate::W<GrxstsrdSpec>;
28920 #[doc = "Field `CHNUM` reader - "]
28921 pub type ChnumR = crate::FieldReader;
28922 #[doc = "Field `CHNUM` writer - "]
28923 pub type ChnumW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
28924 #[doc = "Field `BCNT` reader - "]
28925 pub type BcntR = crate::FieldReader<u16>;
28926 #[doc = "Field `BCNT` writer - "]
28927 pub type BcntW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
28928 #[doc = "Field `DPID_DATA2` reader - "]
28929 pub type DpidData2R = crate::BitReader;
28930 #[doc = "Field `DPID_DATA2` writer - "]
28931 pub type DpidData2W<'a, REG> = crate::BitWriter<'a, REG>;
28932 #[doc = "Field `GLOB_OUT_NAK` reader - "]
28933 pub type GlobOutNakR = crate::BitReader;
28934 #[doc = "Field `GLOB_OUT_NAK` writer - "]
28935 pub type GlobOutNakW<'a, REG> = crate::BitWriter<'a, REG>;
28936 #[doc = "Field `FN` reader - "]
28937 pub type FnR = crate::FieldReader;
28938 #[doc = "Field `FN` writer - "]
28939 pub type FnW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
28940 impl R {
28941 #[doc = "Bits 0:3"]
28942 #[inline(always)]
28943 pub fn chnum(&self) -> ChnumR {
28944 ChnumR::new((self.bits & 0x0f) as u8)
28945 }
28946 #[doc = "Bits 4:14"]
28947 #[inline(always)]
28948 pub fn bcnt(&self) -> BcntR {
28949 BcntR::new(((self.bits >> 4) & 0x07ff) as u16)
28950 }
28951 #[doc = "Bit 15"]
28952 #[inline(always)]
28953 pub fn dpid_data2(&self) -> DpidData2R {
28954 DpidData2R::new(((self.bits >> 15) & 1) != 0)
28955 }
28956 #[doc = "Bit 17"]
28957 #[inline(always)]
28958 pub fn glob_out_nak(&self) -> GlobOutNakR {
28959 GlobOutNakR::new(((self.bits >> 17) & 1) != 0)
28960 }
28961 #[doc = "Bits 21:24"]
28962 #[inline(always)]
28963 pub fn fn_(&self) -> FnR {
28964 FnR::new(((self.bits >> 21) & 0x0f) as u8)
28965 }
28966 }
28967 impl W {
28968 #[doc = "Bits 0:3"]
28969 #[inline(always)]
28970 pub fn chnum(&mut self) -> ChnumW<'_, GrxstsrdSpec> {
28971 ChnumW::new(self, 0)
28972 }
28973 #[doc = "Bits 4:14"]
28974 #[inline(always)]
28975 pub fn bcnt(&mut self) -> BcntW<'_, GrxstsrdSpec> {
28976 BcntW::new(self, 4)
28977 }
28978 #[doc = "Bit 15"]
28979 #[inline(always)]
28980 pub fn dpid_data2(&mut self) -> DpidData2W<'_, GrxstsrdSpec> {
28981 DpidData2W::new(self, 15)
28982 }
28983 #[doc = "Bit 17"]
28984 #[inline(always)]
28985 pub fn glob_out_nak(&mut self) -> GlobOutNakW<'_, GrxstsrdSpec> {
28986 GlobOutNakW::new(self, 17)
28987 }
28988 #[doc = "Bits 21:24"]
28989 #[inline(always)]
28990 pub fn fn_(&mut self) -> FnW<'_, GrxstsrdSpec> {
28991 FnW::new(self, 21)
28992 }
28993 }
28994 #[doc = "DOTG_GRXSTSRD\n\nYou can [`read`](crate::Reg::read) this register and get [`grxstsrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxstsrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
28995 pub struct GrxstsrdSpec;
28996 impl crate::RegisterSpec for GrxstsrdSpec {
28997 type Ux = u32;
28998 }
28999 #[doc = "`read()` method returns [`grxstsrd::R`](R) reader structure"]
29000 impl crate::Readable for GrxstsrdSpec {}
29001 #[doc = "`write(|w| ..)` method takes [`grxstsrd::W`](W) writer structure"]
29002 impl crate::Writable for GrxstsrdSpec {
29003 type Safety = crate::Unsafe;
29004 }
29005 #[doc = "`reset()` method sets GRXSTSRD to value 0"]
29006 impl crate::Resettable for GrxstsrdSpec {}
29007 }
29008 #[doc = "GRXSTSPD (rw) register accessor: DOTG_GRXSTSPD\n\nYou can [`read`](crate::Reg::read) this register and get [`grxstspd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxstspd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstspd`] module"]
29009 #[doc(alias = "GRXSTSPD")]
29010 pub type Grxstspd = crate::Reg<grxstspd::GrxstspdSpec>;
29011 #[doc = "DOTG_GRXSTSPD"]
29012 pub mod grxstspd {
29013 #[doc = "Register `GRXSTSPD` reader"]
29014 pub type R = crate::R<GrxstspdSpec>;
29015 #[doc = "Register `GRXSTSPD` writer"]
29016 pub type W = crate::W<GrxstspdSpec>;
29017 impl core::fmt::Debug for R {
29018 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
29019 write!(f, "{}", self.bits())
29020 }
29021 }
29022 impl W {}
29023 #[doc = "DOTG_GRXSTSPD\n\nYou can [`read`](crate::Reg::read) this register and get [`grxstspd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxstspd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29024 pub struct GrxstspdSpec;
29025 impl crate::RegisterSpec for GrxstspdSpec {
29026 type Ux = u32;
29027 }
29028 #[doc = "`read()` method returns [`grxstspd::R`](R) reader structure"]
29029 impl crate::Readable for GrxstspdSpec {}
29030 #[doc = "`write(|w| ..)` method takes [`grxstspd::W`](W) writer structure"]
29031 impl crate::Writable for GrxstspdSpec {
29032 type Safety = crate::Unsafe;
29033 }
29034 #[doc = "`reset()` method sets GRXSTSPD to value 0"]
29035 impl crate::Resettable for GrxstspdSpec {}
29036 }
29037 #[doc = "GRXFSIZ (rw) register accessor: DOTG_GRXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`grxfsiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxfsiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxfsiz`] module"]
29038 #[doc(alias = "GRXFSIZ")]
29039 pub type Grxfsiz = crate::Reg<grxfsiz::GrxfsizSpec>;
29040 #[doc = "DOTG_GRXFSIZ"]
29041 pub mod grxfsiz {
29042 #[doc = "Register `GRXFSIZ` reader"]
29043 pub type R = crate::R<GrxfsizSpec>;
29044 #[doc = "Register `GRXFSIZ` writer"]
29045 pub type W = crate::W<GrxfsizSpec>;
29046 #[doc = "Field `RXFDEP` reader - "]
29047 pub type RxfdepR = crate::FieldReader<u16>;
29048 #[doc = "Field `RXFDEP` writer - "]
29049 pub type RxfdepW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
29050 impl R {
29051 #[doc = "Bits 0:15"]
29052 #[inline(always)]
29053 pub fn rxfdep(&self) -> RxfdepR {
29054 RxfdepR::new((self.bits & 0xffff) as u16)
29055 }
29056 }
29057 impl W {
29058 #[doc = "Bits 0:15"]
29059 #[inline(always)]
29060 pub fn rxfdep(&mut self) -> RxfdepW<'_, GrxfsizSpec> {
29061 RxfdepW::new(self, 0)
29062 }
29063 }
29064 #[doc = "DOTG_GRXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`grxfsiz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxfsiz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29065 pub struct GrxfsizSpec;
29066 impl crate::RegisterSpec for GrxfsizSpec {
29067 type Ux = u32;
29068 }
29069 #[doc = "`read()` method returns [`grxfsiz::R`](R) reader structure"]
29070 impl crate::Readable for GrxfsizSpec {}
29071 #[doc = "`write(|w| ..)` method takes [`grxfsiz::W`](W) writer structure"]
29072 impl crate::Writable for GrxfsizSpec {
29073 type Safety = crate::Unsafe;
29074 }
29075 #[doc = "`reset()` method sets GRXFSIZ to value 0"]
29076 impl crate::Resettable for GrxfsizSpec {}
29077 }
29078 #[doc = "GNPTXFSIZ (rw) register accessor: DOTG_GNPTXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`gnptxfsiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gnptxfsiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxfsiz`] module"]
29079 #[doc(alias = "GNPTXFSIZ")]
29080 pub type Gnptxfsiz = crate::Reg<gnptxfsiz::GnptxfsizSpec>;
29081 #[doc = "DOTG_GNPTXFSIZ"]
29082 pub mod gnptxfsiz {
29083 #[doc = "Register `GNPTXFSIZ` reader"]
29084 pub type R = crate::R<GnptxfsizSpec>;
29085 #[doc = "Register `GNPTXFSIZ` writer"]
29086 pub type W = crate::W<GnptxfsizSpec>;
29087 #[doc = "Field `NPTXFDEP` reader - "]
29088 pub type NptxfdepR = crate::FieldReader<u16>;
29089 #[doc = "Field `NPTXFDEP` writer - "]
29090 pub type NptxfdepW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
29091 impl R {
29092 #[doc = "Bits 0:15"]
29093 #[inline(always)]
29094 pub fn nptxfdep(&self) -> NptxfdepR {
29095 NptxfdepR::new((self.bits & 0xffff) as u16)
29096 }
29097 }
29098 impl W {
29099 #[doc = "Bits 0:15"]
29100 #[inline(always)]
29101 pub fn nptxfdep(&mut self) -> NptxfdepW<'_, GnptxfsizSpec> {
29102 NptxfdepW::new(self, 0)
29103 }
29104 }
29105 #[doc = "DOTG_GNPTXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`gnptxfsiz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gnptxfsiz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29106 pub struct GnptxfsizSpec;
29107 impl crate::RegisterSpec for GnptxfsizSpec {
29108 type Ux = u32;
29109 }
29110 #[doc = "`read()` method returns [`gnptxfsiz::R`](R) reader structure"]
29111 impl crate::Readable for GnptxfsizSpec {}
29112 #[doc = "`write(|w| ..)` method takes [`gnptxfsiz::W`](W) writer structure"]
29113 impl crate::Writable for GnptxfsizSpec {
29114 type Safety = crate::Unsafe;
29115 }
29116 #[doc = "`reset()` method sets GNPTXFSIZ to value 0"]
29117 impl crate::Resettable for GnptxfsizSpec {}
29118 }
29119 #[doc = "GNPTXSTS (rw) register accessor: DOTG_GNPTXSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`gnptxsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gnptxsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxsts`] module"]
29120 #[doc(alias = "GNPTXSTS")]
29121 pub type Gnptxsts = crate::Reg<gnptxsts::GnptxstsSpec>;
29122 #[doc = "DOTG_GNPTXSTS"]
29123 pub mod gnptxsts {
29124 #[doc = "Register `GNPTXSTS` reader"]
29125 pub type R = crate::R<GnptxstsSpec>;
29126 #[doc = "Register `GNPTXSTS` writer"]
29127 pub type W = crate::W<GnptxstsSpec>;
29128 #[doc = "Field `NPTXFSPCAVAIL` reader - "]
29129 pub type NptxfspcavailR = crate::FieldReader<u16>;
29130 #[doc = "Field `NPTXFSPCAVAIL` writer - "]
29131 pub type NptxfspcavailW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
29132 #[doc = "Field `NPTXQSPCAVAIL` reader - "]
29133 pub type NptxqspcavailR = crate::FieldReader;
29134 #[doc = "Field `NPTXQSPCAVAIL` writer - "]
29135 pub type NptxqspcavailW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29136 #[doc = "Field `NPTXQTOP` reader - "]
29137 pub type NptxqtopR = crate::FieldReader;
29138 #[doc = "Field `NPTXQTOP` writer - "]
29139 pub type NptxqtopW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
29140 impl R {
29141 #[doc = "Bits 0:15"]
29142 #[inline(always)]
29143 pub fn nptxfspcavail(&self) -> NptxfspcavailR {
29144 NptxfspcavailR::new((self.bits & 0xffff) as u16)
29145 }
29146 #[doc = "Bits 16:23"]
29147 #[inline(always)]
29148 pub fn nptxqspcavail(&self) -> NptxqspcavailR {
29149 NptxqspcavailR::new(((self.bits >> 16) & 0xff) as u8)
29150 }
29151 #[doc = "Bits 24:30"]
29152 #[inline(always)]
29153 pub fn nptxqtop(&self) -> NptxqtopR {
29154 NptxqtopR::new(((self.bits >> 24) & 0x7f) as u8)
29155 }
29156 }
29157 impl W {
29158 #[doc = "Bits 0:15"]
29159 #[inline(always)]
29160 pub fn nptxfspcavail(&mut self) -> NptxfspcavailW<'_, GnptxstsSpec> {
29161 NptxfspcavailW::new(self, 0)
29162 }
29163 #[doc = "Bits 16:23"]
29164 #[inline(always)]
29165 pub fn nptxqspcavail(&mut self) -> NptxqspcavailW<'_, GnptxstsSpec> {
29166 NptxqspcavailW::new(self, 16)
29167 }
29168 #[doc = "Bits 24:30"]
29169 #[inline(always)]
29170 pub fn nptxqtop(&mut self) -> NptxqtopW<'_, GnptxstsSpec> {
29171 NptxqtopW::new(self, 24)
29172 }
29173 }
29174 #[doc = "DOTG_GNPTXSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`gnptxsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gnptxsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29175 pub struct GnptxstsSpec;
29176 impl crate::RegisterSpec for GnptxstsSpec {
29177 type Ux = u32;
29178 }
29179 #[doc = "`read()` method returns [`gnptxsts::R`](R) reader structure"]
29180 impl crate::Readable for GnptxstsSpec {}
29181 #[doc = "`write(|w| ..)` method takes [`gnptxsts::W`](W) writer structure"]
29182 impl crate::Writable for GnptxstsSpec {
29183 type Safety = crate::Unsafe;
29184 }
29185 #[doc = "`reset()` method sets GNPTXSTS to value 0"]
29186 impl crate::Resettable for GnptxstsSpec {}
29187 }
29188 #[doc = "GI2CCTL (rw) register accessor: DOTG_GI2CCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gi2cctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gi2cctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gi2cctl`] module"]
29189 #[doc(alias = "GI2CCTL")]
29190 pub type Gi2cctl = crate::Reg<gi2cctl::Gi2cctlSpec>;
29191 #[doc = "DOTG_GI2CCTL"]
29192 pub mod gi2cctl {
29193 #[doc = "Register `GI2CCTL` reader"]
29194 pub type R = crate::R<Gi2cctlSpec>;
29195 #[doc = "Register `GI2CCTL` writer"]
29196 pub type W = crate::W<Gi2cctlSpec>;
29197 #[doc = "Field `RWDATA` reader - "]
29198 pub type RwdataR = crate::FieldReader;
29199 #[doc = "Field `RWDATA` writer - "]
29200 pub type RwdataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29201 #[doc = "Field `REGADDR` reader - "]
29202 pub type RegaddrR = crate::FieldReader;
29203 #[doc = "Field `REGADDR` writer - "]
29204 pub type RegaddrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29205 #[doc = "Field `ADDR` reader - "]
29206 pub type AddrR = crate::FieldReader;
29207 #[doc = "Field `ADDR` writer - "]
29208 pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
29209 #[doc = "Field `I2CEN` reader - "]
29210 pub type I2cenR = crate::BitReader;
29211 #[doc = "Field `I2CEN` writer - "]
29212 pub type I2cenW<'a, REG> = crate::BitWriter<'a, REG>;
29213 #[doc = "Field `ACK` reader - "]
29214 pub type AckR = crate::BitReader;
29215 #[doc = "Field `ACK` writer - "]
29216 pub type AckW<'a, REG> = crate::BitWriter<'a, REG>;
29217 #[doc = "Field `I2CSUSPCTL` reader - "]
29218 pub type I2csuspctlR = crate::BitReader;
29219 #[doc = "Field `I2CSUSPCTL` writer - "]
29220 pub type I2csuspctlW<'a, REG> = crate::BitWriter<'a, REG>;
29221 #[doc = "Field `I2CDEVADR` reader - "]
29222 pub type I2cdevadrR = crate::FieldReader;
29223 #[doc = "Field `I2CDEVADR` writer - "]
29224 pub type I2cdevadrW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29225 #[doc = "Field `I2CDATSE0` reader - "]
29226 pub type I2cdatse0R = crate::BitReader;
29227 #[doc = "Field `I2CDATSE0` writer - "]
29228 pub type I2cdatse0W<'a, REG> = crate::BitWriter<'a, REG>;
29229 #[doc = "Field `RW` reader - "]
29230 pub type RwR = crate::BitReader;
29231 #[doc = "Field `RW` writer - "]
29232 pub type RwW<'a, REG> = crate::BitWriter<'a, REG>;
29233 #[doc = "Field `BSYDNE_SC` reader - "]
29234 pub type BsydneScR = crate::BitReader;
29235 #[doc = "Field `BSYDNE_SC` writer - "]
29236 pub type BsydneScW<'a, REG> = crate::BitWriter<'a, REG>;
29237 impl R {
29238 #[doc = "Bits 0:7"]
29239 #[inline(always)]
29240 pub fn rwdata(&self) -> RwdataR {
29241 RwdataR::new((self.bits & 0xff) as u8)
29242 }
29243 #[doc = "Bits 8:15"]
29244 #[inline(always)]
29245 pub fn regaddr(&self) -> RegaddrR {
29246 RegaddrR::new(((self.bits >> 8) & 0xff) as u8)
29247 }
29248 #[doc = "Bits 16:22"]
29249 #[inline(always)]
29250 pub fn addr(&self) -> AddrR {
29251 AddrR::new(((self.bits >> 16) & 0x7f) as u8)
29252 }
29253 #[doc = "Bit 23"]
29254 #[inline(always)]
29255 pub fn i2cen(&self) -> I2cenR {
29256 I2cenR::new(((self.bits >> 23) & 1) != 0)
29257 }
29258 #[doc = "Bit 24"]
29259 #[inline(always)]
29260 pub fn ack(&self) -> AckR {
29261 AckR::new(((self.bits >> 24) & 1) != 0)
29262 }
29263 #[doc = "Bit 25"]
29264 #[inline(always)]
29265 pub fn i2csuspctl(&self) -> I2csuspctlR {
29266 I2csuspctlR::new(((self.bits >> 25) & 1) != 0)
29267 }
29268 #[doc = "Bits 26:27"]
29269 #[inline(always)]
29270 pub fn i2cdevadr(&self) -> I2cdevadrR {
29271 I2cdevadrR::new(((self.bits >> 26) & 3) as u8)
29272 }
29273 #[doc = "Bit 28"]
29274 #[inline(always)]
29275 pub fn i2cdatse0(&self) -> I2cdatse0R {
29276 I2cdatse0R::new(((self.bits >> 28) & 1) != 0)
29277 }
29278 #[doc = "Bit 30"]
29279 #[inline(always)]
29280 pub fn rw(&self) -> RwR {
29281 RwR::new(((self.bits >> 30) & 1) != 0)
29282 }
29283 #[doc = "Bit 31"]
29284 #[inline(always)]
29285 pub fn bsydne_sc(&self) -> BsydneScR {
29286 BsydneScR::new(((self.bits >> 31) & 1) != 0)
29287 }
29288 }
29289 impl W {
29290 #[doc = "Bits 0:7"]
29291 #[inline(always)]
29292 pub fn rwdata(&mut self) -> RwdataW<'_, Gi2cctlSpec> {
29293 RwdataW::new(self, 0)
29294 }
29295 #[doc = "Bits 8:15"]
29296 #[inline(always)]
29297 pub fn regaddr(&mut self) -> RegaddrW<'_, Gi2cctlSpec> {
29298 RegaddrW::new(self, 8)
29299 }
29300 #[doc = "Bits 16:22"]
29301 #[inline(always)]
29302 pub fn addr(&mut self) -> AddrW<'_, Gi2cctlSpec> {
29303 AddrW::new(self, 16)
29304 }
29305 #[doc = "Bit 23"]
29306 #[inline(always)]
29307 pub fn i2cen(&mut self) -> I2cenW<'_, Gi2cctlSpec> {
29308 I2cenW::new(self, 23)
29309 }
29310 #[doc = "Bit 24"]
29311 #[inline(always)]
29312 pub fn ack(&mut self) -> AckW<'_, Gi2cctlSpec> {
29313 AckW::new(self, 24)
29314 }
29315 #[doc = "Bit 25"]
29316 #[inline(always)]
29317 pub fn i2csuspctl(&mut self) -> I2csuspctlW<'_, Gi2cctlSpec> {
29318 I2csuspctlW::new(self, 25)
29319 }
29320 #[doc = "Bits 26:27"]
29321 #[inline(always)]
29322 pub fn i2cdevadr(&mut self) -> I2cdevadrW<'_, Gi2cctlSpec> {
29323 I2cdevadrW::new(self, 26)
29324 }
29325 #[doc = "Bit 28"]
29326 #[inline(always)]
29327 pub fn i2cdatse0(&mut self) -> I2cdatse0W<'_, Gi2cctlSpec> {
29328 I2cdatse0W::new(self, 28)
29329 }
29330 #[doc = "Bit 30"]
29331 #[inline(always)]
29332 pub fn rw(&mut self) -> RwW<'_, Gi2cctlSpec> {
29333 RwW::new(self, 30)
29334 }
29335 #[doc = "Bit 31"]
29336 #[inline(always)]
29337 pub fn bsydne_sc(&mut self) -> BsydneScW<'_, Gi2cctlSpec> {
29338 BsydneScW::new(self, 31)
29339 }
29340 }
29341 #[doc = "DOTG_GI2CCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gi2cctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gi2cctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29342 pub struct Gi2cctlSpec;
29343 impl crate::RegisterSpec for Gi2cctlSpec {
29344 type Ux = u32;
29345 }
29346 #[doc = "`read()` method returns [`gi2cctl::R`](R) reader structure"]
29347 impl crate::Readable for Gi2cctlSpec {}
29348 #[doc = "`write(|w| ..)` method takes [`gi2cctl::W`](W) writer structure"]
29349 impl crate::Writable for Gi2cctlSpec {
29350 type Safety = crate::Unsafe;
29351 }
29352 #[doc = "`reset()` method sets GI2CCTL to value 0"]
29353 impl crate::Resettable for Gi2cctlSpec {}
29354 }
29355 #[doc = "GPVNDCTL (rw) register accessor: DOTG_GPVNDCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gpvndctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpvndctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpvndctl`] module"]
29356 #[doc(alias = "GPVNDCTL")]
29357 pub type Gpvndctl = crate::Reg<gpvndctl::GpvndctlSpec>;
29358 #[doc = "DOTG_GPVNDCTL"]
29359 pub mod gpvndctl {
29360 #[doc = "Register `GPVNDCTL` reader"]
29361 pub type R = crate::R<GpvndctlSpec>;
29362 #[doc = "Register `GPVNDCTL` writer"]
29363 pub type W = crate::W<GpvndctlSpec>;
29364 #[doc = "Field `REGDATA` reader - "]
29365 pub type RegdataR = crate::FieldReader;
29366 #[doc = "Field `REGDATA` writer - "]
29367 pub type RegdataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29368 #[doc = "Field `VCTRL` reader - "]
29369 pub type VctrlR = crate::FieldReader;
29370 #[doc = "Field `VCTRL` writer - "]
29371 pub type VctrlW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29372 #[doc = "Field `REGADDR` reader - "]
29373 pub type RegaddrR = crate::FieldReader;
29374 #[doc = "Field `REGADDR` writer - "]
29375 pub type RegaddrW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
29376 #[doc = "Field `REGWR` reader - "]
29377 pub type RegwrR = crate::BitReader;
29378 #[doc = "Field `REGWR` writer - "]
29379 pub type RegwrW<'a, REG> = crate::BitWriter<'a, REG>;
29380 #[doc = "Field `NEWREGREQ` reader - "]
29381 pub type NewregreqR = crate::BitReader;
29382 #[doc = "Field `NEWREGREQ` writer - "]
29383 pub type NewregreqW<'a, REG> = crate::BitWriter<'a, REG>;
29384 #[doc = "Field `VSTSBSY` reader - "]
29385 pub type VstsbsyR = crate::BitReader;
29386 #[doc = "Field `VSTSBSY` writer - "]
29387 pub type VstsbsyW<'a, REG> = crate::BitWriter<'a, REG>;
29388 #[doc = "Field `VSTSDONE` reader - "]
29389 pub type VstsdoneR = crate::BitReader;
29390 #[doc = "Field `VSTSDONE` writer - "]
29391 pub type VstsdoneW<'a, REG> = crate::BitWriter<'a, REG>;
29392 #[doc = "Field `DISULPIDRVR` reader - "]
29393 pub type DisulpidrvrR = crate::BitReader;
29394 #[doc = "Field `DISULPIDRVR` writer - "]
29395 pub type DisulpidrvrW<'a, REG> = crate::BitWriter<'a, REG>;
29396 impl R {
29397 #[doc = "Bits 0:7"]
29398 #[inline(always)]
29399 pub fn regdata(&self) -> RegdataR {
29400 RegdataR::new((self.bits & 0xff) as u8)
29401 }
29402 #[doc = "Bits 8:15"]
29403 #[inline(always)]
29404 pub fn vctrl(&self) -> VctrlR {
29405 VctrlR::new(((self.bits >> 8) & 0xff) as u8)
29406 }
29407 #[doc = "Bits 16:21"]
29408 #[inline(always)]
29409 pub fn regaddr(&self) -> RegaddrR {
29410 RegaddrR::new(((self.bits >> 16) & 0x3f) as u8)
29411 }
29412 #[doc = "Bit 22"]
29413 #[inline(always)]
29414 pub fn regwr(&self) -> RegwrR {
29415 RegwrR::new(((self.bits >> 22) & 1) != 0)
29416 }
29417 #[doc = "Bit 25"]
29418 #[inline(always)]
29419 pub fn newregreq(&self) -> NewregreqR {
29420 NewregreqR::new(((self.bits >> 25) & 1) != 0)
29421 }
29422 #[doc = "Bit 26"]
29423 #[inline(always)]
29424 pub fn vstsbsy(&self) -> VstsbsyR {
29425 VstsbsyR::new(((self.bits >> 26) & 1) != 0)
29426 }
29427 #[doc = "Bit 27"]
29428 #[inline(always)]
29429 pub fn vstsdone(&self) -> VstsdoneR {
29430 VstsdoneR::new(((self.bits >> 27) & 1) != 0)
29431 }
29432 #[doc = "Bit 31"]
29433 #[inline(always)]
29434 pub fn disulpidrvr(&self) -> DisulpidrvrR {
29435 DisulpidrvrR::new(((self.bits >> 31) & 1) != 0)
29436 }
29437 }
29438 impl W {
29439 #[doc = "Bits 0:7"]
29440 #[inline(always)]
29441 pub fn regdata(&mut self) -> RegdataW<'_, GpvndctlSpec> {
29442 RegdataW::new(self, 0)
29443 }
29444 #[doc = "Bits 8:15"]
29445 #[inline(always)]
29446 pub fn vctrl(&mut self) -> VctrlW<'_, GpvndctlSpec> {
29447 VctrlW::new(self, 8)
29448 }
29449 #[doc = "Bits 16:21"]
29450 #[inline(always)]
29451 pub fn regaddr(&mut self) -> RegaddrW<'_, GpvndctlSpec> {
29452 RegaddrW::new(self, 16)
29453 }
29454 #[doc = "Bit 22"]
29455 #[inline(always)]
29456 pub fn regwr(&mut self) -> RegwrW<'_, GpvndctlSpec> {
29457 RegwrW::new(self, 22)
29458 }
29459 #[doc = "Bit 25"]
29460 #[inline(always)]
29461 pub fn newregreq(&mut self) -> NewregreqW<'_, GpvndctlSpec> {
29462 NewregreqW::new(self, 25)
29463 }
29464 #[doc = "Bit 26"]
29465 #[inline(always)]
29466 pub fn vstsbsy(&mut self) -> VstsbsyW<'_, GpvndctlSpec> {
29467 VstsbsyW::new(self, 26)
29468 }
29469 #[doc = "Bit 27"]
29470 #[inline(always)]
29471 pub fn vstsdone(&mut self) -> VstsdoneW<'_, GpvndctlSpec> {
29472 VstsdoneW::new(self, 27)
29473 }
29474 #[doc = "Bit 31"]
29475 #[inline(always)]
29476 pub fn disulpidrvr(&mut self) -> DisulpidrvrW<'_, GpvndctlSpec> {
29477 DisulpidrvrW::new(self, 31)
29478 }
29479 }
29480 #[doc = "DOTG_GPVNDCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gpvndctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpvndctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29481 pub struct GpvndctlSpec;
29482 impl crate::RegisterSpec for GpvndctlSpec {
29483 type Ux = u32;
29484 }
29485 #[doc = "`read()` method returns [`gpvndctl::R`](R) reader structure"]
29486 impl crate::Readable for GpvndctlSpec {}
29487 #[doc = "`write(|w| ..)` method takes [`gpvndctl::W`](W) writer structure"]
29488 impl crate::Writable for GpvndctlSpec {
29489 type Safety = crate::Unsafe;
29490 }
29491 #[doc = "`reset()` method sets GPVNDCTL to value 0"]
29492 impl crate::Resettable for GpvndctlSpec {}
29493 }
29494 #[doc = "GGPIO (rw) register accessor: DOTG_GGPIO\n\nYou can [`read`](crate::Reg::read) this register and get [`ggpio::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ggpio::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ggpio`] module"]
29495 #[doc(alias = "GGPIO")]
29496 pub type Ggpio = crate::Reg<ggpio::GgpioSpec>;
29497 #[doc = "DOTG_GGPIO"]
29498 pub mod ggpio {
29499 #[doc = "Register `GGPIO` reader"]
29500 pub type R = crate::R<GgpioSpec>;
29501 #[doc = "Register `GGPIO` writer"]
29502 pub type W = crate::W<GgpioSpec>;
29503 #[doc = "Field `GPI` reader - "]
29504 pub type GpiR = crate::FieldReader<u16>;
29505 #[doc = "Field `GPI` writer - "]
29506 pub type GpiW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
29507 #[doc = "Field `GPO` reader - "]
29508 pub type GpoR = crate::FieldReader<u16>;
29509 #[doc = "Field `GPO` writer - "]
29510 pub type GpoW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
29511 impl R {
29512 #[doc = "Bits 0:15"]
29513 #[inline(always)]
29514 pub fn gpi(&self) -> GpiR {
29515 GpiR::new((self.bits & 0xffff) as u16)
29516 }
29517 #[doc = "Bits 16:31"]
29518 #[inline(always)]
29519 pub fn gpo(&self) -> GpoR {
29520 GpoR::new(((self.bits >> 16) & 0xffff) as u16)
29521 }
29522 }
29523 impl W {
29524 #[doc = "Bits 0:15"]
29525 #[inline(always)]
29526 pub fn gpi(&mut self) -> GpiW<'_, GgpioSpec> {
29527 GpiW::new(self, 0)
29528 }
29529 #[doc = "Bits 16:31"]
29530 #[inline(always)]
29531 pub fn gpo(&mut self) -> GpoW<'_, GgpioSpec> {
29532 GpoW::new(self, 16)
29533 }
29534 }
29535 #[doc = "DOTG_GGPIO\n\nYou can [`read`](crate::Reg::read) this register and get [`ggpio::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ggpio::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29536 pub struct GgpioSpec;
29537 impl crate::RegisterSpec for GgpioSpec {
29538 type Ux = u32;
29539 }
29540 #[doc = "`read()` method returns [`ggpio::R`](R) reader structure"]
29541 impl crate::Readable for GgpioSpec {}
29542 #[doc = "`write(|w| ..)` method takes [`ggpio::W`](W) writer structure"]
29543 impl crate::Writable for GgpioSpec {
29544 type Safety = crate::Unsafe;
29545 }
29546 #[doc = "`reset()` method sets GGPIO to value 0"]
29547 impl crate::Resettable for GgpioSpec {}
29548 }
29549 #[doc = "GUID (rw) register accessor: DOTG_GUID\n\nYou can [`read`](crate::Reg::read) this register and get [`guid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`guid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@guid`] module"]
29550 #[doc(alias = "GUID")]
29551 pub type Guid = crate::Reg<guid::GuidSpec>;
29552 #[doc = "DOTG_GUID"]
29553 pub mod guid {
29554 #[doc = "Register `GUID` reader"]
29555 pub type R = crate::R<GuidSpec>;
29556 #[doc = "Register `GUID` writer"]
29557 pub type W = crate::W<GuidSpec>;
29558 impl core::fmt::Debug for R {
29559 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
29560 write!(f, "{}", self.bits())
29561 }
29562 }
29563 impl W {}
29564 #[doc = "DOTG_GUID\n\nYou can [`read`](crate::Reg::read) this register and get [`guid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`guid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29565 pub struct GuidSpec;
29566 impl crate::RegisterSpec for GuidSpec {
29567 type Ux = u32;
29568 }
29569 #[doc = "`read()` method returns [`guid::R`](R) reader structure"]
29570 impl crate::Readable for GuidSpec {}
29571 #[doc = "`write(|w| ..)` method takes [`guid::W`](W) writer structure"]
29572 impl crate::Writable for GuidSpec {
29573 type Safety = crate::Unsafe;
29574 }
29575 #[doc = "`reset()` method sets GUID to value 0"]
29576 impl crate::Resettable for GuidSpec {}
29577 }
29578 #[doc = "GSNPSID (rw) register accessor: DOTG_GSNPSID\n\nYou can [`read`](crate::Reg::read) this register and get [`gsnpsid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gsnpsid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gsnpsid`] module"]
29579 #[doc(alias = "GSNPSID")]
29580 pub type Gsnpsid = crate::Reg<gsnpsid::GsnpsidSpec>;
29581 #[doc = "DOTG_GSNPSID"]
29582 pub mod gsnpsid {
29583 #[doc = "Register `GSNPSID` reader"]
29584 pub type R = crate::R<GsnpsidSpec>;
29585 #[doc = "Register `GSNPSID` writer"]
29586 pub type W = crate::W<GsnpsidSpec>;
29587 impl core::fmt::Debug for R {
29588 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
29589 write!(f, "{}", self.bits())
29590 }
29591 }
29592 impl W {}
29593 #[doc = "DOTG_GSNPSID\n\nYou can [`read`](crate::Reg::read) this register and get [`gsnpsid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gsnpsid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29594 pub struct GsnpsidSpec;
29595 impl crate::RegisterSpec for GsnpsidSpec {
29596 type Ux = u32;
29597 }
29598 #[doc = "`read()` method returns [`gsnpsid::R`](R) reader structure"]
29599 impl crate::Readable for GsnpsidSpec {}
29600 #[doc = "`write(|w| ..)` method takes [`gsnpsid::W`](W) writer structure"]
29601 impl crate::Writable for GsnpsidSpec {
29602 type Safety = crate::Unsafe;
29603 }
29604 #[doc = "`reset()` method sets GSNPSID to value 0"]
29605 impl crate::Resettable for GsnpsidSpec {}
29606 }
29607 #[doc = "GHWCFG1 (rw) register accessor: DOTG_GHWCFG1\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ghwcfg1`] module"]
29608 #[doc(alias = "GHWCFG1")]
29609 pub type Ghwcfg1 = crate::Reg<ghwcfg1::Ghwcfg1Spec>;
29610 #[doc = "DOTG_GHWCFG1"]
29611 pub mod ghwcfg1 {
29612 #[doc = "Register `GHWCFG1` reader"]
29613 pub type R = crate::R<Ghwcfg1Spec>;
29614 #[doc = "Register `GHWCFG1` writer"]
29615 pub type W = crate::W<Ghwcfg1Spec>;
29616 impl core::fmt::Debug for R {
29617 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
29618 write!(f, "{}", self.bits())
29619 }
29620 }
29621 impl W {}
29622 #[doc = "DOTG_GHWCFG1\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29623 pub struct Ghwcfg1Spec;
29624 impl crate::RegisterSpec for Ghwcfg1Spec {
29625 type Ux = u32;
29626 }
29627 #[doc = "`read()` method returns [`ghwcfg1::R`](R) reader structure"]
29628 impl crate::Readable for Ghwcfg1Spec {}
29629 #[doc = "`write(|w| ..)` method takes [`ghwcfg1::W`](W) writer structure"]
29630 impl crate::Writable for Ghwcfg1Spec {
29631 type Safety = crate::Unsafe;
29632 }
29633 #[doc = "`reset()` method sets GHWCFG1 to value 0"]
29634 impl crate::Resettable for Ghwcfg1Spec {}
29635 }
29636 #[doc = "GHWCFG2 (rw) register accessor: DOTG_GHWCFG2\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ghwcfg2`] module"]
29637 #[doc(alias = "GHWCFG2")]
29638 pub type Ghwcfg2 = crate::Reg<ghwcfg2::Ghwcfg2Spec>;
29639 #[doc = "DOTG_GHWCFG2"]
29640 pub mod ghwcfg2 {
29641 #[doc = "Register `GHWCFG2` reader"]
29642 pub type R = crate::R<Ghwcfg2Spec>;
29643 #[doc = "Register `GHWCFG2` writer"]
29644 pub type W = crate::W<Ghwcfg2Spec>;
29645 #[doc = "Field `OTGMODE` reader - "]
29646 pub type OtgmodeR = crate::FieldReader;
29647 #[doc = "Field `OTGMODE` writer - "]
29648 pub type OtgmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29649 #[doc = "Field `OTGARCH` reader - "]
29650 pub type OtgarchR = crate::FieldReader;
29651 #[doc = "Field `OTGARCH` writer - "]
29652 pub type OtgarchW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29653 #[doc = "Field `SINGPNT` reader - "]
29654 pub type SingpntR = crate::BitReader;
29655 #[doc = "Field `SINGPNT` writer - "]
29656 pub type SingpntW<'a, REG> = crate::BitWriter<'a, REG>;
29657 #[doc = "Field `HSPHYTYPE` reader - "]
29658 pub type HsphytypeR = crate::FieldReader;
29659 #[doc = "Field `HSPHYTYPE` writer - "]
29660 pub type HsphytypeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29661 #[doc = "Field `FSPHYTYPE` reader - "]
29662 pub type FsphytypeR = crate::FieldReader;
29663 #[doc = "Field `FSPHYTYPE` writer - "]
29664 pub type FsphytypeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29665 #[doc = "Field `NUMDEVEPS` reader - "]
29666 pub type NumdevepsR = crate::FieldReader;
29667 #[doc = "Field `NUMDEVEPS` writer - "]
29668 pub type NumdevepsW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29669 #[doc = "Field `NUMHSTCHNL` reader - "]
29670 pub type NumhstchnlR = crate::FieldReader;
29671 #[doc = "Field `NUMHSTCHNL` writer - "]
29672 pub type NumhstchnlW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29673 #[doc = "Field `PERIOSUPPORT` reader - "]
29674 pub type PeriosupportR = crate::BitReader;
29675 #[doc = "Field `PERIOSUPPORT` writer - "]
29676 pub type PeriosupportW<'a, REG> = crate::BitWriter<'a, REG>;
29677 #[doc = "Field `DYNFIFOSIZING` reader - "]
29678 pub type DynfifosizingR = crate::BitReader;
29679 #[doc = "Field `DYNFIFOSIZING` writer - "]
29680 pub type DynfifosizingW<'a, REG> = crate::BitWriter<'a, REG>;
29681 #[doc = "Field `MPI` reader - "]
29682 pub type MpiR = crate::BitReader;
29683 #[doc = "Field `MPI` writer - "]
29684 pub type MpiW<'a, REG> = crate::BitWriter<'a, REG>;
29685 #[doc = "Field `NPTXQDEPTH` reader - "]
29686 pub type NptxqdepthR = crate::FieldReader;
29687 #[doc = "Field `NPTXQDEPTH` writer - "]
29688 pub type NptxqdepthW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29689 #[doc = "Field `PTXQDEPTH` reader - "]
29690 pub type PtxqdepthR = crate::FieldReader;
29691 #[doc = "Field `PTXQDEPTH` writer - "]
29692 pub type PtxqdepthW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29693 #[doc = "Field `TKNQDEPTH` reader - "]
29694 pub type TknqdepthR = crate::FieldReader;
29695 #[doc = "Field `TKNQDEPTH` writer - "]
29696 pub type TknqdepthW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
29697 impl R {
29698 #[doc = "Bits 0:2"]
29699 #[inline(always)]
29700 pub fn otgmode(&self) -> OtgmodeR {
29701 OtgmodeR::new((self.bits & 7) as u8)
29702 }
29703 #[doc = "Bits 3:4"]
29704 #[inline(always)]
29705 pub fn otgarch(&self) -> OtgarchR {
29706 OtgarchR::new(((self.bits >> 3) & 3) as u8)
29707 }
29708 #[doc = "Bit 5"]
29709 #[inline(always)]
29710 pub fn singpnt(&self) -> SingpntR {
29711 SingpntR::new(((self.bits >> 5) & 1) != 0)
29712 }
29713 #[doc = "Bits 6:7"]
29714 #[inline(always)]
29715 pub fn hsphytype(&self) -> HsphytypeR {
29716 HsphytypeR::new(((self.bits >> 6) & 3) as u8)
29717 }
29718 #[doc = "Bits 8:9"]
29719 #[inline(always)]
29720 pub fn fsphytype(&self) -> FsphytypeR {
29721 FsphytypeR::new(((self.bits >> 8) & 3) as u8)
29722 }
29723 #[doc = "Bits 10:13"]
29724 #[inline(always)]
29725 pub fn numdeveps(&self) -> NumdevepsR {
29726 NumdevepsR::new(((self.bits >> 10) & 0x0f) as u8)
29727 }
29728 #[doc = "Bits 14:17"]
29729 #[inline(always)]
29730 pub fn numhstchnl(&self) -> NumhstchnlR {
29731 NumhstchnlR::new(((self.bits >> 14) & 0x0f) as u8)
29732 }
29733 #[doc = "Bit 18"]
29734 #[inline(always)]
29735 pub fn periosupport(&self) -> PeriosupportR {
29736 PeriosupportR::new(((self.bits >> 18) & 1) != 0)
29737 }
29738 #[doc = "Bit 19"]
29739 #[inline(always)]
29740 pub fn dynfifosizing(&self) -> DynfifosizingR {
29741 DynfifosizingR::new(((self.bits >> 19) & 1) != 0)
29742 }
29743 #[doc = "Bit 20"]
29744 #[inline(always)]
29745 pub fn mpi(&self) -> MpiR {
29746 MpiR::new(((self.bits >> 20) & 1) != 0)
29747 }
29748 #[doc = "Bits 22:23"]
29749 #[inline(always)]
29750 pub fn nptxqdepth(&self) -> NptxqdepthR {
29751 NptxqdepthR::new(((self.bits >> 22) & 3) as u8)
29752 }
29753 #[doc = "Bits 24:25"]
29754 #[inline(always)]
29755 pub fn ptxqdepth(&self) -> PtxqdepthR {
29756 PtxqdepthR::new(((self.bits >> 24) & 3) as u8)
29757 }
29758 #[doc = "Bits 26:30"]
29759 #[inline(always)]
29760 pub fn tknqdepth(&self) -> TknqdepthR {
29761 TknqdepthR::new(((self.bits >> 26) & 0x1f) as u8)
29762 }
29763 }
29764 impl W {
29765 #[doc = "Bits 0:2"]
29766 #[inline(always)]
29767 pub fn otgmode(&mut self) -> OtgmodeW<'_, Ghwcfg2Spec> {
29768 OtgmodeW::new(self, 0)
29769 }
29770 #[doc = "Bits 3:4"]
29771 #[inline(always)]
29772 pub fn otgarch(&mut self) -> OtgarchW<'_, Ghwcfg2Spec> {
29773 OtgarchW::new(self, 3)
29774 }
29775 #[doc = "Bit 5"]
29776 #[inline(always)]
29777 pub fn singpnt(&mut self) -> SingpntW<'_, Ghwcfg2Spec> {
29778 SingpntW::new(self, 5)
29779 }
29780 #[doc = "Bits 6:7"]
29781 #[inline(always)]
29782 pub fn hsphytype(&mut self) -> HsphytypeW<'_, Ghwcfg2Spec> {
29783 HsphytypeW::new(self, 6)
29784 }
29785 #[doc = "Bits 8:9"]
29786 #[inline(always)]
29787 pub fn fsphytype(&mut self) -> FsphytypeW<'_, Ghwcfg2Spec> {
29788 FsphytypeW::new(self, 8)
29789 }
29790 #[doc = "Bits 10:13"]
29791 #[inline(always)]
29792 pub fn numdeveps(&mut self) -> NumdevepsW<'_, Ghwcfg2Spec> {
29793 NumdevepsW::new(self, 10)
29794 }
29795 #[doc = "Bits 14:17"]
29796 #[inline(always)]
29797 pub fn numhstchnl(&mut self) -> NumhstchnlW<'_, Ghwcfg2Spec> {
29798 NumhstchnlW::new(self, 14)
29799 }
29800 #[doc = "Bit 18"]
29801 #[inline(always)]
29802 pub fn periosupport(&mut self) -> PeriosupportW<'_, Ghwcfg2Spec> {
29803 PeriosupportW::new(self, 18)
29804 }
29805 #[doc = "Bit 19"]
29806 #[inline(always)]
29807 pub fn dynfifosizing(&mut self) -> DynfifosizingW<'_, Ghwcfg2Spec> {
29808 DynfifosizingW::new(self, 19)
29809 }
29810 #[doc = "Bit 20"]
29811 #[inline(always)]
29812 pub fn mpi(&mut self) -> MpiW<'_, Ghwcfg2Spec> {
29813 MpiW::new(self, 20)
29814 }
29815 #[doc = "Bits 22:23"]
29816 #[inline(always)]
29817 pub fn nptxqdepth(&mut self) -> NptxqdepthW<'_, Ghwcfg2Spec> {
29818 NptxqdepthW::new(self, 22)
29819 }
29820 #[doc = "Bits 24:25"]
29821 #[inline(always)]
29822 pub fn ptxqdepth(&mut self) -> PtxqdepthW<'_, Ghwcfg2Spec> {
29823 PtxqdepthW::new(self, 24)
29824 }
29825 #[doc = "Bits 26:30"]
29826 #[inline(always)]
29827 pub fn tknqdepth(&mut self) -> TknqdepthW<'_, Ghwcfg2Spec> {
29828 TknqdepthW::new(self, 26)
29829 }
29830 }
29831 #[doc = "DOTG_GHWCFG2\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29832 pub struct Ghwcfg2Spec;
29833 impl crate::RegisterSpec for Ghwcfg2Spec {
29834 type Ux = u32;
29835 }
29836 #[doc = "`read()` method returns [`ghwcfg2::R`](R) reader structure"]
29837 impl crate::Readable for Ghwcfg2Spec {}
29838 #[doc = "`write(|w| ..)` method takes [`ghwcfg2::W`](W) writer structure"]
29839 impl crate::Writable for Ghwcfg2Spec {
29840 type Safety = crate::Unsafe;
29841 }
29842 #[doc = "`reset()` method sets GHWCFG2 to value 0"]
29843 impl crate::Resettable for Ghwcfg2Spec {}
29844 }
29845 #[doc = "GHWCFG3 (rw) register accessor: DOTG_GHWCFG3\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ghwcfg3`] module"]
29846 #[doc(alias = "GHWCFG3")]
29847 pub type Ghwcfg3 = crate::Reg<ghwcfg3::Ghwcfg3Spec>;
29848 #[doc = "DOTG_GHWCFG3"]
29849 pub mod ghwcfg3 {
29850 #[doc = "Register `GHWCFG3` reader"]
29851 pub type R = crate::R<Ghwcfg3Spec>;
29852 #[doc = "Register `GHWCFG3` writer"]
29853 pub type W = crate::W<Ghwcfg3Spec>;
29854 #[doc = "Field `XFERSIZEWIDTH` reader - "]
29855 pub type XfersizewidthR = crate::FieldReader;
29856 #[doc = "Field `XFERSIZEWIDTH` writer - "]
29857 pub type XfersizewidthW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29858 #[doc = "Field `PKTSIZEWIDTH` reader - "]
29859 pub type PktsizewidthR = crate::FieldReader;
29860 #[doc = "Field `PKTSIZEWIDTH` writer - "]
29861 pub type PktsizewidthW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29862 #[doc = "Field `OTGEN` reader - "]
29863 pub type OtgenR = crate::BitReader;
29864 #[doc = "Field `OTGEN` writer - "]
29865 pub type OtgenW<'a, REG> = crate::BitWriter<'a, REG>;
29866 #[doc = "Field `I2CINTSEL` reader - "]
29867 pub type I2cintselR = crate::BitReader;
29868 #[doc = "Field `I2CINTSEL` writer - "]
29869 pub type I2cintselW<'a, REG> = crate::BitWriter<'a, REG>;
29870 #[doc = "Field `VNDCTLSUPT` reader - "]
29871 pub type VndctlsuptR = crate::BitReader;
29872 #[doc = "Field `VNDCTLSUPT` writer - "]
29873 pub type VndctlsuptW<'a, REG> = crate::BitWriter<'a, REG>;
29874 #[doc = "Field `OPTFEATURE` reader - "]
29875 pub type OptfeatureR = crate::BitReader;
29876 #[doc = "Field `OPTFEATURE` writer - "]
29877 pub type OptfeatureW<'a, REG> = crate::BitWriter<'a, REG>;
29878 #[doc = "Field `RSTTYPE` reader - "]
29879 pub type RsttypeR = crate::BitReader;
29880 #[doc = "Field `RSTTYPE` writer - "]
29881 pub type RsttypeW<'a, REG> = crate::BitWriter<'a, REG>;
29882 #[doc = "Field `DFIFODEPTH` reader - "]
29883 pub type DfifodepthR = crate::FieldReader<u16>;
29884 #[doc = "Field `DFIFODEPTH` writer - "]
29885 pub type DfifodepthW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
29886 impl R {
29887 #[doc = "Bits 0:3"]
29888 #[inline(always)]
29889 pub fn xfersizewidth(&self) -> XfersizewidthR {
29890 XfersizewidthR::new((self.bits & 0x0f) as u8)
29891 }
29892 #[doc = "Bits 4:6"]
29893 #[inline(always)]
29894 pub fn pktsizewidth(&self) -> PktsizewidthR {
29895 PktsizewidthR::new(((self.bits >> 4) & 7) as u8)
29896 }
29897 #[doc = "Bit 7"]
29898 #[inline(always)]
29899 pub fn otgen(&self) -> OtgenR {
29900 OtgenR::new(((self.bits >> 7) & 1) != 0)
29901 }
29902 #[doc = "Bit 8"]
29903 #[inline(always)]
29904 pub fn i2cintsel(&self) -> I2cintselR {
29905 I2cintselR::new(((self.bits >> 8) & 1) != 0)
29906 }
29907 #[doc = "Bit 9"]
29908 #[inline(always)]
29909 pub fn vndctlsupt(&self) -> VndctlsuptR {
29910 VndctlsuptR::new(((self.bits >> 9) & 1) != 0)
29911 }
29912 #[doc = "Bit 10"]
29913 #[inline(always)]
29914 pub fn optfeature(&self) -> OptfeatureR {
29915 OptfeatureR::new(((self.bits >> 10) & 1) != 0)
29916 }
29917 #[doc = "Bit 11"]
29918 #[inline(always)]
29919 pub fn rsttype(&self) -> RsttypeR {
29920 RsttypeR::new(((self.bits >> 11) & 1) != 0)
29921 }
29922 #[doc = "Bits 16:31"]
29923 #[inline(always)]
29924 pub fn dfifodepth(&self) -> DfifodepthR {
29925 DfifodepthR::new(((self.bits >> 16) & 0xffff) as u16)
29926 }
29927 }
29928 impl W {
29929 #[doc = "Bits 0:3"]
29930 #[inline(always)]
29931 pub fn xfersizewidth(&mut self) -> XfersizewidthW<'_, Ghwcfg3Spec> {
29932 XfersizewidthW::new(self, 0)
29933 }
29934 #[doc = "Bits 4:6"]
29935 #[inline(always)]
29936 pub fn pktsizewidth(&mut self) -> PktsizewidthW<'_, Ghwcfg3Spec> {
29937 PktsizewidthW::new(self, 4)
29938 }
29939 #[doc = "Bit 7"]
29940 #[inline(always)]
29941 pub fn otgen(&mut self) -> OtgenW<'_, Ghwcfg3Spec> {
29942 OtgenW::new(self, 7)
29943 }
29944 #[doc = "Bit 8"]
29945 #[inline(always)]
29946 pub fn i2cintsel(&mut self) -> I2cintselW<'_, Ghwcfg3Spec> {
29947 I2cintselW::new(self, 8)
29948 }
29949 #[doc = "Bit 9"]
29950 #[inline(always)]
29951 pub fn vndctlsupt(&mut self) -> VndctlsuptW<'_, Ghwcfg3Spec> {
29952 VndctlsuptW::new(self, 9)
29953 }
29954 #[doc = "Bit 10"]
29955 #[inline(always)]
29956 pub fn optfeature(&mut self) -> OptfeatureW<'_, Ghwcfg3Spec> {
29957 OptfeatureW::new(self, 10)
29958 }
29959 #[doc = "Bit 11"]
29960 #[inline(always)]
29961 pub fn rsttype(&mut self) -> RsttypeW<'_, Ghwcfg3Spec> {
29962 RsttypeW::new(self, 11)
29963 }
29964 #[doc = "Bits 16:31"]
29965 #[inline(always)]
29966 pub fn dfifodepth(&mut self) -> DfifodepthW<'_, Ghwcfg3Spec> {
29967 DfifodepthW::new(self, 16)
29968 }
29969 }
29970 #[doc = "DOTG_GHWCFG3\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29971 pub struct Ghwcfg3Spec;
29972 impl crate::RegisterSpec for Ghwcfg3Spec {
29973 type Ux = u32;
29974 }
29975 #[doc = "`read()` method returns [`ghwcfg3::R`](R) reader structure"]
29976 impl crate::Readable for Ghwcfg3Spec {}
29977 #[doc = "`write(|w| ..)` method takes [`ghwcfg3::W`](W) writer structure"]
29978 impl crate::Writable for Ghwcfg3Spec {
29979 type Safety = crate::Unsafe;
29980 }
29981 #[doc = "`reset()` method sets GHWCFG3 to value 0"]
29982 impl crate::Resettable for Ghwcfg3Spec {}
29983 }
29984 #[doc = "GHWCFG4 (rw) register accessor: DOTG_GHWCFG4\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ghwcfg4`] module"]
29985 #[doc(alias = "GHWCFG4")]
29986 pub type Ghwcfg4 = crate::Reg<ghwcfg4::Ghwcfg4Spec>;
29987 #[doc = "DOTG_GHWCFG4"]
29988 pub mod ghwcfg4 {
29989 #[doc = "Register `GHWCFG4` reader"]
29990 pub type R = crate::R<Ghwcfg4Spec>;
29991 #[doc = "Register `GHWCFG4` writer"]
29992 pub type W = crate::W<Ghwcfg4Spec>;
29993 #[doc = "Field `NUMDEVPERIOEPS` reader - "]
29994 pub type NumdevperioepsR = crate::FieldReader;
29995 #[doc = "Field `NUMDEVPERIOEPS` writer - "]
29996 pub type NumdevperioepsW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29997 #[doc = "Field `ENABLEPWROPT` reader - "]
29998 pub type EnablepwroptR = crate::BitReader;
29999 #[doc = "Field `ENABLEPWROPT` writer - "]
30000 pub type EnablepwroptW<'a, REG> = crate::BitWriter<'a, REG>;
30001 #[doc = "Field `AHBFREQ` reader - "]
30002 pub type AhbfreqR = crate::BitReader;
30003 #[doc = "Field `AHBFREQ` writer - "]
30004 pub type AhbfreqW<'a, REG> = crate::BitWriter<'a, REG>;
30005 #[doc = "Field `PHYDATAWIDTH` reader - "]
30006 pub type PhydatawidthR = crate::FieldReader;
30007 #[doc = "Field `PHYDATAWIDTH` writer - "]
30008 pub type PhydatawidthW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
30009 #[doc = "Field `NUMCTLEPS` reader - "]
30010 pub type NumctlepsR = crate::FieldReader;
30011 #[doc = "Field `NUMCTLEPS` writer - "]
30012 pub type NumctlepsW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
30013 #[doc = "Field `IDDGFLTR` reader - "]
30014 pub type IddgfltrR = crate::BitReader;
30015 #[doc = "Field `IDDGFLTR` writer - "]
30016 pub type IddgfltrW<'a, REG> = crate::BitWriter<'a, REG>;
30017 #[doc = "Field `VBUSVALIDFLTR` reader - "]
30018 pub type VbusvalidfltrR = crate::BitReader;
30019 #[doc = "Field `VBUSVALIDFLTR` writer - "]
30020 pub type VbusvalidfltrW<'a, REG> = crate::BitWriter<'a, REG>;
30021 #[doc = "Field `AVALIDFLTR` reader - "]
30022 pub type AvalidfltrR = crate::BitReader;
30023 #[doc = "Field `AVALIDFLTR` writer - "]
30024 pub type AvalidfltrW<'a, REG> = crate::BitWriter<'a, REG>;
30025 #[doc = "Field `BVALIDFLTR` reader - "]
30026 pub type BvalidfltrR = crate::BitReader;
30027 #[doc = "Field `BVALIDFLTR` writer - "]
30028 pub type BvalidfltrW<'a, REG> = crate::BitWriter<'a, REG>;
30029 #[doc = "Field `SESSENDFLTR` reader - "]
30030 pub type SessendfltrR = crate::BitReader;
30031 #[doc = "Field `SESSENDFLTR` writer - "]
30032 pub type SessendfltrW<'a, REG> = crate::BitWriter<'a, REG>;
30033 impl R {
30034 #[doc = "Bits 0:3"]
30035 #[inline(always)]
30036 pub fn numdevperioeps(&self) -> NumdevperioepsR {
30037 NumdevperioepsR::new((self.bits & 0x0f) as u8)
30038 }
30039 #[doc = "Bit 4"]
30040 #[inline(always)]
30041 pub fn enablepwropt(&self) -> EnablepwroptR {
30042 EnablepwroptR::new(((self.bits >> 4) & 1) != 0)
30043 }
30044 #[doc = "Bit 5"]
30045 #[inline(always)]
30046 pub fn ahbfreq(&self) -> AhbfreqR {
30047 AhbfreqR::new(((self.bits >> 5) & 1) != 0)
30048 }
30049 #[doc = "Bits 14:15"]
30050 #[inline(always)]
30051 pub fn phydatawidth(&self) -> PhydatawidthR {
30052 PhydatawidthR::new(((self.bits >> 14) & 3) as u8)
30053 }
30054 #[doc = "Bits 16:19"]
30055 #[inline(always)]
30056 pub fn numctleps(&self) -> NumctlepsR {
30057 NumctlepsR::new(((self.bits >> 16) & 0x0f) as u8)
30058 }
30059 #[doc = "Bit 20"]
30060 #[inline(always)]
30061 pub fn iddgfltr(&self) -> IddgfltrR {
30062 IddgfltrR::new(((self.bits >> 20) & 1) != 0)
30063 }
30064 #[doc = "Bit 21"]
30065 #[inline(always)]
30066 pub fn vbusvalidfltr(&self) -> VbusvalidfltrR {
30067 VbusvalidfltrR::new(((self.bits >> 21) & 1) != 0)
30068 }
30069 #[doc = "Bit 22"]
30070 #[inline(always)]
30071 pub fn avalidfltr(&self) -> AvalidfltrR {
30072 AvalidfltrR::new(((self.bits >> 22) & 1) != 0)
30073 }
30074 #[doc = "Bit 23"]
30075 #[inline(always)]
30076 pub fn bvalidfltr(&self) -> BvalidfltrR {
30077 BvalidfltrR::new(((self.bits >> 23) & 1) != 0)
30078 }
30079 #[doc = "Bit 24"]
30080 #[inline(always)]
30081 pub fn sessendfltr(&self) -> SessendfltrR {
30082 SessendfltrR::new(((self.bits >> 24) & 1) != 0)
30083 }
30084 }
30085 impl W {
30086 #[doc = "Bits 0:3"]
30087 #[inline(always)]
30088 pub fn numdevperioeps(&mut self) -> NumdevperioepsW<'_, Ghwcfg4Spec> {
30089 NumdevperioepsW::new(self, 0)
30090 }
30091 #[doc = "Bit 4"]
30092 #[inline(always)]
30093 pub fn enablepwropt(&mut self) -> EnablepwroptW<'_, Ghwcfg4Spec> {
30094 EnablepwroptW::new(self, 4)
30095 }
30096 #[doc = "Bit 5"]
30097 #[inline(always)]
30098 pub fn ahbfreq(&mut self) -> AhbfreqW<'_, Ghwcfg4Spec> {
30099 AhbfreqW::new(self, 5)
30100 }
30101 #[doc = "Bits 14:15"]
30102 #[inline(always)]
30103 pub fn phydatawidth(&mut self) -> PhydatawidthW<'_, Ghwcfg4Spec> {
30104 PhydatawidthW::new(self, 14)
30105 }
30106 #[doc = "Bits 16:19"]
30107 #[inline(always)]
30108 pub fn numctleps(&mut self) -> NumctlepsW<'_, Ghwcfg4Spec> {
30109 NumctlepsW::new(self, 16)
30110 }
30111 #[doc = "Bit 20"]
30112 #[inline(always)]
30113 pub fn iddgfltr(&mut self) -> IddgfltrW<'_, Ghwcfg4Spec> {
30114 IddgfltrW::new(self, 20)
30115 }
30116 #[doc = "Bit 21"]
30117 #[inline(always)]
30118 pub fn vbusvalidfltr(&mut self) -> VbusvalidfltrW<'_, Ghwcfg4Spec> {
30119 VbusvalidfltrW::new(self, 21)
30120 }
30121 #[doc = "Bit 22"]
30122 #[inline(always)]
30123 pub fn avalidfltr(&mut self) -> AvalidfltrW<'_, Ghwcfg4Spec> {
30124 AvalidfltrW::new(self, 22)
30125 }
30126 #[doc = "Bit 23"]
30127 #[inline(always)]
30128 pub fn bvalidfltr(&mut self) -> BvalidfltrW<'_, Ghwcfg4Spec> {
30129 BvalidfltrW::new(self, 23)
30130 }
30131 #[doc = "Bit 24"]
30132 #[inline(always)]
30133 pub fn sessendfltr(&mut self) -> SessendfltrW<'_, Ghwcfg4Spec> {
30134 SessendfltrW::new(self, 24)
30135 }
30136 }
30137 #[doc = "DOTG_GHWCFG4\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30138 pub struct Ghwcfg4Spec;
30139 impl crate::RegisterSpec for Ghwcfg4Spec {
30140 type Ux = u32;
30141 }
30142 #[doc = "`read()` method returns [`ghwcfg4::R`](R) reader structure"]
30143 impl crate::Readable for Ghwcfg4Spec {}
30144 #[doc = "`write(|w| ..)` method takes [`ghwcfg4::W`](W) writer structure"]
30145 impl crate::Writable for Ghwcfg4Spec {
30146 type Safety = crate::Unsafe;
30147 }
30148 #[doc = "`reset()` method sets GHWCFG4 to value 0"]
30149 impl crate::Resettable for Ghwcfg4Spec {}
30150 }
30151 #[doc = "GLPMCFG (rw) register accessor: DOTG_GLPMCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`glpmcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`glpmcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@glpmcfg`] module"]
30152 #[doc(alias = "GLPMCFG")]
30153 pub type Glpmcfg = crate::Reg<glpmcfg::GlpmcfgSpec>;
30154 #[doc = "DOTG_GLPMCFG"]
30155 pub mod glpmcfg {
30156 #[doc = "Register `GLPMCFG` reader"]
30157 pub type R = crate::R<GlpmcfgSpec>;
30158 #[doc = "Register `GLPMCFG` writer"]
30159 pub type W = crate::W<GlpmcfgSpec>;
30160 #[doc = "Field `HSIC_CONN` reader - "]
30161 pub type HsicConnR = crate::BitReader;
30162 #[doc = "Field `HSIC_CONN` writer - "]
30163 pub type HsicConnW<'a, REG> = crate::BitWriter<'a, REG>;
30164 impl R {
30165 #[doc = "Bit 30"]
30166 #[inline(always)]
30167 pub fn hsic_conn(&self) -> HsicConnR {
30168 HsicConnR::new(((self.bits >> 30) & 1) != 0)
30169 }
30170 }
30171 impl W {
30172 #[doc = "Bit 30"]
30173 #[inline(always)]
30174 pub fn hsic_conn(&mut self) -> HsicConnW<'_, GlpmcfgSpec> {
30175 HsicConnW::new(self, 30)
30176 }
30177 }
30178 #[doc = "DOTG_GLPMCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`glpmcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`glpmcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30179 pub struct GlpmcfgSpec;
30180 impl crate::RegisterSpec for GlpmcfgSpec {
30181 type Ux = u32;
30182 }
30183 #[doc = "`read()` method returns [`glpmcfg::R`](R) reader structure"]
30184 impl crate::Readable for GlpmcfgSpec {}
30185 #[doc = "`write(|w| ..)` method takes [`glpmcfg::W`](W) writer structure"]
30186 impl crate::Writable for GlpmcfgSpec {
30187 type Safety = crate::Unsafe;
30188 }
30189 #[doc = "`reset()` method sets GLPMCFG to value 0"]
30190 impl crate::Resettable for GlpmcfgSpec {}
30191 }
30192 #[doc = "GPWRDN (rw) register accessor: DOTG_GPWRDN\n\nYou can [`read`](crate::Reg::read) this register and get [`gpwrdn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpwrdn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpwrdn`] module"]
30193 #[doc(alias = "GPWRDN")]
30194 pub type Gpwrdn = crate::Reg<gpwrdn::GpwrdnSpec>;
30195 #[doc = "DOTG_GPWRDN"]
30196 pub mod gpwrdn {
30197 #[doc = "Register `GPWRDN` reader"]
30198 pub type R = crate::R<GpwrdnSpec>;
30199 #[doc = "Register `GPWRDN` writer"]
30200 pub type W = crate::W<GpwrdnSpec>;
30201 #[doc = "Field `PMU_IRQ_SEL` reader - "]
30202 pub type PmuIrqSelR = crate::BitReader;
30203 #[doc = "Field `PMU_IRQ_SEL` writer - "]
30204 pub type PmuIrqSelW<'a, REG> = crate::BitWriter<'a, REG>;
30205 #[doc = "Field `PMU_ACTIVE` reader - "]
30206 pub type PmuActiveR = crate::BitReader;
30207 #[doc = "Field `PMU_ACTIVE` writer - "]
30208 pub type PmuActiveW<'a, REG> = crate::BitWriter<'a, REG>;
30209 #[doc = "Field `RESTORE` reader - "]
30210 pub type RestoreR = crate::BitReader;
30211 #[doc = "Field `RESTORE` writer - "]
30212 pub type RestoreW<'a, REG> = crate::BitWriter<'a, REG>;
30213 #[doc = "Field `POWER_DOWN_CLAMP` reader - "]
30214 pub type PowerDownClampR = crate::BitReader;
30215 #[doc = "Field `POWER_DOWN_CLAMP` writer - "]
30216 pub type PowerDownClampW<'a, REG> = crate::BitWriter<'a, REG>;
30217 #[doc = "Field `POWER_DOWN_RST` reader - "]
30218 pub type PowerDownRstR = crate::BitReader;
30219 #[doc = "Field `POWER_DOWN_RST` writer - "]
30220 pub type PowerDownRstW<'a, REG> = crate::BitWriter<'a, REG>;
30221 #[doc = "Field `POWER_DOWN` reader - "]
30222 pub type PowerDownR = crate::BitReader;
30223 #[doc = "Field `POWER_DOWN` writer - "]
30224 pub type PowerDownW<'a, REG> = crate::BitWriter<'a, REG>;
30225 #[doc = "Field `DISABLE_VBUS` reader - "]
30226 pub type DisableVbusR = crate::BitReader;
30227 #[doc = "Field `DISABLE_VBUS` writer - "]
30228 pub type DisableVbusW<'a, REG> = crate::BitWriter<'a, REG>;
30229 #[doc = "Field `LINESTATE` reader - "]
30230 pub type LinestateR = crate::BitReader;
30231 #[doc = "Field `LINESTATE` writer - "]
30232 pub type LinestateW<'a, REG> = crate::BitWriter<'a, REG>;
30233 #[doc = "Field `LINESTATE_INT` reader - "]
30234 pub type LinestateIntR = crate::BitReader;
30235 #[doc = "Field `LINESTATE_INT` writer - "]
30236 pub type LinestateIntW<'a, REG> = crate::BitWriter<'a, REG>;
30237 #[doc = "Field `RESETDET` reader - "]
30238 pub type ResetdetR = crate::BitReader;
30239 #[doc = "Field `RESETDET` writer - "]
30240 pub type ResetdetW<'a, REG> = crate::BitWriter<'a, REG>;
30241 #[doc = "Field `RESETDET_INT` reader - "]
30242 pub type ResetdetIntR = crate::BitReader;
30243 #[doc = "Field `RESETDET_INT` writer - "]
30244 pub type ResetdetIntW<'a, REG> = crate::BitWriter<'a, REG>;
30245 #[doc = "Field `DISCONN` reader - "]
30246 pub type DisconnR = crate::BitReader;
30247 #[doc = "Field `DISCONN` writer - "]
30248 pub type DisconnW<'a, REG> = crate::BitWriter<'a, REG>;
30249 #[doc = "Field `DISCONN_INT` reader - "]
30250 pub type DisconnIntR = crate::BitReader;
30251 #[doc = "Field `DISCONN_INT` writer - "]
30252 pub type DisconnIntW<'a, REG> = crate::BitWriter<'a, REG>;
30253 #[doc = "Field `CONNDET` reader - "]
30254 pub type ConndetR = crate::BitReader;
30255 #[doc = "Field `CONNDET` writer - "]
30256 pub type ConndetW<'a, REG> = crate::BitWriter<'a, REG>;
30257 #[doc = "Field `CONNDET_INT` reader - "]
30258 pub type ConndetIntR = crate::BitReader;
30259 #[doc = "Field `CONNDET_INT` writer - "]
30260 pub type ConndetIntW<'a, REG> = crate::BitWriter<'a, REG>;
30261 #[doc = "Field `IDDIG` reader - "]
30262 pub type IddigR = crate::BitReader;
30263 #[doc = "Field `IDDIG` writer - "]
30264 pub type IddigW<'a, REG> = crate::BitWriter<'a, REG>;
30265 #[doc = "Field `BVALID` reader - "]
30266 pub type BvalidR = crate::BitReader;
30267 #[doc = "Field `BVALID` writer - "]
30268 pub type BvalidW<'a, REG> = crate::BitWriter<'a, REG>;
30269 impl R {
30270 #[doc = "Bit 0"]
30271 #[inline(always)]
30272 pub fn pmu_irq_sel(&self) -> PmuIrqSelR {
30273 PmuIrqSelR::new((self.bits & 1) != 0)
30274 }
30275 #[doc = "Bit 1"]
30276 #[inline(always)]
30277 pub fn pmu_active(&self) -> PmuActiveR {
30278 PmuActiveR::new(((self.bits >> 1) & 1) != 0)
30279 }
30280 #[doc = "Bit 2"]
30281 #[inline(always)]
30282 pub fn restore(&self) -> RestoreR {
30283 RestoreR::new(((self.bits >> 2) & 1) != 0)
30284 }
30285 #[doc = "Bit 3"]
30286 #[inline(always)]
30287 pub fn power_down_clamp(&self) -> PowerDownClampR {
30288 PowerDownClampR::new(((self.bits >> 3) & 1) != 0)
30289 }
30290 #[doc = "Bit 4"]
30291 #[inline(always)]
30292 pub fn power_down_rst(&self) -> PowerDownRstR {
30293 PowerDownRstR::new(((self.bits >> 4) & 1) != 0)
30294 }
30295 #[doc = "Bit 5"]
30296 #[inline(always)]
30297 pub fn power_down(&self) -> PowerDownR {
30298 PowerDownR::new(((self.bits >> 5) & 1) != 0)
30299 }
30300 #[doc = "Bit 6"]
30301 #[inline(always)]
30302 pub fn disable_vbus(&self) -> DisableVbusR {
30303 DisableVbusR::new(((self.bits >> 6) & 1) != 0)
30304 }
30305 #[doc = "Bit 7"]
30306 #[inline(always)]
30307 pub fn linestate(&self) -> LinestateR {
30308 LinestateR::new(((self.bits >> 7) & 1) != 0)
30309 }
30310 #[doc = "Bit 8"]
30311 #[inline(always)]
30312 pub fn linestate_int(&self) -> LinestateIntR {
30313 LinestateIntR::new(((self.bits >> 8) & 1) != 0)
30314 }
30315 #[doc = "Bit 9"]
30316 #[inline(always)]
30317 pub fn resetdet(&self) -> ResetdetR {
30318 ResetdetR::new(((self.bits >> 9) & 1) != 0)
30319 }
30320 #[doc = "Bit 10"]
30321 #[inline(always)]
30322 pub fn resetdet_int(&self) -> ResetdetIntR {
30323 ResetdetIntR::new(((self.bits >> 10) & 1) != 0)
30324 }
30325 #[doc = "Bit 11"]
30326 #[inline(always)]
30327 pub fn disconn(&self) -> DisconnR {
30328 DisconnR::new(((self.bits >> 11) & 1) != 0)
30329 }
30330 #[doc = "Bit 12"]
30331 #[inline(always)]
30332 pub fn disconn_int(&self) -> DisconnIntR {
30333 DisconnIntR::new(((self.bits >> 12) & 1) != 0)
30334 }
30335 #[doc = "Bit 13"]
30336 #[inline(always)]
30337 pub fn conndet(&self) -> ConndetR {
30338 ConndetR::new(((self.bits >> 13) & 1) != 0)
30339 }
30340 #[doc = "Bit 14"]
30341 #[inline(always)]
30342 pub fn conndet_int(&self) -> ConndetIntR {
30343 ConndetIntR::new(((self.bits >> 14) & 1) != 0)
30344 }
30345 #[doc = "Bit 21"]
30346 #[inline(always)]
30347 pub fn iddig(&self) -> IddigR {
30348 IddigR::new(((self.bits >> 21) & 1) != 0)
30349 }
30350 #[doc = "Bit 22"]
30351 #[inline(always)]
30352 pub fn bvalid(&self) -> BvalidR {
30353 BvalidR::new(((self.bits >> 22) & 1) != 0)
30354 }
30355 }
30356 impl W {
30357 #[doc = "Bit 0"]
30358 #[inline(always)]
30359 pub fn pmu_irq_sel(&mut self) -> PmuIrqSelW<'_, GpwrdnSpec> {
30360 PmuIrqSelW::new(self, 0)
30361 }
30362 #[doc = "Bit 1"]
30363 #[inline(always)]
30364 pub fn pmu_active(&mut self) -> PmuActiveW<'_, GpwrdnSpec> {
30365 PmuActiveW::new(self, 1)
30366 }
30367 #[doc = "Bit 2"]
30368 #[inline(always)]
30369 pub fn restore(&mut self) -> RestoreW<'_, GpwrdnSpec> {
30370 RestoreW::new(self, 2)
30371 }
30372 #[doc = "Bit 3"]
30373 #[inline(always)]
30374 pub fn power_down_clamp(&mut self) -> PowerDownClampW<'_, GpwrdnSpec> {
30375 PowerDownClampW::new(self, 3)
30376 }
30377 #[doc = "Bit 4"]
30378 #[inline(always)]
30379 pub fn power_down_rst(&mut self) -> PowerDownRstW<'_, GpwrdnSpec> {
30380 PowerDownRstW::new(self, 4)
30381 }
30382 #[doc = "Bit 5"]
30383 #[inline(always)]
30384 pub fn power_down(&mut self) -> PowerDownW<'_, GpwrdnSpec> {
30385 PowerDownW::new(self, 5)
30386 }
30387 #[doc = "Bit 6"]
30388 #[inline(always)]
30389 pub fn disable_vbus(&mut self) -> DisableVbusW<'_, GpwrdnSpec> {
30390 DisableVbusW::new(self, 6)
30391 }
30392 #[doc = "Bit 7"]
30393 #[inline(always)]
30394 pub fn linestate(&mut self) -> LinestateW<'_, GpwrdnSpec> {
30395 LinestateW::new(self, 7)
30396 }
30397 #[doc = "Bit 8"]
30398 #[inline(always)]
30399 pub fn linestate_int(&mut self) -> LinestateIntW<'_, GpwrdnSpec> {
30400 LinestateIntW::new(self, 8)
30401 }
30402 #[doc = "Bit 9"]
30403 #[inline(always)]
30404 pub fn resetdet(&mut self) -> ResetdetW<'_, GpwrdnSpec> {
30405 ResetdetW::new(self, 9)
30406 }
30407 #[doc = "Bit 10"]
30408 #[inline(always)]
30409 pub fn resetdet_int(&mut self) -> ResetdetIntW<'_, GpwrdnSpec> {
30410 ResetdetIntW::new(self, 10)
30411 }
30412 #[doc = "Bit 11"]
30413 #[inline(always)]
30414 pub fn disconn(&mut self) -> DisconnW<'_, GpwrdnSpec> {
30415 DisconnW::new(self, 11)
30416 }
30417 #[doc = "Bit 12"]
30418 #[inline(always)]
30419 pub fn disconn_int(&mut self) -> DisconnIntW<'_, GpwrdnSpec> {
30420 DisconnIntW::new(self, 12)
30421 }
30422 #[doc = "Bit 13"]
30423 #[inline(always)]
30424 pub fn conndet(&mut self) -> ConndetW<'_, GpwrdnSpec> {
30425 ConndetW::new(self, 13)
30426 }
30427 #[doc = "Bit 14"]
30428 #[inline(always)]
30429 pub fn conndet_int(&mut self) -> ConndetIntW<'_, GpwrdnSpec> {
30430 ConndetIntW::new(self, 14)
30431 }
30432 #[doc = "Bit 21"]
30433 #[inline(always)]
30434 pub fn iddig(&mut self) -> IddigW<'_, GpwrdnSpec> {
30435 IddigW::new(self, 21)
30436 }
30437 #[doc = "Bit 22"]
30438 #[inline(always)]
30439 pub fn bvalid(&mut self) -> BvalidW<'_, GpwrdnSpec> {
30440 BvalidW::new(self, 22)
30441 }
30442 }
30443 #[doc = "DOTG_GPWRDN\n\nYou can [`read`](crate::Reg::read) this register and get [`gpwrdn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpwrdn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30444 pub struct GpwrdnSpec;
30445 impl crate::RegisterSpec for GpwrdnSpec {
30446 type Ux = u32;
30447 }
30448 #[doc = "`read()` method returns [`gpwrdn::R`](R) reader structure"]
30449 impl crate::Readable for GpwrdnSpec {}
30450 #[doc = "`write(|w| ..)` method takes [`gpwrdn::W`](W) writer structure"]
30451 impl crate::Writable for GpwrdnSpec {
30452 type Safety = crate::Unsafe;
30453 }
30454 #[doc = "`reset()` method sets GPWRDN to value 0"]
30455 impl crate::Resettable for GpwrdnSpec {}
30456 }
30457 #[doc = "GDFIFOCFG (rw) register accessor: DOTG_GDFIFOCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gdfifocfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gdfifocfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gdfifocfg`] module"]
30458 #[doc(alias = "GDFIFOCFG")]
30459 pub type Gdfifocfg = crate::Reg<gdfifocfg::GdfifocfgSpec>;
30460 #[doc = "DOTG_GDFIFOCFG"]
30461 pub mod gdfifocfg {
30462 #[doc = "Register `GDFIFOCFG` reader"]
30463 pub type R = crate::R<GdfifocfgSpec>;
30464 #[doc = "Register `GDFIFOCFG` writer"]
30465 pub type W = crate::W<GdfifocfgSpec>;
30466 impl core::fmt::Debug for R {
30467 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30468 write!(f, "{}", self.bits())
30469 }
30470 }
30471 impl W {}
30472 #[doc = "DOTG_GDFIFOCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gdfifocfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gdfifocfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30473 pub struct GdfifocfgSpec;
30474 impl crate::RegisterSpec for GdfifocfgSpec {
30475 type Ux = u32;
30476 }
30477 #[doc = "`read()` method returns [`gdfifocfg::R`](R) reader structure"]
30478 impl crate::Readable for GdfifocfgSpec {}
30479 #[doc = "`write(|w| ..)` method takes [`gdfifocfg::W`](W) writer structure"]
30480 impl crate::Writable for GdfifocfgSpec {
30481 type Safety = crate::Unsafe;
30482 }
30483 #[doc = "`reset()` method sets GDFIFOCFG to value 0"]
30484 impl crate::Resettable for GdfifocfgSpec {}
30485 }
30486 #[doc = "GADPCTL (rw) register accessor: DOTG_GADPCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gadpctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gadpctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gadpctl`] module"]
30487 #[doc(alias = "GADPCTL")]
30488 pub type Gadpctl = crate::Reg<gadpctl::GadpctlSpec>;
30489 #[doc = "DOTG_GADPCTL"]
30490 pub mod gadpctl {
30491 #[doc = "Register `GADPCTL` reader"]
30492 pub type R = crate::R<GadpctlSpec>;
30493 #[doc = "Register `GADPCTL` writer"]
30494 pub type W = crate::W<GadpctlSpec>;
30495 impl core::fmt::Debug for R {
30496 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30497 write!(f, "{}", self.bits())
30498 }
30499 }
30500 impl W {}
30501 #[doc = "DOTG_GADPCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gadpctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gadpctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30502 pub struct GadpctlSpec;
30503 impl crate::RegisterSpec for GadpctlSpec {
30504 type Ux = u32;
30505 }
30506 #[doc = "`read()` method returns [`gadpctl::R`](R) reader structure"]
30507 impl crate::Readable for GadpctlSpec {}
30508 #[doc = "`write(|w| ..)` method takes [`gadpctl::W`](W) writer structure"]
30509 impl crate::Writable for GadpctlSpec {
30510 type Safety = crate::Unsafe;
30511 }
30512 #[doc = "`reset()` method sets GADPCTL to value 0"]
30513 impl crate::Resettable for GadpctlSpec {}
30514 }
30515 #[doc = "HPTXFSIZ (rw) register accessor: DOTG_HPTXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`hptxfsiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hptxfsiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxfsiz`] module"]
30516 #[doc(alias = "HPTXFSIZ")]
30517 pub type Hptxfsiz = crate::Reg<hptxfsiz::HptxfsizSpec>;
30518 #[doc = "DOTG_HPTXFSIZ"]
30519 pub mod hptxfsiz {
30520 #[doc = "Register `HPTXFSIZ` reader"]
30521 pub type R = crate::R<HptxfsizSpec>;
30522 #[doc = "Register `HPTXFSIZ` writer"]
30523 pub type W = crate::W<HptxfsizSpec>;
30524 #[doc = "Field `PTXFSTADDR` reader - "]
30525 pub type PtxfstaddrR = crate::FieldReader<u16>;
30526 #[doc = "Field `PTXFSTADDR` writer - "]
30527 pub type PtxfstaddrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
30528 #[doc = "Field `PTXFSIZE` reader - "]
30529 pub type PtxfsizeR = crate::FieldReader<u16>;
30530 #[doc = "Field `PTXFSIZE` writer - "]
30531 pub type PtxfsizeW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
30532 impl R {
30533 #[doc = "Bits 0:15"]
30534 #[inline(always)]
30535 pub fn ptxfstaddr(&self) -> PtxfstaddrR {
30536 PtxfstaddrR::new((self.bits & 0xffff) as u16)
30537 }
30538 #[doc = "Bits 16:31"]
30539 #[inline(always)]
30540 pub fn ptxfsize(&self) -> PtxfsizeR {
30541 PtxfsizeR::new(((self.bits >> 16) & 0xffff) as u16)
30542 }
30543 }
30544 impl W {
30545 #[doc = "Bits 0:15"]
30546 #[inline(always)]
30547 pub fn ptxfstaddr(&mut self) -> PtxfstaddrW<'_, HptxfsizSpec> {
30548 PtxfstaddrW::new(self, 0)
30549 }
30550 #[doc = "Bits 16:31"]
30551 #[inline(always)]
30552 pub fn ptxfsize(&mut self) -> PtxfsizeW<'_, HptxfsizSpec> {
30553 PtxfsizeW::new(self, 16)
30554 }
30555 }
30556 #[doc = "DOTG_HPTXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`hptxfsiz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hptxfsiz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30557 pub struct HptxfsizSpec;
30558 impl crate::RegisterSpec for HptxfsizSpec {
30559 type Ux = u32;
30560 }
30561 #[doc = "`read()` method returns [`hptxfsiz::R`](R) reader structure"]
30562 impl crate::Readable for HptxfsizSpec {}
30563 #[doc = "`write(|w| ..)` method takes [`hptxfsiz::W`](W) writer structure"]
30564 impl crate::Writable for HptxfsizSpec {
30565 type Safety = crate::Unsafe;
30566 }
30567 #[doc = "`reset()` method sets HPTXFSIZ to value 0"]
30568 impl crate::Resettable for HptxfsizSpec {}
30569 }
30570 #[doc = "HCFG (rw) register accessor: DOTG_HCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`hcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcfg`] module"]
30571 #[doc(alias = "HCFG")]
30572 pub type Hcfg = crate::Reg<hcfg::HcfgSpec>;
30573 #[doc = "DOTG_HCFG"]
30574 pub mod hcfg {
30575 #[doc = "Register `HCFG` reader"]
30576 pub type R = crate::R<HcfgSpec>;
30577 #[doc = "Register `HCFG` writer"]
30578 pub type W = crate::W<HcfgSpec>;
30579 #[doc = "Field `FSLSPCLKSEL` reader - "]
30580 pub type FslspclkselR = crate::FieldReader;
30581 #[doc = "Field `FSLSPCLKSEL` writer - "]
30582 pub type FslspclkselW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
30583 #[doc = "Field `FSLSSUPP` reader - "]
30584 pub type FslssuppR = crate::BitReader;
30585 #[doc = "Field `FSLSSUPP` writer - "]
30586 pub type FslssuppW<'a, REG> = crate::BitWriter<'a, REG>;
30587 #[doc = "Field `32KHZSUSPEND` reader - "]
30588 pub type _32khzsuspendR = crate::BitReader;
30589 #[doc = "Field `32KHZSUSPEND` writer - "]
30590 pub type _32khzsuspendW<'a, REG> = crate::BitWriter<'a, REG>;
30591 #[doc = "Field `MULTISEGDMA` reader - "]
30592 pub type MultisegdmaR = crate::BitReader;
30593 #[doc = "Field `MULTISEGDMA` writer - "]
30594 pub type MultisegdmaW<'a, REG> = crate::BitWriter<'a, REG>;
30595 #[doc = "Field `FLENTRIES` reader - "]
30596 pub type FlentriesR = crate::FieldReader;
30597 #[doc = "Field `FLENTRIES` writer - "]
30598 pub type FlentriesW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
30599 #[doc = "Field `PERSCHEDENABLE` reader - "]
30600 pub type PerschedenableR = crate::BitReader;
30601 #[doc = "Field `PERSCHEDENABLE` writer - "]
30602 pub type PerschedenableW<'a, REG> = crate::BitWriter<'a, REG>;
30603 #[doc = "Field `MODECHANGERDY` reader - "]
30604 pub type ModechangerdyR = crate::BitReader;
30605 #[doc = "Field `MODECHANGERDY` writer - "]
30606 pub type ModechangerdyW<'a, REG> = crate::BitWriter<'a, REG>;
30607 impl R {
30608 #[doc = "Bits 0:1"]
30609 #[inline(always)]
30610 pub fn fslspclksel(&self) -> FslspclkselR {
30611 FslspclkselR::new((self.bits & 3) as u8)
30612 }
30613 #[doc = "Bit 2"]
30614 #[inline(always)]
30615 pub fn fslssupp(&self) -> FslssuppR {
30616 FslssuppR::new(((self.bits >> 2) & 1) != 0)
30617 }
30618 #[doc = "Bit 7"]
30619 #[inline(always)]
30620 pub fn _32khzsuspend(&self) -> _32khzsuspendR {
30621 _32khzsuspendR::new(((self.bits >> 7) & 1) != 0)
30622 }
30623 #[doc = "Bit 23"]
30624 #[inline(always)]
30625 pub fn multisegdma(&self) -> MultisegdmaR {
30626 MultisegdmaR::new(((self.bits >> 23) & 1) != 0)
30627 }
30628 #[doc = "Bits 24:25"]
30629 #[inline(always)]
30630 pub fn flentries(&self) -> FlentriesR {
30631 FlentriesR::new(((self.bits >> 24) & 3) as u8)
30632 }
30633 #[doc = "Bit 26"]
30634 #[inline(always)]
30635 pub fn perschedenable(&self) -> PerschedenableR {
30636 PerschedenableR::new(((self.bits >> 26) & 1) != 0)
30637 }
30638 #[doc = "Bit 31"]
30639 #[inline(always)]
30640 pub fn modechangerdy(&self) -> ModechangerdyR {
30641 ModechangerdyR::new(((self.bits >> 31) & 1) != 0)
30642 }
30643 }
30644 impl W {
30645 #[doc = "Bits 0:1"]
30646 #[inline(always)]
30647 pub fn fslspclksel(&mut self) -> FslspclkselW<'_, HcfgSpec> {
30648 FslspclkselW::new(self, 0)
30649 }
30650 #[doc = "Bit 2"]
30651 #[inline(always)]
30652 pub fn fslssupp(&mut self) -> FslssuppW<'_, HcfgSpec> {
30653 FslssuppW::new(self, 2)
30654 }
30655 #[doc = "Bit 7"]
30656 #[inline(always)]
30657 pub fn _32khzsuspend(&mut self) -> _32khzsuspendW<'_, HcfgSpec> {
30658 _32khzsuspendW::new(self, 7)
30659 }
30660 #[doc = "Bit 23"]
30661 #[inline(always)]
30662 pub fn multisegdma(&mut self) -> MultisegdmaW<'_, HcfgSpec> {
30663 MultisegdmaW::new(self, 23)
30664 }
30665 #[doc = "Bits 24:25"]
30666 #[inline(always)]
30667 pub fn flentries(&mut self) -> FlentriesW<'_, HcfgSpec> {
30668 FlentriesW::new(self, 24)
30669 }
30670 #[doc = "Bit 26"]
30671 #[inline(always)]
30672 pub fn perschedenable(&mut self) -> PerschedenableW<'_, HcfgSpec> {
30673 PerschedenableW::new(self, 26)
30674 }
30675 #[doc = "Bit 31"]
30676 #[inline(always)]
30677 pub fn modechangerdy(&mut self) -> ModechangerdyW<'_, HcfgSpec> {
30678 ModechangerdyW::new(self, 31)
30679 }
30680 }
30681 #[doc = "DOTG_HCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`hcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30682 pub struct HcfgSpec;
30683 impl crate::RegisterSpec for HcfgSpec {
30684 type Ux = u32;
30685 }
30686 #[doc = "`read()` method returns [`hcfg::R`](R) reader structure"]
30687 impl crate::Readable for HcfgSpec {}
30688 #[doc = "`write(|w| ..)` method takes [`hcfg::W`](W) writer structure"]
30689 impl crate::Writable for HcfgSpec {
30690 type Safety = crate::Unsafe;
30691 }
30692 #[doc = "`reset()` method sets HCFG to value 0"]
30693 impl crate::Resettable for HcfgSpec {}
30694 }
30695 #[doc = "HFIR (rw) register accessor: DOTG_HFIR\n\nYou can [`read`](crate::Reg::read) this register and get [`hfir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfir`] module"]
30696 #[doc(alias = "HFIR")]
30697 pub type Hfir = crate::Reg<hfir::HfirSpec>;
30698 #[doc = "DOTG_HFIR"]
30699 pub mod hfir {
30700 #[doc = "Register `HFIR` reader"]
30701 pub type R = crate::R<HfirSpec>;
30702 #[doc = "Register `HFIR` writer"]
30703 pub type W = crate::W<HfirSpec>;
30704 #[doc = "Field `FRINT` reader - "]
30705 pub type FrintR = crate::FieldReader<u16>;
30706 #[doc = "Field `FRINT` writer - "]
30707 pub type FrintW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
30708 #[doc = "Field `RELOADCTRL` reader - "]
30709 pub type ReloadctrlR = crate::BitReader;
30710 #[doc = "Field `RELOADCTRL` writer - "]
30711 pub type ReloadctrlW<'a, REG> = crate::BitWriter<'a, REG>;
30712 impl R {
30713 #[doc = "Bits 0:15"]
30714 #[inline(always)]
30715 pub fn frint(&self) -> FrintR {
30716 FrintR::new((self.bits & 0xffff) as u16)
30717 }
30718 #[doc = "Bit 16"]
30719 #[inline(always)]
30720 pub fn reloadctrl(&self) -> ReloadctrlR {
30721 ReloadctrlR::new(((self.bits >> 16) & 1) != 0)
30722 }
30723 }
30724 impl W {
30725 #[doc = "Bits 0:15"]
30726 #[inline(always)]
30727 pub fn frint(&mut self) -> FrintW<'_, HfirSpec> {
30728 FrintW::new(self, 0)
30729 }
30730 #[doc = "Bit 16"]
30731 #[inline(always)]
30732 pub fn reloadctrl(&mut self) -> ReloadctrlW<'_, HfirSpec> {
30733 ReloadctrlW::new(self, 16)
30734 }
30735 }
30736 #[doc = "DOTG_HFIR\n\nYou can [`read`](crate::Reg::read) this register and get [`hfir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30737 pub struct HfirSpec;
30738 impl crate::RegisterSpec for HfirSpec {
30739 type Ux = u32;
30740 }
30741 #[doc = "`read()` method returns [`hfir::R`](R) reader structure"]
30742 impl crate::Readable for HfirSpec {}
30743 #[doc = "`write(|w| ..)` method takes [`hfir::W`](W) writer structure"]
30744 impl crate::Writable for HfirSpec {
30745 type Safety = crate::Unsafe;
30746 }
30747 #[doc = "`reset()` method sets HFIR to value 0"]
30748 impl crate::Resettable for HfirSpec {}
30749 }
30750 #[doc = "HFNUM (rw) register accessor: DOTG_HFNUM\n\nYou can [`read`](crate::Reg::read) this register and get [`hfnum::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfnum::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfnum`] module"]
30751 #[doc(alias = "HFNUM")]
30752 pub type Hfnum = crate::Reg<hfnum::HfnumSpec>;
30753 #[doc = "DOTG_HFNUM"]
30754 pub mod hfnum {
30755 #[doc = "Register `HFNUM` reader"]
30756 pub type R = crate::R<HfnumSpec>;
30757 #[doc = "Register `HFNUM` writer"]
30758 pub type W = crate::W<HfnumSpec>;
30759 #[doc = "Field `FRNUM` reader - "]
30760 pub type FrnumR = crate::FieldReader<u16>;
30761 #[doc = "Field `FRNUM` writer - "]
30762 pub type FrnumW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
30763 #[doc = "Field `FRREM` reader - "]
30764 pub type FrremR = crate::FieldReader<u16>;
30765 #[doc = "Field `FRREM` writer - "]
30766 pub type FrremW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
30767 impl R {
30768 #[doc = "Bits 0:15"]
30769 #[inline(always)]
30770 pub fn frnum(&self) -> FrnumR {
30771 FrnumR::new((self.bits & 0xffff) as u16)
30772 }
30773 #[doc = "Bits 16:31"]
30774 #[inline(always)]
30775 pub fn frrem(&self) -> FrremR {
30776 FrremR::new(((self.bits >> 16) & 0xffff) as u16)
30777 }
30778 }
30779 impl W {
30780 #[doc = "Bits 0:15"]
30781 #[inline(always)]
30782 pub fn frnum(&mut self) -> FrnumW<'_, HfnumSpec> {
30783 FrnumW::new(self, 0)
30784 }
30785 #[doc = "Bits 16:31"]
30786 #[inline(always)]
30787 pub fn frrem(&mut self) -> FrremW<'_, HfnumSpec> {
30788 FrremW::new(self, 16)
30789 }
30790 }
30791 #[doc = "DOTG_HFNUM\n\nYou can [`read`](crate::Reg::read) this register and get [`hfnum::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfnum::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30792 pub struct HfnumSpec;
30793 impl crate::RegisterSpec for HfnumSpec {
30794 type Ux = u32;
30795 }
30796 #[doc = "`read()` method returns [`hfnum::R`](R) reader structure"]
30797 impl crate::Readable for HfnumSpec {}
30798 #[doc = "`write(|w| ..)` method takes [`hfnum::W`](W) writer structure"]
30799 impl crate::Writable for HfnumSpec {
30800 type Safety = crate::Unsafe;
30801 }
30802 #[doc = "`reset()` method sets HFNUM to value 0"]
30803 impl crate::Resettable for HfnumSpec {}
30804 }
30805 #[doc = "HPTXSTS (rw) register accessor: DOTG_HPTXSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`hptxsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hptxsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxsts`] module"]
30806 #[doc(alias = "HPTXSTS")]
30807 pub type Hptxsts = crate::Reg<hptxsts::HptxstsSpec>;
30808 #[doc = "DOTG_HPTXSTS"]
30809 pub mod hptxsts {
30810 #[doc = "Register `HPTXSTS` reader"]
30811 pub type R = crate::R<HptxstsSpec>;
30812 #[doc = "Register `HPTXSTS` writer"]
30813 pub type W = crate::W<HptxstsSpec>;
30814 #[doc = "Field `PTXFSPCAVAIL` reader - "]
30815 pub type PtxfspcavailR = crate::FieldReader<u16>;
30816 #[doc = "Field `PTXFSPCAVAIL` writer - "]
30817 pub type PtxfspcavailW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
30818 #[doc = "Field `PTXQSPCAVAIL` reader - "]
30819 pub type PtxqspcavailR = crate::FieldReader;
30820 #[doc = "Field `PTXQSPCAVAIL` writer - "]
30821 pub type PtxqspcavailW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
30822 #[doc = "Field `TERMINATE` reader - "]
30823 pub type TerminateR = crate::BitReader;
30824 #[doc = "Field `TERMINATE` writer - "]
30825 pub type TerminateW<'a, REG> = crate::BitWriter<'a, REG>;
30826 #[doc = "Field `TOKEN` reader - "]
30827 pub type TokenR = crate::FieldReader;
30828 #[doc = "Field `TOKEN` writer - "]
30829 pub type TokenW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
30830 #[doc = "Field `CHAN` reader - "]
30831 pub type ChanR = crate::FieldReader;
30832 #[doc = "Field `CHAN` writer - "]
30833 pub type ChanW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
30834 #[doc = "Field `ODD` reader - "]
30835 pub type OddR = crate::BitReader;
30836 #[doc = "Field `ODD` writer - "]
30837 pub type OddW<'a, REG> = crate::BitWriter<'a, REG>;
30838 impl R {
30839 #[doc = "Bits 0:15"]
30840 #[inline(always)]
30841 pub fn ptxfspcavail(&self) -> PtxfspcavailR {
30842 PtxfspcavailR::new((self.bits & 0xffff) as u16)
30843 }
30844 #[doc = "Bits 16:23"]
30845 #[inline(always)]
30846 pub fn ptxqspcavail(&self) -> PtxqspcavailR {
30847 PtxqspcavailR::new(((self.bits >> 16) & 0xff) as u8)
30848 }
30849 #[doc = "Bit 24"]
30850 #[inline(always)]
30851 pub fn terminate(&self) -> TerminateR {
30852 TerminateR::new(((self.bits >> 24) & 1) != 0)
30853 }
30854 #[doc = "Bits 25:26"]
30855 #[inline(always)]
30856 pub fn token(&self) -> TokenR {
30857 TokenR::new(((self.bits >> 25) & 3) as u8)
30858 }
30859 #[doc = "Bits 27:30"]
30860 #[inline(always)]
30861 pub fn chan(&self) -> ChanR {
30862 ChanR::new(((self.bits >> 27) & 0x0f) as u8)
30863 }
30864 #[doc = "Bit 31"]
30865 #[inline(always)]
30866 pub fn odd(&self) -> OddR {
30867 OddR::new(((self.bits >> 31) & 1) != 0)
30868 }
30869 }
30870 impl W {
30871 #[doc = "Bits 0:15"]
30872 #[inline(always)]
30873 pub fn ptxfspcavail(&mut self) -> PtxfspcavailW<'_, HptxstsSpec> {
30874 PtxfspcavailW::new(self, 0)
30875 }
30876 #[doc = "Bits 16:23"]
30877 #[inline(always)]
30878 pub fn ptxqspcavail(&mut self) -> PtxqspcavailW<'_, HptxstsSpec> {
30879 PtxqspcavailW::new(self, 16)
30880 }
30881 #[doc = "Bit 24"]
30882 #[inline(always)]
30883 pub fn terminate(&mut self) -> TerminateW<'_, HptxstsSpec> {
30884 TerminateW::new(self, 24)
30885 }
30886 #[doc = "Bits 25:26"]
30887 #[inline(always)]
30888 pub fn token(&mut self) -> TokenW<'_, HptxstsSpec> {
30889 TokenW::new(self, 25)
30890 }
30891 #[doc = "Bits 27:30"]
30892 #[inline(always)]
30893 pub fn chan(&mut self) -> ChanW<'_, HptxstsSpec> {
30894 ChanW::new(self, 27)
30895 }
30896 #[doc = "Bit 31"]
30897 #[inline(always)]
30898 pub fn odd(&mut self) -> OddW<'_, HptxstsSpec> {
30899 OddW::new(self, 31)
30900 }
30901 }
30902 #[doc = "DOTG_HPTXSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`hptxsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hptxsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30903 pub struct HptxstsSpec;
30904 impl crate::RegisterSpec for HptxstsSpec {
30905 type Ux = u32;
30906 }
30907 #[doc = "`read()` method returns [`hptxsts::R`](R) reader structure"]
30908 impl crate::Readable for HptxstsSpec {}
30909 #[doc = "`write(|w| ..)` method takes [`hptxsts::W`](W) writer structure"]
30910 impl crate::Writable for HptxstsSpec {
30911 type Safety = crate::Unsafe;
30912 }
30913 #[doc = "`reset()` method sets HPTXSTS to value 0"]
30914 impl crate::Resettable for HptxstsSpec {}
30915 }
30916 #[doc = "HAINT (rw) register accessor: DOTG_HAINT\n\nYou can [`read`](crate::Reg::read) this register and get [`haint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`haint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haint`] module"]
30917 #[doc(alias = "HAINT")]
30918 pub type Haint = crate::Reg<haint::HaintSpec>;
30919 #[doc = "DOTG_HAINT"]
30920 pub mod haint {
30921 #[doc = "Register `HAINT` reader"]
30922 pub type R = crate::R<HaintSpec>;
30923 #[doc = "Register `HAINT` writer"]
30924 pub type W = crate::W<HaintSpec>;
30925 #[doc = "Field `HAINT` reader - "]
30926 pub type HaintR = crate::FieldReader<u16>;
30927 #[doc = "Field `HAINT` writer - "]
30928 pub type HaintW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
30929 impl R {
30930 #[doc = "Bits 0:15"]
30931 #[inline(always)]
30932 pub fn haint(&self) -> HaintR {
30933 HaintR::new((self.bits & 0xffff) as u16)
30934 }
30935 }
30936 impl W {
30937 #[doc = "Bits 0:15"]
30938 #[inline(always)]
30939 pub fn haint(&mut self) -> HaintW<'_, HaintSpec> {
30940 HaintW::new(self, 0)
30941 }
30942 }
30943 #[doc = "DOTG_HAINT\n\nYou can [`read`](crate::Reg::read) this register and get [`haint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`haint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30944 pub struct HaintSpec;
30945 impl crate::RegisterSpec for HaintSpec {
30946 type Ux = u32;
30947 }
30948 #[doc = "`read()` method returns [`haint::R`](R) reader structure"]
30949 impl crate::Readable for HaintSpec {}
30950 #[doc = "`write(|w| ..)` method takes [`haint::W`](W) writer structure"]
30951 impl crate::Writable for HaintSpec {
30952 type Safety = crate::Unsafe;
30953 }
30954 #[doc = "`reset()` method sets HAINT to value 0"]
30955 impl crate::Resettable for HaintSpec {}
30956 }
30957 #[doc = "HAINTMSK (rw) register accessor: DOTG_HAINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`haintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`haintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haintmsk`] module"]
30958 #[doc(alias = "HAINTMSK")]
30959 pub type Haintmsk = crate::Reg<haintmsk::HaintmskSpec>;
30960 #[doc = "DOTG_HAINTMSK"]
30961 pub mod haintmsk {
30962 #[doc = "Register `HAINTMSK` reader"]
30963 pub type R = crate::R<HaintmskSpec>;
30964 #[doc = "Register `HAINTMSK` writer"]
30965 pub type W = crate::W<HaintmskSpec>;
30966 #[doc = "Field `HAINTMSK` reader - "]
30967 pub type HaintmskR = crate::FieldReader<u16>;
30968 #[doc = "Field `HAINTMSK` writer - "]
30969 pub type HaintmskW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
30970 impl R {
30971 #[doc = "Bits 0:15"]
30972 #[inline(always)]
30973 pub fn haintmsk(&self) -> HaintmskR {
30974 HaintmskR::new((self.bits & 0xffff) as u16)
30975 }
30976 }
30977 impl W {
30978 #[doc = "Bits 0:15"]
30979 #[inline(always)]
30980 pub fn haintmsk(&mut self) -> HaintmskW<'_, HaintmskSpec> {
30981 HaintmskW::new(self, 0)
30982 }
30983 }
30984 #[doc = "DOTG_HAINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`haintmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`haintmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30985 pub struct HaintmskSpec;
30986 impl crate::RegisterSpec for HaintmskSpec {
30987 type Ux = u32;
30988 }
30989 #[doc = "`read()` method returns [`haintmsk::R`](R) reader structure"]
30990 impl crate::Readable for HaintmskSpec {}
30991 #[doc = "`write(|w| ..)` method takes [`haintmsk::W`](W) writer structure"]
30992 impl crate::Writable for HaintmskSpec {
30993 type Safety = crate::Unsafe;
30994 }
30995 #[doc = "`reset()` method sets HAINTMSK to value 0"]
30996 impl crate::Resettable for HaintmskSpec {}
30997 }
30998 #[doc = "HPRT (rw) register accessor: DOTG_HPRT\n\nYou can [`read`](crate::Reg::read) this register and get [`hprt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hprt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hprt`] module"]
30999 #[doc(alias = "HPRT")]
31000 pub type Hprt = crate::Reg<hprt::HprtSpec>;
31001 #[doc = "DOTG_HPRT"]
31002 pub mod hprt {
31003 #[doc = "Register `HPRT` reader"]
31004 pub type R = crate::R<HprtSpec>;
31005 #[doc = "Register `HPRT` writer"]
31006 pub type W = crate::W<HprtSpec>;
31007 #[doc = "Field `PRTCONNSTS` reader - "]
31008 pub type PrtconnstsR = crate::BitReader;
31009 #[doc = "Field `PRTCONNSTS` writer - "]
31010 pub type PrtconnstsW<'a, REG> = crate::BitWriter<'a, REG>;
31011 #[doc = "Field `PRTCONNDET` reader - "]
31012 pub type PrtconndetR = crate::BitReader;
31013 #[doc = "Field `PRTCONNDET` writer - "]
31014 pub type PrtconndetW<'a, REG> = crate::BitWriter<'a, REG>;
31015 #[doc = "Field `PRTENA` reader - "]
31016 pub type PrtenaR = crate::BitReader;
31017 #[doc = "Field `PRTENA` writer - "]
31018 pub type PrtenaW<'a, REG> = crate::BitWriter<'a, REG>;
31019 #[doc = "Field `PRTENCHNG` reader - "]
31020 pub type PrtenchngR = crate::BitReader;
31021 #[doc = "Field `PRTENCHNG` writer - "]
31022 pub type PrtenchngW<'a, REG> = crate::BitWriter<'a, REG>;
31023 #[doc = "Field `PRTOVRCURRACT` reader - "]
31024 pub type PrtovrcurractR = crate::BitReader;
31025 #[doc = "Field `PRTOVRCURRACT` writer - "]
31026 pub type PrtovrcurractW<'a, REG> = crate::BitWriter<'a, REG>;
31027 #[doc = "Field `PRTOVRCURRCHNG` reader - "]
31028 pub type PrtovrcurrchngR = crate::BitReader;
31029 #[doc = "Field `PRTOVRCURRCHNG` writer - "]
31030 pub type PrtovrcurrchngW<'a, REG> = crate::BitWriter<'a, REG>;
31031 #[doc = "Field `PRTRES` reader - "]
31032 pub type PrtresR = crate::BitReader;
31033 #[doc = "Field `PRTRES` writer - "]
31034 pub type PrtresW<'a, REG> = crate::BitWriter<'a, REG>;
31035 #[doc = "Field `PRTSUSP` reader - "]
31036 pub type PrtsuspR = crate::BitReader;
31037 #[doc = "Field `PRTSUSP` writer - "]
31038 pub type PrtsuspW<'a, REG> = crate::BitWriter<'a, REG>;
31039 #[doc = "Field `PRTRST` reader - "]
31040 pub type PrtrstR = crate::BitReader;
31041 #[doc = "Field `PRTRST` writer - "]
31042 pub type PrtrstW<'a, REG> = crate::BitWriter<'a, REG>;
31043 #[doc = "Field `PRTLNSTS` reader - "]
31044 pub type PrtlnstsR = crate::FieldReader;
31045 #[doc = "Field `PRTLNSTS` writer - "]
31046 pub type PrtlnstsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
31047 #[doc = "Field `PRTPWR` reader - "]
31048 pub type PrtpwrR = crate::BitReader;
31049 #[doc = "Field `PRTPWR` writer - "]
31050 pub type PrtpwrW<'a, REG> = crate::BitWriter<'a, REG>;
31051 #[doc = "Field `PRTTSTCTL` reader - "]
31052 pub type PrttstctlR = crate::FieldReader;
31053 #[doc = "Field `PRTTSTCTL` writer - "]
31054 pub type PrttstctlW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
31055 #[doc = "Field `PRTSPD` reader - "]
31056 pub type PrtspdR = crate::FieldReader;
31057 #[doc = "Field `PRTSPD` writer - "]
31058 pub type PrtspdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
31059 impl R {
31060 #[doc = "Bit 0"]
31061 #[inline(always)]
31062 pub fn prtconnsts(&self) -> PrtconnstsR {
31063 PrtconnstsR::new((self.bits & 1) != 0)
31064 }
31065 #[doc = "Bit 1"]
31066 #[inline(always)]
31067 pub fn prtconndet(&self) -> PrtconndetR {
31068 PrtconndetR::new(((self.bits >> 1) & 1) != 0)
31069 }
31070 #[doc = "Bit 2"]
31071 #[inline(always)]
31072 pub fn prtena(&self) -> PrtenaR {
31073 PrtenaR::new(((self.bits >> 2) & 1) != 0)
31074 }
31075 #[doc = "Bit 3"]
31076 #[inline(always)]
31077 pub fn prtenchng(&self) -> PrtenchngR {
31078 PrtenchngR::new(((self.bits >> 3) & 1) != 0)
31079 }
31080 #[doc = "Bit 4"]
31081 #[inline(always)]
31082 pub fn prtovrcurract(&self) -> PrtovrcurractR {
31083 PrtovrcurractR::new(((self.bits >> 4) & 1) != 0)
31084 }
31085 #[doc = "Bit 5"]
31086 #[inline(always)]
31087 pub fn prtovrcurrchng(&self) -> PrtovrcurrchngR {
31088 PrtovrcurrchngR::new(((self.bits >> 5) & 1) != 0)
31089 }
31090 #[doc = "Bit 6"]
31091 #[inline(always)]
31092 pub fn prtres(&self) -> PrtresR {
31093 PrtresR::new(((self.bits >> 6) & 1) != 0)
31094 }
31095 #[doc = "Bit 7"]
31096 #[inline(always)]
31097 pub fn prtsusp(&self) -> PrtsuspR {
31098 PrtsuspR::new(((self.bits >> 7) & 1) != 0)
31099 }
31100 #[doc = "Bit 8"]
31101 #[inline(always)]
31102 pub fn prtrst(&self) -> PrtrstR {
31103 PrtrstR::new(((self.bits >> 8) & 1) != 0)
31104 }
31105 #[doc = "Bits 10:11"]
31106 #[inline(always)]
31107 pub fn prtlnsts(&self) -> PrtlnstsR {
31108 PrtlnstsR::new(((self.bits >> 10) & 3) as u8)
31109 }
31110 #[doc = "Bit 12"]
31111 #[inline(always)]
31112 pub fn prtpwr(&self) -> PrtpwrR {
31113 PrtpwrR::new(((self.bits >> 12) & 1) != 0)
31114 }
31115 #[doc = "Bits 13:16"]
31116 #[inline(always)]
31117 pub fn prttstctl(&self) -> PrttstctlR {
31118 PrttstctlR::new(((self.bits >> 13) & 0x0f) as u8)
31119 }
31120 #[doc = "Bits 17:18"]
31121 #[inline(always)]
31122 pub fn prtspd(&self) -> PrtspdR {
31123 PrtspdR::new(((self.bits >> 17) & 3) as u8)
31124 }
31125 }
31126 impl W {
31127 #[doc = "Bit 0"]
31128 #[inline(always)]
31129 pub fn prtconnsts(&mut self) -> PrtconnstsW<'_, HprtSpec> {
31130 PrtconnstsW::new(self, 0)
31131 }
31132 #[doc = "Bit 1"]
31133 #[inline(always)]
31134 pub fn prtconndet(&mut self) -> PrtconndetW<'_, HprtSpec> {
31135 PrtconndetW::new(self, 1)
31136 }
31137 #[doc = "Bit 2"]
31138 #[inline(always)]
31139 pub fn prtena(&mut self) -> PrtenaW<'_, HprtSpec> {
31140 PrtenaW::new(self, 2)
31141 }
31142 #[doc = "Bit 3"]
31143 #[inline(always)]
31144 pub fn prtenchng(&mut self) -> PrtenchngW<'_, HprtSpec> {
31145 PrtenchngW::new(self, 3)
31146 }
31147 #[doc = "Bit 4"]
31148 #[inline(always)]
31149 pub fn prtovrcurract(&mut self) -> PrtovrcurractW<'_, HprtSpec> {
31150 PrtovrcurractW::new(self, 4)
31151 }
31152 #[doc = "Bit 5"]
31153 #[inline(always)]
31154 pub fn prtovrcurrchng(&mut self) -> PrtovrcurrchngW<'_, HprtSpec> {
31155 PrtovrcurrchngW::new(self, 5)
31156 }
31157 #[doc = "Bit 6"]
31158 #[inline(always)]
31159 pub fn prtres(&mut self) -> PrtresW<'_, HprtSpec> {
31160 PrtresW::new(self, 6)
31161 }
31162 #[doc = "Bit 7"]
31163 #[inline(always)]
31164 pub fn prtsusp(&mut self) -> PrtsuspW<'_, HprtSpec> {
31165 PrtsuspW::new(self, 7)
31166 }
31167 #[doc = "Bit 8"]
31168 #[inline(always)]
31169 pub fn prtrst(&mut self) -> PrtrstW<'_, HprtSpec> {
31170 PrtrstW::new(self, 8)
31171 }
31172 #[doc = "Bits 10:11"]
31173 #[inline(always)]
31174 pub fn prtlnsts(&mut self) -> PrtlnstsW<'_, HprtSpec> {
31175 PrtlnstsW::new(self, 10)
31176 }
31177 #[doc = "Bit 12"]
31178 #[inline(always)]
31179 pub fn prtpwr(&mut self) -> PrtpwrW<'_, HprtSpec> {
31180 PrtpwrW::new(self, 12)
31181 }
31182 #[doc = "Bits 13:16"]
31183 #[inline(always)]
31184 pub fn prttstctl(&mut self) -> PrttstctlW<'_, HprtSpec> {
31185 PrttstctlW::new(self, 13)
31186 }
31187 #[doc = "Bits 17:18"]
31188 #[inline(always)]
31189 pub fn prtspd(&mut self) -> PrtspdW<'_, HprtSpec> {
31190 PrtspdW::new(self, 17)
31191 }
31192 }
31193 #[doc = "DOTG_HPRT\n\nYou can [`read`](crate::Reg::read) this register and get [`hprt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hprt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31194 pub struct HprtSpec;
31195 impl crate::RegisterSpec for HprtSpec {
31196 type Ux = u32;
31197 }
31198 #[doc = "`read()` method returns [`hprt::R`](R) reader structure"]
31199 impl crate::Readable for HprtSpec {}
31200 #[doc = "`write(|w| ..)` method takes [`hprt::W`](W) writer structure"]
31201 impl crate::Writable for HprtSpec {
31202 type Safety = crate::Unsafe;
31203 }
31204 #[doc = "`reset()` method sets HPRT to value 0"]
31205 impl crate::Resettable for HprtSpec {}
31206 }
31207 #[doc = "DCFG (rw) register accessor: DOTG_DCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`dcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcfg`] module"]
31208 #[doc(alias = "DCFG")]
31209 pub type Dcfg = crate::Reg<dcfg::DcfgSpec>;
31210 #[doc = "DOTG_DCFG"]
31211 pub mod dcfg {
31212 #[doc = "Register `DCFG` reader"]
31213 pub type R = crate::R<DcfgSpec>;
31214 #[doc = "Register `DCFG` writer"]
31215 pub type W = crate::W<DcfgSpec>;
31216 #[doc = "Field `DEVSPD` reader - "]
31217 pub type DevspdR = crate::FieldReader;
31218 #[doc = "Field `DEVSPD` writer - "]
31219 pub type DevspdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
31220 #[doc = "Field `NZSTSOUTHSHK` reader - "]
31221 pub type NzstsouthshkR = crate::BitReader;
31222 #[doc = "Field `NZSTSOUTHSHK` writer - "]
31223 pub type NzstsouthshkW<'a, REG> = crate::BitWriter<'a, REG>;
31224 #[doc = "Field `DEVADDR` reader - "]
31225 pub type DevaddrR = crate::FieldReader;
31226 #[doc = "Field `DEVADDR` writer - "]
31227 pub type DevaddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
31228 #[doc = "Field `PERFRINT` reader - "]
31229 pub type PerfrintR = crate::FieldReader;
31230 #[doc = "Field `PERFRINT` writer - "]
31231 pub type PerfrintW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
31232 #[doc = "Field `EPMISCNT` reader - "]
31233 pub type EpmiscntR = crate::FieldReader;
31234 #[doc = "Field `EPMISCNT` writer - "]
31235 pub type EpmiscntW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
31236 impl R {
31237 #[doc = "Bits 0:1"]
31238 #[inline(always)]
31239 pub fn devspd(&self) -> DevspdR {
31240 DevspdR::new((self.bits & 3) as u8)
31241 }
31242 #[doc = "Bit 2"]
31243 #[inline(always)]
31244 pub fn nzstsouthshk(&self) -> NzstsouthshkR {
31245 NzstsouthshkR::new(((self.bits >> 2) & 1) != 0)
31246 }
31247 #[doc = "Bits 4:10"]
31248 #[inline(always)]
31249 pub fn devaddr(&self) -> DevaddrR {
31250 DevaddrR::new(((self.bits >> 4) & 0x7f) as u8)
31251 }
31252 #[doc = "Bits 11:12"]
31253 #[inline(always)]
31254 pub fn perfrint(&self) -> PerfrintR {
31255 PerfrintR::new(((self.bits >> 11) & 3) as u8)
31256 }
31257 #[doc = "Bits 18:22"]
31258 #[inline(always)]
31259 pub fn epmiscnt(&self) -> EpmiscntR {
31260 EpmiscntR::new(((self.bits >> 18) & 0x1f) as u8)
31261 }
31262 }
31263 impl W {
31264 #[doc = "Bits 0:1"]
31265 #[inline(always)]
31266 pub fn devspd(&mut self) -> DevspdW<'_, DcfgSpec> {
31267 DevspdW::new(self, 0)
31268 }
31269 #[doc = "Bit 2"]
31270 #[inline(always)]
31271 pub fn nzstsouthshk(&mut self) -> NzstsouthshkW<'_, DcfgSpec> {
31272 NzstsouthshkW::new(self, 2)
31273 }
31274 #[doc = "Bits 4:10"]
31275 #[inline(always)]
31276 pub fn devaddr(&mut self) -> DevaddrW<'_, DcfgSpec> {
31277 DevaddrW::new(self, 4)
31278 }
31279 #[doc = "Bits 11:12"]
31280 #[inline(always)]
31281 pub fn perfrint(&mut self) -> PerfrintW<'_, DcfgSpec> {
31282 PerfrintW::new(self, 11)
31283 }
31284 #[doc = "Bits 18:22"]
31285 #[inline(always)]
31286 pub fn epmiscnt(&mut self) -> EpmiscntW<'_, DcfgSpec> {
31287 EpmiscntW::new(self, 18)
31288 }
31289 }
31290 #[doc = "DOTG_DCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`dcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31291 pub struct DcfgSpec;
31292 impl crate::RegisterSpec for DcfgSpec {
31293 type Ux = u32;
31294 }
31295 #[doc = "`read()` method returns [`dcfg::R`](R) reader structure"]
31296 impl crate::Readable for DcfgSpec {}
31297 #[doc = "`write(|w| ..)` method takes [`dcfg::W`](W) writer structure"]
31298 impl crate::Writable for DcfgSpec {
31299 type Safety = crate::Unsafe;
31300 }
31301 #[doc = "`reset()` method sets DCFG to value 0"]
31302 impl crate::Resettable for DcfgSpec {}
31303 }
31304 #[doc = "DCTL (rw) register accessor: DOTG_DCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`dctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dctl`] module"]
31305 #[doc(alias = "DCTL")]
31306 pub type Dctl = crate::Reg<dctl::DctlSpec>;
31307 #[doc = "DOTG_DCTL"]
31308 pub mod dctl {
31309 #[doc = "Register `DCTL` reader"]
31310 pub type R = crate::R<DctlSpec>;
31311 #[doc = "Register `DCTL` writer"]
31312 pub type W = crate::W<DctlSpec>;
31313 #[doc = "Field `RMTWKUPSIG` reader - "]
31314 pub type RmtwkupsigR = crate::BitReader;
31315 #[doc = "Field `RMTWKUPSIG` writer - "]
31316 pub type RmtwkupsigW<'a, REG> = crate::BitWriter<'a, REG>;
31317 #[doc = "Field `SFTDISCON` reader - "]
31318 pub type SftdisconR = crate::BitReader;
31319 #[doc = "Field `SFTDISCON` writer - "]
31320 pub type SftdisconW<'a, REG> = crate::BitWriter<'a, REG>;
31321 #[doc = "Field `GNPINNAKSTS` reader - "]
31322 pub type GnpinnakstsR = crate::BitReader;
31323 #[doc = "Field `GNPINNAKSTS` writer - "]
31324 pub type GnpinnakstsW<'a, REG> = crate::BitWriter<'a, REG>;
31325 #[doc = "Field `GOUTNAKSTS` reader - "]
31326 pub type GoutnakstsR = crate::BitReader;
31327 #[doc = "Field `GOUTNAKSTS` writer - "]
31328 pub type GoutnakstsW<'a, REG> = crate::BitWriter<'a, REG>;
31329 #[doc = "Field `TSTCTL` reader - "]
31330 pub type TstctlR = crate::FieldReader;
31331 #[doc = "Field `TSTCTL` writer - "]
31332 pub type TstctlW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
31333 #[doc = "Field `SGNPINNAK` reader - "]
31334 pub type SgnpinnakR = crate::BitReader;
31335 #[doc = "Field `SGNPINNAK` writer - "]
31336 pub type SgnpinnakW<'a, REG> = crate::BitWriter<'a, REG>;
31337 #[doc = "Field `CGNPINNAK` reader - "]
31338 pub type CgnpinnakR = crate::BitReader;
31339 #[doc = "Field `CGNPINNAK` writer - "]
31340 pub type CgnpinnakW<'a, REG> = crate::BitWriter<'a, REG>;
31341 #[doc = "Field `SGOUTNAK` reader - "]
31342 pub type SgoutnakR = crate::BitReader;
31343 #[doc = "Field `SGOUTNAK` writer - "]
31344 pub type SgoutnakW<'a, REG> = crate::BitWriter<'a, REG>;
31345 #[doc = "Field `CGOUTNAK` reader - "]
31346 pub type CgoutnakR = crate::BitReader;
31347 #[doc = "Field `CGOUTNAK` writer - "]
31348 pub type CgoutnakW<'a, REG> = crate::BitWriter<'a, REG>;
31349 #[doc = "Field `PWRONPRGDONE` reader - "]
31350 pub type PwronprgdoneR = crate::BitReader;
31351 #[doc = "Field `PWRONPRGDONE` writer - "]
31352 pub type PwronprgdoneW<'a, REG> = crate::BitWriter<'a, REG>;
31353 impl R {
31354 #[doc = "Bit 0"]
31355 #[inline(always)]
31356 pub fn rmtwkupsig(&self) -> RmtwkupsigR {
31357 RmtwkupsigR::new((self.bits & 1) != 0)
31358 }
31359 #[doc = "Bit 1"]
31360 #[inline(always)]
31361 pub fn sftdiscon(&self) -> SftdisconR {
31362 SftdisconR::new(((self.bits >> 1) & 1) != 0)
31363 }
31364 #[doc = "Bit 2"]
31365 #[inline(always)]
31366 pub fn gnpinnaksts(&self) -> GnpinnakstsR {
31367 GnpinnakstsR::new(((self.bits >> 2) & 1) != 0)
31368 }
31369 #[doc = "Bit 3"]
31370 #[inline(always)]
31371 pub fn goutnaksts(&self) -> GoutnakstsR {
31372 GoutnakstsR::new(((self.bits >> 3) & 1) != 0)
31373 }
31374 #[doc = "Bits 4:6"]
31375 #[inline(always)]
31376 pub fn tstctl(&self) -> TstctlR {
31377 TstctlR::new(((self.bits >> 4) & 7) as u8)
31378 }
31379 #[doc = "Bit 7"]
31380 #[inline(always)]
31381 pub fn sgnpinnak(&self) -> SgnpinnakR {
31382 SgnpinnakR::new(((self.bits >> 7) & 1) != 0)
31383 }
31384 #[doc = "Bit 8"]
31385 #[inline(always)]
31386 pub fn cgnpinnak(&self) -> CgnpinnakR {
31387 CgnpinnakR::new(((self.bits >> 8) & 1) != 0)
31388 }
31389 #[doc = "Bit 9"]
31390 #[inline(always)]
31391 pub fn sgoutnak(&self) -> SgoutnakR {
31392 SgoutnakR::new(((self.bits >> 9) & 1) != 0)
31393 }
31394 #[doc = "Bit 10"]
31395 #[inline(always)]
31396 pub fn cgoutnak(&self) -> CgoutnakR {
31397 CgoutnakR::new(((self.bits >> 10) & 1) != 0)
31398 }
31399 #[doc = "Bit 11"]
31400 #[inline(always)]
31401 pub fn pwronprgdone(&self) -> PwronprgdoneR {
31402 PwronprgdoneR::new(((self.bits >> 11) & 1) != 0)
31403 }
31404 }
31405 impl W {
31406 #[doc = "Bit 0"]
31407 #[inline(always)]
31408 pub fn rmtwkupsig(&mut self) -> RmtwkupsigW<'_, DctlSpec> {
31409 RmtwkupsigW::new(self, 0)
31410 }
31411 #[doc = "Bit 1"]
31412 #[inline(always)]
31413 pub fn sftdiscon(&mut self) -> SftdisconW<'_, DctlSpec> {
31414 SftdisconW::new(self, 1)
31415 }
31416 #[doc = "Bit 2"]
31417 #[inline(always)]
31418 pub fn gnpinnaksts(&mut self) -> GnpinnakstsW<'_, DctlSpec> {
31419 GnpinnakstsW::new(self, 2)
31420 }
31421 #[doc = "Bit 3"]
31422 #[inline(always)]
31423 pub fn goutnaksts(&mut self) -> GoutnakstsW<'_, DctlSpec> {
31424 GoutnakstsW::new(self, 3)
31425 }
31426 #[doc = "Bits 4:6"]
31427 #[inline(always)]
31428 pub fn tstctl(&mut self) -> TstctlW<'_, DctlSpec> {
31429 TstctlW::new(self, 4)
31430 }
31431 #[doc = "Bit 7"]
31432 #[inline(always)]
31433 pub fn sgnpinnak(&mut self) -> SgnpinnakW<'_, DctlSpec> {
31434 SgnpinnakW::new(self, 7)
31435 }
31436 #[doc = "Bit 8"]
31437 #[inline(always)]
31438 pub fn cgnpinnak(&mut self) -> CgnpinnakW<'_, DctlSpec> {
31439 CgnpinnakW::new(self, 8)
31440 }
31441 #[doc = "Bit 9"]
31442 #[inline(always)]
31443 pub fn sgoutnak(&mut self) -> SgoutnakW<'_, DctlSpec> {
31444 SgoutnakW::new(self, 9)
31445 }
31446 #[doc = "Bit 10"]
31447 #[inline(always)]
31448 pub fn cgoutnak(&mut self) -> CgoutnakW<'_, DctlSpec> {
31449 CgoutnakW::new(self, 10)
31450 }
31451 #[doc = "Bit 11"]
31452 #[inline(always)]
31453 pub fn pwronprgdone(&mut self) -> PwronprgdoneW<'_, DctlSpec> {
31454 PwronprgdoneW::new(self, 11)
31455 }
31456 }
31457 #[doc = "DOTG_DCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`dctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31458 pub struct DctlSpec;
31459 impl crate::RegisterSpec for DctlSpec {
31460 type Ux = u32;
31461 }
31462 #[doc = "`read()` method returns [`dctl::R`](R) reader structure"]
31463 impl crate::Readable for DctlSpec {}
31464 #[doc = "`write(|w| ..)` method takes [`dctl::W`](W) writer structure"]
31465 impl crate::Writable for DctlSpec {
31466 type Safety = crate::Unsafe;
31467 }
31468 #[doc = "`reset()` method sets DCTL to value 0"]
31469 impl crate::Resettable for DctlSpec {}
31470 }
31471 #[doc = "DSTS (rw) register accessor: DOTG_DSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`dsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsts`] module"]
31472 #[doc(alias = "DSTS")]
31473 pub type Dsts = crate::Reg<dsts::DstsSpec>;
31474 #[doc = "DOTG_DSTS"]
31475 pub mod dsts {
31476 #[doc = "Register `DSTS` reader"]
31477 pub type R = crate::R<DstsSpec>;
31478 #[doc = "Register `DSTS` writer"]
31479 pub type W = crate::W<DstsSpec>;
31480 #[doc = "Field `SUSPSTS` reader - "]
31481 pub type SuspstsR = crate::BitReader;
31482 #[doc = "Field `SUSPSTS` writer - "]
31483 pub type SuspstsW<'a, REG> = crate::BitWriter<'a, REG>;
31484 #[doc = "Field `ENUMSPD` reader - "]
31485 pub type EnumspdR = crate::FieldReader;
31486 #[doc = "Field `ENUMSPD` writer - "]
31487 pub type EnumspdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
31488 #[doc = "Field `ERRTICERR` reader - "]
31489 pub type ErrticerrR = crate::BitReader;
31490 #[doc = "Field `ERRTICERR` writer - "]
31491 pub type ErrticerrW<'a, REG> = crate::BitWriter<'a, REG>;
31492 #[doc = "Field `SOFFN` reader - "]
31493 pub type SoffnR = crate::FieldReader<u16>;
31494 #[doc = "Field `SOFFN` writer - "]
31495 pub type SoffnW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
31496 impl R {
31497 #[doc = "Bit 0"]
31498 #[inline(always)]
31499 pub fn suspsts(&self) -> SuspstsR {
31500 SuspstsR::new((self.bits & 1) != 0)
31501 }
31502 #[doc = "Bits 1:2"]
31503 #[inline(always)]
31504 pub fn enumspd(&self) -> EnumspdR {
31505 EnumspdR::new(((self.bits >> 1) & 3) as u8)
31506 }
31507 #[doc = "Bit 3"]
31508 #[inline(always)]
31509 pub fn errticerr(&self) -> ErrticerrR {
31510 ErrticerrR::new(((self.bits >> 3) & 1) != 0)
31511 }
31512 #[doc = "Bits 8:21"]
31513 #[inline(always)]
31514 pub fn soffn(&self) -> SoffnR {
31515 SoffnR::new(((self.bits >> 8) & 0x3fff) as u16)
31516 }
31517 }
31518 impl W {
31519 #[doc = "Bit 0"]
31520 #[inline(always)]
31521 pub fn suspsts(&mut self) -> SuspstsW<'_, DstsSpec> {
31522 SuspstsW::new(self, 0)
31523 }
31524 #[doc = "Bits 1:2"]
31525 #[inline(always)]
31526 pub fn enumspd(&mut self) -> EnumspdW<'_, DstsSpec> {
31527 EnumspdW::new(self, 1)
31528 }
31529 #[doc = "Bit 3"]
31530 #[inline(always)]
31531 pub fn errticerr(&mut self) -> ErrticerrW<'_, DstsSpec> {
31532 ErrticerrW::new(self, 3)
31533 }
31534 #[doc = "Bits 8:21"]
31535 #[inline(always)]
31536 pub fn soffn(&mut self) -> SoffnW<'_, DstsSpec> {
31537 SoffnW::new(self, 8)
31538 }
31539 }
31540 #[doc = "DOTG_DSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`dsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31541 pub struct DstsSpec;
31542 impl crate::RegisterSpec for DstsSpec {
31543 type Ux = u32;
31544 }
31545 #[doc = "`read()` method returns [`dsts::R`](R) reader structure"]
31546 impl crate::Readable for DstsSpec {}
31547 #[doc = "`write(|w| ..)` method takes [`dsts::W`](W) writer structure"]
31548 impl crate::Writable for DstsSpec {
31549 type Safety = crate::Unsafe;
31550 }
31551 #[doc = "`reset()` method sets DSTS to value 0"]
31552 impl crate::Resettable for DstsSpec {}
31553 }
31554 #[doc = "DIEPMSK (rw) register accessor: DOTG_DIEPMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`diepmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`diepmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepmsk`] module"]
31555 #[doc(alias = "DIEPMSK")]
31556 pub type Diepmsk = crate::Reg<diepmsk::DiepmskSpec>;
31557 #[doc = "DOTG_DIEPMSK"]
31558 pub mod diepmsk {
31559 #[doc = "Register `DIEPMSK` reader"]
31560 pub type R = crate::R<DiepmskSpec>;
31561 #[doc = "Register `DIEPMSK` writer"]
31562 pub type W = crate::W<DiepmskSpec>;
31563 #[doc = "Field `XFERCOMPLMSK` reader - "]
31564 pub type XfercomplmskR = crate::BitReader;
31565 #[doc = "Field `XFERCOMPLMSK` writer - "]
31566 pub type XfercomplmskW<'a, REG> = crate::BitWriter<'a, REG>;
31567 #[doc = "Field `EPDISBLDMSK` reader - "]
31568 pub type EpdisbldmskR = crate::BitReader;
31569 #[doc = "Field `EPDISBLDMSK` writer - "]
31570 pub type EpdisbldmskW<'a, REG> = crate::BitWriter<'a, REG>;
31571 #[doc = "Field `AHBERRMSK` reader - "]
31572 pub type AhberrmskR = crate::BitReader;
31573 #[doc = "Field `AHBERRMSK` writer - "]
31574 pub type AhberrmskW<'a, REG> = crate::BitWriter<'a, REG>;
31575 #[doc = "Field `TIMEOUTMSK` reader - "]
31576 pub type TimeoutmskR = crate::BitReader;
31577 #[doc = "Field `TIMEOUTMSK` writer - "]
31578 pub type TimeoutmskW<'a, REG> = crate::BitWriter<'a, REG>;
31579 #[doc = "Field `INTKNTXFEMPMSK` reader - "]
31580 pub type IntkntxfempmskR = crate::BitReader;
31581 #[doc = "Field `INTKNTXFEMPMSK` writer - "]
31582 pub type IntkntxfempmskW<'a, REG> = crate::BitWriter<'a, REG>;
31583 #[doc = "Field `INTKNEPMISMSK` reader - "]
31584 pub type IntknepmismskR = crate::BitReader;
31585 #[doc = "Field `INTKNEPMISMSK` writer - "]
31586 pub type IntknepmismskW<'a, REG> = crate::BitWriter<'a, REG>;
31587 #[doc = "Field `INEPNAKEFFMSK` reader - "]
31588 pub type InepnakeffmskR = crate::BitReader;
31589 #[doc = "Field `INEPNAKEFFMSK` writer - "]
31590 pub type InepnakeffmskW<'a, REG> = crate::BitWriter<'a, REG>;
31591 #[doc = "Field `TXFIFOUNDRNMSK` reader - "]
31592 pub type TxfifoundrnmskR = crate::BitReader;
31593 #[doc = "Field `TXFIFOUNDRNMSK` writer - "]
31594 pub type TxfifoundrnmskW<'a, REG> = crate::BitWriter<'a, REG>;
31595 impl R {
31596 #[doc = "Bit 0"]
31597 #[inline(always)]
31598 pub fn xfercomplmsk(&self) -> XfercomplmskR {
31599 XfercomplmskR::new((self.bits & 1) != 0)
31600 }
31601 #[doc = "Bit 1"]
31602 #[inline(always)]
31603 pub fn epdisbldmsk(&self) -> EpdisbldmskR {
31604 EpdisbldmskR::new(((self.bits >> 1) & 1) != 0)
31605 }
31606 #[doc = "Bit 2"]
31607 #[inline(always)]
31608 pub fn ahberrmsk(&self) -> AhberrmskR {
31609 AhberrmskR::new(((self.bits >> 2) & 1) != 0)
31610 }
31611 #[doc = "Bit 3"]
31612 #[inline(always)]
31613 pub fn timeoutmsk(&self) -> TimeoutmskR {
31614 TimeoutmskR::new(((self.bits >> 3) & 1) != 0)
31615 }
31616 #[doc = "Bit 4"]
31617 #[inline(always)]
31618 pub fn intkntxfempmsk(&self) -> IntkntxfempmskR {
31619 IntkntxfempmskR::new(((self.bits >> 4) & 1) != 0)
31620 }
31621 #[doc = "Bit 5"]
31622 #[inline(always)]
31623 pub fn intknepmismsk(&self) -> IntknepmismskR {
31624 IntknepmismskR::new(((self.bits >> 5) & 1) != 0)
31625 }
31626 #[doc = "Bit 6"]
31627 #[inline(always)]
31628 pub fn inepnakeffmsk(&self) -> InepnakeffmskR {
31629 InepnakeffmskR::new(((self.bits >> 6) & 1) != 0)
31630 }
31631 #[doc = "Bit 8"]
31632 #[inline(always)]
31633 pub fn txfifoundrnmsk(&self) -> TxfifoundrnmskR {
31634 TxfifoundrnmskR::new(((self.bits >> 8) & 1) != 0)
31635 }
31636 }
31637 impl W {
31638 #[doc = "Bit 0"]
31639 #[inline(always)]
31640 pub fn xfercomplmsk(&mut self) -> XfercomplmskW<'_, DiepmskSpec> {
31641 XfercomplmskW::new(self, 0)
31642 }
31643 #[doc = "Bit 1"]
31644 #[inline(always)]
31645 pub fn epdisbldmsk(&mut self) -> EpdisbldmskW<'_, DiepmskSpec> {
31646 EpdisbldmskW::new(self, 1)
31647 }
31648 #[doc = "Bit 2"]
31649 #[inline(always)]
31650 pub fn ahberrmsk(&mut self) -> AhberrmskW<'_, DiepmskSpec> {
31651 AhberrmskW::new(self, 2)
31652 }
31653 #[doc = "Bit 3"]
31654 #[inline(always)]
31655 pub fn timeoutmsk(&mut self) -> TimeoutmskW<'_, DiepmskSpec> {
31656 TimeoutmskW::new(self, 3)
31657 }
31658 #[doc = "Bit 4"]
31659 #[inline(always)]
31660 pub fn intkntxfempmsk(&mut self) -> IntkntxfempmskW<'_, DiepmskSpec> {
31661 IntkntxfempmskW::new(self, 4)
31662 }
31663 #[doc = "Bit 5"]
31664 #[inline(always)]
31665 pub fn intknepmismsk(&mut self) -> IntknepmismskW<'_, DiepmskSpec> {
31666 IntknepmismskW::new(self, 5)
31667 }
31668 #[doc = "Bit 6"]
31669 #[inline(always)]
31670 pub fn inepnakeffmsk(&mut self) -> InepnakeffmskW<'_, DiepmskSpec> {
31671 InepnakeffmskW::new(self, 6)
31672 }
31673 #[doc = "Bit 8"]
31674 #[inline(always)]
31675 pub fn txfifoundrnmsk(&mut self) -> TxfifoundrnmskW<'_, DiepmskSpec> {
31676 TxfifoundrnmskW::new(self, 8)
31677 }
31678 }
31679 #[doc = "DOTG_DIEPMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`diepmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`diepmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31680 pub struct DiepmskSpec;
31681 impl crate::RegisterSpec for DiepmskSpec {
31682 type Ux = u32;
31683 }
31684 #[doc = "`read()` method returns [`diepmsk::R`](R) reader structure"]
31685 impl crate::Readable for DiepmskSpec {}
31686 #[doc = "`write(|w| ..)` method takes [`diepmsk::W`](W) writer structure"]
31687 impl crate::Writable for DiepmskSpec {
31688 type Safety = crate::Unsafe;
31689 }
31690 #[doc = "`reset()` method sets DIEPMSK to value 0"]
31691 impl crate::Resettable for DiepmskSpec {}
31692 }
31693 #[doc = "DOEPMSK (rw) register accessor: DOTG_DOEPMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`doepmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doepmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepmsk`] module"]
31694 #[doc(alias = "DOEPMSK")]
31695 pub type Doepmsk = crate::Reg<doepmsk::DoepmskSpec>;
31696 #[doc = "DOTG_DOEPMSK"]
31697 pub mod doepmsk {
31698 #[doc = "Register `DOEPMSK` reader"]
31699 pub type R = crate::R<DoepmskSpec>;
31700 #[doc = "Register `DOEPMSK` writer"]
31701 pub type W = crate::W<DoepmskSpec>;
31702 #[doc = "Field `XFERCOMPLMSK` reader - "]
31703 pub type XfercomplmskR = crate::BitReader;
31704 #[doc = "Field `XFERCOMPLMSK` writer - "]
31705 pub type XfercomplmskW<'a, REG> = crate::BitWriter<'a, REG>;
31706 #[doc = "Field `EPDISBLDMSK` reader - "]
31707 pub type EpdisbldmskR = crate::BitReader;
31708 #[doc = "Field `EPDISBLDMSK` writer - "]
31709 pub type EpdisbldmskW<'a, REG> = crate::BitWriter<'a, REG>;
31710 #[doc = "Field `AHBERRMSK` reader - "]
31711 pub type AhberrmskR = crate::BitReader;
31712 #[doc = "Field `AHBERRMSK` writer - "]
31713 pub type AhberrmskW<'a, REG> = crate::BitWriter<'a, REG>;
31714 #[doc = "Field `SETUPMSK` reader - "]
31715 pub type SetupmskR = crate::BitReader;
31716 #[doc = "Field `SETUPMSK` writer - "]
31717 pub type SetupmskW<'a, REG> = crate::BitWriter<'a, REG>;
31718 #[doc = "Field `OUTTKNEPDISMSK` reader - "]
31719 pub type OuttknepdismskR = crate::BitReader;
31720 #[doc = "Field `OUTTKNEPDISMSK` writer - "]
31721 pub type OuttknepdismskW<'a, REG> = crate::BitWriter<'a, REG>;
31722 #[doc = "Field `BACK2BACKSETUP` reader - "]
31723 pub type Back2backsetupR = crate::BitReader;
31724 #[doc = "Field `BACK2BACKSETUP` writer - "]
31725 pub type Back2backsetupW<'a, REG> = crate::BitWriter<'a, REG>;
31726 #[doc = "Field `OUTPKTERRMSK` reader - "]
31727 pub type OutpkterrmskR = crate::BitReader;
31728 #[doc = "Field `OUTPKTERRMSK` writer - "]
31729 pub type OutpkterrmskW<'a, REG> = crate::BitWriter<'a, REG>;
31730 impl R {
31731 #[doc = "Bit 0"]
31732 #[inline(always)]
31733 pub fn xfercomplmsk(&self) -> XfercomplmskR {
31734 XfercomplmskR::new((self.bits & 1) != 0)
31735 }
31736 #[doc = "Bit 1"]
31737 #[inline(always)]
31738 pub fn epdisbldmsk(&self) -> EpdisbldmskR {
31739 EpdisbldmskR::new(((self.bits >> 1) & 1) != 0)
31740 }
31741 #[doc = "Bit 2"]
31742 #[inline(always)]
31743 pub fn ahberrmsk(&self) -> AhberrmskR {
31744 AhberrmskR::new(((self.bits >> 2) & 1) != 0)
31745 }
31746 #[doc = "Bit 3"]
31747 #[inline(always)]
31748 pub fn setupmsk(&self) -> SetupmskR {
31749 SetupmskR::new(((self.bits >> 3) & 1) != 0)
31750 }
31751 #[doc = "Bit 4"]
31752 #[inline(always)]
31753 pub fn outtknepdismsk(&self) -> OuttknepdismskR {
31754 OuttknepdismskR::new(((self.bits >> 4) & 1) != 0)
31755 }
31756 #[doc = "Bit 6"]
31757 #[inline(always)]
31758 pub fn back2backsetup(&self) -> Back2backsetupR {
31759 Back2backsetupR::new(((self.bits >> 6) & 1) != 0)
31760 }
31761 #[doc = "Bit 8"]
31762 #[inline(always)]
31763 pub fn outpkterrmsk(&self) -> OutpkterrmskR {
31764 OutpkterrmskR::new(((self.bits >> 8) & 1) != 0)
31765 }
31766 }
31767 impl W {
31768 #[doc = "Bit 0"]
31769 #[inline(always)]
31770 pub fn xfercomplmsk(&mut self) -> XfercomplmskW<'_, DoepmskSpec> {
31771 XfercomplmskW::new(self, 0)
31772 }
31773 #[doc = "Bit 1"]
31774 #[inline(always)]
31775 pub fn epdisbldmsk(&mut self) -> EpdisbldmskW<'_, DoepmskSpec> {
31776 EpdisbldmskW::new(self, 1)
31777 }
31778 #[doc = "Bit 2"]
31779 #[inline(always)]
31780 pub fn ahberrmsk(&mut self) -> AhberrmskW<'_, DoepmskSpec> {
31781 AhberrmskW::new(self, 2)
31782 }
31783 #[doc = "Bit 3"]
31784 #[inline(always)]
31785 pub fn setupmsk(&mut self) -> SetupmskW<'_, DoepmskSpec> {
31786 SetupmskW::new(self, 3)
31787 }
31788 #[doc = "Bit 4"]
31789 #[inline(always)]
31790 pub fn outtknepdismsk(&mut self) -> OuttknepdismskW<'_, DoepmskSpec> {
31791 OuttknepdismskW::new(self, 4)
31792 }
31793 #[doc = "Bit 6"]
31794 #[inline(always)]
31795 pub fn back2backsetup(&mut self) -> Back2backsetupW<'_, DoepmskSpec> {
31796 Back2backsetupW::new(self, 6)
31797 }
31798 #[doc = "Bit 8"]
31799 #[inline(always)]
31800 pub fn outpkterrmsk(&mut self) -> OutpkterrmskW<'_, DoepmskSpec> {
31801 OutpkterrmskW::new(self, 8)
31802 }
31803 }
31804 #[doc = "DOTG_DOEPMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`doepmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doepmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31805 pub struct DoepmskSpec;
31806 impl crate::RegisterSpec for DoepmskSpec {
31807 type Ux = u32;
31808 }
31809 #[doc = "`read()` method returns [`doepmsk::R`](R) reader structure"]
31810 impl crate::Readable for DoepmskSpec {}
31811 #[doc = "`write(|w| ..)` method takes [`doepmsk::W`](W) writer structure"]
31812 impl crate::Writable for DoepmskSpec {
31813 type Safety = crate::Unsafe;
31814 }
31815 #[doc = "`reset()` method sets DOEPMSK to value 0"]
31816 impl crate::Resettable for DoepmskSpec {}
31817 }
31818 #[doc = "DAINT (rw) register accessor: DOTG_DAINT\n\nYou can [`read`](crate::Reg::read) this register and get [`daint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daint`] module"]
31819 #[doc(alias = "DAINT")]
31820 pub type Daint = crate::Reg<daint::DaintSpec>;
31821 #[doc = "DOTG_DAINT"]
31822 pub mod daint {
31823 #[doc = "Register `DAINT` reader"]
31824 pub type R = crate::R<DaintSpec>;
31825 #[doc = "Register `DAINT` writer"]
31826 pub type W = crate::W<DaintSpec>;
31827 #[doc = "Field `INEPINT` reader - "]
31828 pub type InepintR = crate::FieldReader<u16>;
31829 #[doc = "Field `INEPINT` writer - "]
31830 pub type InepintW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
31831 impl R {
31832 #[doc = "Bits 0:15"]
31833 #[inline(always)]
31834 pub fn inepint(&self) -> InepintR {
31835 InepintR::new((self.bits & 0xffff) as u16)
31836 }
31837 }
31838 impl W {
31839 #[doc = "Bits 0:15"]
31840 #[inline(always)]
31841 pub fn inepint(&mut self) -> InepintW<'_, DaintSpec> {
31842 InepintW::new(self, 0)
31843 }
31844 }
31845 #[doc = "DOTG_DAINT\n\nYou can [`read`](crate::Reg::read) this register and get [`daint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31846 pub struct DaintSpec;
31847 impl crate::RegisterSpec for DaintSpec {
31848 type Ux = u32;
31849 }
31850 #[doc = "`read()` method returns [`daint::R`](R) reader structure"]
31851 impl crate::Readable for DaintSpec {}
31852 #[doc = "`write(|w| ..)` method takes [`daint::W`](W) writer structure"]
31853 impl crate::Writable for DaintSpec {
31854 type Safety = crate::Unsafe;
31855 }
31856 #[doc = "`reset()` method sets DAINT to value 0"]
31857 impl crate::Resettable for DaintSpec {}
31858 }
31859 #[doc = "DAINTMSK (rw) register accessor: DOTG_DAINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`daintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daintmsk`] module"]
31860 #[doc(alias = "DAINTMSK")]
31861 pub type Daintmsk = crate::Reg<daintmsk::DaintmskSpec>;
31862 #[doc = "DOTG_DAINTMSK"]
31863 pub mod daintmsk {
31864 #[doc = "Register `DAINTMSK` reader"]
31865 pub type R = crate::R<DaintmskSpec>;
31866 #[doc = "Register `DAINTMSK` writer"]
31867 pub type W = crate::W<DaintmskSpec>;
31868 #[doc = "Field `INEPINT` reader - "]
31869 pub type InepintR = crate::FieldReader<u16>;
31870 #[doc = "Field `INEPINT` writer - "]
31871 pub type InepintW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
31872 impl R {
31873 #[doc = "Bits 0:15"]
31874 #[inline(always)]
31875 pub fn inepint(&self) -> InepintR {
31876 InepintR::new((self.bits & 0xffff) as u16)
31877 }
31878 }
31879 impl W {
31880 #[doc = "Bits 0:15"]
31881 #[inline(always)]
31882 pub fn inepint(&mut self) -> InepintW<'_, DaintmskSpec> {
31883 InepintW::new(self, 0)
31884 }
31885 }
31886 #[doc = "DOTG_DAINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`daintmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daintmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31887 pub struct DaintmskSpec;
31888 impl crate::RegisterSpec for DaintmskSpec {
31889 type Ux = u32;
31890 }
31891 #[doc = "`read()` method returns [`daintmsk::R`](R) reader structure"]
31892 impl crate::Readable for DaintmskSpec {}
31893 #[doc = "`write(|w| ..)` method takes [`daintmsk::W`](W) writer structure"]
31894 impl crate::Writable for DaintmskSpec {
31895 type Safety = crate::Unsafe;
31896 }
31897 #[doc = "`reset()` method sets DAINTMSK to value 0"]
31898 impl crate::Resettable for DaintmskSpec {}
31899 }
31900 #[doc = "DTKNQR1 (rw) register accessor: DOTG_DTKNQR1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtknqr1`] module"]
31901 #[doc(alias = "DTKNQR1")]
31902 pub type Dtknqr1 = crate::Reg<dtknqr1::Dtknqr1Spec>;
31903 #[doc = "DOTG_DTKNQR1"]
31904 pub mod dtknqr1 {
31905 #[doc = "Register `DTKNQR1` reader"]
31906 pub type R = crate::R<Dtknqr1Spec>;
31907 #[doc = "Register `DTKNQR1` writer"]
31908 pub type W = crate::W<Dtknqr1Spec>;
31909 #[doc = "Field `INTKNWPTR` reader - "]
31910 pub type IntknwptrR = crate::FieldReader;
31911 #[doc = "Field `INTKNWPTR` writer - "]
31912 pub type IntknwptrW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
31913 #[doc = "Field `WRAPBIT` reader - "]
31914 pub type WrapbitR = crate::BitReader;
31915 #[doc = "Field `WRAPBIT` writer - "]
31916 pub type WrapbitW<'a, REG> = crate::BitWriter<'a, REG>;
31917 #[doc = "Field `EPTKN` reader - "]
31918 pub type EptknR = crate::FieldReader<u32>;
31919 #[doc = "Field `EPTKN` writer - "]
31920 pub type EptknW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
31921 impl R {
31922 #[doc = "Bits 0:4"]
31923 #[inline(always)]
31924 pub fn intknwptr(&self) -> IntknwptrR {
31925 IntknwptrR::new((self.bits & 0x1f) as u8)
31926 }
31927 #[doc = "Bit 7"]
31928 #[inline(always)]
31929 pub fn wrapbit(&self) -> WrapbitR {
31930 WrapbitR::new(((self.bits >> 7) & 1) != 0)
31931 }
31932 #[doc = "Bits 8:31"]
31933 #[inline(always)]
31934 pub fn eptkn(&self) -> EptknR {
31935 EptknR::new((self.bits >> 8) & 0x00ff_ffff)
31936 }
31937 }
31938 impl W {
31939 #[doc = "Bits 0:4"]
31940 #[inline(always)]
31941 pub fn intknwptr(&mut self) -> IntknwptrW<'_, Dtknqr1Spec> {
31942 IntknwptrW::new(self, 0)
31943 }
31944 #[doc = "Bit 7"]
31945 #[inline(always)]
31946 pub fn wrapbit(&mut self) -> WrapbitW<'_, Dtknqr1Spec> {
31947 WrapbitW::new(self, 7)
31948 }
31949 #[doc = "Bits 8:31"]
31950 #[inline(always)]
31951 pub fn eptkn(&mut self) -> EptknW<'_, Dtknqr1Spec> {
31952 EptknW::new(self, 8)
31953 }
31954 }
31955 #[doc = "DOTG_DTKNQR1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31956 pub struct Dtknqr1Spec;
31957 impl crate::RegisterSpec for Dtknqr1Spec {
31958 type Ux = u32;
31959 }
31960 #[doc = "`read()` method returns [`dtknqr1::R`](R) reader structure"]
31961 impl crate::Readable for Dtknqr1Spec {}
31962 #[doc = "`write(|w| ..)` method takes [`dtknqr1::W`](W) writer structure"]
31963 impl crate::Writable for Dtknqr1Spec {
31964 type Safety = crate::Unsafe;
31965 }
31966 #[doc = "`reset()` method sets DTKNQR1 to value 0"]
31967 impl crate::Resettable for Dtknqr1Spec {}
31968 }
31969 #[doc = "DTKNQR2 (rw) register accessor: DOTG_DTKNQR2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtknqr2`] module"]
31970 #[doc(alias = "DTKNQR2")]
31971 pub type Dtknqr2 = crate::Reg<dtknqr2::Dtknqr2Spec>;
31972 #[doc = "DOTG_DTKNQR2"]
31973 pub mod dtknqr2 {
31974 #[doc = "Register `DTKNQR2` reader"]
31975 pub type R = crate::R<Dtknqr2Spec>;
31976 #[doc = "Register `DTKNQR2` writer"]
31977 pub type W = crate::W<Dtknqr2Spec>;
31978 impl core::fmt::Debug for R {
31979 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
31980 write!(f, "{}", self.bits())
31981 }
31982 }
31983 impl W {}
31984 #[doc = "DOTG_DTKNQR2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31985 pub struct Dtknqr2Spec;
31986 impl crate::RegisterSpec for Dtknqr2Spec {
31987 type Ux = u32;
31988 }
31989 #[doc = "`read()` method returns [`dtknqr2::R`](R) reader structure"]
31990 impl crate::Readable for Dtknqr2Spec {}
31991 #[doc = "`write(|w| ..)` method takes [`dtknqr2::W`](W) writer structure"]
31992 impl crate::Writable for Dtknqr2Spec {
31993 type Safety = crate::Unsafe;
31994 }
31995 #[doc = "`reset()` method sets DTKNQR2 to value 0"]
31996 impl crate::Resettable for Dtknqr2Spec {}
31997 }
31998 #[doc = "DVBUSDIS (rw) register accessor: DOTG_DVBUSDIS\n\nYou can [`read`](crate::Reg::read) this register and get [`dvbusdis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dvbusdis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbusdis`] module"]
31999 #[doc(alias = "DVBUSDIS")]
32000 pub type Dvbusdis = crate::Reg<dvbusdis::DvbusdisSpec>;
32001 #[doc = "DOTG_DVBUSDIS"]
32002 pub mod dvbusdis {
32003 #[doc = "Register `DVBUSDIS` reader"]
32004 pub type R = crate::R<DvbusdisSpec>;
32005 #[doc = "Register `DVBUSDIS` writer"]
32006 pub type W = crate::W<DvbusdisSpec>;
32007 #[doc = "Field `DVBUSDIS` reader - "]
32008 pub type DvbusdisR = crate::FieldReader<u16>;
32009 #[doc = "Field `DVBUSDIS` writer - "]
32010 pub type DvbusdisW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
32011 impl R {
32012 #[doc = "Bits 0:15"]
32013 #[inline(always)]
32014 pub fn dvbusdis(&self) -> DvbusdisR {
32015 DvbusdisR::new((self.bits & 0xffff) as u16)
32016 }
32017 }
32018 impl W {
32019 #[doc = "Bits 0:15"]
32020 #[inline(always)]
32021 pub fn dvbusdis(&mut self) -> DvbusdisW<'_, DvbusdisSpec> {
32022 DvbusdisW::new(self, 0)
32023 }
32024 }
32025 #[doc = "DOTG_DVBUSDIS\n\nYou can [`read`](crate::Reg::read) this register and get [`dvbusdis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dvbusdis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32026 pub struct DvbusdisSpec;
32027 impl crate::RegisterSpec for DvbusdisSpec {
32028 type Ux = u32;
32029 }
32030 #[doc = "`read()` method returns [`dvbusdis::R`](R) reader structure"]
32031 impl crate::Readable for DvbusdisSpec {}
32032 #[doc = "`write(|w| ..)` method takes [`dvbusdis::W`](W) writer structure"]
32033 impl crate::Writable for DvbusdisSpec {
32034 type Safety = crate::Unsafe;
32035 }
32036 #[doc = "`reset()` method sets DVBUSDIS to value 0"]
32037 impl crate::Resettable for DvbusdisSpec {}
32038 }
32039 #[doc = "DVBUSPULSE (rw) register accessor: DOTG_DVBUSPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`dvbuspulse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dvbuspulse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbuspulse`] module"]
32040 #[doc(alias = "DVBUSPULSE")]
32041 pub type Dvbuspulse = crate::Reg<dvbuspulse::DvbuspulseSpec>;
32042 #[doc = "DOTG_DVBUSPULSE"]
32043 pub mod dvbuspulse {
32044 #[doc = "Register `DVBUSPULSE` reader"]
32045 pub type R = crate::R<DvbuspulseSpec>;
32046 #[doc = "Register `DVBUSPULSE` writer"]
32047 pub type W = crate::W<DvbuspulseSpec>;
32048 #[doc = "Field `DVBUSPULSE` reader - "]
32049 pub type DvbuspulseR = crate::FieldReader<u16>;
32050 #[doc = "Field `DVBUSPULSE` writer - "]
32051 pub type DvbuspulseW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
32052 impl R {
32053 #[doc = "Bits 0:11"]
32054 #[inline(always)]
32055 pub fn dvbuspulse(&self) -> DvbuspulseR {
32056 DvbuspulseR::new((self.bits & 0x0fff) as u16)
32057 }
32058 }
32059 impl W {
32060 #[doc = "Bits 0:11"]
32061 #[inline(always)]
32062 pub fn dvbuspulse(&mut self) -> DvbuspulseW<'_, DvbuspulseSpec> {
32063 DvbuspulseW::new(self, 0)
32064 }
32065 }
32066 #[doc = "DOTG_DVBUSPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`dvbuspulse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dvbuspulse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32067 pub struct DvbuspulseSpec;
32068 impl crate::RegisterSpec for DvbuspulseSpec {
32069 type Ux = u32;
32070 }
32071 #[doc = "`read()` method returns [`dvbuspulse::R`](R) reader structure"]
32072 impl crate::Readable for DvbuspulseSpec {}
32073 #[doc = "`write(|w| ..)` method takes [`dvbuspulse::W`](W) writer structure"]
32074 impl crate::Writable for DvbuspulseSpec {
32075 type Safety = crate::Unsafe;
32076 }
32077 #[doc = "`reset()` method sets DVBUSPULSE to value 0"]
32078 impl crate::Resettable for DvbuspulseSpec {}
32079 }
32080 #[doc = "DTHRCTL (rw) register accessor: DOTG_DTHRCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`dthrctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dthrctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dthrctl`] module"]
32081 #[doc(alias = "DTHRCTL")]
32082 pub type Dthrctl = crate::Reg<dthrctl::DthrctlSpec>;
32083 #[doc = "DOTG_DTHRCTL"]
32084 pub mod dthrctl {
32085 #[doc = "Register `DTHRCTL` reader"]
32086 pub type R = crate::R<DthrctlSpec>;
32087 #[doc = "Register `DTHRCTL` writer"]
32088 pub type W = crate::W<DthrctlSpec>;
32089 #[doc = "Field `NONISOTHREN` reader - "]
32090 pub type NonisothrenR = crate::BitReader;
32091 #[doc = "Field `NONISOTHREN` writer - "]
32092 pub type NonisothrenW<'a, REG> = crate::BitWriter<'a, REG>;
32093 #[doc = "Field `ISOTHREN` reader - "]
32094 pub type IsothrenR = crate::BitReader;
32095 #[doc = "Field `ISOTHREN` writer - "]
32096 pub type IsothrenW<'a, REG> = crate::BitWriter<'a, REG>;
32097 #[doc = "Field `TXTHRLEN` reader - "]
32098 pub type TxthrlenR = crate::FieldReader<u16>;
32099 #[doc = "Field `TXTHRLEN` writer - "]
32100 pub type TxthrlenW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
32101 #[doc = "Field `RXTHREN` reader - "]
32102 pub type RxthrenR = crate::BitReader;
32103 #[doc = "Field `RXTHREN` writer - "]
32104 pub type RxthrenW<'a, REG> = crate::BitWriter<'a, REG>;
32105 #[doc = "Field `RXTHRLEN` reader - "]
32106 pub type RxthrlenR = crate::FieldReader<u16>;
32107 #[doc = "Field `RXTHRLEN` writer - "]
32108 pub type RxthrlenW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
32109 #[doc = "Field `ARBPRKEN` reader - "]
32110 pub type ArbprkenR = crate::BitReader;
32111 #[doc = "Field `ARBPRKEN` writer - "]
32112 pub type ArbprkenW<'a, REG> = crate::BitWriter<'a, REG>;
32113 impl R {
32114 #[doc = "Bit 0"]
32115 #[inline(always)]
32116 pub fn nonisothren(&self) -> NonisothrenR {
32117 NonisothrenR::new((self.bits & 1) != 0)
32118 }
32119 #[doc = "Bit 1"]
32120 #[inline(always)]
32121 pub fn isothren(&self) -> IsothrenR {
32122 IsothrenR::new(((self.bits >> 1) & 1) != 0)
32123 }
32124 #[doc = "Bits 2:10"]
32125 #[inline(always)]
32126 pub fn txthrlen(&self) -> TxthrlenR {
32127 TxthrlenR::new(((self.bits >> 2) & 0x01ff) as u16)
32128 }
32129 #[doc = "Bit 16"]
32130 #[inline(always)]
32131 pub fn rxthren(&self) -> RxthrenR {
32132 RxthrenR::new(((self.bits >> 16) & 1) != 0)
32133 }
32134 #[doc = "Bits 17:25"]
32135 #[inline(always)]
32136 pub fn rxthrlen(&self) -> RxthrlenR {
32137 RxthrlenR::new(((self.bits >> 17) & 0x01ff) as u16)
32138 }
32139 #[doc = "Bit 27"]
32140 #[inline(always)]
32141 pub fn arbprken(&self) -> ArbprkenR {
32142 ArbprkenR::new(((self.bits >> 27) & 1) != 0)
32143 }
32144 }
32145 impl W {
32146 #[doc = "Bit 0"]
32147 #[inline(always)]
32148 pub fn nonisothren(&mut self) -> NonisothrenW<'_, DthrctlSpec> {
32149 NonisothrenW::new(self, 0)
32150 }
32151 #[doc = "Bit 1"]
32152 #[inline(always)]
32153 pub fn isothren(&mut self) -> IsothrenW<'_, DthrctlSpec> {
32154 IsothrenW::new(self, 1)
32155 }
32156 #[doc = "Bits 2:10"]
32157 #[inline(always)]
32158 pub fn txthrlen(&mut self) -> TxthrlenW<'_, DthrctlSpec> {
32159 TxthrlenW::new(self, 2)
32160 }
32161 #[doc = "Bit 16"]
32162 #[inline(always)]
32163 pub fn rxthren(&mut self) -> RxthrenW<'_, DthrctlSpec> {
32164 RxthrenW::new(self, 16)
32165 }
32166 #[doc = "Bits 17:25"]
32167 #[inline(always)]
32168 pub fn rxthrlen(&mut self) -> RxthrlenW<'_, DthrctlSpec> {
32169 RxthrlenW::new(self, 17)
32170 }
32171 #[doc = "Bit 27"]
32172 #[inline(always)]
32173 pub fn arbprken(&mut self) -> ArbprkenW<'_, DthrctlSpec> {
32174 ArbprkenW::new(self, 27)
32175 }
32176 }
32177 #[doc = "DOTG_DTHRCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`dthrctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dthrctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32178 pub struct DthrctlSpec;
32179 impl crate::RegisterSpec for DthrctlSpec {
32180 type Ux = u32;
32181 }
32182 #[doc = "`read()` method returns [`dthrctl::R`](R) reader structure"]
32183 impl crate::Readable for DthrctlSpec {}
32184 #[doc = "`write(|w| ..)` method takes [`dthrctl::W`](W) writer structure"]
32185 impl crate::Writable for DthrctlSpec {
32186 type Safety = crate::Unsafe;
32187 }
32188 #[doc = "`reset()` method sets DTHRCTL to value 0"]
32189 impl crate::Resettable for DthrctlSpec {}
32190 }
32191 #[doc = "DTKNQR4 (rw) register accessor: DOTG_DTKNQR4\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtknqr4`] module"]
32192 #[doc(alias = "DTKNQR4")]
32193 pub type Dtknqr4 = crate::Reg<dtknqr4::Dtknqr4Spec>;
32194 #[doc = "DOTG_DTKNQR4"]
32195 pub mod dtknqr4 {
32196 #[doc = "Register `DTKNQR4` reader"]
32197 pub type R = crate::R<Dtknqr4Spec>;
32198 #[doc = "Register `DTKNQR4` writer"]
32199 pub type W = crate::W<Dtknqr4Spec>;
32200 impl core::fmt::Debug for R {
32201 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
32202 write!(f, "{}", self.bits())
32203 }
32204 }
32205 impl W {}
32206 #[doc = "DOTG_DTKNQR4\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32207 pub struct Dtknqr4Spec;
32208 impl crate::RegisterSpec for Dtknqr4Spec {
32209 type Ux = u32;
32210 }
32211 #[doc = "`read()` method returns [`dtknqr4::R`](R) reader structure"]
32212 impl crate::Readable for Dtknqr4Spec {}
32213 #[doc = "`write(|w| ..)` method takes [`dtknqr4::W`](W) writer structure"]
32214 impl crate::Writable for Dtknqr4Spec {
32215 type Safety = crate::Unsafe;
32216 }
32217 #[doc = "`reset()` method sets DTKNQR4 to value 0"]
32218 impl crate::Resettable for Dtknqr4Spec {}
32219 }
32220 #[doc = "DEACHINT (rw) register accessor: DOTG_DEACHINT\n\nYou can [`read`](crate::Reg::read) this register and get [`deachint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deachint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachint`] module"]
32221 #[doc(alias = "DEACHINT")]
32222 pub type Deachint = crate::Reg<deachint::DeachintSpec>;
32223 #[doc = "DOTG_DEACHINT"]
32224 pub mod deachint {
32225 #[doc = "Register `DEACHINT` reader"]
32226 pub type R = crate::R<DeachintSpec>;
32227 #[doc = "Register `DEACHINT` writer"]
32228 pub type W = crate::W<DeachintSpec>;
32229 impl core::fmt::Debug for R {
32230 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
32231 write!(f, "{}", self.bits())
32232 }
32233 }
32234 impl W {}
32235 #[doc = "DOTG_DEACHINT\n\nYou can [`read`](crate::Reg::read) this register and get [`deachint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deachint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32236 pub struct DeachintSpec;
32237 impl crate::RegisterSpec for DeachintSpec {
32238 type Ux = u32;
32239 }
32240 #[doc = "`read()` method returns [`deachint::R`](R) reader structure"]
32241 impl crate::Readable for DeachintSpec {}
32242 #[doc = "`write(|w| ..)` method takes [`deachint::W`](W) writer structure"]
32243 impl crate::Writable for DeachintSpec {
32244 type Safety = crate::Unsafe;
32245 }
32246 #[doc = "`reset()` method sets DEACHINT to value 0"]
32247 impl crate::Resettable for DeachintSpec {}
32248 }
32249 #[doc = "DEACHINTMSK (rw) register accessor: DOTG_DEACHINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`deachintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deachintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachintmsk`] module"]
32250 #[doc(alias = "DEACHINTMSK")]
32251 pub type Deachintmsk = crate::Reg<deachintmsk::DeachintmskSpec>;
32252 #[doc = "DOTG_DEACHINTMSK"]
32253 pub mod deachintmsk {
32254 #[doc = "Register `DEACHINTMSK` reader"]
32255 pub type R = crate::R<DeachintmskSpec>;
32256 #[doc = "Register `DEACHINTMSK` writer"]
32257 pub type W = crate::W<DeachintmskSpec>;
32258 impl core::fmt::Debug for R {
32259 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
32260 write!(f, "{}", self.bits())
32261 }
32262 }
32263 impl W {}
32264 #[doc = "DOTG_DEACHINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`deachintmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deachintmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32265 pub struct DeachintmskSpec;
32266 impl crate::RegisterSpec for DeachintmskSpec {
32267 type Ux = u32;
32268 }
32269 #[doc = "`read()` method returns [`deachintmsk::R`](R) reader structure"]
32270 impl crate::Readable for DeachintmskSpec {}
32271 #[doc = "`write(|w| ..)` method takes [`deachintmsk::W`](W) writer structure"]
32272 impl crate::Writable for DeachintmskSpec {
32273 type Safety = crate::Unsafe;
32274 }
32275 #[doc = "`reset()` method sets DEACHINTMSK to value 0"]
32276 impl crate::Resettable for DeachintmskSpec {}
32277 }
32278 #[doc = "PCGCCTL (rw) register accessor: DOTG_PCGCCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`pcgcctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcgcctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcgcctl`] module"]
32279 #[doc(alias = "PCGCCTL")]
32280 pub type Pcgcctl = crate::Reg<pcgcctl::PcgcctlSpec>;
32281 #[doc = "DOTG_PCGCCTL"]
32282 pub mod pcgcctl {
32283 #[doc = "Register `PCGCCTL` reader"]
32284 pub type R = crate::R<PcgcctlSpec>;
32285 #[doc = "Register `PCGCCTL` writer"]
32286 pub type W = crate::W<PcgcctlSpec>;
32287 impl core::fmt::Debug for R {
32288 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
32289 write!(f, "{}", self.bits())
32290 }
32291 }
32292 impl W {}
32293 #[doc = "DOTG_PCGCCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`pcgcctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcgcctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32294 pub struct PcgcctlSpec;
32295 impl crate::RegisterSpec for PcgcctlSpec {
32296 type Ux = u32;
32297 }
32298 #[doc = "`read()` method returns [`pcgcctl::R`](R) reader structure"]
32299 impl crate::Readable for PcgcctlSpec {}
32300 #[doc = "`write(|w| ..)` method takes [`pcgcctl::W`](W) writer structure"]
32301 impl crate::Writable for PcgcctlSpec {
32302 type Safety = crate::Unsafe;
32303 }
32304 #[doc = "`reset()` method sets PCGCCTL to value 0"]
32305 impl crate::Resettable for PcgcctlSpec {}
32306 }
32307}
32308#[unsafe(no_mangle)]
32309static mut DEVICE_PERIPHERALS: bool = false;
32310#[doc = r" All the peripherals."]
32311#[allow(non_snake_case)]
32312pub struct Peripherals {
32313 #[doc = "GLB_CTL_M"]
32314 pub glb_ctl_m: GlbCtlM,
32315 #[doc = "GPIO0"]
32316 pub gpio0: Gpio0,
32317 #[doc = "UART0"]
32318 pub uart0: Uart0,
32319 #[doc = "TIMER"]
32320 pub timer: Timer,
32321 #[doc = "WDT"]
32322 pub wdt: Wdt,
32323 #[doc = "TCXO"]
32324 pub tcxo: Tcxo,
32325 #[doc = "I2C0"]
32326 pub i2c0: I2c0,
32327 #[doc = "SPI0"]
32328 pub spi0: Spi0,
32329 #[doc = "PWM"]
32330 pub pwm: Pwm,
32331 #[doc = "DMA"]
32332 pub dma: Dma,
32333 #[doc = "RTC"]
32334 pub rtc: Rtc,
32335 #[doc = "TRNG"]
32336 pub trng: Trng,
32337 #[doc = "GPIO1"]
32338 pub gpio1: Gpio1,
32339 #[doc = "GPIO2"]
32340 pub gpio2: Gpio2,
32341 #[doc = "GPIO3"]
32342 pub gpio3: Gpio3,
32343 #[doc = "GPIO4"]
32344 pub gpio4: Gpio4,
32345 #[doc = "ULP_GPIO"]
32346 pub ulp_gpio: UlpGpio,
32347 #[doc = "UART1"]
32348 pub uart1: Uart1,
32349 #[doc = "UART2"]
32350 pub uart2: Uart2,
32351 #[doc = "I2C1"]
32352 pub i2c1: I2c1,
32353 #[doc = "SPI1"]
32354 pub spi1: Spi1,
32355 #[doc = "SPI2"]
32356 pub spi2: Spi2,
32357 #[doc = "SDMA"]
32358 pub sdma: Sdma,
32359 #[doc = "GADC"]
32360 pub gadc: Gadc,
32361 #[doc = "KEYSCAN"]
32362 pub keyscan: Keyscan,
32363 #[doc = "PDM"]
32364 pub pdm: Pdm,
32365 #[doc = "QDEC"]
32366 pub qdec: Qdec,
32367 #[doc = "USB"]
32368 pub usb: Usb,
32369}
32370impl Peripherals {
32371 #[doc = r" Returns all the peripherals *once*."]
32372 #[cfg(feature = "critical-section")]
32373 #[inline]
32374 pub fn take() -> Option<Self> {
32375 critical_section::with(|_| {
32376 if unsafe { DEVICE_PERIPHERALS } {
32377 return None;
32378 }
32379 Some(unsafe { Peripherals::steal() })
32380 })
32381 }
32382 #[doc = r" Unchecked version of `Peripherals::take`."]
32383 #[doc = r""]
32384 #[doc = r" # Safety"]
32385 #[doc = r""]
32386 #[doc = r" Each of the returned peripherals must be used at most once."]
32387 #[inline]
32388 pub unsafe fn steal() -> Self {
32389 unsafe {
32390 DEVICE_PERIPHERALS = true;
32391 Peripherals {
32392 glb_ctl_m: GlbCtlM::steal(),
32393 gpio0: Gpio0::steal(),
32394 uart0: Uart0::steal(),
32395 timer: Timer::steal(),
32396 wdt: Wdt::steal(),
32397 tcxo: Tcxo::steal(),
32398 i2c0: I2c0::steal(),
32399 spi0: Spi0::steal(),
32400 pwm: Pwm::steal(),
32401 dma: Dma::steal(),
32402 rtc: Rtc::steal(),
32403 trng: Trng::steal(),
32404 gpio1: Gpio1::steal(),
32405 gpio2: Gpio2::steal(),
32406 gpio3: Gpio3::steal(),
32407 gpio4: Gpio4::steal(),
32408 ulp_gpio: UlpGpio::steal(),
32409 uart1: Uart1::steal(),
32410 uart2: Uart2::steal(),
32411 i2c1: I2c1::steal(),
32412 spi1: Spi1::steal(),
32413 spi2: Spi2::steal(),
32414 sdma: Sdma::steal(),
32415 gadc: Gadc::steal(),
32416 keyscan: Keyscan::steal(),
32417 pdm: Pdm::steal(),
32418 qdec: Qdec::steal(),
32419 usb: Usb::steal(),
32420 }
32421 }
32422 }
32423}