bs2x-pac 0.1.0

#![doc = "Peripheral access API for BS2X microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 3;
#[allow(unused_imports)]
use generic::*;
#[doc = r"Common register and bit access and modify traits"]
pub mod generic {
    use core::marker;
    #[doc = " Generic peripheral accessor"]
    pub struct Periph<RB, const A: usize> {
        _marker: marker::PhantomData<RB>,
    }
    unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
    impl<RB, const A: usize> Periph<RB, A> {
        #[doc = "Pointer to the register block"]
        pub const PTR: *const RB = A as *const _;
        #[doc = "Return the pointer to the register block"]
        #[inline(always)]
        pub const fn ptr() -> *const RB {
            Self::PTR
        }
        #[doc = " Steal an instance of this peripheral"]
        #[doc = ""]
        #[doc = " # Safety"]
        #[doc = ""]
        #[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
        #[doc = " that may race with any existing instances, for example by only"]
        #[doc = " accessing read-only or write-only registers, or by consuming the"]
        #[doc = " original peripheral and using critical sections to coordinate"]
        #[doc = " access between multiple new instances."]
        #[doc = ""]
        #[doc = " Additionally, other software such as HALs may rely on only one"]
        #[doc = " peripheral instance existing to ensure memory safety; ensure"]
        #[doc = " no stolen instances are passed to such software."]
        pub unsafe fn steal() -> Self {
            Self {
                _marker: marker::PhantomData,
            }
        }
    }
    impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
        type Target = RB;
        #[inline(always)]
        fn deref(&self) -> &Self::Target {
            unsafe { &*Self::PTR }
        }
    }
    #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
    pub trait RawReg:
        Copy
        + From<bool>
        + core::ops::BitOr<Output = Self>
        + core::ops::BitAnd<Output = Self>
        + core::ops::BitOrAssign
        + core::ops::BitAndAssign
        + core::ops::Not<Output = Self>
        + core::ops::Shl<u8, Output = Self>
    {
        #[doc = " Mask for bits of width `WI`"]
        fn mask<const WI: u8>() -> Self;
        #[doc = " `0`"]
        const ZERO: Self;
        #[doc = " `1`"]
        const ONE: Self;
    }
    macro_rules! raw_reg {
        ($ U : ty , $ size : literal , $ mask : ident) => {
            impl RawReg for $U {
                #[inline(always)]
                fn mask<const WI: u8>() -> Self {
                    $mask::<WI>()
                }
                const ZERO: Self = 0;
                const ONE: Self = 1;
            }
            const fn $mask<const WI: u8>() -> $U {
                <$U>::MAX >> ($size - WI)
            }
            impl FieldSpec for $U {
                type Ux = $U;
            }
        };
    }
    raw_reg!(u8, 8, mask_u8);
    raw_reg!(u16, 16, mask_u16);
    raw_reg!(u32, 32, mask_u32);
    raw_reg!(u64, 64, mask_u64);
    #[doc = " Raw register type"]
    pub trait RegisterSpec {
        #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
        type Ux: RawReg;
    }
    #[doc = " Raw field type"]
    pub trait FieldSpec: Sized {
        #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
        type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
    }
    #[doc = " Marker for fields with fixed values"]
    pub trait IsEnum: FieldSpec {}
    #[doc = " Trait implemented by readable registers to enable the `read` method."]
    #[doc = ""]
    #[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
    pub trait Readable: RegisterSpec {}
    #[doc = " Trait implemented by writeable registers."]
    #[doc = ""]
    #[doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
    #[doc = ""]
    #[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
    pub trait Writable: RegisterSpec {
        #[doc = " Is it safe to write any bits to register"]
        type Safety;
        #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
        const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
        #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
        const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
    }
    #[doc = " Reset value of the register."]
    #[doc = ""]
    #[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
    #[doc = " register by using the `reset` method."]
    pub trait Resettable: RegisterSpec {
        #[doc = " Reset value of the register."]
        const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
        #[doc = " Reset value of the register."]
        #[inline(always)]
        fn reset_value() -> Self::Ux {
            Self::RESET_VALUE
        }
    }
    #[doc(hidden)]
    pub mod raw {
        use super::{BitM, FieldSpec, RegisterSpec, Unsafe, Writable, marker};
        pub struct R<REG: RegisterSpec> {
            pub(crate) bits: REG::Ux,
            pub(super) _reg: marker::PhantomData<REG>,
        }
        pub struct W<REG: RegisterSpec> {
            #[doc = "Writable bits"]
            pub(crate) bits: REG::Ux,
            pub(super) _reg: marker::PhantomData<REG>,
        }
        pub struct FieldReader<FI = u8>
        where
            FI: FieldSpec,
        {
            pub(crate) bits: FI::Ux,
            _reg: marker::PhantomData<FI>,
        }
        impl<FI: FieldSpec> FieldReader<FI> {
            #[doc = " Creates a new instance of the reader."]
            #[allow(unused)]
            #[inline(always)]
            pub(crate) const fn new(bits: FI::Ux) -> Self {
                Self {
                    bits,
                    _reg: marker::PhantomData,
                }
            }
        }
        pub struct BitReader<FI = bool> {
            pub(crate) bits: bool,
            _reg: marker::PhantomData<FI>,
        }
        impl<FI> BitReader<FI> {
            #[doc = " Creates a new instance of the reader."]
            #[allow(unused)]
            #[inline(always)]
            pub(crate) const fn new(bits: bool) -> Self {
                Self {
                    bits,
                    _reg: marker::PhantomData,
                }
            }
        }
        #[must_use = "after creating `FieldWriter` you need to call field value setting method"]
        pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
        where
            REG: Writable + RegisterSpec,
            FI: FieldSpec,
        {
            pub(crate) w: &'a mut W<REG>,
            pub(crate) o: u8,
            _field: marker::PhantomData<(FI, Safety)>,
        }
        impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
        where
            REG: Writable + RegisterSpec,
            FI: FieldSpec,
        {
            #[doc = " Creates a new instance of the writer"]
            #[allow(unused)]
            #[inline(always)]
            pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
                Self {
                    w,
                    o,
                    _field: marker::PhantomData,
                }
            }
        }
        #[must_use = "after creating `BitWriter` you need to call bit setting method"]
        pub struct BitWriter<'a, REG, FI = bool, M = BitM>
        where
            REG: Writable + RegisterSpec,
            bool: From<FI>,
        {
            pub(crate) w: &'a mut W<REG>,
            pub(crate) o: u8,
            _field: marker::PhantomData<(FI, M)>,
        }
        impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
        where
            REG: Writable + RegisterSpec,
            bool: From<FI>,
        {
            #[doc = " Creates a new instance of the writer"]
            #[allow(unused)]
            #[inline(always)]
            pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
                Self {
                    w,
                    o,
                    _field: marker::PhantomData,
                }
            }
        }
    }
    #[doc = " Register reader."]
    #[doc = ""]
    #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
    #[doc = " method."]
    pub type R<REG> = raw::R<REG>;
    impl<REG: RegisterSpec> R<REG> {
        #[doc = " Reads raw bits from register."]
        #[inline(always)]
        pub const fn bits(&self) -> REG::Ux {
            self.bits
        }
    }
    impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
    where
        REG::Ux: PartialEq,
        FI: Copy,
        REG::Ux: From<FI>,
    {
        #[inline(always)]
        fn eq(&self, other: &FI) -> bool {
            self.bits.eq(&REG::Ux::from(*other))
        }
    }
    #[doc = " Register writer."]
    #[doc = ""]
    #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
    pub type W<REG> = raw::W<REG>;
    impl<REG: Writable> W<REG> {
        #[doc = " Writes raw bits to the register."]
        #[doc = ""]
        #[doc = " # Safety"]
        #[doc = ""]
        #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
        #[inline(always)]
        pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
            self.bits = bits;
            self
        }
    }
    impl<REG> W<REG>
    where
        REG: Writable<Safety = Safe>,
    {
        #[doc = " Writes raw bits to the register."]
        #[inline(always)]
        pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
            self.bits = bits;
            self
        }
    }
    #[doc = " Field reader."]
    #[doc = ""]
    #[doc = " Result of the `read` methods of fields."]
    pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
    #[doc = " Bit-wise field reader"]
    pub type BitReader<FI = bool> = raw::BitReader<FI>;
    impl<FI: FieldSpec> FieldReader<FI> {
        #[doc = " Reads raw bits from field."]
        #[inline(always)]
        pub const fn bits(&self) -> FI::Ux {
            self.bits
        }
    }
    impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
        fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
            core::fmt::Debug::fmt(&self.bits, f)
        }
    }
    impl<FI> PartialEq<FI> for FieldReader<FI>
    where
        FI: FieldSpec + Copy,
    {
        #[inline(always)]
        fn eq(&self, other: &FI) -> bool {
            self.bits.eq(&FI::Ux::from(*other))
        }
    }
    impl<FI> PartialEq<FI> for BitReader<FI>
    where
        FI: Copy,
        bool: From<FI>,
    {
        #[inline(always)]
        fn eq(&self, other: &FI) -> bool {
            self.bits.eq(&bool::from(*other))
        }
    }
    impl<FI> BitReader<FI> {
        #[doc = " Value of the field as raw bits."]
        #[inline(always)]
        pub const fn bit(&self) -> bool {
            self.bits
        }
        #[doc = " Returns `true` if the bit is clear (0)."]
        #[inline(always)]
        pub const fn bit_is_clear(&self) -> bool {
            !self.bit()
        }
        #[doc = " Returns `true` if the bit is set (1)."]
        #[inline(always)]
        pub const fn bit_is_set(&self) -> bool {
            self.bit()
        }
    }
    impl<FI> core::fmt::Debug for BitReader<FI> {
        fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
            core::fmt::Debug::fmt(&self.bits, f)
        }
    }
    #[doc = " Marker for register/field writers which can take any value of specified width"]
    pub struct Safe;
    #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
    pub struct Unsafe;
    #[doc = " Marker for field writers are safe to write in specified inclusive range"]
    pub struct Range<const MIN: u64, const MAX: u64>;
    #[doc = " Marker for field writers are safe to write in specified inclusive range"]
    pub struct RangeFrom<const MIN: u64>;
    #[doc = " Marker for field writers are safe to write in specified inclusive range"]
    pub struct RangeTo<const MAX: u64>;
    #[doc = " Write field Proxy"]
    pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
        raw::FieldWriter<'a, REG, WI, FI, Safety>;
    impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
    where
        REG: Writable + RegisterSpec,
        FI: FieldSpec,
    {
        #[doc = " Field width"]
        pub const WIDTH: u8 = WI;
        #[doc = " Field width"]
        #[inline(always)]
        pub const fn width(&self) -> u8 {
            WI
        }
        #[doc = " Field offset"]
        #[inline(always)]
        pub const fn offset(&self) -> u8 {
            self.o
        }
    }
    impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
    where
        REG: Writable + RegisterSpec,
        FI: FieldSpec,
        REG::Ux: From<FI::Ux>,
    {
        #[doc = " Writes raw bits to the field"]
        #[doc = ""]
        #[doc = " # Safety"]
        #[doc = ""]
        #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
        #[inline(always)]
        pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
            self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
            self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
            self.w
        }
    }
    impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
    where
        REG: Writable + RegisterSpec,
        FI: FieldSpec,
        REG::Ux: From<FI::Ux>,
    {
        #[doc = " Writes raw bits to the field"]
        #[inline(always)]
        pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
            unsafe { self.bits(value) }
        }
    }
    impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
        FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
    where
        REG: Writable + RegisterSpec,
        FI: FieldSpec,
        REG::Ux: From<FI::Ux>,
        u64: From<FI::Ux>,
    {
        #[doc = " Writes raw bits to the field"]
        #[inline(always)]
        pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
            {
                let value = u64::from(value);
                assert!(value >= MIN && value <= MAX);
            }
            unsafe { self.bits(value) }
        }
    }
    impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
    where
        REG: Writable + RegisterSpec,
        FI: FieldSpec,
        REG::Ux: From<FI::Ux>,
        u64: From<FI::Ux>,
    {
        #[doc = " Writes raw bits to the field"]
        #[inline(always)]
        pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
            {
                let value = u64::from(value);
                assert!(value >= MIN);
            }
            unsafe { self.bits(value) }
        }
    }
    impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
    where
        REG: Writable + RegisterSpec,
        FI: FieldSpec,
        REG::Ux: From<FI::Ux>,
        u64: From<FI::Ux>,
    {
        #[doc = " Writes raw bits to the field"]
        #[inline(always)]
        pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
            {
                let value = u64::from(value);
                assert!(value <= MAX);
            }
            unsafe { self.bits(value) }
        }
    }
    impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
    where
        REG: Writable + RegisterSpec,
        FI: IsEnum,
        REG::Ux: From<FI::Ux>,
    {
        #[doc = " Writes `variant` to the field"]
        #[inline(always)]
        pub fn variant(self, variant: FI) -> &'a mut W<REG> {
            unsafe { self.bits(FI::Ux::from(variant)) }
        }
    }
    macro_rules! bit_proxy {
        ($ writer : ident , $ mwv : ident) => {
            #[doc(hidden)]
            pub struct $mwv;
            #[doc = " Bit-wise write field proxy"]
            pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
            impl<'a, REG, FI> $writer<'a, REG, FI>
            where
                REG: Writable + RegisterSpec,
                bool: From<FI>,
            {
                #[doc = " Field width"]
                pub const WIDTH: u8 = 1;
                #[doc = " Field width"]
                #[inline(always)]
                pub const fn width(&self) -> u8 {
                    Self::WIDTH
                }
                #[doc = " Field offset"]
                #[inline(always)]
                pub const fn offset(&self) -> u8 {
                    self.o
                }
                #[doc = " Writes bit to the field"]
                #[inline(always)]
                pub fn bit(self, value: bool) -> &'a mut W<REG> {
                    self.w.bits &= !(REG::Ux::ONE << self.o);
                    self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
                    self.w
                }
                #[doc = " Writes `variant` to the field"]
                #[inline(always)]
                pub fn variant(self, variant: FI) -> &'a mut W<REG> {
                    self.bit(bool::from(variant))
                }
            }
        };
    }
    bit_proxy!(BitWriter, BitM);
    bit_proxy!(BitWriter1S, Bit1S);
    bit_proxy!(BitWriter0C, Bit0C);
    bit_proxy!(BitWriter1C, Bit1C);
    bit_proxy!(BitWriter0S, Bit0S);
    bit_proxy!(BitWriter1T, Bit1T);
    bit_proxy!(BitWriter0T, Bit0T);
    impl<'a, REG, FI> BitWriter<'a, REG, FI>
    where
        REG: Writable + RegisterSpec,
        bool: From<FI>,
    {
        #[doc = " Sets the field bit"]
        #[inline(always)]
        pub fn set_bit(self) -> &'a mut W<REG> {
            self.w.bits |= REG::Ux::ONE << self.o;
            self.w
        }
        #[doc = " Clears the field bit"]
        #[inline(always)]
        pub fn clear_bit(self) -> &'a mut W<REG> {
            self.w.bits &= !(REG::Ux::ONE << self.o);
            self.w
        }
    }
    impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
    where
        REG: Writable + RegisterSpec,
        bool: From<FI>,
    {
        #[doc = " Sets the field bit"]
        #[inline(always)]
        pub fn set_bit(self) -> &'a mut W<REG> {
            self.w.bits |= REG::Ux::ONE << self.o;
            self.w
        }
    }
    impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
    where
        REG: Writable + RegisterSpec,
        bool: From<FI>,
    {
        #[doc = " Clears the field bit"]
        #[inline(always)]
        pub fn clear_bit(self) -> &'a mut W<REG> {
            self.w.bits &= !(REG::Ux::ONE << self.o);
            self.w
        }
    }
    impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
    where
        REG: Writable + RegisterSpec,
        bool: From<FI>,
    {
        #[doc = "Clears the field bit by passing one"]
        #[inline(always)]
        pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
            self.w.bits |= REG::Ux::ONE << self.o;
            self.w
        }
    }
    impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
    where
        REG: Writable + RegisterSpec,
        bool: From<FI>,
    {
        #[doc = "Sets the field bit by passing zero"]
        #[inline(always)]
        pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
            self.w.bits &= !(REG::Ux::ONE << self.o);
            self.w
        }
    }
    impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
    where
        REG: Writable + RegisterSpec,
        bool: From<FI>,
    {
        #[doc = "Toggle the field bit by passing one"]
        #[inline(always)]
        pub fn toggle_bit(self) -> &'a mut W<REG> {
            self.w.bits |= REG::Ux::ONE << self.o;
            self.w
        }
    }
    impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
    where
        REG: Writable + RegisterSpec,
        bool: From<FI>,
    {
        #[doc = "Toggle the field bit by passing zero"]
        #[inline(always)]
        pub fn toggle_bit(self) -> &'a mut W<REG> {
            self.w.bits &= !(REG::Ux::ONE << self.o);
            self.w
        }
    }
    #[doc = " This structure provides volatile access to registers."]
    #[repr(transparent)]
    pub struct Reg<REG: RegisterSpec> {
        register: vcell::VolatileCell<REG::Ux>,
        _marker: marker::PhantomData<REG>,
    }
    unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
    impl<REG: RegisterSpec> Reg<REG> {
        #[doc = " Returns the underlying memory address of register."]
        #[doc = ""]
        #[doc = " ```ignore"]
        #[doc = " let reg_ptr = periph.reg.as_ptr();"]
        #[doc = " ```"]
        #[inline(always)]
        pub fn as_ptr(&self) -> *mut REG::Ux {
            self.register.as_ptr()
        }
    }
    impl<REG: Readable> Reg<REG> {
        #[doc = " Reads the contents of a `Readable` register."]
        #[doc = ""]
        #[doc = " You can read the raw contents of a register by using `bits`:"]
        #[doc = " ```ignore"]
        #[doc = " let bits = periph.reg.read().bits();"]
        #[doc = " ```"]
        #[doc = " or get the content of a particular field of a register:"]
        #[doc = " ```ignore"]
        #[doc = " let reader = periph.reg.read();"]
        #[doc = " let bits = reader.field1().bits();"]
        #[doc = " let flag = reader.field2().bit_is_set();"]
        #[doc = " ```"]
        #[inline(always)]
        pub fn read(&self) -> R<REG> {
            R {
                bits: self.register.get(),
                _reg: marker::PhantomData,
            }
        }
    }
    impl<REG: Resettable + Writable> Reg<REG> {
        #[doc = " Writes the reset value to `Writable` register."]
        #[doc = ""]
        #[doc = " Resets the register to its initial state."]
        #[inline(always)]
        pub fn reset(&self) {
            self.register.set(REG::RESET_VALUE)
        }
        #[doc = " Writes bits to a `Writable` register."]
        #[doc = ""]
        #[doc = " You can write raw bits into a register:"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
        #[doc = " ```"]
        #[doc = " or write only the fields you need:"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.write(|w| w"]
        #[doc = "     .field1().bits(newfield1bits)"]
        #[doc = "     .field2().set_bit()"]
        #[doc = "     .field3().variant(VARIANT)"]
        #[doc = " );"]
        #[doc = " ```"]
        #[doc = " or an alternative way of saying the same:"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.write(|w| {"]
        #[doc = "     w.field1().bits(newfield1bits);"]
        #[doc = "     w.field2().set_bit();"]
        #[doc = "     w.field3().variant(VARIANT)"]
        #[doc = " });"]
        #[doc = " ```"]
        #[doc = " In the latter case, other fields will be set to their reset value."]
        #[inline(always)]
        pub fn write<F>(&self, f: F) -> REG::Ux
        where
            F: FnOnce(&mut W<REG>) -> &mut W<REG>,
        {
            let value = f(&mut W {
                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
                _reg: marker::PhantomData,
            })
            .bits;
            self.register.set(value);
            value
        }
        #[doc = " Writes bits to a `Writable` register and produce a value."]
        #[doc = ""]
        #[doc = " You can write raw bits into a register:"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
        #[doc = " ```"]
        #[doc = " or write only the fields you need:"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.write_and(|w| {"]
        #[doc = "     w.field1().bits(newfield1bits)"]
        #[doc = "         .field2().set_bit()"]
        #[doc = "         .field3().variant(VARIANT);"]
        #[doc = " });"]
        #[doc = " ```"]
        #[doc = " or an alternative way of saying the same:"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.write_and(|w| {"]
        #[doc = "     w.field1().bits(newfield1bits);"]
        #[doc = "     w.field2().set_bit();"]
        #[doc = "     w.field3().variant(VARIANT);"]
        #[doc = " });"]
        #[doc = " ```"]
        #[doc = " In the latter case, other fields will be set to their reset value."]
        #[doc = ""]
        #[doc = " Values can be returned from the closure:"]
        #[doc = " ```ignore"]
        #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
        #[doc = " ```"]
        #[inline(always)]
        pub fn from_write<F, T>(&self, f: F) -> T
        where
            F: FnOnce(&mut W<REG>) -> T,
        {
            let mut writer = W {
                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
                _reg: marker::PhantomData,
            };
            let result = f(&mut writer);
            self.register.set(writer.bits);
            result
        }
    }
    impl<REG: Writable> Reg<REG> {
        #[doc = " Writes 0 to a `Writable` register."]
        #[doc = ""]
        #[doc = " Similar to `write`, but unused bits will contain 0."]
        #[doc = ""]
        #[doc = " # Safety"]
        #[doc = ""]
        #[doc = " Unsafe to use with registers which don't allow to write 0."]
        #[inline(always)]
        pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
        where
            F: FnOnce(&mut W<REG>) -> &mut W<REG>,
        {
            let value = f(&mut W {
                bits: REG::Ux::ZERO,
                _reg: marker::PhantomData,
            })
            .bits;
            self.register.set(value);
            value
        }
        #[doc = " Writes 0 to a `Writable` register and produces a value."]
        #[doc = ""]
        #[doc = " Similar to `write`, but unused bits will contain 0."]
        #[doc = ""]
        #[doc = " # Safety"]
        #[doc = ""]
        #[doc = " Unsafe to use with registers which don't allow to write 0."]
        #[inline(always)]
        pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
        where
            F: FnOnce(&mut W<REG>) -> T,
        {
            let mut writer = W {
                bits: REG::Ux::ZERO,
                _reg: marker::PhantomData,
            };
            let result = f(&mut writer);
            self.register.set(writer.bits);
            result
        }
    }
    impl<REG: Readable + Writable> Reg<REG> {
        #[doc = " Modifies the contents of the register by reading and then writing it."]
        #[doc = ""]
        #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
        #[doc = "    r.bits() | 3"]
        #[doc = " ) });"]
        #[doc = " ```"]
        #[doc = " or"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.modify(|_, w| w"]
        #[doc = "     .field1().bits(newfield1bits)"]
        #[doc = "     .field2().set_bit()"]
        #[doc = "     .field3().variant(VARIANT)"]
        #[doc = " );"]
        #[doc = " ```"]
        #[doc = " or an alternative way of saying the same:"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.modify(|_, w| {"]
        #[doc = "     w.field1().bits(newfield1bits);"]
        #[doc = "     w.field2().set_bit();"]
        #[doc = "     w.field3().variant(VARIANT)"]
        #[doc = " });"]
        #[doc = " ```"]
        #[doc = " Other fields will have the value they had before the call to `modify`."]
        #[inline(always)]
        pub fn modify<F>(&self, f: F) -> REG::Ux
        where
            for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
        {
            let bits = self.register.get();
            let value = f(
                &R {
                    bits,
                    _reg: marker::PhantomData,
                },
                &mut W {
                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
                    _reg: marker::PhantomData,
                },
            )
            .bits;
            self.register.set(value);
            value
        }
        #[doc = " Modifies the contents of the register by reading and then writing it"]
        #[doc = " and produces a value."]
        #[doc = ""]
        #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
        #[doc = " ```ignore"]
        #[doc = " let bits = periph.reg.modify(|r, w| {"]
        #[doc = "     let new_bits = r.bits() | 3;"]
        #[doc = "     unsafe {"]
        #[doc = "         w.bits(new_bits);"]
        #[doc = "     }"]
        #[doc = ""]
        #[doc = "     new_bits"]
        #[doc = " });"]
        #[doc = " ```"]
        #[doc = " or"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.modify(|_, w| {"]
        #[doc = "     w.field1().bits(newfield1bits)"]
        #[doc = "         .field2().set_bit()"]
        #[doc = "         .field3().variant(VARIANT);"]
        #[doc = " });"]
        #[doc = " ```"]
        #[doc = " or an alternative way of saying the same:"]
        #[doc = " ```ignore"]
        #[doc = " periph.reg.modify(|_, w| {"]
        #[doc = "     w.field1().bits(newfield1bits);"]
        #[doc = "     w.field2().set_bit();"]
        #[doc = "     w.field3().variant(VARIANT);"]
        #[doc = " });"]
        #[doc = " ```"]
        #[doc = " Other fields will have the value they had before the call to `modify`."]
        #[inline(always)]
        pub fn from_modify<F, T>(&self, f: F) -> T
        where
            for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
        {
            let bits = self.register.get();
            let mut writer = W {
                bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
                _reg: marker::PhantomData,
            };
            let result = f(
                &R {
                    bits,
                    _reg: marker::PhantomData,
                },
                &mut writer,
            );
            self.register.set(writer.bits);
            result
        }
    }
    impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
    where
        R<REG>: core::fmt::Debug,
    {
        fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
            core::fmt::Debug::fmt(&self.read(), f)
        }
    }
}
#[doc = r" Interrupt numbers, priority levels, and HART IDs."]
pub mod interrupt {
    #[cfg(target_arch = "riscv32")]
    pub use riscv::interrupt::Exception;
    #[cfg(target_arch = "riscv32")]
    pub use riscv::interrupt::Interrupt as CoreInterrupt;
    #[cfg(target_arch = "riscv32")]
    pub use riscv::{
        ExceptionNumber, HartIdNumber, InterruptNumber, PriorityNumber,
        interrupt::{disable, enable, free, nested},
    };
    #[cfg(target_arch = "riscv32")]
    pub type Trap = riscv::interrupt::Trap<CoreInterrupt, Exception>;
    #[doc = r" Retrieves the cause of a trap in the current hart."]
    #[doc = r""]
    #[doc = r" If the raw cause is not a valid interrupt or exception for the target, it returns an error."]
    #[inline]
    #[cfg(target_arch = "riscv32")]
    pub fn try_cause() -> riscv::result::Result<Trap> {
        riscv::interrupt::try_cause()
    }
    #[doc = r" Retrieves the cause of a trap in the current hart (machine mode)."]
    #[doc = r""]
    #[doc = r" If the raw cause is not a valid interrupt or exception for the target, it panics."]
    #[inline]
    #[cfg(target_arch = "riscv32")]
    pub fn cause() -> Trap {
        try_cause().unwrap()
    }
    #[doc = r" External interrupts. These interrupts are handled by the external peripherals."]
    #[cfg_attr(target_arch = "riscv32", riscv :: pac_enum (unsafe ExternalInterruptNumber))]
    #[derive(Debug, Clone, Copy, PartialEq, Eq)]
    pub enum ExternalInterrupt {
        #[doc = "26 - BT_INT0 (IRQ 26)"]
        BT_INT0 = 26,
        #[doc = "27 - BT_INT1 (IRQ 27)"]
        BT_INT1 = 27,
        #[doc = "28 - GADC_DONE (IRQ 28)"]
        GADC_DONE = 28,
        #[doc = "29 - GADC_ALARM (IRQ 29)"]
        GADC_ALARM = 29,
        #[doc = "32 - MCU_PCLR_LOCK (IRQ 32)"]
        MCU_PCLR_LOCK = 32,
        #[doc = "33 - ULP_GPIO (IRQ 33)"]
        ULP_GPIO = 33,
        #[doc = "34 - GPIO_0 (IRQ 34)"]
        GPIO_0 = 34,
        #[doc = "35 - GPIO_1 (IRQ 35)"]
        GPIO_1 = 35,
        #[doc = "36 - BT_TOGGLE_POS (IRQ 36)"]
        BT_TOGGLE_POS = 36,
        #[doc = "37 - BT_TOGGLE_NEG (IRQ 37)"]
        BT_TOGGLE_NEG = 37,
        #[doc = "38 - KEY_SCAN_LOW_POWER (IRQ 38)"]
        KEY_SCAN_LOW_POWER = 38,
        #[doc = "39 - UART_0 (IRQ 39)"]
        UART_0 = 39,
        #[doc = "40 - MCU_SIMO1P1_VSET (IRQ 40)"]
        MCU_SIMO1P1_VSET = 40,
        #[doc = "41 - UART_1 (IRQ 41)"]
        UART_1 = 41,
        #[doc = "42 - UART_2 (IRQ 42)"]
        UART_2 = 42,
        #[doc = "43 - QSPI0_2CS (IRQ 43)"]
        QSPI0_2CS = 43,
        #[doc = "44 - PDM (IRQ 44)"]
        PDM = 44,
        #[doc = "46 - KEY_SCAN (IRQ 46)"]
        KEY_SCAN = 46,
        #[doc = "47 - M_WAKEUP (IRQ 47)"]
        M_WAKEUP = 47,
        #[doc = "48 - M_SLEEP (IRQ 48)"]
        M_SLEEP = 48,
        #[doc = "49 - RTC_0 (IRQ 49)"]
        RTC_0 = 49,
        #[doc = "50 - RTC_1 (IRQ 50)"]
        RTC_1 = 50,
        #[doc = "51 - RTC_2 (IRQ 51)"]
        RTC_2 = 51,
        #[doc = "52 - RTC_3 (IRQ 52)"]
        RTC_3 = 52,
        #[doc = "53 - TIMER_0 (IRQ 53)"]
        TIMER_0 = 53,
        #[doc = "54 - TIMER_1 (IRQ 54)"]
        TIMER_1 = 54,
        #[doc = "55 - TIMER_2 (IRQ 55)"]
        TIMER_2 = 55,
        #[doc = "56 - TIMER_3 (IRQ 56)"]
        TIMER_3 = 56,
        #[doc = "57 - M_SDMA (IRQ 57)"]
        M_SDMA = 57,
        #[doc = "59 - SPI_M_S_0 (IRQ 59)"]
        SPI_M_S_0 = 59,
        #[doc = "60 - SPI_M_S_1 (IRQ 60)"]
        SPI_M_S_1 = 60,
        #[doc = "61 - SPI_M (IRQ 61)"]
        SPI_M = 61,
        #[doc = "63 - I2C_1 (IRQ 63)"]
        I2C_1 = 63,
        #[doc = "64 - BT_BB_BT (IRQ 64)"]
        BT_BB_BT = 64,
        #[doc = "65 - BT_BB_BLE (IRQ 65)"]
        BT_BB_BLE = 65,
        #[doc = "66 - BT_BB_GLE (IRQ 66)"]
        BT_BB_GLE = 66,
        #[doc = "67 - I2S (IRQ 67)"]
        I2S = 67,
        #[doc = "68 - RF_PRT (IRQ 68)"]
        RF_PRT = 68,
        #[doc = "69 - NFC (IRQ 69)"]
        NFC = 69,
        #[doc = "70 - SEC (IRQ 70)"]
        SEC = 70,
        #[doc = "71 - PWM_0 (IRQ 71)"]
        PWM_0 = 71,
        #[doc = "72 - PWM_1 (IRQ 72)"]
        PWM_1 = 72,
        #[doc = "73 - OSC_EN_WKUP (IRQ 73)"]
        OSC_EN_WKUP = 73,
        #[doc = "74 - OSC_EN_SLEEP (IRQ 74)"]
        OSC_EN_SLEEP = 74,
        #[doc = "78 - PMU_CMU_ERR (IRQ 78)"]
        PMU_CMU_ERR = 78,
        #[doc = "79 - ULP_INT (IRQ 79)"]
        ULP_INT = 79,
        #[doc = "85 - PMU2_CLK_32K_CALI (IRQ 85)"]
        PMU2_CLK_32K_CALI = 85,
        #[doc = "86 - ULP_WKUP_INT (IRQ 86)"]
        ULP_WKUP_INT = 86,
        #[doc = "87 - TSENSOR (IRQ 87)"]
        TSENSOR = 87,
        #[doc = "88 - QDEC (IRQ 88)"]
        QDEC = 88,
        #[doc = "89 - USB (IRQ 89)"]
        USB = 89,
    }
}
#[doc = "Main core global control - BCPU/MCPU reset status, chip reset, AON CRG"]
pub type GlbCtlM = crate::Periph<glb_ctl_m::RegisterBlock, 0x5700_0000>;
impl core::fmt::Debug for GlbCtlM {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GlbCtlM").finish()
    }
}
#[doc = "Main core global control - BCPU/MCPU reset status, chip reset, AON CRG"]
pub mod glb_ctl_m {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x30],
        bcpu_reset_sts: BcpuResetSts,
        mcpu_reset_sts: McpuResetSts,
        _reserved2: [u8; 0x04],
        reset_sts_clear: ResetStsClear,
        _reserved3: [u8; 0xc0],
        aon_crg_cken_ctl: AonCrgCkenCtl,
        _reserved4: [u8; 0x0c],
        _reserved_4_chip_reset: [u8; 0x04],
    }
    impl RegisterBlock {
        #[doc = "0x30 - BCPU reset status register"]
        #[inline(always)]
        pub const fn bcpu_reset_sts(&self) -> &BcpuResetSts {
            &self.bcpu_reset_sts
        }
        #[doc = "0x34 - MCPU reset status register"]
        #[inline(always)]
        pub const fn mcpu_reset_sts(&self) -> &McpuResetSts {
            &self.mcpu_reset_sts
        }
        #[doc = "0x3c - Reset status clear register"]
        #[inline(always)]
        pub const fn reset_sts_clear(&self) -> &ResetStsClear {
            &self.reset_sts_clear
        }
        #[doc = "0x100 - AON CRG clock enable control"]
        #[inline(always)]
        pub const fn aon_crg_cken_ctl(&self) -> &AonCrgCkenCtl {
            &self.aon_crg_cken_ctl
        }
        #[doc = "0x110 - AON soft reset control"]
        #[inline(always)]
        pub const fn aon_soft_rst_ctl(&self) -> &AonSoftRstCtl {
            unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(272).cast() }
        }
        #[doc = "0x110 - Chip reset control register"]
        #[inline(always)]
        pub const fn chip_reset(&self) -> &ChipReset {
            unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(272).cast() }
        }
    }
    #[doc = "BCPU_RESET_STS (rw) register accessor: BCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcpu_reset_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcpu_reset_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bcpu_reset_sts`] module"]
    #[doc(alias = "BCPU_RESET_STS")]
    pub type BcpuResetSts = crate::Reg<bcpu_reset_sts::BcpuResetStsSpec>;
    #[doc = "BCPU reset status register"]
    pub mod bcpu_reset_sts {
        #[doc = "Register `BCPU_RESET_STS` reader"]
        pub type R = crate::R<BcpuResetStsSpec>;
        #[doc = "Register `BCPU_RESET_STS` writer"]
        pub type W = crate::W<BcpuResetStsSpec>;
        #[doc = "Field `bcpu_reset_sts` reader - BCPU reset status"]
        pub type BcpuResetStsR = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - BCPU reset status"]
            #[inline(always)]
            pub fn bcpu_reset_sts(&self) -> BcpuResetStsR {
                BcpuResetStsR::new(self.bits)
            }
        }
        impl W {}
        #[doc = "BCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcpu_reset_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcpu_reset_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BcpuResetStsSpec;
        impl crate::RegisterSpec for BcpuResetStsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bcpu_reset_sts::R`](R) reader structure"]
        impl crate::Readable for BcpuResetStsSpec {}
        #[doc = "`write(|w| ..)` method takes [`bcpu_reset_sts::W`](W) writer structure"]
        impl crate::Writable for BcpuResetStsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets BCPU_RESET_STS to value 0"]
        impl crate::Resettable for BcpuResetStsSpec {}
    }
    #[doc = "MCPU_RESET_STS (rw) register accessor: MCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mcpu_reset_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcpu_reset_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcpu_reset_sts`] module"]
    #[doc(alias = "MCPU_RESET_STS")]
    pub type McpuResetSts = crate::Reg<mcpu_reset_sts::McpuResetStsSpec>;
    #[doc = "MCPU reset status register"]
    pub mod mcpu_reset_sts {
        #[doc = "Register `MCPU_RESET_STS` reader"]
        pub type R = crate::R<McpuResetStsSpec>;
        #[doc = "Register `MCPU_RESET_STS` writer"]
        pub type W = crate::W<McpuResetStsSpec>;
        #[doc = "Field `mcpu_reset_sts` reader - MCPU reset status"]
        pub type McpuResetStsR = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - MCPU reset status"]
            #[inline(always)]
            pub fn mcpu_reset_sts(&self) -> McpuResetStsR {
                McpuResetStsR::new(self.bits)
            }
        }
        impl W {}
        #[doc = "MCPU reset status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mcpu_reset_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcpu_reset_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct McpuResetStsSpec;
        impl crate::RegisterSpec for McpuResetStsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`mcpu_reset_sts::R`](R) reader structure"]
        impl crate::Readable for McpuResetStsSpec {}
        #[doc = "`write(|w| ..)` method takes [`mcpu_reset_sts::W`](W) writer structure"]
        impl crate::Writable for McpuResetStsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets MCPU_RESET_STS to value 0"]
        impl crate::Resettable for McpuResetStsSpec {}
    }
    #[doc = "RESET_STS_CLEAR (rw) register accessor: Reset status clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_sts_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_sts_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_sts_clear`] module"]
    #[doc(alias = "RESET_STS_CLEAR")]
    pub type ResetStsClear = crate::Reg<reset_sts_clear::ResetStsClearSpec>;
    #[doc = "Reset status clear register"]
    pub mod reset_sts_clear {
        #[doc = "Register `RESET_STS_CLEAR` reader"]
        pub type R = crate::R<ResetStsClearSpec>;
        #[doc = "Register `RESET_STS_CLEAR` writer"]
        pub type W = crate::W<ResetStsClearSpec>;
        #[doc = "Field `rst_sts_clear` writer - Write 0xFF to clear all reset status bits"]
        pub type RstStsClearW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - Write 0xFF to clear all reset status bits"]
            #[inline(always)]
            pub fn rst_sts_clear(&mut self) -> RstStsClearW<'_, ResetStsClearSpec> {
                RstStsClearW::new(self, 0)
            }
        }
        #[doc = "Reset status clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_sts_clear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_sts_clear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ResetStsClearSpec;
        impl crate::RegisterSpec for ResetStsClearSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`reset_sts_clear::R`](R) reader structure"]
        impl crate::Readable for ResetStsClearSpec {}
        #[doc = "`write(|w| ..)` method takes [`reset_sts_clear::W`](W) writer structure"]
        impl crate::Writable for ResetStsClearSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RESET_STS_CLEAR to value 0"]
        impl crate::Resettable for ResetStsClearSpec {}
    }
    #[doc = "AON_CRG_CKEN_CTL (rw) register accessor: AON CRG clock enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_crg_cken_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_crg_cken_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_crg_cken_ctl`] module"]
    #[doc(alias = "AON_CRG_CKEN_CTL")]
    pub type AonCrgCkenCtl = crate::Reg<aon_crg_cken_ctl::AonCrgCkenCtlSpec>;
    #[doc = "AON CRG clock enable control"]
    pub mod aon_crg_cken_ctl {
        #[doc = "Register `AON_CRG_CKEN_CTL` reader"]
        pub type R = crate::R<AonCrgCkenCtlSpec>;
        #[doc = "Register `AON_CRG_CKEN_CTL` writer"]
        pub type W = crate::W<AonCrgCkenCtlSpec>;
        #[doc = "Field `wdt_gate` reader - WDT clock gate control at bit\\[4\\]"]
        pub type WdtGateR = crate::BitReader;
        #[doc = "Field `wdt_gate` writer - WDT clock gate control at bit\\[4\\]"]
        pub type WdtGateW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 4 - WDT clock gate control at bit\\[4\\]"]
            #[inline(always)]
            pub fn wdt_gate(&self) -> WdtGateR {
                WdtGateR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 4 - WDT clock gate control at bit\\[4\\]"]
            #[inline(always)]
            pub fn wdt_gate(&mut self) -> WdtGateW<'_, AonCrgCkenCtlSpec> {
                WdtGateW::new(self, 4)
            }
        }
        #[doc = "AON CRG clock enable control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_crg_cken_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_crg_cken_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct AonCrgCkenCtlSpec;
        impl crate::RegisterSpec for AonCrgCkenCtlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`aon_crg_cken_ctl::R`](R) reader structure"]
        impl crate::Readable for AonCrgCkenCtlSpec {}
        #[doc = "`write(|w| ..)` method takes [`aon_crg_cken_ctl::W`](W) writer structure"]
        impl crate::Writable for AonCrgCkenCtlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets AON_CRG_CKEN_CTL to value 0"]
        impl crate::Resettable for AonCrgCkenCtlSpec {}
    }
    #[doc = "CHIP_RESET (rw) register accessor: Chip reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`chip_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chip_reset`] module"]
    #[doc(alias = "CHIP_RESET")]
    pub type ChipReset = crate::Reg<chip_reset::ChipResetSpec>;
    #[doc = "Chip reset control register"]
    pub mod chip_reset {
        #[doc = "Register `CHIP_RESET` reader"]
        pub type R = crate::R<ChipResetSpec>;
        #[doc = "Register `CHIP_RESET` writer"]
        pub type W = crate::W<ChipResetSpec>;
        #[doc = "Field `chip_reset_en` reader - Chip reset enable: 1=assert chip reset"]
        pub type ChipResetEnR = crate::BitReader;
        #[doc = "Field `chip_reset_en` writer - Chip reset enable: 1=assert chip reset"]
        pub type ChipResetEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 2 - Chip reset enable: 1=assert chip reset"]
            #[inline(always)]
            pub fn chip_reset_en(&self) -> ChipResetEnR {
                ChipResetEnR::new(((self.bits >> 2) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 2 - Chip reset enable: 1=assert chip reset"]
            #[inline(always)]
            pub fn chip_reset_en(&mut self) -> ChipResetEnW<'_, ChipResetSpec> {
                ChipResetEnW::new(self, 2)
            }
        }
        #[doc = "Chip reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`chip_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ChipResetSpec;
        impl crate::RegisterSpec for ChipResetSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`chip_reset::R`](R) reader structure"]
        impl crate::Readable for ChipResetSpec {}
        #[doc = "`write(|w| ..)` method takes [`chip_reset::W`](W) writer structure"]
        impl crate::Writable for ChipResetSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CHIP_RESET to value 0"]
        impl crate::Resettable for ChipResetSpec {}
    }
    #[doc = "AON_SOFT_RST_CTL (rw) register accessor: AON soft reset control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_soft_rst_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_soft_rst_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aon_soft_rst_ctl`] module"]
    #[doc(alias = "AON_SOFT_RST_CTL")]
    pub type AonSoftRstCtl = crate::Reg<aon_soft_rst_ctl::AonSoftRstCtlSpec>;
    #[doc = "AON soft reset control"]
    pub mod aon_soft_rst_ctl {
        #[doc = "Register `AON_SOFT_RST_CTL` reader"]
        pub type R = crate::R<AonSoftRstCtlSpec>;
        #[doc = "Register `AON_SOFT_RST_CTL` writer"]
        pub type W = crate::W<AonSoftRstCtlSpec>;
        #[doc = "Field `wdt_soft_rst` reader - WDT soft reset at bit\\[1\\]"]
        pub type WdtSoftRstR = crate::BitReader;
        #[doc = "Field `wdt_soft_rst` writer - WDT soft reset at bit\\[1\\]"]
        pub type WdtSoftRstW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 1 - WDT soft reset at bit\\[1\\]"]
            #[inline(always)]
            pub fn wdt_soft_rst(&self) -> WdtSoftRstR {
                WdtSoftRstR::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 1 - WDT soft reset at bit\\[1\\]"]
            #[inline(always)]
            pub fn wdt_soft_rst(&mut self) -> WdtSoftRstW<'_, AonSoftRstCtlSpec> {
                WdtSoftRstW::new(self, 1)
            }
        }
        #[doc = "AON soft reset control\n\nYou can [`read`](crate::Reg::read) this register and get [`aon_soft_rst_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aon_soft_rst_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct AonSoftRstCtlSpec;
        impl crate::RegisterSpec for AonSoftRstCtlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`aon_soft_rst_ctl::R`](R) reader structure"]
        impl crate::Readable for AonSoftRstCtlSpec {}
        #[doc = "`write(|w| ..)` method takes [`aon_soft_rst_ctl::W`](W) writer structure"]
        impl crate::Writable for AonSoftRstCtlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets AON_SOFT_RST_CTL to value 0"]
        impl crate::Resettable for AonSoftRstCtlSpec {}
    }
}
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub type Gpio0 = crate::Periph<gpio0::RegisterBlock, 0x5701_0000>;
impl core::fmt::Debug for Gpio0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Gpio0").finish()
    }
}
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub mod gpio0 {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        gpio_sw_out: GpioSwOut,
        gpio_sw_oen: GpioSwOen,
        _reserved2: [u8; 0x04],
        gpio_int_en: GpioIntEn,
        gpio_int_mask: GpioIntMask,
        gpio_int_type: GpioIntType,
        gpio_int_polarity: GpioIntPolarity,
        gpio_int_dedge: GpioIntDedge,
        gpio_int_debounce: GpioIntDebounce,
        gpio_int_raw: GpioIntRaw,
        gpio_intr: GpioIntr,
        gpio_int_eoi: GpioIntEoi,
        gpio_data_set: GpioDataSet,
        gpio_data_clr: GpioDataClr,
    }
    impl RegisterBlock {
        #[doc = "0x00 - GPIO data register"]
        #[inline(always)]
        pub const fn gpio_sw_out(&self) -> &GpioSwOut {
            &self.gpio_sw_out
        }
        #[doc = "0x04 - GPIO data direction register"]
        #[inline(always)]
        pub const fn gpio_sw_oen(&self) -> &GpioSwOen {
            &self.gpio_sw_oen
        }
        #[doc = "0x0c - GPIO interrupt enable register"]
        #[inline(always)]
        pub const fn gpio_int_en(&self) -> &GpioIntEn {
            &self.gpio_int_en
        }
        #[doc = "0x10 - GPIO interrupt mask register"]
        #[inline(always)]
        pub const fn gpio_int_mask(&self) -> &GpioIntMask {
            &self.gpio_int_mask
        }
        #[doc = "0x14 - GPIO interrupt type register"]
        #[inline(always)]
        pub const fn gpio_int_type(&self) -> &GpioIntType {
            &self.gpio_int_type
        }
        #[doc = "0x18 - GPIO interrupt polarity register"]
        #[inline(always)]
        pub const fn gpio_int_polarity(&self) -> &GpioIntPolarity {
            &self.gpio_int_polarity
        }
        #[doc = "0x1c - GPIO dual-edge interrupt enable register"]
        #[inline(always)]
        pub const fn gpio_int_dedge(&self) -> &GpioIntDedge {
            &self.gpio_int_dedge
        }
        #[doc = "0x20 - GPIO interrupt debounce control register"]
        #[inline(always)]
        pub const fn gpio_int_debounce(&self) -> &GpioIntDebounce {
            &self.gpio_int_debounce
        }
        #[doc = "0x24 - GPIO raw interrupt status register"]
        #[inline(always)]
        pub const fn gpio_int_raw(&self) -> &GpioIntRaw {
            &self.gpio_int_raw
        }
        #[doc = "0x28 - GPIO interrupt status register"]
        #[inline(always)]
        pub const fn gpio_intr(&self) -> &GpioIntr {
            &self.gpio_intr
        }
        #[doc = "0x2c - GPIO interrupt clear register"]
        #[inline(always)]
        pub const fn gpio_int_eoi(&self) -> &GpioIntEoi {
            &self.gpio_int_eoi
        }
        #[doc = "0x30 - GPIO data set register"]
        #[inline(always)]
        pub const fn gpio_data_set(&self) -> &GpioDataSet {
            &self.gpio_data_set
        }
        #[doc = "0x34 - GPIO data clear register"]
        #[inline(always)]
        pub const fn gpio_data_clr(&self) -> &GpioDataClr {
            &self.gpio_data_clr
        }
    }
    #[doc = "GPIO_SW_OUT (rw) register accessor: GPIO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_sw_out`] module"]
    #[doc(alias = "GPIO_SW_OUT")]
    pub type GpioSwOut = crate::Reg<gpio_sw_out::GpioSwOutSpec>;
    #[doc = "GPIO data register"]
    pub mod gpio_sw_out {
        #[doc = "Register `GPIO_SW_OUT` reader"]
        pub type R = crate::R<GpioSwOutSpec>;
        #[doc = "Register `GPIO_SW_OUT` writer"]
        pub type W = crate::W<GpioSwOutSpec>;
        #[doc = "Field `gpio_sw_out` reader - GPIO data. Output: written value drives I/O; Input: reads external port"]
        pub type GpioSwOutR = crate::FieldReader;
        #[doc = "Field `gpio_sw_out` writer - GPIO data. Output: written value drives I/O; Input: reads external port"]
        pub type GpioSwOutW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - GPIO data. Output: written value drives I/O; Input: reads external port"]
            #[inline(always)]
            pub fn gpio_sw_out(&self) -> GpioSwOutR {
                GpioSwOutR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - GPIO data. Output: written value drives I/O; Input: reads external port"]
            #[inline(always)]
            pub fn gpio_sw_out(&mut self) -> GpioSwOutW<'_, GpioSwOutSpec> {
                GpioSwOutW::new(self, 0)
            }
        }
        #[doc = "GPIO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioSwOutSpec;
        impl crate::RegisterSpec for GpioSwOutSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_sw_out::R`](R) reader structure"]
        impl crate::Readable for GpioSwOutSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_sw_out::W`](W) writer structure"]
        impl crate::Writable for GpioSwOutSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_SW_OUT to value 0"]
        impl crate::Resettable for GpioSwOutSpec {}
    }
    #[doc = "GPIO_SW_OEN (rw) register accessor: GPIO data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_oen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_oen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_sw_oen`] module"]
    #[doc(alias = "GPIO_SW_OEN")]
    pub type GpioSwOen = crate::Reg<gpio_sw_oen::GpioSwOenSpec>;
    #[doc = "GPIO data direction register"]
    pub mod gpio_sw_oen {
        #[doc = "Register `GPIO_SW_OEN` reader"]
        pub type R = crate::R<GpioSwOenSpec>;
        #[doc = "Register `GPIO_SW_OEN` writer"]
        pub type W = crate::W<GpioSwOenSpec>;
        #[doc = "GPIO direction: 0=output; 1=input (default)\n\nValue on reset: 255"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum GpioSwOen {
            #[doc = "0: Output direction"]
            Output = 0,
            #[doc = "1: Input direction"]
            Input = 1,
        }
        impl From<GpioSwOen> for u8 {
            #[inline(always)]
            fn from(variant: GpioSwOen) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for GpioSwOen {
            type Ux = u8;
        }
        impl crate::IsEnum for GpioSwOen {}
        #[doc = "Field `gpio_sw_oen` reader - GPIO direction: 0=output; 1=input (default)"]
        pub type GpioSwOenR = crate::FieldReader<GpioSwOen>;
        impl GpioSwOenR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Option<GpioSwOen> {
                match self.bits {
                    0 => Some(GpioSwOen::Output),
                    1 => Some(GpioSwOen::Input),
                    _ => None,
                }
            }
            #[doc = "Output direction"]
            #[inline(always)]
            pub fn is_output(&self) -> bool {
                *self == GpioSwOen::Output
            }
            #[doc = "Input direction"]
            #[inline(always)]
            pub fn is_input(&self) -> bool {
                *self == GpioSwOen::Input
            }
        }
        #[doc = "Field `gpio_sw_oen` writer - GPIO direction: 0=output; 1=input (default)"]
        pub type GpioSwOenW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioSwOen>;
        impl<'a, REG> GpioSwOenW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "Output direction"]
            #[inline(always)]
            pub fn output(self) -> &'a mut crate::W<REG> {
                self.variant(GpioSwOen::Output)
            }
            #[doc = "Input direction"]
            #[inline(always)]
            pub fn input(self) -> &'a mut crate::W<REG> {
                self.variant(GpioSwOen::Input)
            }
        }
        impl R {
            #[doc = "Bits 0:7 - GPIO direction: 0=output; 1=input (default)"]
            #[inline(always)]
            pub fn gpio_sw_oen(&self) -> GpioSwOenR {
                GpioSwOenR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - GPIO direction: 0=output; 1=input (default)"]
            #[inline(always)]
            pub fn gpio_sw_oen(&mut self) -> GpioSwOenW<'_, GpioSwOenSpec> {
                GpioSwOenW::new(self, 0)
            }
        }
        #[doc = "GPIO data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_sw_oen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_sw_oen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioSwOenSpec;
        impl crate::RegisterSpec for GpioSwOenSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_sw_oen::R`](R) reader structure"]
        impl crate::Readable for GpioSwOenSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_sw_oen::W`](W) writer structure"]
        impl crate::Writable for GpioSwOenSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_SW_OEN to value 0xff"]
        impl crate::Resettable for GpioSwOenSpec {
            const RESET_VALUE: u32 = 0xff;
        }
    }
    #[doc = "GPIO_INT_EN (rw) register accessor: GPIO interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_en`] module"]
    #[doc(alias = "GPIO_INT_EN")]
    pub type GpioIntEn = crate::Reg<gpio_int_en::GpioIntEnSpec>;
    #[doc = "GPIO interrupt enable register"]
    pub mod gpio_int_en {
        #[doc = "Register `GPIO_INT_EN` reader"]
        pub type R = crate::R<GpioIntEnSpec>;
        #[doc = "Register `GPIO_INT_EN` writer"]
        pub type W = crate::W<GpioIntEnSpec>;
        #[doc = "Field `gpio_int_en` reader - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
        pub type GpioIntEnR = crate::FieldReader;
        #[doc = "Field `gpio_int_en` writer - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
        pub type GpioIntEnW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
            #[inline(always)]
            pub fn gpio_int_en(&self) -> GpioIntEnR {
                GpioIntEnR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Interrupt enable: 0=normal GPIO; 1=interrupt port"]
            #[inline(always)]
            pub fn gpio_int_en(&mut self) -> GpioIntEnW<'_, GpioIntEnSpec> {
                GpioIntEnW::new(self, 0)
            }
        }
        #[doc = "GPIO interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioIntEnSpec;
        impl crate::RegisterSpec for GpioIntEnSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_int_en::R`](R) reader structure"]
        impl crate::Readable for GpioIntEnSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_int_en::W`](W) writer structure"]
        impl crate::Writable for GpioIntEnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_INT_EN to value 0"]
        impl crate::Resettable for GpioIntEnSpec {}
    }
    #[doc = "GPIO_INT_MASK (rw) register accessor: GPIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_mask`] module"]
    #[doc(alias = "GPIO_INT_MASK")]
    pub type GpioIntMask = crate::Reg<gpio_int_mask::GpioIntMaskSpec>;
    #[doc = "GPIO interrupt mask register"]
    pub mod gpio_int_mask {
        #[doc = "Register `GPIO_INT_MASK` reader"]
        pub type R = crate::R<GpioIntMaskSpec>;
        #[doc = "Register `GPIO_INT_MASK` writer"]
        pub type W = crate::W<GpioIntMaskSpec>;
        #[doc = "Field `gpio_int_mask` reader - Interrupt mask: 0=not masked; 1=masked"]
        pub type GpioIntMaskR = crate::FieldReader;
        #[doc = "Field `gpio_int_mask` writer - Interrupt mask: 0=not masked; 1=masked"]
        pub type GpioIntMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Interrupt mask: 0=not masked; 1=masked"]
            #[inline(always)]
            pub fn gpio_int_mask(&self) -> GpioIntMaskR {
                GpioIntMaskR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Interrupt mask: 0=not masked; 1=masked"]
            #[inline(always)]
            pub fn gpio_int_mask(&mut self) -> GpioIntMaskW<'_, GpioIntMaskSpec> {
                GpioIntMaskW::new(self, 0)
            }
        }
        #[doc = "GPIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioIntMaskSpec;
        impl crate::RegisterSpec for GpioIntMaskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_int_mask::R`](R) reader structure"]
        impl crate::Readable for GpioIntMaskSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_int_mask::W`](W) writer structure"]
        impl crate::Writable for GpioIntMaskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_INT_MASK to value 0"]
        impl crate::Resettable for GpioIntMaskSpec {}
    }
    #[doc = "GPIO_INT_TYPE (rw) register accessor: GPIO interrupt type register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_type`] module"]
    #[doc(alias = "GPIO_INT_TYPE")]
    pub type GpioIntType = crate::Reg<gpio_int_type::GpioIntTypeSpec>;
    #[doc = "GPIO interrupt type register"]
    pub mod gpio_int_type {
        #[doc = "Register `GPIO_INT_TYPE` reader"]
        pub type R = crate::R<GpioIntTypeSpec>;
        #[doc = "Register `GPIO_INT_TYPE` writer"]
        pub type W = crate::W<GpioIntTypeSpec>;
        #[doc = "Interrupt type: 0=level; 1=edge\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum GpioIntType {
            #[doc = "0: Level-sensitive"]
            Level = 0,
            #[doc = "1: Edge-triggered"]
            Edge = 1,
        }
        impl From<GpioIntType> for u8 {
            #[inline(always)]
            fn from(variant: GpioIntType) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for GpioIntType {
            type Ux = u8;
        }
        impl crate::IsEnum for GpioIntType {}
        #[doc = "Field `gpio_int_type` reader - Interrupt type: 0=level; 1=edge"]
        pub type GpioIntTypeR = crate::FieldReader<GpioIntType>;
        impl GpioIntTypeR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Option<GpioIntType> {
                match self.bits {
                    0 => Some(GpioIntType::Level),
                    1 => Some(GpioIntType::Edge),
                    _ => None,
                }
            }
            #[doc = "Level-sensitive"]
            #[inline(always)]
            pub fn is_level(&self) -> bool {
                *self == GpioIntType::Level
            }
            #[doc = "Edge-triggered"]
            #[inline(always)]
            pub fn is_edge(&self) -> bool {
                *self == GpioIntType::Edge
            }
        }
        #[doc = "Field `gpio_int_type` writer - Interrupt type: 0=level; 1=edge"]
        pub type GpioIntTypeW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioIntType>;
        impl<'a, REG> GpioIntTypeW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "Level-sensitive"]
            #[inline(always)]
            pub fn level(self) -> &'a mut crate::W<REG> {
                self.variant(GpioIntType::Level)
            }
            #[doc = "Edge-triggered"]
            #[inline(always)]
            pub fn edge(self) -> &'a mut crate::W<REG> {
                self.variant(GpioIntType::Edge)
            }
        }
        impl R {
            #[doc = "Bits 0:7 - Interrupt type: 0=level; 1=edge"]
            #[inline(always)]
            pub fn gpio_int_type(&self) -> GpioIntTypeR {
                GpioIntTypeR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Interrupt type: 0=level; 1=edge"]
            #[inline(always)]
            pub fn gpio_int_type(&mut self) -> GpioIntTypeW<'_, GpioIntTypeSpec> {
                GpioIntTypeW::new(self, 0)
            }
        }
        #[doc = "GPIO interrupt type register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioIntTypeSpec;
        impl crate::RegisterSpec for GpioIntTypeSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_int_type::R`](R) reader structure"]
        impl crate::Readable for GpioIntTypeSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_int_type::W`](W) writer structure"]
        impl crate::Writable for GpioIntTypeSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_INT_TYPE to value 0"]
        impl crate::Resettable for GpioIntTypeSpec {}
    }
    #[doc = "GPIO_INT_POLARITY (rw) register accessor: GPIO interrupt polarity register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_polarity::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_polarity::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_polarity`] module"]
    #[doc(alias = "GPIO_INT_POLARITY")]
    pub type GpioIntPolarity = crate::Reg<gpio_int_polarity::GpioIntPolaritySpec>;
    #[doc = "GPIO interrupt polarity register"]
    pub mod gpio_int_polarity {
        #[doc = "Register `GPIO_INT_POLARITY` reader"]
        pub type R = crate::R<GpioIntPolaritySpec>;
        #[doc = "Register `GPIO_INT_POLARITY` writer"]
        pub type W = crate::W<GpioIntPolaritySpec>;
        #[doc = "Interrupt polarity: 0=low/falling; 1=high/rising\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum GpioIntPolarity {
            #[doc = "0: Low level or falling edge"]
            LowFalling = 0,
            #[doc = "1: High level or rising edge"]
            HighRising = 1,
        }
        impl From<GpioIntPolarity> for u8 {
            #[inline(always)]
            fn from(variant: GpioIntPolarity) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for GpioIntPolarity {
            type Ux = u8;
        }
        impl crate::IsEnum for GpioIntPolarity {}
        #[doc = "Field `gpio_int_polarity` reader - Interrupt polarity: 0=low/falling; 1=high/rising"]
        pub type GpioIntPolarityR = crate::FieldReader<GpioIntPolarity>;
        impl GpioIntPolarityR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Option<GpioIntPolarity> {
                match self.bits {
                    0 => Some(GpioIntPolarity::LowFalling),
                    1 => Some(GpioIntPolarity::HighRising),
                    _ => None,
                }
            }
            #[doc = "Low level or falling edge"]
            #[inline(always)]
            pub fn is_low_falling(&self) -> bool {
                *self == GpioIntPolarity::LowFalling
            }
            #[doc = "High level or rising edge"]
            #[inline(always)]
            pub fn is_high_rising(&self) -> bool {
                *self == GpioIntPolarity::HighRising
            }
        }
        #[doc = "Field `gpio_int_polarity` writer - Interrupt polarity: 0=low/falling; 1=high/rising"]
        pub type GpioIntPolarityW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioIntPolarity>;
        impl<'a, REG> GpioIntPolarityW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "Low level or falling edge"]
            #[inline(always)]
            pub fn low_falling(self) -> &'a mut crate::W<REG> {
                self.variant(GpioIntPolarity::LowFalling)
            }
            #[doc = "High level or rising edge"]
            #[inline(always)]
            pub fn high_rising(self) -> &'a mut crate::W<REG> {
                self.variant(GpioIntPolarity::HighRising)
            }
        }
        impl R {
            #[doc = "Bits 0:7 - Interrupt polarity: 0=low/falling; 1=high/rising"]
            #[inline(always)]
            pub fn gpio_int_polarity(&self) -> GpioIntPolarityR {
                GpioIntPolarityR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Interrupt polarity: 0=low/falling; 1=high/rising"]
            #[inline(always)]
            pub fn gpio_int_polarity(&mut self) -> GpioIntPolarityW<'_, GpioIntPolaritySpec> {
                GpioIntPolarityW::new(self, 0)
            }
        }
        #[doc = "GPIO interrupt polarity register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_polarity::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_polarity::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioIntPolaritySpec;
        impl crate::RegisterSpec for GpioIntPolaritySpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_int_polarity::R`](R) reader structure"]
        impl crate::Readable for GpioIntPolaritySpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_int_polarity::W`](W) writer structure"]
        impl crate::Writable for GpioIntPolaritySpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_INT_POLARITY to value 0"]
        impl crate::Resettable for GpioIntPolaritySpec {}
    }
    #[doc = "GPIO_INT_DEDGE (rw) register accessor: GPIO dual-edge interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_dedge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_dedge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_dedge`] module"]
    #[doc(alias = "GPIO_INT_DEDGE")]
    pub type GpioIntDedge = crate::Reg<gpio_int_dedge::GpioIntDedgeSpec>;
    #[doc = "GPIO dual-edge interrupt enable register"]
    pub mod gpio_int_dedge {
        #[doc = "Register `GPIO_INT_DEDGE` reader"]
        pub type R = crate::R<GpioIntDedgeSpec>;
        #[doc = "Register `GPIO_INT_DEDGE` writer"]
        pub type W = crate::W<GpioIntDedgeSpec>;
        #[doc = "Dual-edge interrupt enable: 0=disabled; 1=enabled\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum GpioIntDedge {
            #[doc = "0: Single-edge mode"]
            Disabled = 0,
            #[doc = "1: Dual-edge triggered"]
            Enabled = 1,
        }
        impl From<GpioIntDedge> for u8 {
            #[inline(always)]
            fn from(variant: GpioIntDedge) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for GpioIntDedge {
            type Ux = u8;
        }
        impl crate::IsEnum for GpioIntDedge {}
        #[doc = "Field `gpio_int_dedge` reader - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
        pub type GpioIntDedgeR = crate::FieldReader<GpioIntDedge>;
        impl GpioIntDedgeR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Option<GpioIntDedge> {
                match self.bits {
                    0 => Some(GpioIntDedge::Disabled),
                    1 => Some(GpioIntDedge::Enabled),
                    _ => None,
                }
            }
            #[doc = "Single-edge mode"]
            #[inline(always)]
            pub fn is_disabled(&self) -> bool {
                *self == GpioIntDedge::Disabled
            }
            #[doc = "Dual-edge triggered"]
            #[inline(always)]
            pub fn is_enabled(&self) -> bool {
                *self == GpioIntDedge::Enabled
            }
        }
        #[doc = "Field `gpio_int_dedge` writer - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
        pub type GpioIntDedgeW<'a, REG> = crate::FieldWriter<'a, REG, 8, GpioIntDedge>;
        impl<'a, REG> GpioIntDedgeW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "Single-edge mode"]
            #[inline(always)]
            pub fn disabled(self) -> &'a mut crate::W<REG> {
                self.variant(GpioIntDedge::Disabled)
            }
            #[doc = "Dual-edge triggered"]
            #[inline(always)]
            pub fn enabled(self) -> &'a mut crate::W<REG> {
                self.variant(GpioIntDedge::Enabled)
            }
        }
        impl R {
            #[doc = "Bits 0:7 - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn gpio_int_dedge(&self) -> GpioIntDedgeR {
                GpioIntDedgeR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Dual-edge interrupt enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn gpio_int_dedge(&mut self) -> GpioIntDedgeW<'_, GpioIntDedgeSpec> {
                GpioIntDedgeW::new(self, 0)
            }
        }
        #[doc = "GPIO dual-edge interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_dedge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_dedge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioIntDedgeSpec;
        impl crate::RegisterSpec for GpioIntDedgeSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_int_dedge::R`](R) reader structure"]
        impl crate::Readable for GpioIntDedgeSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_int_dedge::W`](W) writer structure"]
        impl crate::Writable for GpioIntDedgeSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_INT_DEDGE to value 0"]
        impl crate::Resettable for GpioIntDedgeSpec {}
    }
    #[doc = "GPIO_INT_DEBOUNCE (rw) register accessor: GPIO interrupt debounce control register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_debounce::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_debounce::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_debounce`] module"]
    #[doc(alias = "GPIO_INT_DEBOUNCE")]
    pub type GpioIntDebounce = crate::Reg<gpio_int_debounce::GpioIntDebounceSpec>;
    #[doc = "GPIO interrupt debounce control register"]
    pub mod gpio_int_debounce {
        #[doc = "Register `GPIO_INT_DEBOUNCE` reader"]
        pub type R = crate::R<GpioIntDebounceSpec>;
        #[doc = "Register `GPIO_INT_DEBOUNCE` writer"]
        pub type W = crate::W<GpioIntDebounceSpec>;
        #[doc = "Field `gpio_int_debounce` reader - Debounce enable: 0=disabled; 1=enabled"]
        pub type GpioIntDebounceR = crate::FieldReader;
        #[doc = "Field `gpio_int_debounce` writer - Debounce enable: 0=disabled; 1=enabled"]
        pub type GpioIntDebounceW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Debounce enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn gpio_int_debounce(&self) -> GpioIntDebounceR {
                GpioIntDebounceR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Debounce enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn gpio_int_debounce(&mut self) -> GpioIntDebounceW<'_, GpioIntDebounceSpec> {
                GpioIntDebounceW::new(self, 0)
            }
        }
        #[doc = "GPIO interrupt debounce control register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_debounce::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_debounce::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioIntDebounceSpec;
        impl crate::RegisterSpec for GpioIntDebounceSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_int_debounce::R`](R) reader structure"]
        impl crate::Readable for GpioIntDebounceSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_int_debounce::W`](W) writer structure"]
        impl crate::Writable for GpioIntDebounceSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_INT_DEBOUNCE to value 0"]
        impl crate::Resettable for GpioIntDebounceSpec {}
    }
    #[doc = "GPIO_INT_RAW (rw) register accessor: GPIO raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_raw`] module"]
    #[doc(alias = "GPIO_INT_RAW")]
    pub type GpioIntRaw = crate::Reg<gpio_int_raw::GpioIntRawSpec>;
    #[doc = "GPIO raw interrupt status register"]
    pub mod gpio_int_raw {
        #[doc = "Register `GPIO_INT_RAW` reader"]
        pub type R = crate::R<GpioIntRawSpec>;
        #[doc = "Register `GPIO_INT_RAW` writer"]
        pub type W = crate::W<GpioIntRawSpec>;
        #[doc = "Field `gpio_int_raw` reader - Raw interrupt status (before mask): 0=no interrupt; 1=interrupt"]
        pub type GpioIntRawR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - Raw interrupt status (before mask): 0=no interrupt; 1=interrupt"]
            #[inline(always)]
            pub fn gpio_int_raw(&self) -> GpioIntRawR {
                GpioIntRawR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {}
        #[doc = "GPIO raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioIntRawSpec;
        impl crate::RegisterSpec for GpioIntRawSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_int_raw::R`](R) reader structure"]
        impl crate::Readable for GpioIntRawSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_int_raw::W`](W) writer structure"]
        impl crate::Writable for GpioIntRawSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_INT_RAW to value 0"]
        impl crate::Resettable for GpioIntRawSpec {}
    }
    #[doc = "GPIO_INTR (rw) register accessor: GPIO interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_intr`] module"]
    #[doc(alias = "GPIO_INTR")]
    pub type GpioIntr = crate::Reg<gpio_intr::GpioIntrSpec>;
    #[doc = "GPIO interrupt status register"]
    pub mod gpio_intr {
        #[doc = "Register `GPIO_INTR` reader"]
        pub type R = crate::R<GpioIntrSpec>;
        #[doc = "Register `GPIO_INTR` writer"]
        pub type W = crate::W<GpioIntrSpec>;
        #[doc = "Field `gpio_intr` reader - Interrupt status (after mask): 0=no interrupt; 1=interrupt"]
        pub type GpioIntrR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - Interrupt status (after mask): 0=no interrupt; 1=interrupt"]
            #[inline(always)]
            pub fn gpio_intr(&self) -> GpioIntrR {
                GpioIntrR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {}
        #[doc = "GPIO interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioIntrSpec;
        impl crate::RegisterSpec for GpioIntrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_intr::R`](R) reader structure"]
        impl crate::Readable for GpioIntrSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_intr::W`](W) writer structure"]
        impl crate::Writable for GpioIntrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_INTR to value 0"]
        impl crate::Resettable for GpioIntrSpec {}
    }
    #[doc = "GPIO_INT_EOI (rw) register accessor: GPIO interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int_eoi`] module"]
    #[doc(alias = "GPIO_INT_EOI")]
    pub type GpioIntEoi = crate::Reg<gpio_int_eoi::GpioIntEoiSpec>;
    #[doc = "GPIO interrupt clear register"]
    pub mod gpio_int_eoi {
        #[doc = "Register `GPIO_INT_EOI` reader"]
        pub type R = crate::R<GpioIntEoiSpec>;
        #[doc = "Register `GPIO_INT_EOI` writer"]
        pub type W = crate::W<GpioIntEoiSpec>;
        #[doc = "Field `gpio_int_eoi` writer - Edge interrupt clear: 0=no clear; 1=clear interrupt"]
        pub type GpioIntEoiW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl W {
            #[doc = "Bits 0:7 - Edge interrupt clear: 0=no clear; 1=clear interrupt"]
            #[inline(always)]
            pub fn gpio_int_eoi(&mut self) -> GpioIntEoiW<'_, GpioIntEoiSpec> {
                GpioIntEoiW::new(self, 0)
            }
        }
        #[doc = "GPIO interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_int_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_int_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioIntEoiSpec;
        impl crate::RegisterSpec for GpioIntEoiSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_int_eoi::R`](R) reader structure"]
        impl crate::Readable for GpioIntEoiSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_int_eoi::W`](W) writer structure"]
        impl crate::Writable for GpioIntEoiSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_INT_EOI to value 0"]
        impl crate::Resettable for GpioIntEoiSpec {}
    }
    #[doc = "GPIO_DATA_SET (rw) register accessor: GPIO data set register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_data_set`] module"]
    #[doc(alias = "GPIO_DATA_SET")]
    pub type GpioDataSet = crate::Reg<gpio_data_set::GpioDataSetSpec>;
    #[doc = "GPIO data set register"]
    pub mod gpio_data_set {
        #[doc = "Register `GPIO_DATA_SET` reader"]
        pub type R = crate::R<GpioDataSetSpec>;
        #[doc = "Register `GPIO_DATA_SET` writer"]
        pub type W = crate::W<GpioDataSetSpec>;
        #[doc = "Field `gpio_data_set` writer - Write 1 to set corresponding GPIO_SW_OUT bits"]
        pub type GpioDataSetW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl W {
            #[doc = "Bits 0:7 - Write 1 to set corresponding GPIO_SW_OUT bits"]
            #[inline(always)]
            pub fn gpio_data_set(&mut self) -> GpioDataSetW<'_, GpioDataSetSpec> {
                GpioDataSetW::new(self, 0)
            }
        }
        #[doc = "GPIO data set register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioDataSetSpec;
        impl crate::RegisterSpec for GpioDataSetSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_data_set::R`](R) reader structure"]
        impl crate::Readable for GpioDataSetSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_data_set::W`](W) writer structure"]
        impl crate::Writable for GpioDataSetSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_DATA_SET to value 0"]
        impl crate::Resettable for GpioDataSetSpec {}
    }
    #[doc = "GPIO_DATA_CLR (rw) register accessor: GPIO data clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_data_clr`] module"]
    #[doc(alias = "GPIO_DATA_CLR")]
    pub type GpioDataClr = crate::Reg<gpio_data_clr::GpioDataClrSpec>;
    #[doc = "GPIO data clear register"]
    pub mod gpio_data_clr {
        #[doc = "Register `GPIO_DATA_CLR` reader"]
        pub type R = crate::R<GpioDataClrSpec>;
        #[doc = "Register `GPIO_DATA_CLR` writer"]
        pub type W = crate::W<GpioDataClrSpec>;
        #[doc = "Field `gpio_data_clr` writer - Write 1 to clear corresponding GPIO_SW_OUT bits"]
        pub type GpioDataClrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl W {
            #[doc = "Bits 0:7 - Write 1 to clear corresponding GPIO_SW_OUT bits"]
            #[inline(always)]
            pub fn gpio_data_clr(&mut self) -> GpioDataClrW<'_, GpioDataClrSpec> {
                GpioDataClrW::new(self, 0)
            }
        }
        #[doc = "GPIO data clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio_data_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_data_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpioDataClrSpec;
        impl crate::RegisterSpec for GpioDataClrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpio_data_clr::R`](R) reader structure"]
        impl crate::Readable for GpioDataClrSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpio_data_clr::W`](W) writer structure"]
        impl crate::Writable for GpioDataClrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPIO_DATA_CLR to value 0"]
        impl crate::Resettable for GpioDataClrSpec {}
    }
}
#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
pub type Uart0 = crate::Periph<uart0::RegisterBlock, 0x5208_1000>;
impl core::fmt::Debug for Uart0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Uart0").finish()
    }
}
#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
pub mod uart0 {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        intr_id: IntrId,
        _reserved1: [u8; 0x02],
        data: Data,
        _reserved2: [u8; 0x02],
        uart_ctl: UartCtl,
        _reserved3: [u8; 0x02],
        div_h: DivH,
        _reserved4: [u8; 0x02],
        div_l: DivL,
        _reserved5: [u8; 0x02],
        div_fra: DivFra,
        _reserved6: [u8; 0x02],
        intr_en: IntrEn,
        _reserved7: [u8; 0x02],
        intr_status: IntrStatus,
        _reserved8: [u8; 0x06],
        fifo_ctl: FifoCtl,
        _reserved9: [u8; 0x02],
        far: Far,
        _reserved10: [u8; 0x02],
        modem_ctl: ModemCtl,
        _reserved11: [u8; 0x02],
        modem_status: ModemStatus,
        _reserved12: [u8; 0x02],
        line_status: LineStatus,
        _reserved13: [u8; 0x02],
        uart_gp_reg: UartGpReg,
        _reserved14: [u8; 0x02],
        tx_fifo_read: TxFifoRead,
        _reserved15: [u8; 0x02],
        rx_fifo_write: RxFifoWrite,
        _reserved16: [u8; 0x02],
        fifo_status: FifoStatus,
        _reserved17: [u8; 0x02],
        tx_fifo_cnt: TxFifoCnt,
        _reserved18: [u8; 0x02],
        rx_fifo_cnt: RxFifoCnt,
        _reserved19: [u8; 0x02],
        halt_tx: HaltTx,
        _reserved20: [u8; 0x02],
        dma_sw_ack: DmaSwAck,
        _reserved21: [u8; 0x02],
        baud_ctl: BaudCtl,
        _reserved22: [u8; 0x02],
        stp_ctl: StpCtl,
        _reserved23: [u8; 0x02],
        uart_parameter: UartParameter,
    }
    impl RegisterBlock {
        #[doc = "0x00 - Interrupt ID register"]
        #[inline(always)]
        pub const fn intr_id(&self) -> &IntrId {
            &self.intr_id
        }
        #[doc = "0x04 - Data register"]
        #[inline(always)]
        pub const fn data(&self) -> &Data {
            &self.data
        }
        #[doc = "0x08 - UART control register"]
        #[inline(always)]
        pub const fn uart_ctl(&self) -> &UartCtl {
            &self.uart_ctl
        }
        #[doc = "0x0c - Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
        #[inline(always)]
        pub const fn div_h(&self) -> &DivH {
            &self.div_h
        }
        #[doc = "0x10 - Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
        #[inline(always)]
        pub const fn div_l(&self) -> &DivL {
            &self.div_l
        }
        #[doc = "0x14 - Baud rate divider fractional part"]
        #[inline(always)]
        pub const fn div_fra(&self) -> &DivFra {
            &self.div_fra
        }
        #[doc = "0x18 - Interrupt enable register"]
        #[inline(always)]
        pub const fn intr_en(&self) -> &IntrEn {
            &self.intr_en
        }
        #[doc = "0x1c - Interrupt status register"]
        #[inline(always)]
        pub const fn intr_status(&self) -> &IntrStatus {
            &self.intr_status
        }
        #[doc = "0x24 - FIFO control register"]
        #[inline(always)]
        pub const fn fifo_ctl(&self) -> &FifoCtl {
            &self.fifo_ctl
        }
        #[doc = "0x28 - FIFO access mode enable register"]
        #[inline(always)]
        pub const fn far(&self) -> &Far {
            &self.far
        }
        #[doc = "0x2c - Modem control register"]
        #[inline(always)]
        pub const fn modem_ctl(&self) -> &ModemCtl {
            &self.modem_ctl
        }
        #[doc = "0x30 - Modem status register"]
        #[inline(always)]
        pub const fn modem_status(&self) -> &ModemStatus {
            &self.modem_status
        }
        #[doc = "0x34 - Line status register"]
        #[inline(always)]
        pub const fn line_status(&self) -> &LineStatus {
            &self.line_status
        }
        #[doc = "0x38 - UART general purpose register"]
        #[inline(always)]
        pub const fn uart_gp_reg(&self) -> &UartGpReg {
            &self.uart_gp_reg
        }
        #[doc = "0x3c - TX FIFO read register"]
        #[inline(always)]
        pub const fn tx_fifo_read(&self) -> &TxFifoRead {
            &self.tx_fifo_read
        }
        #[doc = "0x40 - RX FIFO write register"]
        #[inline(always)]
        pub const fn rx_fifo_write(&self) -> &RxFifoWrite {
            &self.rx_fifo_write
        }
        #[doc = "0x44 - FIFO status register"]
        #[inline(always)]
        pub const fn fifo_status(&self) -> &FifoStatus {
            &self.fifo_status
        }
        #[doc = "0x48 - TX FIFO data counter"]
        #[inline(always)]
        pub const fn tx_fifo_cnt(&self) -> &TxFifoCnt {
            &self.tx_fifo_cnt
        }
        #[doc = "0x4c - RX FIFO data counter"]
        #[inline(always)]
        pub const fn rx_fifo_cnt(&self) -> &RxFifoCnt {
            &self.rx_fifo_cnt
        }
        #[doc = "0x50 - TX halt register"]
        #[inline(always)]
        pub const fn halt_tx(&self) -> &HaltTx {
            &self.halt_tx
        }
        #[doc = "0x54 - DMA software acknowledge register"]
        #[inline(always)]
        pub const fn dma_sw_ack(&self) -> &DmaSwAck {
            &self.dma_sw_ack
        }
        #[doc = "0x58 - Baud rate control register"]
        #[inline(always)]
        pub const fn baud_ctl(&self) -> &BaudCtl {
            &self.baud_ctl
        }
        #[doc = "0x5c - Stop bit control register"]
        #[inline(always)]
        pub const fn stp_ctl(&self) -> &StpCtl {
            &self.stp_ctl
        }
        #[doc = "0x60 - UART parameter register"]
        #[inline(always)]
        pub const fn uart_parameter(&self) -> &UartParameter {
            &self.uart_parameter
        }
    }
    #[doc = "INTR_ID (rw) register accessor: Interrupt ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_id`] module"]
    #[doc(alias = "INTR_ID")]
    pub type IntrId = crate::Reg<intr_id::IntrIdSpec>;
    #[doc = "Interrupt ID register"]
    pub mod intr_id {
        #[doc = "Register `INTR_ID` reader"]
        pub type R = crate::R<IntrIdSpec>;
        #[doc = "Register `INTR_ID` writer"]
        pub type W = crate::W<IntrIdSpec>;
        #[doc = "Field `intr_id` reader - Interrupt ID: 0x0=modem status; 0x1=no interrupt; 0x2=THR empty; 0x4=rx data; 0x6=rx line status; 0x7=busy; 0xC=char timeout"]
        pub type IntrIdR = crate::FieldReader;
        #[doc = "Field `fifo_en_s` reader - FIFO enable status: 0=FIFO disabled; 1=FIFO enabled"]
        pub type FifoEnSR = crate::BitReader;
        impl R {
            #[doc = "Bits 0:3 - Interrupt ID: 0x0=modem status; 0x1=no interrupt; 0x2=THR empty; 0x4=rx data; 0x6=rx line status; 0x7=busy; 0xC=char timeout"]
            #[inline(always)]
            pub fn intr_id(&self) -> IntrIdR {
                IntrIdR::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bit 4 - FIFO enable status: 0=FIFO disabled; 1=FIFO enabled"]
            #[inline(always)]
            pub fn fifo_en_s(&self) -> FifoEnSR {
                FifoEnSR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Interrupt ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IntrIdSpec;
        impl crate::RegisterSpec for IntrIdSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`intr_id::R`](R) reader structure"]
        impl crate::Readable for IntrIdSpec {}
        #[doc = "`write(|w| ..)` method takes [`intr_id::W`](W) writer structure"]
        impl crate::Writable for IntrIdSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets INTR_ID to value 0x01"]
        impl crate::Resettable for IntrIdSpec {
            const RESET_VALUE: u16 = 0x01;
        }
    }
    #[doc = "DATA (rw) register accessor: Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
    #[doc(alias = "DATA")]
    pub type Data = crate::Reg<data::DataSpec>;
    #[doc = "Data register"]
    pub mod data {
        #[doc = "Register `DATA` reader"]
        pub type R = crate::R<DataSpec>;
        #[doc = "Register `DATA` writer"]
        pub type W = crate::W<DataSpec>;
        #[doc = "Field `data` reader - Write: TX data; Read: RX data"]
        pub type DataR = crate::FieldReader;
        #[doc = "Field `data` writer - Write: TX data; Read: RX data"]
        pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Write: TX data; Read: RX data"]
            #[inline(always)]
            pub fn data(&self) -> DataR {
                DataR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Write: TX data; Read: RX data"]
            #[inline(always)]
            pub fn data(&mut self) -> DataW<'_, DataSpec> {
                DataW::new(self, 0)
            }
        }
        #[doc = "Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DataSpec;
        impl crate::RegisterSpec for DataSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`data::R`](R) reader structure"]
        impl crate::Readable for DataSpec {}
        #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
        impl crate::Writable for DataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DATA to value 0"]
        impl crate::Resettable for DataSpec {}
    }
    #[doc = "UART_CTL (rw) register accessor: UART control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_ctl`] module"]
    #[doc(alias = "UART_CTL")]
    pub type UartCtl = crate::Reg<uart_ctl::UartCtlSpec>;
    #[doc = "UART control register"]
    pub mod uart_ctl {
        #[doc = "Register `UART_CTL` reader"]
        pub type R = crate::R<UartCtlSpec>;
        #[doc = "Register `UART_CTL` writer"]
        pub type W = crate::W<UartCtlSpec>;
        #[doc = "Field `div_en` reader - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
        pub type DivEnR = crate::BitReader;
        #[doc = "Field `div_en` writer - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
        pub type DivEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `xbreak` reader - Break control: 0=normal; 1=force TX to space"]
        pub type XbreakR = crate::BitReader;
        #[doc = "Field `xbreak` writer - Break control: 0=normal; 1=force TX to space"]
        pub type XbreakW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum Dlen {
            #[doc = "0: 5-bit data"]
            Bits5 = 0,
            #[doc = "1: 6-bit data"]
            Bits6 = 1,
            #[doc = "2: 7-bit data"]
            Bits7 = 2,
            #[doc = "3: 8-bit data"]
            Bits8 = 3,
        }
        impl From<Dlen> for u8 {
            #[inline(always)]
            fn from(variant: Dlen) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for Dlen {
            type Ux = u8;
        }
        impl crate::IsEnum for Dlen {}
        #[doc = "Field `dlen` reader - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
        pub type DlenR = crate::FieldReader<Dlen>;
        impl DlenR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Dlen {
                match self.bits {
                    0 => Dlen::Bits5,
                    1 => Dlen::Bits6,
                    2 => Dlen::Bits7,
                    3 => Dlen::Bits8,
                    _ => unreachable!(),
                }
            }
            #[doc = "5-bit data"]
            #[inline(always)]
            pub fn is_bits5(&self) -> bool {
                *self == Dlen::Bits5
            }
            #[doc = "6-bit data"]
            #[inline(always)]
            pub fn is_bits6(&self) -> bool {
                *self == Dlen::Bits6
            }
            #[doc = "7-bit data"]
            #[inline(always)]
            pub fn is_bits7(&self) -> bool {
                *self == Dlen::Bits7
            }
            #[doc = "8-bit data"]
            #[inline(always)]
            pub fn is_bits8(&self) -> bool {
                *self == Dlen::Bits8
            }
        }
        #[doc = "Field `dlen` writer - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
        pub type DlenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dlen, crate::Safe>;
        impl<'a, REG> DlenW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "5-bit data"]
            #[inline(always)]
            pub fn bits5(self) -> &'a mut crate::W<REG> {
                self.variant(Dlen::Bits5)
            }
            #[doc = "6-bit data"]
            #[inline(always)]
            pub fn bits6(self) -> &'a mut crate::W<REG> {
                self.variant(Dlen::Bits6)
            }
            #[doc = "7-bit data"]
            #[inline(always)]
            pub fn bits7(self) -> &'a mut crate::W<REG> {
                self.variant(Dlen::Bits7)
            }
            #[doc = "8-bit data"]
            #[inline(always)]
            pub fn bits8(self) -> &'a mut crate::W<REG> {
                self.variant(Dlen::Bits8)
            }
        }
        #[doc = "Parity select: 0=odd; 1=even\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum Eps {
            #[doc = "0: Odd parity"]
            Odd = 0,
            #[doc = "1: Even parity"]
            Even = 1,
        }
        impl From<Eps> for bool {
            #[inline(always)]
            fn from(variant: Eps) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `eps` reader - Parity select: 0=odd; 1=even"]
        pub type EpsR = crate::BitReader<Eps>;
        impl EpsR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Eps {
                match self.bits {
                    false => Eps::Odd,
                    true => Eps::Even,
                }
            }
            #[doc = "Odd parity"]
            #[inline(always)]
            pub fn is_odd(&self) -> bool {
                *self == Eps::Odd
            }
            #[doc = "Even parity"]
            #[inline(always)]
            pub fn is_even(&self) -> bool {
                *self == Eps::Even
            }
        }
        #[doc = "Field `eps` writer - Parity select: 0=odd; 1=even"]
        pub type EpsW<'a, REG> = crate::BitWriter<'a, REG, Eps>;
        impl<'a, REG> EpsW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Odd parity"]
            #[inline(always)]
            pub fn odd(self) -> &'a mut crate::W<REG> {
                self.variant(Eps::Odd)
            }
            #[doc = "Even parity"]
            #[inline(always)]
            pub fn even(self) -> &'a mut crate::W<REG> {
                self.variant(Eps::Even)
            }
        }
        #[doc = "Parity enable: 0=disabled; 1=enabled\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum Pen {
            #[doc = "0: No parity"]
            Disabled = 0,
            #[doc = "1: Parity enabled"]
            Enabled = 1,
        }
        impl From<Pen> for bool {
            #[inline(always)]
            fn from(variant: Pen) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pen` reader - Parity enable: 0=disabled; 1=enabled"]
        pub type PenR = crate::BitReader<Pen>;
        impl PenR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Pen {
                match self.bits {
                    false => Pen::Disabled,
                    true => Pen::Enabled,
                }
            }
            #[doc = "No parity"]
            #[inline(always)]
            pub fn is_disabled(&self) -> bool {
                *self == Pen::Disabled
            }
            #[doc = "Parity enabled"]
            #[inline(always)]
            pub fn is_enabled(&self) -> bool {
                *self == Pen::Enabled
            }
        }
        #[doc = "Field `pen` writer - Parity enable: 0=disabled; 1=enabled"]
        pub type PenW<'a, REG> = crate::BitWriter<'a, REG, Pen>;
        impl<'a, REG> PenW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "No parity"]
            #[inline(always)]
            pub fn disabled(self) -> &'a mut crate::W<REG> {
                self.variant(Pen::Disabled)
            }
            #[doc = "Parity enabled"]
            #[inline(always)]
            pub fn enabled(self) -> &'a mut crate::W<REG> {
                self.variant(Pen::Enabled)
            }
        }
        #[doc = "Field `sps` reader - Sticky parity: 0=disabled; 1=enabled"]
        pub type SpsR = crate::BitReader;
        #[doc = "Field `sps` writer - Sticky parity: 0=disabled; 1=enabled"]
        pub type SpsW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Stop bits: 0=1bit; 1=1.5/2bit\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum Stp {
            #[doc = "0: 1 stop bit"]
            Stop1 = 0,
            #[doc = "1: 1.5 (5-bit data) or 2 stop bits"]
            Stop1_5Or2 = 1,
        }
        impl From<Stp> for bool {
            #[inline(always)]
            fn from(variant: Stp) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `stp` reader - Stop bits: 0=1bit; 1=1.5/2bit"]
        pub type StpR = crate::BitReader<Stp>;
        impl StpR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Stp {
                match self.bits {
                    false => Stp::Stop1,
                    true => Stp::Stop1_5Or2,
                }
            }
            #[doc = "1 stop bit"]
            #[inline(always)]
            pub fn is_stop1(&self) -> bool {
                *self == Stp::Stop1
            }
            #[doc = "1.5 (5-bit data) or 2 stop bits"]
            #[inline(always)]
            pub fn is_stop1_5_or_2(&self) -> bool {
                *self == Stp::Stop1_5Or2
            }
        }
        #[doc = "Field `stp` writer - Stop bits: 0=1bit; 1=1.5/2bit"]
        pub type StpW<'a, REG> = crate::BitWriter<'a, REG, Stp>;
        impl<'a, REG> StpW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "1 stop bit"]
            #[inline(always)]
            pub fn stop1(self) -> &'a mut crate::W<REG> {
                self.variant(Stp::Stop1)
            }
            #[doc = "1.5 (5-bit data) or 2 stop bits"]
            #[inline(always)]
            pub fn stop1_5_or_2(self) -> &'a mut crate::W<REG> {
                self.variant(Stp::Stop1_5Or2)
            }
        }
        impl R {
            #[doc = "Bit 0 - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
            #[inline(always)]
            pub fn div_en(&self) -> DivEnR {
                DivEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Break control: 0=normal; 1=force TX to space"]
            #[inline(always)]
            pub fn xbreak(&self) -> XbreakR {
                XbreakR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bits 2:3 - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
            #[inline(always)]
            pub fn dlen(&self) -> DlenR {
                DlenR::new(((self.bits >> 2) & 3) as u8)
            }
            #[doc = "Bit 4 - Parity select: 0=odd; 1=even"]
            #[inline(always)]
            pub fn eps(&self) -> EpsR {
                EpsR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Parity enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn pen(&self) -> PenR {
                PenR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Sticky parity: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn sps(&self) -> SpsR {
                SpsR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Stop bits: 0=1bit; 1=1.5/2bit"]
            #[inline(always)]
            pub fn stp(&self) -> StpR {
                StpR::new(((self.bits >> 7) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Divider enable: 0=div accessible when not busy; 1=div accessible anytime"]
            #[inline(always)]
            pub fn div_en(&mut self) -> DivEnW<'_, UartCtlSpec> {
                DivEnW::new(self, 0)
            }
            #[doc = "Bit 1 - Break control: 0=normal; 1=force TX to space"]
            #[inline(always)]
            pub fn xbreak(&mut self) -> XbreakW<'_, UartCtlSpec> {
                XbreakW::new(self, 1)
            }
            #[doc = "Bits 2:3 - Data length: 00=5bit; 01=6bit; 10=7bit; 11=8bit"]
            #[inline(always)]
            pub fn dlen(&mut self) -> DlenW<'_, UartCtlSpec> {
                DlenW::new(self, 2)
            }
            #[doc = "Bit 4 - Parity select: 0=odd; 1=even"]
            #[inline(always)]
            pub fn eps(&mut self) -> EpsW<'_, UartCtlSpec> {
                EpsW::new(self, 4)
            }
            #[doc = "Bit 5 - Parity enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn pen(&mut self) -> PenW<'_, UartCtlSpec> {
                PenW::new(self, 5)
            }
            #[doc = "Bit 6 - Sticky parity: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn sps(&mut self) -> SpsW<'_, UartCtlSpec> {
                SpsW::new(self, 6)
            }
            #[doc = "Bit 7 - Stop bits: 0=1bit; 1=1.5/2bit"]
            #[inline(always)]
            pub fn stp(&mut self) -> StpW<'_, UartCtlSpec> {
                StpW::new(self, 7)
            }
        }
        #[doc = "UART control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UartCtlSpec;
        impl crate::RegisterSpec for UartCtlSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`uart_ctl::R`](R) reader structure"]
        impl crate::Readable for UartCtlSpec {}
        #[doc = "`write(|w| ..)` method takes [`uart_ctl::W`](W) writer structure"]
        impl crate::Writable for UartCtlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets UART_CTL to value 0"]
        impl crate::Resettable for UartCtlSpec {}
    }
    #[doc = "DIV_H (rw) register accessor: Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_h`] module"]
    #[doc(alias = "DIV_H")]
    pub type DivH = crate::Reg<div_h::DivHSpec>;
    #[doc = "Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
    pub mod div_h {
        #[doc = "Register `DIV_H` reader"]
        pub type R = crate::R<DivHSpec>;
        #[doc = "Register `DIV_H` writer"]
        pub type W = crate::W<DivHSpec>;
        #[doc = "Field `div_h` reader - Divider integer high 8 bits"]
        pub type DivHR = crate::FieldReader;
        #[doc = "Field `div_h` writer - Divider integer high 8 bits"]
        pub type DivHW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Divider integer high 8 bits"]
            #[inline(always)]
            pub fn div_h(&self) -> DivHR {
                DivHR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Divider integer high 8 bits"]
            #[inline(always)]
            pub fn div_h(&mut self) -> DivHW<'_, DivHSpec> {
                DivHW::new(self, 0)
            }
        }
        #[doc = "Baud rate divider high byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DivHSpec;
        impl crate::RegisterSpec for DivHSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`div_h::R`](R) reader structure"]
        impl crate::Readable for DivHSpec {}
        #[doc = "`write(|w| ..)` method takes [`div_h::W`](W) writer structure"]
        impl crate::Writable for DivHSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DIV_H to value 0"]
        impl crate::Resettable for DivHSpec {}
    }
    #[doc = "DIV_L (rw) register accessor: Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_l`] module"]
    #[doc(alias = "DIV_L")]
    pub type DivL = crate::Reg<div_l::DivLSpec>;
    #[doc = "Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)"]
    pub mod div_l {
        #[doc = "Register `DIV_L` reader"]
        pub type R = crate::R<DivLSpec>;
        #[doc = "Register `DIV_L` writer"]
        pub type W = crate::W<DivLSpec>;
        #[doc = "Field `div_l` reader - Divider integer low 8 bits"]
        pub type DivLR = crate::FieldReader;
        #[doc = "Field `div_l` writer - Divider integer low 8 bits"]
        pub type DivLW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Divider integer low 8 bits"]
            #[inline(always)]
            pub fn div_l(&self) -> DivLR {
                DivLR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Divider integer low 8 bits"]
            #[inline(always)]
            pub fn div_l(&mut self) -> DivLW<'_, DivLSpec> {
                DivLW::new(self, 0)
            }
        }
        #[doc = "Baud rate divider low byte (write only when UART_CTL\\[div_en\\]=1 or UART not busy)\n\nYou can [`read`](crate::Reg::read) this register and get [`div_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DivLSpec;
        impl crate::RegisterSpec for DivLSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`div_l::R`](R) reader structure"]
        impl crate::Readable for DivLSpec {}
        #[doc = "`write(|w| ..)` method takes [`div_l::W`](W) writer structure"]
        impl crate::Writable for DivLSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DIV_L to value 0"]
        impl crate::Resettable for DivLSpec {}
    }
    #[doc = "DIV_FRA (rw) register accessor: Baud rate divider fractional part\n\nYou can [`read`](crate::Reg::read) this register and get [`div_fra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_fra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div_fra`] module"]
    #[doc(alias = "DIV_FRA")]
    pub type DivFra = crate::Reg<div_fra::DivFraSpec>;
    #[doc = "Baud rate divider fractional part"]
    pub mod div_fra {
        #[doc = "Register `DIV_FRA` reader"]
        pub type R = crate::R<DivFraSpec>;
        #[doc = "Register `DIV_FRA` writer"]
        pub type W = crate::W<DivFraSpec>;
        #[doc = "Field `div_fra` reader - Divider fractional part (divided by 2^6)"]
        pub type DivFraR = crate::FieldReader;
        #[doc = "Field `div_fra` writer - Divider fractional part (divided by 2^6)"]
        pub type DivFraW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 0:5 - Divider fractional part (divided by 2^6)"]
            #[inline(always)]
            pub fn div_fra(&self) -> DivFraR {
                DivFraR::new((self.bits & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:5 - Divider fractional part (divided by 2^6)"]
            #[inline(always)]
            pub fn div_fra(&mut self) -> DivFraW<'_, DivFraSpec> {
                DivFraW::new(self, 0)
            }
        }
        #[doc = "Baud rate divider fractional part\n\nYou can [`read`](crate::Reg::read) this register and get [`div_fra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div_fra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DivFraSpec;
        impl crate::RegisterSpec for DivFraSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`div_fra::R`](R) reader structure"]
        impl crate::Readable for DivFraSpec {}
        #[doc = "`write(|w| ..)` method takes [`div_fra::W`](W) writer structure"]
        impl crate::Writable for DivFraSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DIV_FRA to value 0"]
        impl crate::Resettable for DivFraSpec {}
    }
    #[doc = "INTR_EN (rw) register accessor: Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_en`] module"]
    #[doc(alias = "INTR_EN")]
    pub type IntrEn = crate::Reg<intr_en::IntrEnSpec>;
    #[doc = "Interrupt enable register"]
    pub mod intr_en {
        #[doc = "Register `INTR_EN` reader"]
        pub type R = crate::R<IntrEnSpec>;
        #[doc = "Register `INTR_EN` writer"]
        pub type W = crate::W<IntrEnSpec>;
        #[doc = "Field `rece_line_stat_intr_en` reader - RX line status interrupt enable"]
        pub type ReceLineStatIntrEnR = crate::BitReader;
        #[doc = "Field `rece_line_stat_intr_en` writer - RX line status interrupt enable"]
        pub type ReceLineStatIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `modem_intr_en` reader - Modem status interrupt enable"]
        pub type ModemIntrEnR = crate::BitReader;
        #[doc = "Field `modem_intr_en` writer - Modem status interrupt enable"]
        pub type ModemIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rece_data_intr_en` reader - RX data available interrupt enable"]
        pub type ReceDataIntrEnR = crate::BitReader;
        #[doc = "Field `rece_data_intr_en` writer - RX data available interrupt enable"]
        pub type ReceDataIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tran_em_intr_en` reader - TX empty interrupt enable"]
        pub type TranEmIntrEnR = crate::BitReader;
        #[doc = "Field `tran_em_intr_en` writer - TX empty interrupt enable"]
        pub type TranEmIntrEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ptim_en` reader - Programmable THRE interrupt mode enable"]
        pub type PtimEnR = crate::BitReader;
        #[doc = "Field `ptim_en` writer - Programmable THRE interrupt mode enable"]
        pub type PtimEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - RX line status interrupt enable"]
            #[inline(always)]
            pub fn rece_line_stat_intr_en(&self) -> ReceLineStatIntrEnR {
                ReceLineStatIntrEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Modem status interrupt enable"]
            #[inline(always)]
            pub fn modem_intr_en(&self) -> ModemIntrEnR {
                ModemIntrEnR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - RX data available interrupt enable"]
            #[inline(always)]
            pub fn rece_data_intr_en(&self) -> ReceDataIntrEnR {
                ReceDataIntrEnR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - TX empty interrupt enable"]
            #[inline(always)]
            pub fn tran_em_intr_en(&self) -> TranEmIntrEnR {
                TranEmIntrEnR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Programmable THRE interrupt mode enable"]
            #[inline(always)]
            pub fn ptim_en(&self) -> PtimEnR {
                PtimEnR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - RX line status interrupt enable"]
            #[inline(always)]
            pub fn rece_line_stat_intr_en(&mut self) -> ReceLineStatIntrEnW<'_, IntrEnSpec> {
                ReceLineStatIntrEnW::new(self, 0)
            }
            #[doc = "Bit 1 - Modem status interrupt enable"]
            #[inline(always)]
            pub fn modem_intr_en(&mut self) -> ModemIntrEnW<'_, IntrEnSpec> {
                ModemIntrEnW::new(self, 1)
            }
            #[doc = "Bit 2 - RX data available interrupt enable"]
            #[inline(always)]
            pub fn rece_data_intr_en(&mut self) -> ReceDataIntrEnW<'_, IntrEnSpec> {
                ReceDataIntrEnW::new(self, 2)
            }
            #[doc = "Bit 3 - TX empty interrupt enable"]
            #[inline(always)]
            pub fn tran_em_intr_en(&mut self) -> TranEmIntrEnW<'_, IntrEnSpec> {
                TranEmIntrEnW::new(self, 3)
            }
            #[doc = "Bit 4 - Programmable THRE interrupt mode enable"]
            #[inline(always)]
            pub fn ptim_en(&mut self) -> PtimEnW<'_, IntrEnSpec> {
                PtimEnW::new(self, 4)
            }
        }
        #[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IntrEnSpec;
        impl crate::RegisterSpec for IntrEnSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`intr_en::R`](R) reader structure"]
        impl crate::Readable for IntrEnSpec {}
        #[doc = "`write(|w| ..)` method takes [`intr_en::W`](W) writer structure"]
        impl crate::Writable for IntrEnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets INTR_EN to value 0"]
        impl crate::Resettable for IntrEnSpec {}
    }
    #[doc = "INTR_STATUS (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status`] module"]
    #[doc(alias = "INTR_STATUS")]
    pub type IntrStatus = crate::Reg<intr_status::IntrStatusSpec>;
    #[doc = "Interrupt status register"]
    pub mod intr_status {
        #[doc = "Register `INTR_STATUS` reader"]
        pub type R = crate::R<IntrStatusSpec>;
        #[doc = "Register `INTR_STATUS` writer"]
        pub type W = crate::W<IntrStatusSpec>;
        #[doc = "Field `busy_det_intr` reader - Busy detect interrupt status"]
        pub type BusyDetIntrR = crate::BitReader;
        #[doc = "Field `modem_intr_status` reader - Modem interrupt status"]
        pub type ModemIntrStatusR = crate::BitReader;
        #[doc = "Field `thre_intr_status` reader - THR empty interrupt status"]
        pub type ThreIntrStatusR = crate::BitReader;
        #[doc = "Field `char_to_intr_status` reader - Character timeout interrupt status"]
        pub type CharToIntrStatusR = crate::BitReader;
        #[doc = "Field `data_avail_intr_status` reader - RX data available interrupt status"]
        pub type DataAvailIntrStatusR = crate::BitReader;
        #[doc = "Field `line_intr_status` reader - RX line interrupt status"]
        pub type LineIntrStatusR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Busy detect interrupt status"]
            #[inline(always)]
            pub fn busy_det_intr(&self) -> BusyDetIntrR {
                BusyDetIntrR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Modem interrupt status"]
            #[inline(always)]
            pub fn modem_intr_status(&self) -> ModemIntrStatusR {
                ModemIntrStatusR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - THR empty interrupt status"]
            #[inline(always)]
            pub fn thre_intr_status(&self) -> ThreIntrStatusR {
                ThreIntrStatusR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Character timeout interrupt status"]
            #[inline(always)]
            pub fn char_to_intr_status(&self) -> CharToIntrStatusR {
                CharToIntrStatusR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - RX data available interrupt status"]
            #[inline(always)]
            pub fn data_avail_intr_status(&self) -> DataAvailIntrStatusR {
                DataAvailIntrStatusR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - RX line interrupt status"]
            #[inline(always)]
            pub fn line_intr_status(&self) -> LineIntrStatusR {
                LineIntrStatusR::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IntrStatusSpec;
        impl crate::RegisterSpec for IntrStatusSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`intr_status::R`](R) reader structure"]
        impl crate::Readable for IntrStatusSpec {}
        #[doc = "`write(|w| ..)` method takes [`intr_status::W`](W) writer structure"]
        impl crate::Writable for IntrStatusSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets INTR_STATUS to value 0"]
        impl crate::Resettable for IntrStatusSpec {}
    }
    #[doc = "FIFO_CTL (rw) register accessor: FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_ctl`] module"]
    #[doc(alias = "FIFO_CTL")]
    pub type FifoCtl = crate::Reg<fifo_ctl::FifoCtlSpec>;
    #[doc = "FIFO control register"]
    pub mod fifo_ctl {
        #[doc = "Register `FIFO_CTL` reader"]
        pub type R = crate::R<FifoCtlSpec>;
        #[doc = "Register `FIFO_CTL` writer"]
        pub type W = crate::W<FifoCtlSpec>;
        #[doc = "TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum TxEmptyTrig {
            #[doc = "0: FIFO empty"]
            Empty = 0,
            #[doc = "1: 2 characters remaining"]
            Chars2 = 1,
            #[doc = "2: FIFO 1/4 full"]
            Quarter = 2,
            #[doc = "3: FIFO 1/2 full"]
            Half = 3,
        }
        impl From<TxEmptyTrig> for u8 {
            #[inline(always)]
            fn from(variant: TxEmptyTrig) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for TxEmptyTrig {
            type Ux = u8;
        }
        impl crate::IsEnum for TxEmptyTrig {}
        #[doc = "Field `tx_empty_trig` writer - TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2"]
        pub type TxEmptyTrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, TxEmptyTrig, crate::Safe>;
        impl<'a, REG> TxEmptyTrigW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "FIFO empty"]
            #[inline(always)]
            pub fn empty(self) -> &'a mut crate::W<REG> {
                self.variant(TxEmptyTrig::Empty)
            }
            #[doc = "2 characters remaining"]
            #[inline(always)]
            pub fn chars2(self) -> &'a mut crate::W<REG> {
                self.variant(TxEmptyTrig::Chars2)
            }
            #[doc = "FIFO 1/4 full"]
            #[inline(always)]
            pub fn quarter(self) -> &'a mut crate::W<REG> {
                self.variant(TxEmptyTrig::Quarter)
            }
            #[doc = "FIFO 1/2 full"]
            #[inline(always)]
            pub fn half(self) -> &'a mut crate::W<REG> {
                self.variant(TxEmptyTrig::Half)
            }
        }
        #[doc = "RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum RxEmptyTrig {
            #[doc = "0: 1 character in FIFO"]
            Char1 = 0,
            #[doc = "1: FIFO 1/4 full"]
            Quarter = 1,
            #[doc = "2: FIFO 1/2 full"]
            Half = 2,
            #[doc = "3: 2 below full"]
            Less2 = 3,
        }
        impl From<RxEmptyTrig> for u8 {
            #[inline(always)]
            fn from(variant: RxEmptyTrig) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for RxEmptyTrig {
            type Ux = u8;
        }
        impl crate::IsEnum for RxEmptyTrig {}
        #[doc = "Field `rx_empty_trig` writer - RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full"]
        pub type RxEmptyTrigW<'a, REG> = crate::FieldWriter<'a, REG, 2, RxEmptyTrig, crate::Safe>;
        impl<'a, REG> RxEmptyTrigW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "1 character in FIFO"]
            #[inline(always)]
            pub fn char1(self) -> &'a mut crate::W<REG> {
                self.variant(RxEmptyTrig::Char1)
            }
            #[doc = "FIFO 1/4 full"]
            #[inline(always)]
            pub fn quarter(self) -> &'a mut crate::W<REG> {
                self.variant(RxEmptyTrig::Quarter)
            }
            #[doc = "FIFO 1/2 full"]
            #[inline(always)]
            pub fn half(self) -> &'a mut crate::W<REG> {
                self.variant(RxEmptyTrig::Half)
            }
            #[doc = "2 below full"]
            #[inline(always)]
            pub fn less2(self) -> &'a mut crate::W<REG> {
                self.variant(RxEmptyTrig::Less2)
            }
        }
        #[doc = "Field `fifo_en` writer - FIFO enable"]
        pub type FifoEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tx_fifo_rst` writer - TX FIFO reset: 0=no reset; 1=reset"]
        pub type TxFifoRstW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rx_fifo_rst` writer - RX FIFO reset: 0=no reset; 1=reset"]
        pub type RxFifoRstW<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bits 0:1 - TX empty trigger: 00=empty; 01=2chars; 10=1/4; 11=1/2"]
            #[inline(always)]
            pub fn tx_empty_trig(&mut self) -> TxEmptyTrigW<'_, FifoCtlSpec> {
                TxEmptyTrigW::new(self, 0)
            }
            #[doc = "Bits 2:3 - RX trigger: 00=1char; 01=1/4; 10=1/2; 11=2below full"]
            #[inline(always)]
            pub fn rx_empty_trig(&mut self) -> RxEmptyTrigW<'_, FifoCtlSpec> {
                RxEmptyTrigW::new(self, 2)
            }
            #[doc = "Bit 4 - FIFO enable"]
            #[inline(always)]
            pub fn fifo_en(&mut self) -> FifoEnW<'_, FifoCtlSpec> {
                FifoEnW::new(self, 4)
            }
            #[doc = "Bit 5 - TX FIFO reset: 0=no reset; 1=reset"]
            #[inline(always)]
            pub fn tx_fifo_rst(&mut self) -> TxFifoRstW<'_, FifoCtlSpec> {
                TxFifoRstW::new(self, 5)
            }
            #[doc = "Bit 6 - RX FIFO reset: 0=no reset; 1=reset"]
            #[inline(always)]
            pub fn rx_fifo_rst(&mut self) -> RxFifoRstW<'_, FifoCtlSpec> {
                RxFifoRstW::new(self, 6)
            }
        }
        #[doc = "FIFO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FifoCtlSpec;
        impl crate::RegisterSpec for FifoCtlSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`fifo_ctl::R`](R) reader structure"]
        impl crate::Readable for FifoCtlSpec {}
        #[doc = "`write(|w| ..)` method takes [`fifo_ctl::W`](W) writer structure"]
        impl crate::Writable for FifoCtlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets FIFO_CTL to value 0"]
        impl crate::Resettable for FifoCtlSpec {}
    }
    #[doc = "FAR (rw) register accessor: FIFO access mode enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`far::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`far::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@far`] module"]
    #[doc(alias = "FAR")]
    pub type Far = crate::Reg<far::FarSpec>;
    #[doc = "FIFO access mode enable register"]
    pub mod far {
        #[doc = "Register `FAR` reader"]
        pub type R = crate::R<FarSpec>;
        #[doc = "Register `FAR` writer"]
        pub type W = crate::W<FarSpec>;
        #[doc = "Field `far` reader - FIFO access mode: 0=disabled; 1=enabled"]
        pub type FarR = crate::BitReader;
        #[doc = "Field `far` writer - FIFO access mode: 0=disabled; 1=enabled"]
        pub type FarW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - FIFO access mode: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn far(&self) -> FarR {
                FarR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - FIFO access mode: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn far(&mut self) -> FarW<'_, FarSpec> {
                FarW::new(self, 0)
            }
        }
        #[doc = "FIFO access mode enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`far::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`far::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FarSpec;
        impl crate::RegisterSpec for FarSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`far::R`](R) reader structure"]
        impl crate::Readable for FarSpec {}
        #[doc = "`write(|w| ..)` method takes [`far::W`](W) writer structure"]
        impl crate::Writable for FarSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets FAR to value 0"]
        impl crate::Resettable for FarSpec {}
    }
    #[doc = "MODEM_CTL (rw) register accessor: Modem control register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modem_ctl`] module"]
    #[doc(alias = "MODEM_CTL")]
    pub type ModemCtl = crate::Reg<modem_ctl::ModemCtlSpec>;
    #[doc = "Modem control register"]
    pub mod modem_ctl {
        #[doc = "Register `MODEM_CTL` reader"]
        pub type R = crate::R<ModemCtlSpec>;
        #[doc = "Register `MODEM_CTL` writer"]
        pub type W = crate::W<ModemCtlSpec>;
        #[doc = "Field `afc_en` reader - Auto flow control enable"]
        pub type AfcEnR = crate::BitReader;
        #[doc = "Field `afc_en` writer - Auto flow control enable"]
        pub type AfcEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `lb_mode` reader - Loopback mode: 0=disabled; 1=enabled"]
        pub type LbModeR = crate::BitReader;
        #[doc = "Field `lb_mode` writer - Loopback mode: 0=disabled; 1=enabled"]
        pub type LbModeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rts` reader - RTS software control"]
        pub type RtsR = crate::BitReader;
        #[doc = "Field `rts` writer - RTS software control"]
        pub type RtsW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Auto flow control enable"]
            #[inline(always)]
            pub fn afc_en(&self) -> AfcEnR {
                AfcEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Loopback mode: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn lb_mode(&self) -> LbModeR {
                LbModeR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - RTS software control"]
            #[inline(always)]
            pub fn rts(&self) -> RtsR {
                RtsR::new(((self.bits >> 2) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Auto flow control enable"]
            #[inline(always)]
            pub fn afc_en(&mut self) -> AfcEnW<'_, ModemCtlSpec> {
                AfcEnW::new(self, 0)
            }
            #[doc = "Bit 1 - Loopback mode: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn lb_mode(&mut self) -> LbModeW<'_, ModemCtlSpec> {
                LbModeW::new(self, 1)
            }
            #[doc = "Bit 2 - RTS software control"]
            #[inline(always)]
            pub fn rts(&mut self) -> RtsW<'_, ModemCtlSpec> {
                RtsW::new(self, 2)
            }
        }
        #[doc = "Modem control register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ModemCtlSpec;
        impl crate::RegisterSpec for ModemCtlSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`modem_ctl::R`](R) reader structure"]
        impl crate::Readable for ModemCtlSpec {}
        #[doc = "`write(|w| ..)` method takes [`modem_ctl::W`](W) writer structure"]
        impl crate::Writable for ModemCtlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets MODEM_CTL to value 0"]
        impl crate::Resettable for ModemCtlSpec {}
    }
    #[doc = "MODEM_STATUS (rw) register accessor: Modem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modem_status`] module"]
    #[doc(alias = "MODEM_STATUS")]
    pub type ModemStatus = crate::Reg<modem_status::ModemStatusSpec>;
    #[doc = "Modem status register"]
    pub mod modem_status {
        #[doc = "Register `MODEM_STATUS` reader"]
        pub type R = crate::R<ModemStatusSpec>;
        #[doc = "Register `MODEM_STATUS` writer"]
        pub type W = crate::W<ModemStatusSpec>;
        #[doc = "Field `dcts` reader - CTS change indicator"]
        pub type DctsR = crate::BitReader;
        #[doc = "Field `cts` reader - CTS signal state"]
        pub type CtsR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - CTS change indicator"]
            #[inline(always)]
            pub fn dcts(&self) -> DctsR {
                DctsR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - CTS signal state"]
            #[inline(always)]
            pub fn cts(&self) -> CtsR {
                CtsR::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Modem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`modem_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`modem_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ModemStatusSpec;
        impl crate::RegisterSpec for ModemStatusSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`modem_status::R`](R) reader structure"]
        impl crate::Readable for ModemStatusSpec {}
        #[doc = "`write(|w| ..)` method takes [`modem_status::W`](W) writer structure"]
        impl crate::Writable for ModemStatusSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets MODEM_STATUS to value 0"]
        impl crate::Resettable for ModemStatusSpec {}
    }
    #[doc = "LINE_STATUS (rw) register accessor: Line status register\n\nYou can [`read`](crate::Reg::read) this register and get [`line_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`line_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@line_status`] module"]
    #[doc(alias = "LINE_STATUS")]
    pub type LineStatus = crate::Reg<line_status::LineStatusSpec>;
    #[doc = "Line status register"]
    pub mod line_status {
        #[doc = "Register `LINE_STATUS` reader"]
        pub type R = crate::R<LineStatusSpec>;
        #[doc = "Register `LINE_STATUS` writer"]
        pub type W = crate::W<LineStatusSpec>;
        #[doc = "Field `rx_fifo_err` reader - RX FIFO error status"]
        pub type RxFifoErrR = crate::BitReader;
        #[doc = "Field `frame_err` reader - Framing error"]
        pub type FrameErrR = crate::BitReader;
        #[doc = "Field `parity_err` reader - Parity error"]
        pub type ParityErrR = crate::BitReader;
        #[doc = "Field `overrun_err` reader - Overrun error"]
        pub type OverrunErrR = crate::BitReader;
        #[doc = "Field `break_intr` reader - Break interrupt"]
        pub type BreakIntrR = crate::BitReader;
        #[doc = "Field `data_available` reader - Data available in RX FIFO/RBR"]
        pub type DataAvailableR = crate::BitReader;
        #[doc = "Field `thre_s` reader - THR empty flag"]
        pub type ThreSR = crate::BitReader;
        #[doc = "Field `tx_empty_s` reader - Transmitter empty flag"]
        pub type TxEmptySR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - RX FIFO error status"]
            #[inline(always)]
            pub fn rx_fifo_err(&self) -> RxFifoErrR {
                RxFifoErrR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Framing error"]
            #[inline(always)]
            pub fn frame_err(&self) -> FrameErrR {
                FrameErrR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Parity error"]
            #[inline(always)]
            pub fn parity_err(&self) -> ParityErrR {
                ParityErrR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Overrun error"]
            #[inline(always)]
            pub fn overrun_err(&self) -> OverrunErrR {
                OverrunErrR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Break interrupt"]
            #[inline(always)]
            pub fn break_intr(&self) -> BreakIntrR {
                BreakIntrR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Data available in RX FIFO/RBR"]
            #[inline(always)]
            pub fn data_available(&self) -> DataAvailableR {
                DataAvailableR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - THR empty flag"]
            #[inline(always)]
            pub fn thre_s(&self) -> ThreSR {
                ThreSR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Transmitter empty flag"]
            #[inline(always)]
            pub fn tx_empty_s(&self) -> TxEmptySR {
                TxEmptySR::new(((self.bits >> 7) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Line status register\n\nYou can [`read`](crate::Reg::read) this register and get [`line_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`line_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LineStatusSpec;
        impl crate::RegisterSpec for LineStatusSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`line_status::R`](R) reader structure"]
        impl crate::Readable for LineStatusSpec {}
        #[doc = "`write(|w| ..)` method takes [`line_status::W`](W) writer structure"]
        impl crate::Writable for LineStatusSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets LINE_STATUS to value 0xc0"]
        impl crate::Resettable for LineStatusSpec {
            const RESET_VALUE: u16 = 0xc0;
        }
    }
    #[doc = "UART_GP_REG (rw) register accessor: UART general purpose register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_gp_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_gp_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_gp_reg`] module"]
    #[doc(alias = "UART_GP_REG")]
    pub type UartGpReg = crate::Reg<uart_gp_reg::UartGpRegSpec>;
    #[doc = "UART general purpose register"]
    pub mod uart_gp_reg {
        #[doc = "Register `UART_GP_REG` reader"]
        pub type R = crate::R<UartGpRegSpec>;
        #[doc = "Register `UART_GP_REG` writer"]
        pub type W = crate::W<UartGpRegSpec>;
        #[doc = "Field `uart_gp_reg` reader - General purpose storage"]
        pub type UartGpRegR = crate::FieldReader;
        #[doc = "Field `uart_gp_reg` writer - General purpose storage"]
        pub type UartGpRegW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - General purpose storage"]
            #[inline(always)]
            pub fn uart_gp_reg(&self) -> UartGpRegR {
                UartGpRegR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - General purpose storage"]
            #[inline(always)]
            pub fn uart_gp_reg(&mut self) -> UartGpRegW<'_, UartGpRegSpec> {
                UartGpRegW::new(self, 0)
            }
        }
        #[doc = "UART general purpose register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_gp_reg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_gp_reg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UartGpRegSpec;
        impl crate::RegisterSpec for UartGpRegSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`uart_gp_reg::R`](R) reader structure"]
        impl crate::Readable for UartGpRegSpec {}
        #[doc = "`write(|w| ..)` method takes [`uart_gp_reg::W`](W) writer structure"]
        impl crate::Writable for UartGpRegSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets UART_GP_REG to value 0"]
        impl crate::Resettable for UartGpRegSpec {}
    }
    #[doc = "TX_FIFO_READ (rw) register accessor: TX FIFO read register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_read::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_read::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_fifo_read`] module"]
    #[doc(alias = "TX_FIFO_READ")]
    pub type TxFifoRead = crate::Reg<tx_fifo_read::TxFifoReadSpec>;
    #[doc = "TX FIFO read register"]
    pub mod tx_fifo_read {
        #[doc = "Register `TX_FIFO_READ` reader"]
        pub type R = crate::R<TxFifoReadSpec>;
        #[doc = "Register `TX_FIFO_READ` writer"]
        pub type W = crate::W<TxFifoReadSpec>;
        #[doc = "Field `tx_fifo_read` reader - TX FIFO top data"]
        pub type TxFifoReadR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - TX FIFO top data"]
            #[inline(always)]
            pub fn tx_fifo_read(&self) -> TxFifoReadR {
                TxFifoReadR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {}
        #[doc = "TX FIFO read register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_read::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_read::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TxFifoReadSpec;
        impl crate::RegisterSpec for TxFifoReadSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`tx_fifo_read::R`](R) reader structure"]
        impl crate::Readable for TxFifoReadSpec {}
        #[doc = "`write(|w| ..)` method takes [`tx_fifo_read::W`](W) writer structure"]
        impl crate::Writable for TxFifoReadSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TX_FIFO_READ to value 0"]
        impl crate::Resettable for TxFifoReadSpec {}
    }
    #[doc = "RX_FIFO_WRITE (rw) register accessor: RX FIFO write register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_write::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_write::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_fifo_write`] module"]
    #[doc(alias = "RX_FIFO_WRITE")]
    pub type RxFifoWrite = crate::Reg<rx_fifo_write::RxFifoWriteSpec>;
    #[doc = "RX FIFO write register"]
    pub mod rx_fifo_write {
        #[doc = "Register `RX_FIFO_WRITE` reader"]
        pub type R = crate::R<RxFifoWriteSpec>;
        #[doc = "Register `RX_FIFO_WRITE` writer"]
        pub type W = crate::W<RxFifoWriteSpec>;
        #[doc = "Field `rx_fifo_write` reader - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
        pub type RxFifoWriteR = crate::FieldReader;
        #[doc = "Field `rx_fifo_write` writer - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
        pub type RxFifoWriteW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `rx_fifo_pe` writer - RX FIFO parity error"]
        pub type RxFifoPeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rx_fifo_fe` writer - RX FIFO framing error"]
        pub type RxFifoFeW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:7 - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
            #[inline(always)]
            pub fn rx_fifo_write(&self) -> RxFifoWriteR {
                RxFifoWriteR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Write: push data to RX FIFO; Read: rx_fifo_level\\[6:0\\]"]
            #[inline(always)]
            pub fn rx_fifo_write(&mut self) -> RxFifoWriteW<'_, RxFifoWriteSpec> {
                RxFifoWriteW::new(self, 0)
            }
            #[doc = "Bit 8 - RX FIFO parity error"]
            #[inline(always)]
            pub fn rx_fifo_pe(&mut self) -> RxFifoPeW<'_, RxFifoWriteSpec> {
                RxFifoPeW::new(self, 8)
            }
            #[doc = "Bit 9 - RX FIFO framing error"]
            #[inline(always)]
            pub fn rx_fifo_fe(&mut self) -> RxFifoFeW<'_, RxFifoWriteSpec> {
                RxFifoFeW::new(self, 9)
            }
        }
        #[doc = "RX FIFO write register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_write::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_write::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RxFifoWriteSpec;
        impl crate::RegisterSpec for RxFifoWriteSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`rx_fifo_write::R`](R) reader structure"]
        impl crate::Readable for RxFifoWriteSpec {}
        #[doc = "`write(|w| ..)` method takes [`rx_fifo_write::W`](W) writer structure"]
        impl crate::Writable for RxFifoWriteSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RX_FIFO_WRITE to value 0"]
        impl crate::Resettable for RxFifoWriteSpec {}
    }
    #[doc = "FIFO_STATUS (rw) register accessor: FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_status`] module"]
    #[doc(alias = "FIFO_STATUS")]
    pub type FifoStatus = crate::Reg<fifo_status::FifoStatusSpec>;
    #[doc = "FIFO status register"]
    pub mod fifo_status {
        #[doc = "Register `FIFO_STATUS` reader"]
        pub type R = crate::R<FifoStatusSpec>;
        #[doc = "Register `FIFO_STATUS` writer"]
        pub type W = crate::W<FifoStatusSpec>;
        #[doc = "Field `tx_fifo_full` reader - TX FIFO full flag"]
        pub type TxFifoFullR = crate::BitReader;
        #[doc = "Field `tx_fifo_empty` reader - TX FIFO empty flag"]
        pub type TxFifoEmptyR = crate::BitReader;
        #[doc = "Field `rx_fifo_full` reader - RX FIFO full flag"]
        pub type RxFifoFullR = crate::BitReader;
        #[doc = "Field `rx_fifo_empty` reader - RX FIFO empty flag"]
        pub type RxFifoEmptyR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - TX FIFO full flag"]
            #[inline(always)]
            pub fn tx_fifo_full(&self) -> TxFifoFullR {
                TxFifoFullR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TX FIFO empty flag"]
            #[inline(always)]
            pub fn tx_fifo_empty(&self) -> TxFifoEmptyR {
                TxFifoEmptyR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - RX FIFO full flag"]
            #[inline(always)]
            pub fn rx_fifo_full(&self) -> RxFifoFullR {
                RxFifoFullR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - RX FIFO empty flag"]
            #[inline(always)]
            pub fn rx_fifo_empty(&self) -> RxFifoEmptyR {
                RxFifoEmptyR::new(((self.bits >> 3) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FifoStatusSpec;
        impl crate::RegisterSpec for FifoStatusSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`fifo_status::R`](R) reader structure"]
        impl crate::Readable for FifoStatusSpec {}
        #[doc = "`write(|w| ..)` method takes [`fifo_status::W`](W) writer structure"]
        impl crate::Writable for FifoStatusSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets FIFO_STATUS to value 0x02"]
        impl crate::Resettable for FifoStatusSpec {
            const RESET_VALUE: u16 = 0x02;
        }
    }
    #[doc = "TX_FIFO_CNT (rw) register accessor: TX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_fifo_cnt`] module"]
    #[doc(alias = "TX_FIFO_CNT")]
    pub type TxFifoCnt = crate::Reg<tx_fifo_cnt::TxFifoCntSpec>;
    #[doc = "TX FIFO data counter"]
    pub mod tx_fifo_cnt {
        #[doc = "Register `TX_FIFO_CNT` reader"]
        pub type R = crate::R<TxFifoCntSpec>;
        #[doc = "Register `TX_FIFO_CNT` writer"]
        pub type W = crate::W<TxFifoCntSpec>;
        #[doc = "Field `tx_fifo_level` reader - TX FIFO data count"]
        pub type TxFifoLevelR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:6 - TX FIFO data count"]
            #[inline(always)]
            pub fn tx_fifo_level(&self) -> TxFifoLevelR {
                TxFifoLevelR::new((self.bits & 0x7f) as u8)
            }
        }
        impl W {}
        #[doc = "TX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_fifo_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_fifo_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TxFifoCntSpec;
        impl crate::RegisterSpec for TxFifoCntSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`tx_fifo_cnt::R`](R) reader structure"]
        impl crate::Readable for TxFifoCntSpec {}
        #[doc = "`write(|w| ..)` method takes [`tx_fifo_cnt::W`](W) writer structure"]
        impl crate::Writable for TxFifoCntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TX_FIFO_CNT to value 0"]
        impl crate::Resettable for TxFifoCntSpec {}
    }
    #[doc = "RX_FIFO_CNT (rw) register accessor: RX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_fifo_cnt`] module"]
    #[doc(alias = "RX_FIFO_CNT")]
    pub type RxFifoCnt = crate::Reg<rx_fifo_cnt::RxFifoCntSpec>;
    #[doc = "RX FIFO data counter"]
    pub mod rx_fifo_cnt {
        #[doc = "Register `RX_FIFO_CNT` reader"]
        pub type R = crate::R<RxFifoCntSpec>;
        #[doc = "Register `RX_FIFO_CNT` writer"]
        pub type W = crate::W<RxFifoCntSpec>;
        impl W {}
        #[doc = "RX FIFO data counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_fifo_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_fifo_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RxFifoCntSpec;
        impl crate::RegisterSpec for RxFifoCntSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`rx_fifo_cnt::R`](R) reader structure"]
        impl crate::Readable for RxFifoCntSpec {}
        #[doc = "`write(|w| ..)` method takes [`rx_fifo_cnt::W`](W) writer structure"]
        impl crate::Writable for RxFifoCntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RX_FIFO_CNT to value 0"]
        impl crate::Resettable for RxFifoCntSpec {}
    }
    #[doc = "HALT_TX (rw) register accessor: TX halt register\n\nYou can [`read`](crate::Reg::read) this register and get [`halt_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halt_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@halt_tx`] module"]
    #[doc(alias = "HALT_TX")]
    pub type HaltTx = crate::Reg<halt_tx::HaltTxSpec>;
    #[doc = "TX halt register"]
    pub mod halt_tx {
        #[doc = "Register `HALT_TX` reader"]
        pub type R = crate::R<HaltTxSpec>;
        #[doc = "Register `HALT_TX` writer"]
        pub type W = crate::W<HaltTxSpec>;
        #[doc = "Field `halt_tx` reader - TX halt: 0=disabled; 1=enabled"]
        pub type HaltTxR = crate::BitReader;
        #[doc = "Field `halt_tx` writer - TX halt: 0=disabled; 1=enabled"]
        pub type HaltTxW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - TX halt: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn halt_tx(&self) -> HaltTxR {
                HaltTxR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - TX halt: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn halt_tx(&mut self) -> HaltTxW<'_, HaltTxSpec> {
                HaltTxW::new(self, 0)
            }
        }
        #[doc = "TX halt register\n\nYou can [`read`](crate::Reg::read) this register and get [`halt_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`halt_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HaltTxSpec;
        impl crate::RegisterSpec for HaltTxSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`halt_tx::R`](R) reader structure"]
        impl crate::Readable for HaltTxSpec {}
        #[doc = "`write(|w| ..)` method takes [`halt_tx::W`](W) writer structure"]
        impl crate::Writable for HaltTxSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets HALT_TX to value 0"]
        impl crate::Resettable for HaltTxSpec {}
    }
    #[doc = "DMA_SW_ACK (rw) register accessor: DMA software acknowledge register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sw_ack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sw_ack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_sw_ack`] module"]
    #[doc(alias = "DMA_SW_ACK")]
    pub type DmaSwAck = crate::Reg<dma_sw_ack::DmaSwAckSpec>;
    #[doc = "DMA software acknowledge register"]
    pub mod dma_sw_ack {
        #[doc = "Register `DMA_SW_ACK` reader"]
        pub type R = crate::R<DmaSwAckSpec>;
        #[doc = "Register `DMA_SW_ACK` writer"]
        pub type W = crate::W<DmaSwAckSpec>;
        #[doc = "Field `dma_sw_ack` writer - DMA software acknowledge (write-clear)"]
        pub type DmaSwAckW<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - DMA software acknowledge (write-clear)"]
            #[inline(always)]
            pub fn dma_sw_ack(&mut self) -> DmaSwAckW<'_, DmaSwAckSpec> {
                DmaSwAckW::new(self, 0)
            }
        }
        #[doc = "DMA software acknowledge register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sw_ack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sw_ack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmaSwAckSpec;
        impl crate::RegisterSpec for DmaSwAckSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`dma_sw_ack::R`](R) reader structure"]
        impl crate::Readable for DmaSwAckSpec {}
        #[doc = "`write(|w| ..)` method takes [`dma_sw_ack::W`](W) writer structure"]
        impl crate::Writable for DmaSwAckSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMA_SW_ACK to value 0"]
        impl crate::Resettable for DmaSwAckSpec {}
    }
    #[doc = "BAUD_CTL (rw) register accessor: Baud rate control register\n\nYou can [`read`](crate::Reg::read) this register and get [`baud_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud_ctl`] module"]
    #[doc(alias = "BAUD_CTL")]
    pub type BaudCtl = crate::Reg<baud_ctl::BaudCtlSpec>;
    #[doc = "Baud rate control register"]
    pub mod baud_ctl {
        #[doc = "Register `BAUD_CTL` reader"]
        pub type R = crate::R<BaudCtlSpec>;
        #[doc = "Register `BAUD_CTL` writer"]
        pub type W = crate::W<BaudCtlSpec>;
        #[doc = "Baud rate oversampling: 0x7=8x; 0xF=16x\n\nValue on reset: 15"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum BaudDiv {
            #[doc = "7: 8x oversampling"]
            Div8 = 7,
            #[doc = "15: 16x oversampling"]
            Div16 = 15,
        }
        impl From<BaudDiv> for u8 {
            #[inline(always)]
            fn from(variant: BaudDiv) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for BaudDiv {
            type Ux = u8;
        }
        impl crate::IsEnum for BaudDiv {}
        #[doc = "Field `baud_div` reader - Baud rate oversampling: 0x7=8x; 0xF=16x"]
        pub type BaudDivR = crate::FieldReader<BaudDiv>;
        impl BaudDivR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Option<BaudDiv> {
                match self.bits {
                    7 => Some(BaudDiv::Div8),
                    15 => Some(BaudDiv::Div16),
                    _ => None,
                }
            }
            #[doc = "8x oversampling"]
            #[inline(always)]
            pub fn is_div8(&self) -> bool {
                *self == BaudDiv::Div8
            }
            #[doc = "16x oversampling"]
            #[inline(always)]
            pub fn is_div16(&self) -> bool {
                *self == BaudDiv::Div16
            }
        }
        #[doc = "Field `baud_div` writer - Baud rate oversampling: 0x7=8x; 0xF=16x"]
        pub type BaudDivW<'a, REG> = crate::FieldWriter<'a, REG, 4, BaudDiv>;
        impl<'a, REG> BaudDivW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "8x oversampling"]
            #[inline(always)]
            pub fn div8(self) -> &'a mut crate::W<REG> {
                self.variant(BaudDiv::Div8)
            }
            #[doc = "16x oversampling"]
            #[inline(always)]
            pub fn div16(self) -> &'a mut crate::W<REG> {
                self.variant(BaudDiv::Div16)
            }
        }
        #[doc = "Field `sample_phase` reader - RX sample phase"]
        pub type SamplePhaseR = crate::FieldReader;
        #[doc = "Field `sample_phase` writer - RX sample phase"]
        pub type SamplePhaseW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3 - Baud rate oversampling: 0x7=8x; 0xF=16x"]
            #[inline(always)]
            pub fn baud_div(&self) -> BaudDivR {
                BaudDivR::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:7 - RX sample phase"]
            #[inline(always)]
            pub fn sample_phase(&self) -> SamplePhaseR {
                SamplePhaseR::new(((self.bits >> 4) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - Baud rate oversampling: 0x7=8x; 0xF=16x"]
            #[inline(always)]
            pub fn baud_div(&mut self) -> BaudDivW<'_, BaudCtlSpec> {
                BaudDivW::new(self, 0)
            }
            #[doc = "Bits 4:7 - RX sample phase"]
            #[inline(always)]
            pub fn sample_phase(&mut self) -> SamplePhaseW<'_, BaudCtlSpec> {
                SamplePhaseW::new(self, 4)
            }
        }
        #[doc = "Baud rate control register\n\nYou can [`read`](crate::Reg::read) this register and get [`baud_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`baud_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BaudCtlSpec;
        impl crate::RegisterSpec for BaudCtlSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`baud_ctl::R`](R) reader structure"]
        impl crate::Readable for BaudCtlSpec {}
        #[doc = "`write(|w| ..)` method takes [`baud_ctl::W`](W) writer structure"]
        impl crate::Writable for BaudCtlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets BAUD_CTL to value 0x7f"]
        impl crate::Resettable for BaudCtlSpec {
            const RESET_VALUE: u16 = 0x7f;
        }
    }
    #[doc = "STP_CTL (rw) register accessor: Stop bit control register\n\nYou can [`read`](crate::Reg::read) this register and get [`stp_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stp_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stp_ctl`] module"]
    #[doc(alias = "STP_CTL")]
    pub type StpCtl = crate::Reg<stp_ctl::StpCtlSpec>;
    #[doc = "Stop bit control register"]
    pub mod stp_ctl {
        #[doc = "Register `STP_CTL` reader"]
        pub type R = crate::R<StpCtlSpec>;
        #[doc = "Register `STP_CTL` writer"]
        pub type W = crate::W<StpCtlSpec>;
        #[doc = "Field `rx_sp` reader - RX stop bits when stp_mode=1"]
        pub type RxSpR = crate::BitReader;
        #[doc = "Field `rx_sp` writer - RX stop bits when stp_mode=1"]
        pub type RxSpW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tx_sp` reader - TX stop bits when stp_mode=1"]
        pub type TxSpR = crate::BitReader;
        #[doc = "Field `tx_sp` writer - TX stop bits when stp_mode=1"]
        pub type TxSpW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `stp_mode` reader - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
        pub type StpModeR = crate::BitReader;
        #[doc = "Field `stp_mode` writer - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
        pub type StpModeW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - RX stop bits when stp_mode=1"]
            #[inline(always)]
            pub fn rx_sp(&self) -> RxSpR {
                RxSpR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TX stop bits when stp_mode=1"]
            #[inline(always)]
            pub fn tx_sp(&self) -> TxSpR {
                TxSpR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
            #[inline(always)]
            pub fn stp_mode(&self) -> StpModeR {
                StpModeR::new(((self.bits >> 2) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - RX stop bits when stp_mode=1"]
            #[inline(always)]
            pub fn rx_sp(&mut self) -> RxSpW<'_, StpCtlSpec> {
                RxSpW::new(self, 0)
            }
            #[doc = "Bit 1 - TX stop bits when stp_mode=1"]
            #[inline(always)]
            pub fn tx_sp(&mut self) -> TxSpW<'_, StpCtlSpec> {
                TxSpW::new(self, 1)
            }
            #[doc = "Bit 2 - Stop bit control mode: 0=UART_CTL stp; 1=STP_CTL"]
            #[inline(always)]
            pub fn stp_mode(&mut self) -> StpModeW<'_, StpCtlSpec> {
                StpModeW::new(self, 2)
            }
        }
        #[doc = "Stop bit control register\n\nYou can [`read`](crate::Reg::read) this register and get [`stp_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stp_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct StpCtlSpec;
        impl crate::RegisterSpec for StpCtlSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`stp_ctl::R`](R) reader structure"]
        impl crate::Readable for StpCtlSpec {}
        #[doc = "`write(|w| ..)` method takes [`stp_ctl::W`](W) writer structure"]
        impl crate::Writable for StpCtlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets STP_CTL to value 0"]
        impl crate::Resettable for StpCtlSpec {}
    }
    #[doc = "UART_PARAMETER (rw) register accessor: UART parameter register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_parameter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_parameter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_parameter`] module"]
    #[doc(alias = "UART_PARAMETER")]
    pub type UartParameter = crate::Reg<uart_parameter::UartParameterSpec>;
    #[doc = "UART parameter register"]
    pub mod uart_parameter {
        #[doc = "Register `UART_PARAMETER` reader"]
        pub type R = crate::R<UartParameterSpec>;
        #[doc = "Register `UART_PARAMETER` writer"]
        pub type W = crate::W<UartParameterSpec>;
        #[doc = "Field `fifo_depth` reader - FIFO depth: 0x4=64"]
        pub type FifoDepthR = crate::FieldReader;
        #[doc = "Field `apb_data_width` reader - APB data width: 0x1=16bit"]
        pub type ApbDataWidthR = crate::FieldReader;
        #[doc = "Field `afce_mode` reader - AFCE mode: 0=disabled; 1=enabled"]
        pub type AfceModeR = crate::BitReader;
        #[doc = "Field `dma_mode` reader - DMA mode: 0=DMA_EXTRA disabled; 1=enabled"]
        pub type DmaModeR = crate::BitReader;
        #[doc = "Field `shadow` reader - Shadow feature enable"]
        pub type ShadowR = crate::BitReader;
        impl R {
            #[doc = "Bits 0:7 - FIFO depth: 0x4=64"]
            #[inline(always)]
            pub fn fifo_depth(&self) -> FifoDepthR {
                FifoDepthR::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:9 - APB data width: 0x1=16bit"]
            #[inline(always)]
            pub fn apb_data_width(&self) -> ApbDataWidthR {
                ApbDataWidthR::new(((self.bits >> 8) & 3) as u8)
            }
            #[doc = "Bit 10 - AFCE mode: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn afce_mode(&self) -> AfceModeR {
                AfceModeR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - DMA mode: 0=DMA_EXTRA disabled; 1=enabled"]
            #[inline(always)]
            pub fn dma_mode(&self) -> DmaModeR {
                DmaModeR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - Shadow feature enable"]
            #[inline(always)]
            pub fn shadow(&self) -> ShadowR {
                ShadowR::new(((self.bits >> 12) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "UART parameter register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart_parameter::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart_parameter::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UartParameterSpec;
        impl crate::RegisterSpec for UartParameterSpec {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`uart_parameter::R`](R) reader structure"]
        impl crate::Readable for UartParameterSpec {}
        #[doc = "`write(|w| ..)` method takes [`uart_parameter::W`](W) writer structure"]
        impl crate::Writable for UartParameterSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets UART_PARAMETER to value 0x0d04"]
        impl crate::Resettable for UartParameterSpec {
            const RESET_VALUE: u16 = 0x0d04;
        }
    }
}
#[doc = "Timer module with 3 independent 32-bit timers (v150)"]
pub type Timer = crate::Periph<timer::RegisterBlock, 0x5200_2000>;
impl core::fmt::Debug for Timer {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Timer").finish()
    }
}
#[doc = "Timer module with 3 independent 32-bit timers (v150)"]
pub mod timer {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x60],
        abnor_intr_raw: AbnorIntrRaw,
        abnor_imsk: AbnorImsk,
        abnor_intr_stat: AbnorIntrStat,
        _reserved3: [u8; 0x0c],
        eoi_ren: EoiRen,
        raw_intr_stat: RawIntrStat,
        intr_stat: IntrStat,
        _reserved6: [u8; 0x7c],
        timer0_load_count: (),
        _reserved7: [u8; 0x08],
        timer0_current_value: (),
        _reserved8: [u8; 0x08],
        timer0_control: (),
        _reserved9: [u8; 0x04],
        timer0_eoi: (),
        _reserved10: [u8; 0x04],
        timer0_raw_intr: (),
    }
    impl RegisterBlock {
        #[doc = "0x60 - Abnormal interrupt raw status"]
        #[inline(always)]
        pub const fn abnor_intr_raw(&self) -> &AbnorIntrRaw {
            &self.abnor_intr_raw
        }
        #[doc = "0x64 - Abnormal interrupt mask"]
        #[inline(always)]
        pub const fn abnor_imsk(&self) -> &AbnorImsk {
            &self.abnor_imsk
        }
        #[doc = "0x68 - Abnormal interrupt status"]
        #[inline(always)]
        pub const fn abnor_intr_stat(&self) -> &AbnorIntrStat {
            &self.abnor_intr_stat
        }
        #[doc = "0x78 - End-of-interrupt register"]
        #[inline(always)]
        pub const fn eoi_ren(&self) -> &EoiRen {
            &self.eoi_ren
        }
        #[doc = "0x7c - Raw interrupt status"]
        #[inline(always)]
        pub const fn raw_intr_stat(&self) -> &RawIntrStat {
            &self.raw_intr_stat
        }
        #[doc = "0x80 - Interrupt status (masked)"]
        #[inline(always)]
        pub const fn intr_stat(&self) -> &IntrStat {
            &self.intr_stat
        }
        #[doc = "0x100..0x10c - Timer %s \\[dim=3\\] load count"]
        #[inline(always)]
        pub const fn timer0_load_count(&self, n: usize) -> &TimerLoadCount {
            #[allow(clippy::no_effect)]
            [(); 3][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(256)
                    .add(256 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x100..0x10c - Timer %s \\[dim=3\\] load count"]
        #[inline(always)]
        pub fn timer0_load_count_iter(&self) -> impl Iterator<Item = &TimerLoadCount> {
            (0..3).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(256)
                    .add(256 * n)
                    .cast()
            })
        }
        #[doc = "0x200 - Timer 1 \\[dim=3\\] load count"]
        #[inline(always)]
        pub const fn timer1_load_count(&self) -> &TimerLoadCount {
            self.timer0_load_count(1)
        }
        #[doc = "0x300 - Timer 2 \\[dim=3\\] load count"]
        #[inline(always)]
        pub const fn timer2_load_count(&self) -> &TimerLoadCount {
            self.timer0_load_count(2)
        }
        #[doc = "0x108..0x114 - Timer %s \\[dim=3\\] current value"]
        #[inline(always)]
        pub const fn timer0_current_value(&self, n: usize) -> &TimerCurrentValue {
            #[allow(clippy::no_effect)]
            [(); 3][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(264)
                    .add(256 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x108..0x114 - Timer %s \\[dim=3\\] current value"]
        #[inline(always)]
        pub fn timer0_current_value_iter(&self) -> impl Iterator<Item = &TimerCurrentValue> {
            (0..3).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(264)
                    .add(256 * n)
                    .cast()
            })
        }
        #[doc = "0x208 - Timer 1 \\[dim=3\\] current value"]
        #[inline(always)]
        pub const fn timer1_current_value(&self) -> &TimerCurrentValue {
            self.timer0_current_value(1)
        }
        #[doc = "0x308 - Timer 2 \\[dim=3\\] current value"]
        #[inline(always)]
        pub const fn timer2_current_value(&self) -> &TimerCurrentValue {
            self.timer0_current_value(2)
        }
        #[doc = "0x110..0x11c - Timer %s \\[dim=3\\] control register"]
        #[inline(always)]
        pub const fn timer0_control(&self, n: usize) -> &TimerControl {
            #[allow(clippy::no_effect)]
            [(); 3][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(272)
                    .add(256 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x110..0x11c - Timer %s \\[dim=3\\] control register"]
        #[inline(always)]
        pub fn timer0_control_iter(&self) -> impl Iterator<Item = &TimerControl> {
            (0..3).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(272)
                    .add(256 * n)
                    .cast()
            })
        }
        #[doc = "0x210 - Timer 1 \\[dim=3\\] control register"]
        #[inline(always)]
        pub const fn timer1_control(&self) -> &TimerControl {
            self.timer0_control(1)
        }
        #[doc = "0x310 - Timer 2 \\[dim=3\\] control register"]
        #[inline(always)]
        pub const fn timer2_control(&self) -> &TimerControl {
            self.timer0_control(2)
        }
        #[doc = "0x114..0x120 - Timer %s \\[dim=3\\] end-of-interrupt"]
        #[inline(always)]
        pub const fn timer0_eoi(&self, n: usize) -> &TimerEoi {
            #[allow(clippy::no_effect)]
            [(); 3][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(276)
                    .add(256 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x114..0x120 - Timer %s \\[dim=3\\] end-of-interrupt"]
        #[inline(always)]
        pub fn timer0_eoi_iter(&self) -> impl Iterator<Item = &TimerEoi> {
            (0..3).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(276)
                    .add(256 * n)
                    .cast()
            })
        }
        #[doc = "0x214 - Timer 1 \\[dim=3\\] end-of-interrupt"]
        #[inline(always)]
        pub const fn timer1_eoi(&self) -> &TimerEoi {
            self.timer0_eoi(1)
        }
        #[doc = "0x314 - Timer 2 \\[dim=3\\] end-of-interrupt"]
        #[inline(always)]
        pub const fn timer2_eoi(&self) -> &TimerEoi {
            self.timer0_eoi(2)
        }
        #[doc = "0x118..0x124 - Timer %s \\[dim=3\\] raw interrupt status"]
        #[inline(always)]
        pub const fn timer0_raw_intr(&self, n: usize) -> &TimerRawIntr {
            #[allow(clippy::no_effect)]
            [(); 3][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(280)
                    .add(256 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x118..0x124 - Timer %s \\[dim=3\\] raw interrupt status"]
        #[inline(always)]
        pub fn timer0_raw_intr_iter(&self) -> impl Iterator<Item = &TimerRawIntr> {
            (0..3).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(280)
                    .add(256 * n)
                    .cast()
            })
        }
        #[doc = "0x218 - Timer 1 \\[dim=3\\] raw interrupt status"]
        #[inline(always)]
        pub const fn timer1_raw_intr(&self) -> &TimerRawIntr {
            self.timer0_raw_intr(1)
        }
        #[doc = "0x318 - Timer 2 \\[dim=3\\] raw interrupt status"]
        #[inline(always)]
        pub const fn timer2_raw_intr(&self) -> &TimerRawIntr {
            self.timer0_raw_intr(2)
        }
    }
    #[doc = "ABNOR_INTR_RAW (rw) register accessor: Abnormal interrupt raw status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_intr_raw`] module"]
    #[doc(alias = "ABNOR_INTR_RAW")]
    pub type AbnorIntrRaw = crate::Reg<abnor_intr_raw::AbnorIntrRawSpec>;
    #[doc = "Abnormal interrupt raw status"]
    pub mod abnor_intr_raw {
        #[doc = "Register `ABNOR_INTR_RAW` reader"]
        pub type R = crate::R<AbnorIntrRawSpec>;
        #[doc = "Register `ABNOR_INTR_RAW` writer"]
        pub type W = crate::W<AbnorIntrRawSpec>;
        #[doc = "Field `abnor_intr_raw` reader - Abnormal interrupt raw status for all timers"]
        pub type AbnorIntrRawR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:2 - Abnormal interrupt raw status for all timers"]
            #[inline(always)]
            pub fn abnor_intr_raw(&self) -> AbnorIntrRawR {
                AbnorIntrRawR::new((self.bits & 7) as u8)
            }
        }
        impl W {}
        #[doc = "Abnormal interrupt raw status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct AbnorIntrRawSpec;
        impl crate::RegisterSpec for AbnorIntrRawSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`abnor_intr_raw::R`](R) reader structure"]
        impl crate::Readable for AbnorIntrRawSpec {}
        #[doc = "`write(|w| ..)` method takes [`abnor_intr_raw::W`](W) writer structure"]
        impl crate::Writable for AbnorIntrRawSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets ABNOR_INTR_RAW to value 0"]
        impl crate::Resettable for AbnorIntrRawSpec {}
    }
    #[doc = "ABNOR_IMSK (rw) register accessor: Abnormal interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_imsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_imsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_imsk`] module"]
    #[doc(alias = "ABNOR_IMSK")]
    pub type AbnorImsk = crate::Reg<abnor_imsk::AbnorImskSpec>;
    #[doc = "Abnormal interrupt mask"]
    pub mod abnor_imsk {
        #[doc = "Register `ABNOR_IMSK` reader"]
        pub type R = crate::R<AbnorImskSpec>;
        #[doc = "Register `ABNOR_IMSK` writer"]
        pub type W = crate::W<AbnorImskSpec>;
        #[doc = "Field `abnor_imsk` reader - Abnormal interrupt mask for all timers"]
        pub type AbnorImskR = crate::FieldReader;
        #[doc = "Field `abnor_imsk` writer - Abnormal interrupt mask for all timers"]
        pub type AbnorImskW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:2 - Abnormal interrupt mask for all timers"]
            #[inline(always)]
            pub fn abnor_imsk(&self) -> AbnorImskR {
                AbnorImskR::new((self.bits & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - Abnormal interrupt mask for all timers"]
            #[inline(always)]
            pub fn abnor_imsk(&mut self) -> AbnorImskW<'_, AbnorImskSpec> {
                AbnorImskW::new(self, 0)
            }
        }
        #[doc = "Abnormal interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_imsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_imsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct AbnorImskSpec;
        impl crate::RegisterSpec for AbnorImskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`abnor_imsk::R`](R) reader structure"]
        impl crate::Readable for AbnorImskSpec {}
        #[doc = "`write(|w| ..)` method takes [`abnor_imsk::W`](W) writer structure"]
        impl crate::Writable for AbnorImskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets ABNOR_IMSK to value 0"]
        impl crate::Resettable for AbnorImskSpec {}
    }
    #[doc = "ABNOR_INTR_STAT (rw) register accessor: Abnormal interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abnor_intr_stat`] module"]
    #[doc(alias = "ABNOR_INTR_STAT")]
    pub type AbnorIntrStat = crate::Reg<abnor_intr_stat::AbnorIntrStatSpec>;
    #[doc = "Abnormal interrupt status"]
    pub mod abnor_intr_stat {
        #[doc = "Register `ABNOR_INTR_STAT` reader"]
        pub type R = crate::R<AbnorIntrStatSpec>;
        #[doc = "Register `ABNOR_INTR_STAT` writer"]
        pub type W = crate::W<AbnorIntrStatSpec>;
        #[doc = "Field `abnor_intr_stat` reader - Abnormal interrupt status for all timers"]
        pub type AbnorIntrStatR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:2 - Abnormal interrupt status for all timers"]
            #[inline(always)]
            pub fn abnor_intr_stat(&self) -> AbnorIntrStatR {
                AbnorIntrStatR::new((self.bits & 7) as u8)
            }
        }
        impl W {}
        #[doc = "Abnormal interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`abnor_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abnor_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct AbnorIntrStatSpec;
        impl crate::RegisterSpec for AbnorIntrStatSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`abnor_intr_stat::R`](R) reader structure"]
        impl crate::Readable for AbnorIntrStatSpec {}
        #[doc = "`write(|w| ..)` method takes [`abnor_intr_stat::W`](W) writer structure"]
        impl crate::Writable for AbnorIntrStatSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets ABNOR_INTR_STAT to value 0"]
        impl crate::Resettable for AbnorIntrStatSpec {}
    }
    #[doc = "EOI_REN (rw) register accessor: End-of-interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi_ren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi_ren`] module"]
    #[doc(alias = "EOI_REN")]
    pub type EoiRen = crate::Reg<eoi_ren::EoiRenSpec>;
    #[doc = "End-of-interrupt register"]
    pub mod eoi_ren {
        #[doc = "Register `EOI_REN` reader"]
        pub type R = crate::R<EoiRenSpec>;
        #[doc = "Register `EOI_REN` writer"]
        pub type W = crate::W<EoiRenSpec>;
        #[doc = "Field `eoi` reader - Clear interrupts for all timers (read to clear)"]
        pub type EoiR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:2 - Clear interrupts for all timers (read to clear)"]
            #[inline(always)]
            pub fn eoi(&self) -> EoiR {
                EoiR::new((self.bits & 7) as u8)
            }
        }
        impl W {}
        #[doc = "End-of-interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eoi_ren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct EoiRenSpec;
        impl crate::RegisterSpec for EoiRenSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`eoi_ren::R`](R) reader structure"]
        impl crate::Readable for EoiRenSpec {}
        #[doc = "`write(|w| ..)` method takes [`eoi_ren::W`](W) writer structure"]
        impl crate::Writable for EoiRenSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets EOI_REN to value 0"]
        impl crate::Resettable for EoiRenSpec {}
    }
    #[doc = "RAW_INTR_STAT (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr_stat`] module"]
    #[doc(alias = "RAW_INTR_STAT")]
    pub type RawIntrStat = crate::Reg<raw_intr_stat::RawIntrStatSpec>;
    #[doc = "Raw interrupt status"]
    pub mod raw_intr_stat {
        #[doc = "Register `RAW_INTR_STAT` reader"]
        pub type R = crate::R<RawIntrStatSpec>;
        #[doc = "Register `RAW_INTR_STAT` writer"]
        pub type W = crate::W<RawIntrStatSpec>;
        #[doc = "Field `raw_intr` reader - Raw interrupt status for all timers"]
        pub type RawIntrR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:2 - Raw interrupt status for all timers"]
            #[inline(always)]
            pub fn raw_intr(&self) -> RawIntrR {
                RawIntrR::new((self.bits & 7) as u8)
            }
        }
        impl W {}
        #[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RawIntrStatSpec;
        impl crate::RegisterSpec for RawIntrStatSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`raw_intr_stat::R`](R) reader structure"]
        impl crate::Readable for RawIntrStatSpec {}
        #[doc = "`write(|w| ..)` method takes [`raw_intr_stat::W`](W) writer structure"]
        impl crate::Writable for RawIntrStatSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RAW_INTR_STAT to value 0"]
        impl crate::Resettable for RawIntrStatSpec {}
    }
    #[doc = "INTR_STAT (rw) register accessor: Interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_stat`] module"]
    #[doc(alias = "INTR_STAT")]
    pub type IntrStat = crate::Reg<intr_stat::IntrStatSpec>;
    #[doc = "Interrupt status (masked)"]
    pub mod intr_stat {
        #[doc = "Register `INTR_STAT` reader"]
        pub type R = crate::R<IntrStatSpec>;
        #[doc = "Register `INTR_STAT` writer"]
        pub type W = crate::W<IntrStatSpec>;
        #[doc = "Field `intr_stat` reader - Interrupt status for all timers (after mask)"]
        pub type IntrStatR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:2 - Interrupt status for all timers (after mask)"]
            #[inline(always)]
            pub fn intr_stat(&self) -> IntrStatR {
                IntrStatR::new((self.bits & 7) as u8)
            }
        }
        impl W {}
        #[doc = "Interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IntrStatSpec;
        impl crate::RegisterSpec for IntrStatSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`intr_stat::R`](R) reader structure"]
        impl crate::Readable for IntrStatSpec {}
        #[doc = "`write(|w| ..)` method takes [`intr_stat::W`](W) writer structure"]
        impl crate::Writable for IntrStatSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets INTR_STAT to value 0"]
        impl crate::Resettable for IntrStatSpec {}
    }
    #[doc = "TIMER_LOAD_COUNT (rw) register accessor: Timer %s \\[dim=3\\] load count\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_load_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_load_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_load_count`] module"]
    #[doc(alias = "TIMER_LOAD_COUNT")]
    pub type TimerLoadCount = crate::Reg<timer_load_count::TimerLoadCountSpec>;
    #[doc = "Timer %s \\[dim=3\\] load count"]
    pub mod timer_load_count {
        #[doc = "Register `TIMER%s_LOAD_COUNT` reader"]
        pub type R = crate::R<TimerLoadCountSpec>;
        #[doc = "Register `TIMER%s_LOAD_COUNT` writer"]
        pub type W = crate::W<TimerLoadCountSpec>;
        #[doc = "Field `load_count` reader - Timer 0 load count value"]
        pub type LoadCountR = crate::FieldReader<u32>;
        #[doc = "Field `load_count` writer - Timer 0 load count value"]
        pub type LoadCountW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Timer 0 load count value"]
            #[inline(always)]
            pub fn load_count(&self) -> LoadCountR {
                LoadCountR::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Timer 0 load count value"]
            #[inline(always)]
            pub fn load_count(&mut self) -> LoadCountW<'_, TimerLoadCountSpec> {
                LoadCountW::new(self, 0)
            }
        }
        #[doc = "Timer %s \\[dim=3\\] load count\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_load_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_load_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TimerLoadCountSpec;
        impl crate::RegisterSpec for TimerLoadCountSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timer_load_count::R`](R) reader structure"]
        impl crate::Readable for TimerLoadCountSpec {}
        #[doc = "`write(|w| ..)` method takes [`timer_load_count::W`](W) writer structure"]
        impl crate::Writable for TimerLoadCountSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TIMER%s_LOAD_COUNT to value 0"]
        impl crate::Resettable for TimerLoadCountSpec {}
    }
    #[doc = "TIMER_CURRENT_VALUE (rw) register accessor: Timer %s \\[dim=3\\] current value\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_current_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_current_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_current_value`] module"]
    #[doc(alias = "TIMER_CURRENT_VALUE")]
    pub type TimerCurrentValue = crate::Reg<timer_current_value::TimerCurrentValueSpec>;
    #[doc = "Timer %s \\[dim=3\\] current value"]
    pub mod timer_current_value {
        #[doc = "Register `TIMER%s_CURRENT_VALUE` reader"]
        pub type R = crate::R<TimerCurrentValueSpec>;
        #[doc = "Register `TIMER%s_CURRENT_VALUE` writer"]
        pub type W = crate::W<TimerCurrentValueSpec>;
        #[doc = "Field `current_value` reader - Timer 0 current count value"]
        pub type CurrentValueR = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Timer 0 current count value"]
            #[inline(always)]
            pub fn current_value(&self) -> CurrentValueR {
                CurrentValueR::new(self.bits)
            }
        }
        impl W {}
        #[doc = "Timer %s \\[dim=3\\] current value\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_current_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_current_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TimerCurrentValueSpec;
        impl crate::RegisterSpec for TimerCurrentValueSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timer_current_value::R`](R) reader structure"]
        impl crate::Readable for TimerCurrentValueSpec {}
        #[doc = "`write(|w| ..)` method takes [`timer_current_value::W`](W) writer structure"]
        impl crate::Writable for TimerCurrentValueSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TIMER%s_CURRENT_VALUE to value 0"]
        impl crate::Resettable for TimerCurrentValueSpec {}
    }
    #[doc = "TIMER_CONTROL (rw) register accessor: Timer %s \\[dim=3\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_control`] module"]
    #[doc(alias = "TIMER_CONTROL")]
    pub type TimerControl = crate::Reg<timer_control::TimerControlSpec>;
    #[doc = "Timer %s \\[dim=3\\] control register"]
    pub mod timer_control {
        #[doc = "Register `TIMER%s_CONTROL` reader"]
        pub type R = crate::R<TimerControlSpec>;
        #[doc = "Register `TIMER%s_CONTROL` writer"]
        pub type W = crate::W<TimerControlSpec>;
        #[doc = "Field `enable` reader - Timer enable: 0=disabled; 1=enabled"]
        pub type EnableR = crate::BitReader;
        #[doc = "Field `enable` writer - Timer enable: 0=disabled; 1=enabled"]
        pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Timer mode: 00=free running; 01=one-shot; 10=periodic\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum Mode {
            #[doc = "0: Free-running mode"]
            FreeRunning = 0,
            #[doc = "1: One-shot mode"]
            OneShot = 1,
            #[doc = "2: Periodic mode"]
            Periodic = 2,
        }
        impl From<Mode> for u8 {
            #[inline(always)]
            fn from(variant: Mode) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for Mode {
            type Ux = u8;
        }
        impl crate::IsEnum for Mode {}
        #[doc = "Field `mode` reader - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
        pub type ModeR = crate::FieldReader<Mode>;
        impl ModeR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Option<Mode> {
                match self.bits {
                    0 => Some(Mode::FreeRunning),
                    1 => Some(Mode::OneShot),
                    2 => Some(Mode::Periodic),
                    _ => None,
                }
            }
            #[doc = "Free-running mode"]
            #[inline(always)]
            pub fn is_free_running(&self) -> bool {
                *self == Mode::FreeRunning
            }
            #[doc = "One-shot mode"]
            #[inline(always)]
            pub fn is_one_shot(&self) -> bool {
                *self == Mode::OneShot
            }
            #[doc = "Periodic mode"]
            #[inline(always)]
            pub fn is_periodic(&self) -> bool {
                *self == Mode::Periodic
            }
        }
        #[doc = "Field `mode` writer - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
        pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mode>;
        impl<'a, REG> ModeW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "Free-running mode"]
            #[inline(always)]
            pub fn free_running(self) -> &'a mut crate::W<REG> {
                self.variant(Mode::FreeRunning)
            }
            #[doc = "One-shot mode"]
            #[inline(always)]
            pub fn one_shot(self) -> &'a mut crate::W<REG> {
                self.variant(Mode::OneShot)
            }
            #[doc = "Periodic mode"]
            #[inline(always)]
            pub fn periodic(self) -> &'a mut crate::W<REG> {
                self.variant(Mode::Periodic)
            }
        }
        #[doc = "Field `int_mask` reader - Interrupt mask: 0=unmasked; 1=masked"]
        pub type IntMaskR = crate::BitReader;
        #[doc = "Field `int_mask` writer - Interrupt mask: 0=unmasked; 1=masked"]
        pub type IntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rstfsm` writer - Reset FSM: 1=reset timer FSM"]
        pub type RstfsmW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Timer enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn enable(&self) -> EnableR {
                EnableR::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 1:2 - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
            #[inline(always)]
            pub fn mode(&self) -> ModeR {
                ModeR::new(((self.bits >> 1) & 3) as u8)
            }
            #[doc = "Bit 3 - Interrupt mask: 0=unmasked; 1=masked"]
            #[inline(always)]
            pub fn int_mask(&self) -> IntMaskR {
                IntMaskR::new(((self.bits >> 3) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Timer enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn enable(&mut self) -> EnableW<'_, TimerControlSpec> {
                EnableW::new(self, 0)
            }
            #[doc = "Bits 1:2 - Timer mode: 00=free running; 01=one-shot; 10=periodic"]
            #[inline(always)]
            pub fn mode(&mut self) -> ModeW<'_, TimerControlSpec> {
                ModeW::new(self, 1)
            }
            #[doc = "Bit 3 - Interrupt mask: 0=unmasked; 1=masked"]
            #[inline(always)]
            pub fn int_mask(&mut self) -> IntMaskW<'_, TimerControlSpec> {
                IntMaskW::new(self, 3)
            }
            #[doc = "Bit 4 - Reset FSM: 1=reset timer FSM"]
            #[inline(always)]
            pub fn rstfsm(&mut self) -> RstfsmW<'_, TimerControlSpec> {
                RstfsmW::new(self, 4)
            }
        }
        #[doc = "Timer %s \\[dim=3\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TimerControlSpec;
        impl crate::RegisterSpec for TimerControlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timer_control::R`](R) reader structure"]
        impl crate::Readable for TimerControlSpec {}
        #[doc = "`write(|w| ..)` method takes [`timer_control::W`](W) writer structure"]
        impl crate::Writable for TimerControlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TIMER%s_CONTROL to value 0"]
        impl crate::Resettable for TimerControlSpec {}
    }
    #[doc = "TIMER_EOI (rw) register accessor: Timer %s \\[dim=3\\] end-of-interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_eoi`] module"]
    #[doc(alias = "TIMER_EOI")]
    pub type TimerEoi = crate::Reg<timer_eoi::TimerEoiSpec>;
    #[doc = "Timer %s \\[dim=3\\] end-of-interrupt"]
    pub mod timer_eoi {
        #[doc = "Register `TIMER%s_EOI` reader"]
        pub type R = crate::R<TimerEoiSpec>;
        #[doc = "Register `TIMER%s_EOI` writer"]
        pub type W = crate::W<TimerEoiSpec>;
        #[doc = "Field `eoi` reader - Read to clear timer 0 interrupt"]
        pub type EoiR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Read to clear timer 0 interrupt"]
            #[inline(always)]
            pub fn eoi(&self) -> EoiR {
                EoiR::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Timer %s \\[dim=3\\] end-of-interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TimerEoiSpec;
        impl crate::RegisterSpec for TimerEoiSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timer_eoi::R`](R) reader structure"]
        impl crate::Readable for TimerEoiSpec {}
        #[doc = "`write(|w| ..)` method takes [`timer_eoi::W`](W) writer structure"]
        impl crate::Writable for TimerEoiSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TIMER%s_EOI to value 0"]
        impl crate::Resettable for TimerEoiSpec {}
    }
    #[doc = "TIMER_RAW_INTR (rw) register accessor: Timer %s \\[dim=3\\] raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_raw_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_raw_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_raw_intr`] module"]
    #[doc(alias = "TIMER_RAW_INTR")]
    pub type TimerRawIntr = crate::Reg<timer_raw_intr::TimerRawIntrSpec>;
    #[doc = "Timer %s \\[dim=3\\] raw interrupt status"]
    pub mod timer_raw_intr {
        #[doc = "Register `TIMER%s_RAW_INTR` reader"]
        pub type R = crate::R<TimerRawIntrSpec>;
        #[doc = "Register `TIMER%s_RAW_INTR` writer"]
        pub type W = crate::W<TimerRawIntrSpec>;
        #[doc = "Field `raw_intr` reader - Raw interrupt status"]
        pub type RawIntrR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Raw interrupt status"]
            #[inline(always)]
            pub fn raw_intr(&self) -> RawIntrR {
                RawIntrR::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Timer %s \\[dim=3\\] raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_raw_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_raw_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TimerRawIntrSpec;
        impl crate::RegisterSpec for TimerRawIntrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timer_raw_intr::R`](R) reader structure"]
        impl crate::Readable for TimerRawIntrSpec {}
        #[doc = "`write(|w| ..)` method takes [`timer_raw_intr::W`](W) writer structure"]
        impl crate::Writable for TimerRawIntrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TIMER%s_RAW_INTR to value 0"]
        impl crate::Resettable for TimerRawIntrSpec {}
    }
}
#[doc = "Watchdog timer (v151)"]
pub type Wdt = crate::Periph<wdt::RegisterBlock, 0x5200_3000>;
impl core::fmt::Debug for Wdt {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Wdt").finish()
    }
}
#[doc = "Watchdog timer (v151)"]
pub mod wdt {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        wdt_lock: WdtLock,
        wdt_load: WdtLoad,
        wdt_restart: WdtRestart,
        wdt_eoi: WdtEoi,
        wdt_cr: WdtCr,
        wdt_cnt: WdtCnt,
        wdt_raw_intr: WdtRawIntr,
        wdt_intr: WdtIntr,
        wdt_lpif_state: WdtLpifState,
        wdt_status: WdtStatus,
        wdt_ccvr_en: WdtCcvrEn,
    }
    impl RegisterBlock {
        #[doc = "0x00 - Watchdog lock register"]
        #[inline(always)]
        pub const fn wdt_lock(&self) -> &WdtLock {
            &self.wdt_lock
        }
        #[doc = "0x04 - Watchdog load value"]
        #[inline(always)]
        pub const fn wdt_load(&self) -> &WdtLoad {
            &self.wdt_load
        }
        #[doc = "0x08 - Watchdog restart register"]
        #[inline(always)]
        pub const fn wdt_restart(&self) -> &WdtRestart {
            &self.wdt_restart
        }
        #[doc = "0x0c - Watchdog interrupt clear (read to clear)"]
        #[inline(always)]
        pub const fn wdt_eoi(&self) -> &WdtEoi {
            &self.wdt_eoi
        }
        #[doc = "0x10 - Watchdog control register"]
        #[inline(always)]
        pub const fn wdt_cr(&self) -> &WdtCr {
            &self.wdt_cr
        }
        #[doc = "0x14 - Watchdog current counter value"]
        #[inline(always)]
        pub const fn wdt_cnt(&self) -> &WdtCnt {
            &self.wdt_cnt
        }
        #[doc = "0x18 - Watchdog raw interrupt status"]
        #[inline(always)]
        pub const fn wdt_raw_intr(&self) -> &WdtRawIntr {
            &self.wdt_raw_intr
        }
        #[doc = "0x1c - Watchdog interrupt status (masked)"]
        #[inline(always)]
        pub const fn wdt_intr(&self) -> &WdtIntr {
            &self.wdt_intr
        }
        #[doc = "0x20 - Watchdog low power state"]
        #[inline(always)]
        pub const fn wdt_lpif_state(&self) -> &WdtLpifState {
            &self.wdt_lpif_state
        }
        #[doc = "0x24 - Watchdog status"]
        #[inline(always)]
        pub const fn wdt_status(&self) -> &WdtStatus {
            &self.wdt_status
        }
        #[doc = "0x28 - Watchdog counter value request"]
        #[inline(always)]
        pub const fn wdt_ccvr_en(&self) -> &WdtCcvrEn {
            &self.wdt_ccvr_en
        }
    }
    #[doc = "WDT_LOCK (rw) register accessor: Watchdog lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_lock`] module"]
    #[doc(alias = "WDT_LOCK")]
    pub type WdtLock = crate::Reg<wdt_lock::WdtLockSpec>;
    #[doc = "Watchdog lock register"]
    pub mod wdt_lock {
        #[doc = "Register `WDT_LOCK` reader"]
        pub type R = crate::R<WdtLockSpec>;
        #[doc = "Register `WDT_LOCK` writer"]
        pub type W = crate::W<WdtLockSpec>;
        #[doc = "Field `wdt_lock` writer - Write 0x5A5A5A5A to unlock, other values lock"]
        pub type WdtLockW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - Write 0x5A5A5A5A to unlock, other values lock"]
            #[inline(always)]
            pub fn wdt_lock(&mut self) -> WdtLockW<'_, WdtLockSpec> {
                WdtLockW::new(self, 0)
            }
        }
        #[doc = "Watchdog lock register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtLockSpec;
        impl crate::RegisterSpec for WdtLockSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_lock::R`](R) reader structure"]
        impl crate::Readable for WdtLockSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_lock::W`](W) writer structure"]
        impl crate::Writable for WdtLockSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_LOCK to value 0"]
        impl crate::Resettable for WdtLockSpec {}
    }
    #[doc = "WDT_LOAD (rw) register accessor: Watchdog load value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_load::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_load::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_load`] module"]
    #[doc(alias = "WDT_LOAD")]
    pub type WdtLoad = crate::Reg<wdt_load::WdtLoadSpec>;
    #[doc = "Watchdog load value"]
    pub mod wdt_load {
        #[doc = "Register `WDT_LOAD` reader"]
        pub type R = crate::R<WdtLoadSpec>;
        #[doc = "Register `WDT_LOAD` writer"]
        pub type W = crate::W<WdtLoadSpec>;
        #[doc = "Field `wdt_load` reader - Load count value (24-bit, low 8 bits reserved)"]
        pub type WdtLoadR = crate::FieldReader<u32>;
        #[doc = "Field `wdt_load` writer - Load count value (24-bit, low 8 bits reserved)"]
        pub type WdtLoadW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bits 8:31 - Load count value (24-bit, low 8 bits reserved)"]
            #[inline(always)]
            pub fn wdt_load(&self) -> WdtLoadR {
                WdtLoadR::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 8:31 - Load count value (24-bit, low 8 bits reserved)"]
            #[inline(always)]
            pub fn wdt_load(&mut self) -> WdtLoadW<'_, WdtLoadSpec> {
                WdtLoadW::new(self, 8)
            }
        }
        #[doc = "Watchdog load value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_load::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_load::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtLoadSpec;
        impl crate::RegisterSpec for WdtLoadSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_load::R`](R) reader structure"]
        impl crate::Readable for WdtLoadSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_load::W`](W) writer structure"]
        impl crate::Writable for WdtLoadSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_LOAD to value 0"]
        impl crate::Resettable for WdtLoadSpec {}
    }
    #[doc = "WDT_RESTART (rw) register accessor: Watchdog restart register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_restart::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_restart::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_restart`] module"]
    #[doc(alias = "WDT_RESTART")]
    pub type WdtRestart = crate::Reg<wdt_restart::WdtRestartSpec>;
    #[doc = "Watchdog restart register"]
    pub mod wdt_restart {
        #[doc = "Register `WDT_RESTART` reader"]
        pub type R = crate::R<WdtRestartSpec>;
        #[doc = "Register `WDT_RESTART` writer"]
        pub type W = crate::W<WdtRestartSpec>;
        #[doc = "Field `wdt_restart` writer - Write anything except 0x5A5A5A5A to restart counter"]
        pub type WdtRestartW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - Write anything except 0x5A5A5A5A to restart counter"]
            #[inline(always)]
            pub fn wdt_restart(&mut self) -> WdtRestartW<'_, WdtRestartSpec> {
                WdtRestartW::new(self, 0)
            }
        }
        #[doc = "Watchdog restart register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_restart::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_restart::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtRestartSpec;
        impl crate::RegisterSpec for WdtRestartSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_restart::R`](R) reader structure"]
        impl crate::Readable for WdtRestartSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_restart::W`](W) writer structure"]
        impl crate::Writable for WdtRestartSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_RESTART to value 0"]
        impl crate::Resettable for WdtRestartSpec {}
    }
    #[doc = "WDT_EOI (rw) register accessor: Watchdog interrupt clear (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_eoi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_eoi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_eoi`] module"]
    #[doc(alias = "WDT_EOI")]
    pub type WdtEoi = crate::Reg<wdt_eoi::WdtEoiSpec>;
    #[doc = "Watchdog interrupt clear (read to clear)"]
    pub mod wdt_eoi {
        #[doc = "Register `WDT_EOI` reader"]
        pub type R = crate::R<WdtEoiSpec>;
        #[doc = "Register `WDT_EOI` writer"]
        pub type W = crate::W<WdtEoiSpec>;
        #[doc = "Field `wdt_eoi` reader - Read to clear watchdog interrupt"]
        pub type WdtEoiR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Read to clear watchdog interrupt"]
            #[inline(always)]
            pub fn wdt_eoi(&self) -> WdtEoiR {
                WdtEoiR::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Watchdog interrupt clear (read to clear)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_eoi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_eoi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtEoiSpec;
        impl crate::RegisterSpec for WdtEoiSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_eoi::R`](R) reader structure"]
        impl crate::Readable for WdtEoiSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_eoi::W`](W) writer structure"]
        impl crate::Writable for WdtEoiSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_EOI to value 0"]
        impl crate::Resettable for WdtEoiSpec {}
    }
    #[doc = "WDT_CR (rw) register accessor: Watchdog control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cr`] module"]
    #[doc(alias = "WDT_CR")]
    pub type WdtCr = crate::Reg<wdt_cr::WdtCrSpec>;
    #[doc = "Watchdog control register"]
    pub mod wdt_cr {
        #[doc = "Register `WDT_CR` reader"]
        pub type R = crate::R<WdtCrSpec>;
        #[doc = "Register `WDT_CR` writer"]
        pub type W = crate::W<WdtCrSpec>;
        #[doc = "Field `wdt_en` reader - Watchdog enable: 0=disabled; 1=enabled"]
        pub type WdtEnR = crate::BitReader;
        #[doc = "Field `wdt_en` writer - Watchdog enable: 0=disabled; 1=enabled"]
        pub type WdtEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rst_en` reader - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
        pub type RstEnR = crate::BitReader;
        #[doc = "Field `rst_en` writer - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
        pub type RstEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rst_pl` reader - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
        pub type RstPlR = crate::FieldReader;
        #[doc = "Field `rst_pl` writer - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
        pub type RstPlW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `wdt_imsk` reader - Interrupt mask: 0=unmasked; 1=masked"]
        pub type WdtImskR = crate::BitReader;
        #[doc = "Field `wdt_imsk` writer - Interrupt mask: 0=unmasked; 1=masked"]
        pub type WdtImskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Mode: 0=one interrupt then reset; 1=two interrupts then reset\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum WdtMode {
            #[doc = "0: Single interrupt then reset"]
            Mode1 = 0,
            #[doc = "1: Two interrupts then reset"]
            Mode2 = 1,
        }
        impl From<WdtMode> for bool {
            #[inline(always)]
            fn from(variant: WdtMode) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `wdt_mode` reader - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
        pub type WdtModeR = crate::BitReader<WdtMode>;
        impl WdtModeR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> WdtMode {
                match self.bits {
                    false => WdtMode::Mode1,
                    true => WdtMode::Mode2,
                }
            }
            #[doc = "Single interrupt then reset"]
            #[inline(always)]
            pub fn is_mode1(&self) -> bool {
                *self == WdtMode::Mode1
            }
            #[doc = "Two interrupts then reset"]
            #[inline(always)]
            pub fn is_mode2(&self) -> bool {
                *self == WdtMode::Mode2
            }
        }
        #[doc = "Field `wdt_mode` writer - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
        pub type WdtModeW<'a, REG> = crate::BitWriter<'a, REG, WdtMode>;
        impl<'a, REG> WdtModeW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Single interrupt then reset"]
            #[inline(always)]
            pub fn mode1(self) -> &'a mut crate::W<REG> {
                self.variant(WdtMode::Mode1)
            }
            #[doc = "Two interrupts then reset"]
            #[inline(always)]
            pub fn mode2(self) -> &'a mut crate::W<REG> {
                self.variant(WdtMode::Mode2)
            }
        }
        impl R {
            #[doc = "Bit 0 - Watchdog enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn wdt_en(&self) -> WdtEnR {
                WdtEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 2 - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
            #[inline(always)]
            pub fn rst_en(&self) -> RstEnR {
                RstEnR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bits 3:5 - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
            #[inline(always)]
            pub fn rst_pl(&self) -> RstPlR {
                RstPlR::new(((self.bits >> 3) & 7) as u8)
            }
            #[doc = "Bit 6 - Interrupt mask: 0=unmasked; 1=masked"]
            #[inline(always)]
            pub fn wdt_imsk(&self) -> WdtImskR {
                WdtImskR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
            #[inline(always)]
            pub fn wdt_mode(&self) -> WdtModeR {
                WdtModeR::new(((self.bits >> 7) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Watchdog enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn wdt_en(&mut self) -> WdtEnW<'_, WdtCrSpec> {
                WdtEnW::new(self, 0)
            }
            #[doc = "Bit 2 - Reset enable: 0=no reset on timeout; 1=reset on timeout"]
            #[inline(always)]
            pub fn rst_en(&mut self) -> RstEnW<'_, WdtCrSpec> {
                RstEnW::new(self, 2)
            }
            #[doc = "Bits 3:5 - Reset pulse length: 000=2 clocks; up to 111=256 clocks"]
            #[inline(always)]
            pub fn rst_pl(&mut self) -> RstPlW<'_, WdtCrSpec> {
                RstPlW::new(self, 3)
            }
            #[doc = "Bit 6 - Interrupt mask: 0=unmasked; 1=masked"]
            #[inline(always)]
            pub fn wdt_imsk(&mut self) -> WdtImskW<'_, WdtCrSpec> {
                WdtImskW::new(self, 6)
            }
            #[doc = "Bit 7 - Mode: 0=one interrupt then reset; 1=two interrupts then reset"]
            #[inline(always)]
            pub fn wdt_mode(&mut self) -> WdtModeW<'_, WdtCrSpec> {
                WdtModeW::new(self, 7)
            }
        }
        #[doc = "Watchdog control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtCrSpec;
        impl crate::RegisterSpec for WdtCrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_cr::R`](R) reader structure"]
        impl crate::Readable for WdtCrSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_cr::W`](W) writer structure"]
        impl crate::Writable for WdtCrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_CR to value 0"]
        impl crate::Resettable for WdtCrSpec {}
    }
    #[doc = "WDT_CNT (rw) register accessor: Watchdog current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_cnt`] module"]
    #[doc(alias = "WDT_CNT")]
    pub type WdtCnt = crate::Reg<wdt_cnt::WdtCntSpec>;
    #[doc = "Watchdog current counter value"]
    pub mod wdt_cnt {
        #[doc = "Register `WDT_CNT` reader"]
        pub type R = crate::R<WdtCntSpec>;
        #[doc = "Register `WDT_CNT` writer"]
        pub type W = crate::W<WdtCntSpec>;
        #[doc = "Field `wdt_cnt` reader - Current counter value"]
        pub type WdtCntR = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Current counter value"]
            #[inline(always)]
            pub fn wdt_cnt(&self) -> WdtCntR {
                WdtCntR::new(self.bits)
            }
        }
        impl W {}
        #[doc = "Watchdog current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtCntSpec;
        impl crate::RegisterSpec for WdtCntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_cnt::R`](R) reader structure"]
        impl crate::Readable for WdtCntSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_cnt::W`](W) writer structure"]
        impl crate::Writable for WdtCntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_CNT to value 0"]
        impl crate::Resettable for WdtCntSpec {}
    }
    #[doc = "WDT_RAW_INTR (rw) register accessor: Watchdog raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_raw_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_raw_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_raw_intr`] module"]
    #[doc(alias = "WDT_RAW_INTR")]
    pub type WdtRawIntr = crate::Reg<wdt_raw_intr::WdtRawIntrSpec>;
    #[doc = "Watchdog raw interrupt status"]
    pub mod wdt_raw_intr {
        #[doc = "Register `WDT_RAW_INTR` reader"]
        pub type R = crate::R<WdtRawIntrSpec>;
        #[doc = "Register `WDT_RAW_INTR` writer"]
        pub type W = crate::W<WdtRawIntrSpec>;
        #[doc = "Field `wdt_raw_intr` reader - Raw interrupt status"]
        pub type WdtRawIntrR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Raw interrupt status"]
            #[inline(always)]
            pub fn wdt_raw_intr(&self) -> WdtRawIntrR {
                WdtRawIntrR::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Watchdog raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_raw_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_raw_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtRawIntrSpec;
        impl crate::RegisterSpec for WdtRawIntrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_raw_intr::R`](R) reader structure"]
        impl crate::Readable for WdtRawIntrSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_raw_intr::W`](W) writer structure"]
        impl crate::Writable for WdtRawIntrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_RAW_INTR to value 0"]
        impl crate::Resettable for WdtRawIntrSpec {}
    }
    #[doc = "WDT_INTR (rw) register accessor: Watchdog interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_intr`] module"]
    #[doc(alias = "WDT_INTR")]
    pub type WdtIntr = crate::Reg<wdt_intr::WdtIntrSpec>;
    #[doc = "Watchdog interrupt status (masked)"]
    pub mod wdt_intr {
        #[doc = "Register `WDT_INTR` reader"]
        pub type R = crate::R<WdtIntrSpec>;
        #[doc = "Register `WDT_INTR` writer"]
        pub type W = crate::W<WdtIntrSpec>;
        #[doc = "Field `wdt_intr` reader - Interrupt status after mask"]
        pub type WdtIntrR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Interrupt status after mask"]
            #[inline(always)]
            pub fn wdt_intr(&self) -> WdtIntrR {
                WdtIntrR::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Watchdog interrupt status (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtIntrSpec;
        impl crate::RegisterSpec for WdtIntrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_intr::R`](R) reader structure"]
        impl crate::Readable for WdtIntrSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_intr::W`](W) writer structure"]
        impl crate::Writable for WdtIntrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_INTR to value 0"]
        impl crate::Resettable for WdtIntrSpec {}
    }
    #[doc = "WDT_LPIF_STATE (rw) register accessor: Watchdog low power state\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lpif_state::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lpif_state::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_lpif_state`] module"]
    #[doc(alias = "WDT_LPIF_STATE")]
    pub type WdtLpifState = crate::Reg<wdt_lpif_state::WdtLpifStateSpec>;
    #[doc = "Watchdog low power state"]
    pub mod wdt_lpif_state {
        #[doc = "Register `WDT_LPIF_STATE` reader"]
        pub type R = crate::R<WdtLpifStateSpec>;
        #[doc = "Register `WDT_LPIF_STATE` writer"]
        pub type W = crate::W<WdtLpifStateSpec>;
        #[doc = "Field `wdt_lpif_state` reader - Low power interface state"]
        pub type WdtLpifStateR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:2 - Low power interface state"]
            #[inline(always)]
            pub fn wdt_lpif_state(&self) -> WdtLpifStateR {
                WdtLpifStateR::new((self.bits & 7) as u8)
            }
        }
        impl W {}
        #[doc = "Watchdog low power state\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_lpif_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_lpif_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtLpifStateSpec;
        impl crate::RegisterSpec for WdtLpifStateSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_lpif_state::R`](R) reader structure"]
        impl crate::Readable for WdtLpifStateSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_lpif_state::W`](W) writer structure"]
        impl crate::Writable for WdtLpifStateSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_LPIF_STATE to value 0"]
        impl crate::Resettable for WdtLpifStateSpec {}
    }
    #[doc = "WDT_STATUS (rw) register accessor: Watchdog status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_status`] module"]
    #[doc(alias = "WDT_STATUS")]
    pub type WdtStatus = crate::Reg<wdt_status::WdtStatusSpec>;
    #[doc = "Watchdog status"]
    pub mod wdt_status {
        #[doc = "Register `WDT_STATUS` reader"]
        pub type R = crate::R<WdtStatusSpec>;
        #[doc = "Register `WDT_STATUS` writer"]
        pub type W = crate::W<WdtStatusSpec>;
        #[doc = "Field `wdt_status` reader - Status: 0=busy; 1=free"]
        pub type WdtStatusR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Status: 0=busy; 1=free"]
            #[inline(always)]
            pub fn wdt_status(&self) -> WdtStatusR {
                WdtStatusR::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Watchdog status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtStatusSpec;
        impl crate::RegisterSpec for WdtStatusSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_status::R`](R) reader structure"]
        impl crate::Readable for WdtStatusSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_status::W`](W) writer structure"]
        impl crate::Writable for WdtStatusSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_STATUS to value 0"]
        impl crate::Resettable for WdtStatusSpec {}
    }
    #[doc = "WDT_CCVR_EN (rw) register accessor: Watchdog counter value request\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_ccvr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_ccvr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_ccvr_en`] module"]
    #[doc(alias = "WDT_CCVR_EN")]
    pub type WdtCcvrEn = crate::Reg<wdt_ccvr_en::WdtCcvrEnSpec>;
    #[doc = "Watchdog counter value request"]
    pub mod wdt_ccvr_en {
        #[doc = "Register `WDT_CCVR_EN` reader"]
        pub type R = crate::R<WdtCcvrEnSpec>;
        #[doc = "Register `WDT_CCVR_EN` writer"]
        pub type W = crate::W<WdtCcvrEnSpec>;
        #[doc = "Field `ccvr_req` writer - Write 1 to request current counter value"]
        pub type CcvrReqW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ccvr_ack` reader - Acknowledge: 1=counter value valid"]
        pub type CcvrAckR = crate::BitReader;
        impl R {
            #[doc = "Bit 1 - Acknowledge: 1=counter value valid"]
            #[inline(always)]
            pub fn ccvr_ack(&self) -> CcvrAckR {
                CcvrAckR::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Write 1 to request current counter value"]
            #[inline(always)]
            pub fn ccvr_req(&mut self) -> CcvrReqW<'_, WdtCcvrEnSpec> {
                CcvrReqW::new(self, 0)
            }
        }
        #[doc = "Watchdog counter value request\n\nYou can [`read`](crate::Reg::read) this register and get [`wdt_ccvr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdt_ccvr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WdtCcvrEnSpec;
        impl crate::RegisterSpec for WdtCcvrEnSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_ccvr_en::R`](R) reader structure"]
        impl crate::Readable for WdtCcvrEnSpec {}
        #[doc = "`write(|w| ..)` method takes [`wdt_ccvr_en::W`](W) writer structure"]
        impl crate::Writable for WdtCcvrEnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets WDT_CCVR_EN to value 0"]
        impl crate::Resettable for WdtCcvrEnSpec {}
    }
}
#[doc = "TCXO 64-bit free-running counter (v150)"]
pub type Tcxo = crate::Periph<tcxo::RegisterBlock, 0x5700_0200>;
impl core::fmt::Debug for Tcxo {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tcxo").finish()
    }
}
#[doc = "TCXO 64-bit free-running counter (v150)"]
pub mod tcxo {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        tcxo_status: TcxoStatus,
        tcxo_count0: TcxoCount0,
        tcxo_count1: TcxoCount1,
        tcxo_count2: TcxoCount2,
        tcxo_count3: TcxoCount3,
    }
    impl RegisterBlock {
        #[doc = "0x00 - TCXO status and control register"]
        #[inline(always)]
        pub const fn tcxo_status(&self) -> &TcxoStatus {
            &self.tcxo_status
        }
        #[doc = "0x04 - TCXO count bits \\[15:0\\]"]
        #[inline(always)]
        pub const fn tcxo_count0(&self) -> &TcxoCount0 {
            &self.tcxo_count0
        }
        #[doc = "0x08 - TCXO count bits \\[31:16\\]"]
        #[inline(always)]
        pub const fn tcxo_count1(&self) -> &TcxoCount1 {
            &self.tcxo_count1
        }
        #[doc = "0x0c - TCXO count bits \\[47:32\\]"]
        #[inline(always)]
        pub const fn tcxo_count2(&self) -> &TcxoCount2 {
            &self.tcxo_count2
        }
        #[doc = "0x10 - TCXO count bits \\[63:48\\]"]
        #[inline(always)]
        pub const fn tcxo_count3(&self) -> &TcxoCount3 {
            &self.tcxo_count3
        }
    }
    #[doc = "TCXO_STATUS (rw) register accessor: TCXO status and control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_status`] module"]
    #[doc(alias = "TCXO_STATUS")]
    pub type TcxoStatus = crate::Reg<tcxo_status::TcxoStatusSpec>;
    #[doc = "TCXO status and control register"]
    pub mod tcxo_status {
        #[doc = "Register `TCXO_STATUS` reader"]
        pub type R = crate::R<TcxoStatusSpec>;
        #[doc = "Register `TCXO_STATUS` writer"]
        pub type W = crate::W<TcxoStatusSpec>;
        #[doc = "Field `refresh` reader - TCXO count refresh: 1=trigger count latch"]
        pub type RefreshR = crate::BitReader;
        #[doc = "Field `refresh` writer - TCXO count refresh: 1=trigger count latch"]
        pub type RefreshW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `clear` reader - TCXO count clear: 1=clear counter"]
        pub type ClearR = crate::BitReader;
        #[doc = "Field `clear` writer - TCXO count clear: 1=clear counter"]
        pub type ClearW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `enable` reader - TCXO count enable: 1=enable counting"]
        pub type EnableR = crate::BitReader;
        #[doc = "Field `enable` writer - TCXO count enable: 1=enable counting"]
        pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `valid` reader - TCXO count value valid flag"]
        pub type ValidR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - TCXO count refresh: 1=trigger count latch"]
            #[inline(always)]
            pub fn refresh(&self) -> RefreshR {
                RefreshR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TCXO count clear: 1=clear counter"]
            #[inline(always)]
            pub fn clear(&self) -> ClearR {
                ClearR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - TCXO count enable: 1=enable counting"]
            #[inline(always)]
            pub fn enable(&self) -> EnableR {
                EnableR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 4 - TCXO count value valid flag"]
            #[inline(always)]
            pub fn valid(&self) -> ValidR {
                ValidR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - TCXO count refresh: 1=trigger count latch"]
            #[inline(always)]
            pub fn refresh(&mut self) -> RefreshW<'_, TcxoStatusSpec> {
                RefreshW::new(self, 0)
            }
            #[doc = "Bit 1 - TCXO count clear: 1=clear counter"]
            #[inline(always)]
            pub fn clear(&mut self) -> ClearW<'_, TcxoStatusSpec> {
                ClearW::new(self, 1)
            }
            #[doc = "Bit 2 - TCXO count enable: 1=enable counting"]
            #[inline(always)]
            pub fn enable(&mut self) -> EnableW<'_, TcxoStatusSpec> {
                EnableW::new(self, 2)
            }
        }
        #[doc = "TCXO status and control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TcxoStatusSpec;
        impl crate::RegisterSpec for TcxoStatusSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tcxo_status::R`](R) reader structure"]
        impl crate::Readable for TcxoStatusSpec {}
        #[doc = "`write(|w| ..)` method takes [`tcxo_status::W`](W) writer structure"]
        impl crate::Writable for TcxoStatusSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TCXO_STATUS to value 0"]
        impl crate::Resettable for TcxoStatusSpec {}
    }
    #[doc = "TCXO_COUNT0 (rw) register accessor: TCXO count bits \\[15:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count0`] module"]
    #[doc(alias = "TCXO_COUNT0")]
    pub type TcxoCount0 = crate::Reg<tcxo_count0::TcxoCount0Spec>;
    #[doc = "TCXO count bits \\[15:0\\]"]
    pub mod tcxo_count0 {
        #[doc = "Register `TCXO_COUNT0` reader"]
        pub type R = crate::R<TcxoCount0Spec>;
        #[doc = "Register `TCXO_COUNT0` writer"]
        pub type W = crate::W<TcxoCount0Spec>;
        #[doc = "Field `count0` reader - Counter value bits \\[15:0\\]"]
        pub type Count0R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Counter value bits \\[15:0\\]"]
            #[inline(always)]
            pub fn count0(&self) -> Count0R {
                Count0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "TCXO count bits \\[15:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TcxoCount0Spec;
        impl crate::RegisterSpec for TcxoCount0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tcxo_count0::R`](R) reader structure"]
        impl crate::Readable for TcxoCount0Spec {}
        #[doc = "`write(|w| ..)` method takes [`tcxo_count0::W`](W) writer structure"]
        impl crate::Writable for TcxoCount0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TCXO_COUNT0 to value 0"]
        impl crate::Resettable for TcxoCount0Spec {}
    }
    #[doc = "TCXO_COUNT1 (rw) register accessor: TCXO count bits \\[31:16\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count1`] module"]
    #[doc(alias = "TCXO_COUNT1")]
    pub type TcxoCount1 = crate::Reg<tcxo_count1::TcxoCount1Spec>;
    #[doc = "TCXO count bits \\[31:16\\]"]
    pub mod tcxo_count1 {
        #[doc = "Register `TCXO_COUNT1` reader"]
        pub type R = crate::R<TcxoCount1Spec>;
        #[doc = "Register `TCXO_COUNT1` writer"]
        pub type W = crate::W<TcxoCount1Spec>;
        #[doc = "Field `count1` reader - Counter value bits \\[31:16\\]"]
        pub type Count1R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Counter value bits \\[31:16\\]"]
            #[inline(always)]
            pub fn count1(&self) -> Count1R {
                Count1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "TCXO count bits \\[31:16\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TcxoCount1Spec;
        impl crate::RegisterSpec for TcxoCount1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tcxo_count1::R`](R) reader structure"]
        impl crate::Readable for TcxoCount1Spec {}
        #[doc = "`write(|w| ..)` method takes [`tcxo_count1::W`](W) writer structure"]
        impl crate::Writable for TcxoCount1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TCXO_COUNT1 to value 0"]
        impl crate::Resettable for TcxoCount1Spec {}
    }
    #[doc = "TCXO_COUNT2 (rw) register accessor: TCXO count bits \\[47:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count2`] module"]
    #[doc(alias = "TCXO_COUNT2")]
    pub type TcxoCount2 = crate::Reg<tcxo_count2::TcxoCount2Spec>;
    #[doc = "TCXO count bits \\[47:32\\]"]
    pub mod tcxo_count2 {
        #[doc = "Register `TCXO_COUNT2` reader"]
        pub type R = crate::R<TcxoCount2Spec>;
        #[doc = "Register `TCXO_COUNT2` writer"]
        pub type W = crate::W<TcxoCount2Spec>;
        #[doc = "Field `count2` reader - Counter value bits \\[47:32\\]"]
        pub type Count2R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Counter value bits \\[47:32\\]"]
            #[inline(always)]
            pub fn count2(&self) -> Count2R {
                Count2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "TCXO count bits \\[47:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TcxoCount2Spec;
        impl crate::RegisterSpec for TcxoCount2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tcxo_count2::R`](R) reader structure"]
        impl crate::Readable for TcxoCount2Spec {}
        #[doc = "`write(|w| ..)` method takes [`tcxo_count2::W`](W) writer structure"]
        impl crate::Writable for TcxoCount2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TCXO_COUNT2 to value 0"]
        impl crate::Resettable for TcxoCount2Spec {}
    }
    #[doc = "TCXO_COUNT3 (rw) register accessor: TCXO count bits \\[63:48\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcxo_count3`] module"]
    #[doc(alias = "TCXO_COUNT3")]
    pub type TcxoCount3 = crate::Reg<tcxo_count3::TcxoCount3Spec>;
    #[doc = "TCXO count bits \\[63:48\\]"]
    pub mod tcxo_count3 {
        #[doc = "Register `TCXO_COUNT3` reader"]
        pub type R = crate::R<TcxoCount3Spec>;
        #[doc = "Register `TCXO_COUNT3` writer"]
        pub type W = crate::W<TcxoCount3Spec>;
        #[doc = "Field `count3` reader - Counter value bits \\[63:48\\]"]
        pub type Count3R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Counter value bits \\[63:48\\]"]
            #[inline(always)]
            pub fn count3(&self) -> Count3R {
                Count3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "TCXO count bits \\[63:48\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`tcxo_count3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcxo_count3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TcxoCount3Spec;
        impl crate::RegisterSpec for TcxoCount3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tcxo_count3::R`](R) reader structure"]
        impl crate::Readable for TcxoCount3Spec {}
        #[doc = "`write(|w| ..)` method takes [`tcxo_count3::W`](W) writer structure"]
        impl crate::Writable for TcxoCount3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TCXO_COUNT3 to value 0"]
        impl crate::Resettable for TcxoCount3Spec {}
    }
}
#[doc = "I2C0 master controller (DesignWare SSI, IP v151)"]
pub type I2c0 = crate::Periph<i2c0::RegisterBlock, 0x5208_3000>;
impl core::fmt::Debug for I2c0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2c0").finish()
    }
}
#[doc = "I2C0 master controller (DesignWare SSI, IP v151)"]
pub mod i2c0 {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        ic_con: IcCon,
        ic_enable: IcEnable,
        _reserved2: [u8; 0x08],
        ic_tar: IcTar,
        ic_sar: IcSar,
        ic_hs_maddr: IcHsMaddr,
        ic_data_cmd: IcDataCmd,
        _reserved6: [u8; 0x10],
        ic_ss_scl_hcnt: IcSsSclHcnt,
        ic_ss_scl_lcnt: IcSsSclLcnt,
        _reserved8: [u8; 0x04],
        ic_fs_scl_hcnt: IcFsSclHcnt,
        ic_fs_scl_lcnt: IcFsSclLcnt,
        ic_hs_scl_hcnt: IcHsSclHcnt,
        ic_hs_scl_lcnt: IcHsSclLcnt,
        _reserved12: [u8; 0x04],
        ic_rx_tl: IcRxTl,
        ic_tx_tl: IcTxTl,
        ic_slv_data_nack_only: IcSlvDataNackOnly,
        _reserved15: [u8; 0x04],
        ic_status: IcStatus,
        ic_txflr: IcTxflr,
        ic_rxflr: IcRxflr,
        ic_sda_hold: IcSdaHold,
        ic_sda_hold_tx: IcSdaHoldTx,
        ic_tx_flush_cnt: IcTxFlushCnt,
        ic_tx_abrt_source: IcTxAbrtSource,
        ic_tx_abrt_slv_intx: IcTxAbrtSlvIntx,
        ic_ack_general_call: IcAckGeneralCall,
        ic_enable_status: IcEnableStatus,
        _reserved25: [u8; 0x18],
        ic_dma_cr: IcDmaCr,
        ic_dma_tdlr: IcDmaTdlr,
        ic_dma_rdlr: IcDmaRdlr,
        ic_sda_setup: IcSdaSetup,
        ic_intr_mask: IcIntrMask,
        ic_intr_stat: IcIntrStat,
        ic_raw_intr_stat: IcRawIntrStat,
        ic_intr_stat_all: IcIntrStatAll,
        ic_clr_intr: IcClrIntr,
        ic_clr_int: IcClrInt,
    }
    impl RegisterBlock {
        #[doc = "0x00 - IC_CON"]
        #[inline(always)]
        pub const fn ic_con(&self) -> &IcCon {
            &self.ic_con
        }
        #[doc = "0x04 - IC_ENABLE"]
        #[inline(always)]
        pub const fn ic_enable(&self) -> &IcEnable {
            &self.ic_enable
        }
        #[doc = "0x10 - IC_TAR"]
        #[inline(always)]
        pub const fn ic_tar(&self) -> &IcTar {
            &self.ic_tar
        }
        #[doc = "0x14 - IC_SAR"]
        #[inline(always)]
        pub const fn ic_sar(&self) -> &IcSar {
            &self.ic_sar
        }
        #[doc = "0x18 - IC_HS_MADDR"]
        #[inline(always)]
        pub const fn ic_hs_maddr(&self) -> &IcHsMaddr {
            &self.ic_hs_maddr
        }
        #[doc = "0x1c - IC_DATA_CMD"]
        #[inline(always)]
        pub const fn ic_data_cmd(&self) -> &IcDataCmd {
            &self.ic_data_cmd
        }
        #[doc = "0x30 - IC_SS_SCL_HCNT"]
        #[inline(always)]
        pub const fn ic_ss_scl_hcnt(&self) -> &IcSsSclHcnt {
            &self.ic_ss_scl_hcnt
        }
        #[doc = "0x34 - IC_SS_SCL_LCNT"]
        #[inline(always)]
        pub const fn ic_ss_scl_lcnt(&self) -> &IcSsSclLcnt {
            &self.ic_ss_scl_lcnt
        }
        #[doc = "0x3c - IC_FS_SCL_HCNT"]
        #[inline(always)]
        pub const fn ic_fs_scl_hcnt(&self) -> &IcFsSclHcnt {
            &self.ic_fs_scl_hcnt
        }
        #[doc = "0x40 - IC_FS_SCL_LCNT"]
        #[inline(always)]
        pub const fn ic_fs_scl_lcnt(&self) -> &IcFsSclLcnt {
            &self.ic_fs_scl_lcnt
        }
        #[doc = "0x44 - IC_HS_SCL_HCNT"]
        #[inline(always)]
        pub const fn ic_hs_scl_hcnt(&self) -> &IcHsSclHcnt {
            &self.ic_hs_scl_hcnt
        }
        #[doc = "0x48 - IC_HS_SCL_LCNT"]
        #[inline(always)]
        pub const fn ic_hs_scl_lcnt(&self) -> &IcHsSclLcnt {
            &self.ic_hs_scl_lcnt
        }
        #[doc = "0x50 - IC_RX_TL"]
        #[inline(always)]
        pub const fn ic_rx_tl(&self) -> &IcRxTl {
            &self.ic_rx_tl
        }
        #[doc = "0x54 - IC_TX_TL"]
        #[inline(always)]
        pub const fn ic_tx_tl(&self) -> &IcTxTl {
            &self.ic_tx_tl
        }
        #[doc = "0x58 - IC_SLV_DATA_NACK_ONLY"]
        #[inline(always)]
        pub const fn ic_slv_data_nack_only(&self) -> &IcSlvDataNackOnly {
            &self.ic_slv_data_nack_only
        }
        #[doc = "0x60 - IC_STATUS"]
        #[inline(always)]
        pub const fn ic_status(&self) -> &IcStatus {
            &self.ic_status
        }
        #[doc = "0x64 - IC_TXFLR"]
        #[inline(always)]
        pub const fn ic_txflr(&self) -> &IcTxflr {
            &self.ic_txflr
        }
        #[doc = "0x68 - IC_RXFLR"]
        #[inline(always)]
        pub const fn ic_rxflr(&self) -> &IcRxflr {
            &self.ic_rxflr
        }
        #[doc = "0x6c - IC_SDA_HOLD"]
        #[inline(always)]
        pub const fn ic_sda_hold(&self) -> &IcSdaHold {
            &self.ic_sda_hold
        }
        #[doc = "0x70 - IC_SDA_HOLD_TX"]
        #[inline(always)]
        pub const fn ic_sda_hold_tx(&self) -> &IcSdaHoldTx {
            &self.ic_sda_hold_tx
        }
        #[doc = "0x74 - IC_TX_FLUSH_CNT"]
        #[inline(always)]
        pub const fn ic_tx_flush_cnt(&self) -> &IcTxFlushCnt {
            &self.ic_tx_flush_cnt
        }
        #[doc = "0x78 - IC_TX_ABRT_SOURCE"]
        #[inline(always)]
        pub const fn ic_tx_abrt_source(&self) -> &IcTxAbrtSource {
            &self.ic_tx_abrt_source
        }
        #[doc = "0x7c - IC_TX_ABRT_SLV_INTX"]
        #[inline(always)]
        pub const fn ic_tx_abrt_slv_intx(&self) -> &IcTxAbrtSlvIntx {
            &self.ic_tx_abrt_slv_intx
        }
        #[doc = "0x80 - IC_ACK_GENERAL_CALL"]
        #[inline(always)]
        pub const fn ic_ack_general_call(&self) -> &IcAckGeneralCall {
            &self.ic_ack_general_call
        }
        #[doc = "0x84 - IC_ENABLE_STATUS"]
        #[inline(always)]
        pub const fn ic_enable_status(&self) -> &IcEnableStatus {
            &self.ic_enable_status
        }
        #[doc = "0xa0 - IC_DMA_CR"]
        #[inline(always)]
        pub const fn ic_dma_cr(&self) -> &IcDmaCr {
            &self.ic_dma_cr
        }
        #[doc = "0xa4 - IC_DMA_TDLR"]
        #[inline(always)]
        pub const fn ic_dma_tdlr(&self) -> &IcDmaTdlr {
            &self.ic_dma_tdlr
        }
        #[doc = "0xa8 - IC_DMA_RDLR"]
        #[inline(always)]
        pub const fn ic_dma_rdlr(&self) -> &IcDmaRdlr {
            &self.ic_dma_rdlr
        }
        #[doc = "0xac - IC_SDA_SETUP"]
        #[inline(always)]
        pub const fn ic_sda_setup(&self) -> &IcSdaSetup {
            &self.ic_sda_setup
        }
        #[doc = "0xb0 - IC_INTR_MASK"]
        #[inline(always)]
        pub const fn ic_intr_mask(&self) -> &IcIntrMask {
            &self.ic_intr_mask
        }
        #[doc = "0xb4 - IC_INTR_STAT"]
        #[inline(always)]
        pub const fn ic_intr_stat(&self) -> &IcIntrStat {
            &self.ic_intr_stat
        }
        #[doc = "0xb8 - IC_RAW_INTR_STAT"]
        #[inline(always)]
        pub const fn ic_raw_intr_stat(&self) -> &IcRawIntrStat {
            &self.ic_raw_intr_stat
        }
        #[doc = "0xbc - IC_INTR_STAT_ALL"]
        #[inline(always)]
        pub const fn ic_intr_stat_all(&self) -> &IcIntrStatAll {
            &self.ic_intr_stat_all
        }
        #[doc = "0xc0 - IC_CLR_INTR"]
        #[inline(always)]
        pub const fn ic_clr_intr(&self) -> &IcClrIntr {
            &self.ic_clr_intr
        }
        #[doc = "0xc4 - IC_CLR_INT"]
        #[inline(always)]
        pub const fn ic_clr_int(&self) -> &IcClrInt {
            &self.ic_clr_int
        }
    }
    #[doc = "IC_CON (rw) register accessor: IC_CON\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_con::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_con::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_con`] module"]
    #[doc(alias = "IC_CON")]
    pub type IcCon = crate::Reg<ic_con::IcConSpec>;
    #[doc = "IC_CON"]
    pub mod ic_con {
        #[doc = "Register `IC_CON` reader"]
        pub type R = crate::R<IcConSpec>;
        #[doc = "Register `IC_CON` writer"]
        pub type W = crate::W<IcConSpec>;
        #[doc = "Field `master_mode` reader - 1=master"]
        pub type MasterModeR = crate::BitReader;
        #[doc = "Field `master_mode` writer - 1=master"]
        pub type MasterModeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `speed` reader - 1=SS 2=FS 3=HS"]
        pub type SpeedR = crate::FieldReader;
        #[doc = "Field `speed` writer - 1=SS 2=FS 3=HS"]
        pub type SpeedW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `ic_10bitaddr_slave` reader - "]
        pub type Ic10bitaddrSlaveR = crate::BitReader;
        #[doc = "Field `ic_10bitaddr_slave` writer - "]
        pub type Ic10bitaddrSlaveW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ic_10bitaddr_master` reader - "]
        pub type Ic10bitaddrMasterR = crate::BitReader;
        #[doc = "Field `ic_10bitaddr_master` writer - "]
        pub type Ic10bitaddrMasterW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ic_restart_en` reader - "]
        pub type IcRestartEnR = crate::BitReader;
        #[doc = "Field `ic_restart_en` writer - "]
        pub type IcRestartEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ic_slave_disable` reader - "]
        pub type IcSlaveDisableR = crate::BitReader;
        #[doc = "Field `ic_slave_disable` writer - "]
        pub type IcSlaveDisableW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `stop_det_ifaddressed` reader - "]
        pub type StopDetIfaddressedR = crate::BitReader;
        #[doc = "Field `stop_det_ifaddressed` writer - "]
        pub type StopDetIfaddressedW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tx_empty_ctrl` reader - "]
        pub type TxEmptyCtrlR = crate::BitReader;
        #[doc = "Field `tx_empty_ctrl` writer - "]
        pub type TxEmptyCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rx_fifo_full_hld_ctrl` reader - "]
        pub type RxFifoFullHldCtrlR = crate::BitReader;
        #[doc = "Field `rx_fifo_full_hld_ctrl` writer - "]
        pub type RxFifoFullHldCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `stop_det_if_master_active` reader - "]
        pub type StopDetIfMasterActiveR = crate::BitReader;
        #[doc = "Field `stop_det_if_master_active` writer - "]
        pub type StopDetIfMasterActiveW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `bus_clear_feature_ctrl` reader - "]
        pub type BusClearFeatureCtrlR = crate::BitReader;
        #[doc = "Field `bus_clear_feature_ctrl` writer - "]
        pub type BusClearFeatureCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - 1=master"]
            #[inline(always)]
            pub fn master_mode(&self) -> MasterModeR {
                MasterModeR::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 1:2 - 1=SS 2=FS 3=HS"]
            #[inline(always)]
            pub fn speed(&self) -> SpeedR {
                SpeedR::new(((self.bits >> 1) & 3) as u8)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn ic_10bitaddr_slave(&self) -> Ic10bitaddrSlaveR {
                Ic10bitaddrSlaveR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn ic_10bitaddr_master(&self) -> Ic10bitaddrMasterR {
                Ic10bitaddrMasterR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn ic_restart_en(&self) -> IcRestartEnR {
                IcRestartEnR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn ic_slave_disable(&self) -> IcSlaveDisableR {
                IcSlaveDisableR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn stop_det_ifaddressed(&self) -> StopDetIfaddressedR {
                StopDetIfaddressedR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn tx_empty_ctrl(&self) -> TxEmptyCtrlR {
                TxEmptyCtrlR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn rx_fifo_full_hld_ctrl(&self) -> RxFifoFullHldCtrlR {
                RxFifoFullHldCtrlR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn stop_det_if_master_active(&self) -> StopDetIfMasterActiveR {
                StopDetIfMasterActiveR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn bus_clear_feature_ctrl(&self) -> BusClearFeatureCtrlR {
                BusClearFeatureCtrlR::new(((self.bits >> 11) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - 1=master"]
            #[inline(always)]
            pub fn master_mode(&mut self) -> MasterModeW<'_, IcConSpec> {
                MasterModeW::new(self, 0)
            }
            #[doc = "Bits 1:2 - 1=SS 2=FS 3=HS"]
            #[inline(always)]
            pub fn speed(&mut self) -> SpeedW<'_, IcConSpec> {
                SpeedW::new(self, 1)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn ic_10bitaddr_slave(&mut self) -> Ic10bitaddrSlaveW<'_, IcConSpec> {
                Ic10bitaddrSlaveW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn ic_10bitaddr_master(&mut self) -> Ic10bitaddrMasterW<'_, IcConSpec> {
                Ic10bitaddrMasterW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn ic_restart_en(&mut self) -> IcRestartEnW<'_, IcConSpec> {
                IcRestartEnW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn ic_slave_disable(&mut self) -> IcSlaveDisableW<'_, IcConSpec> {
                IcSlaveDisableW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn stop_det_ifaddressed(&mut self) -> StopDetIfaddressedW<'_, IcConSpec> {
                StopDetIfaddressedW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn tx_empty_ctrl(&mut self) -> TxEmptyCtrlW<'_, IcConSpec> {
                TxEmptyCtrlW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn rx_fifo_full_hld_ctrl(&mut self) -> RxFifoFullHldCtrlW<'_, IcConSpec> {
                RxFifoFullHldCtrlW::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn stop_det_if_master_active(&mut self) -> StopDetIfMasterActiveW<'_, IcConSpec> {
                StopDetIfMasterActiveW::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn bus_clear_feature_ctrl(&mut self) -> BusClearFeatureCtrlW<'_, IcConSpec> {
                BusClearFeatureCtrlW::new(self, 11)
            }
        }
        #[doc = "IC_CON\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_con::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_con::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcConSpec;
        impl crate::RegisterSpec for IcConSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_con::R`](R) reader structure"]
        impl crate::Readable for IcConSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_con::W`](W) writer structure"]
        impl crate::Writable for IcConSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_CON to value 0"]
        impl crate::Resettable for IcConSpec {}
    }
    #[doc = "IC_ENABLE (rw) register accessor: IC_ENABLE\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_enable`] module"]
    #[doc(alias = "IC_ENABLE")]
    pub type IcEnable = crate::Reg<ic_enable::IcEnableSpec>;
    #[doc = "IC_ENABLE"]
    pub mod ic_enable {
        #[doc = "Register `IC_ENABLE` reader"]
        pub type R = crate::R<IcEnableSpec>;
        #[doc = "Register `IC_ENABLE` writer"]
        pub type W = crate::W<IcEnableSpec>;
        #[doc = "Field `enable` reader - "]
        pub type EnableR = crate::BitReader;
        #[doc = "Field `enable` writer - "]
        pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `abort` reader - "]
        pub type AbortR = crate::BitReader;
        #[doc = "Field `abort` writer - "]
        pub type AbortW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tx_cmd_block` reader - "]
        pub type TxCmdBlockR = crate::BitReader;
        #[doc = "Field `tx_cmd_block` writer - "]
        pub type TxCmdBlockW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `sda_stuck_recovery_enable` reader - "]
        pub type SdaStuckRecoveryEnableR = crate::BitReader;
        #[doc = "Field `sda_stuck_recovery_enable` writer - "]
        pub type SdaStuckRecoveryEnableW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn enable(&self) -> EnableR {
                EnableR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn abort(&self) -> AbortR {
                AbortR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn tx_cmd_block(&self) -> TxCmdBlockR {
                TxCmdBlockR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn sda_stuck_recovery_enable(&self) -> SdaStuckRecoveryEnableR {
                SdaStuckRecoveryEnableR::new(((self.bits >> 3) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn enable(&mut self) -> EnableW<'_, IcEnableSpec> {
                EnableW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn abort(&mut self) -> AbortW<'_, IcEnableSpec> {
                AbortW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn tx_cmd_block(&mut self) -> TxCmdBlockW<'_, IcEnableSpec> {
                TxCmdBlockW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn sda_stuck_recovery_enable(
                &mut self,
            ) -> SdaStuckRecoveryEnableW<'_, IcEnableSpec> {
                SdaStuckRecoveryEnableW::new(self, 3)
            }
        }
        #[doc = "IC_ENABLE\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcEnableSpec;
        impl crate::RegisterSpec for IcEnableSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_enable::R`](R) reader structure"]
        impl crate::Readable for IcEnableSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_enable::W`](W) writer structure"]
        impl crate::Writable for IcEnableSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_ENABLE to value 0"]
        impl crate::Resettable for IcEnableSpec {}
    }
    #[doc = "IC_TAR (rw) register accessor: IC_TAR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tar`] module"]
    #[doc(alias = "IC_TAR")]
    pub type IcTar = crate::Reg<ic_tar::IcTarSpec>;
    #[doc = "IC_TAR"]
    pub mod ic_tar {
        #[doc = "Register `IC_TAR` reader"]
        pub type R = crate::R<IcTarSpec>;
        #[doc = "Register `IC_TAR` writer"]
        pub type W = crate::W<IcTarSpec>;
        #[doc = "Field `ic_tar` reader - target address"]
        pub type IcTarR = crate::FieldReader<u16>;
        #[doc = "Field `ic_tar` writer - target address"]
        pub type IcTarW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
        #[doc = "Field `gc_or_start` reader - "]
        pub type GcOrStartR = crate::BitReader;
        #[doc = "Field `gc_or_start` writer - "]
        pub type GcOrStartW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `special` reader - "]
        pub type SpecialR = crate::BitReader;
        #[doc = "Field `special` writer - "]
        pub type SpecialW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `master_10bitaddr` reader - "]
        pub type Master10bitaddrR = crate::BitReader;
        #[doc = "Field `master_10bitaddr` writer - "]
        pub type Master10bitaddrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `device_id` reader - "]
        pub type DeviceIdR = crate::BitReader;
        #[doc = "Field `device_id` writer - "]
        pub type DeviceIdW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:9 - target address"]
            #[inline(always)]
            pub fn ic_tar(&self) -> IcTarR {
                IcTarR::new((self.bits & 0x03ff) as u16)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn gc_or_start(&self) -> GcOrStartR {
                GcOrStartR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn special(&self) -> SpecialR {
                SpecialR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn master_10bitaddr(&self) -> Master10bitaddrR {
                Master10bitaddrR::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13"]
            #[inline(always)]
            pub fn device_id(&self) -> DeviceIdR {
                DeviceIdR::new(((self.bits >> 13) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:9 - target address"]
            #[inline(always)]
            pub fn ic_tar(&mut self) -> IcTarW<'_, IcTarSpec> {
                IcTarW::new(self, 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn gc_or_start(&mut self) -> GcOrStartW<'_, IcTarSpec> {
                GcOrStartW::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn special(&mut self) -> SpecialW<'_, IcTarSpec> {
                SpecialW::new(self, 11)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn master_10bitaddr(&mut self) -> Master10bitaddrW<'_, IcTarSpec> {
                Master10bitaddrW::new(self, 12)
            }
            #[doc = "Bit 13"]
            #[inline(always)]
            pub fn device_id(&mut self) -> DeviceIdW<'_, IcTarSpec> {
                DeviceIdW::new(self, 13)
            }
        }
        #[doc = "IC_TAR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcTarSpec;
        impl crate::RegisterSpec for IcTarSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_tar::R`](R) reader structure"]
        impl crate::Readable for IcTarSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_tar::W`](W) writer structure"]
        impl crate::Writable for IcTarSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_TAR to value 0"]
        impl crate::Resettable for IcTarSpec {}
    }
    #[doc = "IC_SAR (rw) register accessor: IC_SAR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_sar`] module"]
    #[doc(alias = "IC_SAR")]
    pub type IcSar = crate::Reg<ic_sar::IcSarSpec>;
    #[doc = "IC_SAR"]
    pub mod ic_sar {
        #[doc = "Register `IC_SAR` reader"]
        pub type R = crate::R<IcSarSpec>;
        #[doc = "Register `IC_SAR` writer"]
        pub type W = crate::W<IcSarSpec>;
        #[doc = "Field `ic_sar` reader - slave address"]
        pub type IcSarR = crate::FieldReader<u16>;
        #[doc = "Field `ic_sar` writer - slave address"]
        pub type IcSarW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
        impl R {
            #[doc = "Bits 0:9 - slave address"]
            #[inline(always)]
            pub fn ic_sar(&self) -> IcSarR {
                IcSarR::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:9 - slave address"]
            #[inline(always)]
            pub fn ic_sar(&mut self) -> IcSarW<'_, IcSarSpec> {
                IcSarW::new(self, 0)
            }
        }
        #[doc = "IC_SAR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcSarSpec;
        impl crate::RegisterSpec for IcSarSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_sar::R`](R) reader structure"]
        impl crate::Readable for IcSarSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_sar::W`](W) writer structure"]
        impl crate::Writable for IcSarSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_SAR to value 0"]
        impl crate::Resettable for IcSarSpec {}
    }
    #[doc = "IC_HS_MADDR (rw) register accessor: IC_HS_MADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_maddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_maddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_hs_maddr`] module"]
    #[doc(alias = "IC_HS_MADDR")]
    pub type IcHsMaddr = crate::Reg<ic_hs_maddr::IcHsMaddrSpec>;
    #[doc = "IC_HS_MADDR"]
    pub mod ic_hs_maddr {
        #[doc = "Register `IC_HS_MADDR` reader"]
        pub type R = crate::R<IcHsMaddrSpec>;
        #[doc = "Register `IC_HS_MADDR` writer"]
        pub type W = crate::W<IcHsMaddrSpec>;
        #[doc = "Field `ic_hs_mar` reader - "]
        pub type IcHsMarR = crate::FieldReader;
        #[doc = "Field `ic_hs_mar` writer - "]
        pub type IcHsMarW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn ic_hs_mar(&self) -> IcHsMarR {
                IcHsMarR::new((self.bits & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn ic_hs_mar(&mut self) -> IcHsMarW<'_, IcHsMaddrSpec> {
                IcHsMarW::new(self, 0)
            }
        }
        #[doc = "IC_HS_MADDR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_maddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_maddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcHsMaddrSpec;
        impl crate::RegisterSpec for IcHsMaddrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_hs_maddr::R`](R) reader structure"]
        impl crate::Readable for IcHsMaddrSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_hs_maddr::W`](W) writer structure"]
        impl crate::Writable for IcHsMaddrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_HS_MADDR to value 0"]
        impl crate::Resettable for IcHsMaddrSpec {}
    }
    #[doc = "IC_DATA_CMD (rw) register accessor: IC_DATA_CMD\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_data_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_data_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_data_cmd`] module"]
    #[doc(alias = "IC_DATA_CMD")]
    pub type IcDataCmd = crate::Reg<ic_data_cmd::IcDataCmdSpec>;
    #[doc = "IC_DATA_CMD"]
    pub mod ic_data_cmd {
        #[doc = "Register `IC_DATA_CMD` reader"]
        pub type R = crate::R<IcDataCmdSpec>;
        #[doc = "Register `IC_DATA_CMD` writer"]
        pub type W = crate::W<IcDataCmdSpec>;
        #[doc = "Field `dat` reader - data byte"]
        pub type DatR = crate::FieldReader;
        #[doc = "Field `dat` writer - data byte"]
        pub type DatW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `cmd` reader - 1=read 0=write"]
        pub type CmdR = crate::BitReader;
        #[doc = "Field `cmd` writer - 1=read 0=write"]
        pub type CmdW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `stop` reader - "]
        pub type StopR = crate::BitReader;
        #[doc = "Field `stop` writer - "]
        pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `restart` reader - "]
        pub type RestartR = crate::BitReader;
        #[doc = "Field `restart` writer - "]
        pub type RestartW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `first_data_byte` reader - "]
        pub type FirstDataByteR = crate::BitReader;
        impl R {
            #[doc = "Bits 0:7 - data byte"]
            #[inline(always)]
            pub fn dat(&self) -> DatR {
                DatR::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bit 8 - 1=read 0=write"]
            #[inline(always)]
            pub fn cmd(&self) -> CmdR {
                CmdR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn stop(&self) -> StopR {
                StopR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn restart(&self) -> RestartR {
                RestartR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn first_data_byte(&self) -> FirstDataByteR {
                FirstDataByteR::new(((self.bits >> 11) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - data byte"]
            #[inline(always)]
            pub fn dat(&mut self) -> DatW<'_, IcDataCmdSpec> {
                DatW::new(self, 0)
            }
            #[doc = "Bit 8 - 1=read 0=write"]
            #[inline(always)]
            pub fn cmd(&mut self) -> CmdW<'_, IcDataCmdSpec> {
                CmdW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn stop(&mut self) -> StopW<'_, IcDataCmdSpec> {
                StopW::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn restart(&mut self) -> RestartW<'_, IcDataCmdSpec> {
                RestartW::new(self, 10)
            }
        }
        #[doc = "IC_DATA_CMD\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_data_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_data_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcDataCmdSpec;
        impl crate::RegisterSpec for IcDataCmdSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_data_cmd::R`](R) reader structure"]
        impl crate::Readable for IcDataCmdSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_data_cmd::W`](W) writer structure"]
        impl crate::Writable for IcDataCmdSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_DATA_CMD to value 0"]
        impl crate::Resettable for IcDataCmdSpec {}
    }
    #[doc = "IC_SS_SCL_HCNT (rw) register accessor: IC_SS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_ss_scl_hcnt`] module"]
    #[doc(alias = "IC_SS_SCL_HCNT")]
    pub type IcSsSclHcnt = crate::Reg<ic_ss_scl_hcnt::IcSsSclHcntSpec>;
    #[doc = "IC_SS_SCL_HCNT"]
    pub mod ic_ss_scl_hcnt {
        #[doc = "Register `IC_SS_SCL_HCNT` reader"]
        pub type R = crate::R<IcSsSclHcntSpec>;
        #[doc = "Register `IC_SS_SCL_HCNT` writer"]
        pub type W = crate::W<IcSsSclHcntSpec>;
        #[doc = "Field `cnt` reader - "]
        pub type CntR = crate::FieldReader<u16>;
        #[doc = "Field `cnt` writer - "]
        pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&self) -> CntR {
                CntR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&mut self) -> CntW<'_, IcSsSclHcntSpec> {
                CntW::new(self, 0)
            }
        }
        #[doc = "IC_SS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcSsSclHcntSpec;
        impl crate::RegisterSpec for IcSsSclHcntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_ss_scl_hcnt::R`](R) reader structure"]
        impl crate::Readable for IcSsSclHcntSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_ss_scl_hcnt::W`](W) writer structure"]
        impl crate::Writable for IcSsSclHcntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_SS_SCL_HCNT to value 0"]
        impl crate::Resettable for IcSsSclHcntSpec {}
    }
    #[doc = "IC_SS_SCL_LCNT (rw) register accessor: IC_SS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_ss_scl_lcnt`] module"]
    #[doc(alias = "IC_SS_SCL_LCNT")]
    pub type IcSsSclLcnt = crate::Reg<ic_ss_scl_lcnt::IcSsSclLcntSpec>;
    #[doc = "IC_SS_SCL_LCNT"]
    pub mod ic_ss_scl_lcnt {
        #[doc = "Register `IC_SS_SCL_LCNT` reader"]
        pub type R = crate::R<IcSsSclLcntSpec>;
        #[doc = "Register `IC_SS_SCL_LCNT` writer"]
        pub type W = crate::W<IcSsSclLcntSpec>;
        #[doc = "Field `cnt` reader - "]
        pub type CntR = crate::FieldReader<u16>;
        #[doc = "Field `cnt` writer - "]
        pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&self) -> CntR {
                CntR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&mut self) -> CntW<'_, IcSsSclLcntSpec> {
                CntW::new(self, 0)
            }
        }
        #[doc = "IC_SS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcSsSclLcntSpec;
        impl crate::RegisterSpec for IcSsSclLcntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_ss_scl_lcnt::R`](R) reader structure"]
        impl crate::Readable for IcSsSclLcntSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_ss_scl_lcnt::W`](W) writer structure"]
        impl crate::Writable for IcSsSclLcntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_SS_SCL_LCNT to value 0"]
        impl crate::Resettable for IcSsSclLcntSpec {}
    }
    #[doc = "IC_FS_SCL_HCNT (rw) register accessor: IC_FS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_fs_scl_hcnt`] module"]
    #[doc(alias = "IC_FS_SCL_HCNT")]
    pub type IcFsSclHcnt = crate::Reg<ic_fs_scl_hcnt::IcFsSclHcntSpec>;
    #[doc = "IC_FS_SCL_HCNT"]
    pub mod ic_fs_scl_hcnt {
        #[doc = "Register `IC_FS_SCL_HCNT` reader"]
        pub type R = crate::R<IcFsSclHcntSpec>;
        #[doc = "Register `IC_FS_SCL_HCNT` writer"]
        pub type W = crate::W<IcFsSclHcntSpec>;
        #[doc = "Field `cnt` reader - "]
        pub type CntR = crate::FieldReader<u16>;
        #[doc = "Field `cnt` writer - "]
        pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&self) -> CntR {
                CntR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&mut self) -> CntW<'_, IcFsSclHcntSpec> {
                CntW::new(self, 0)
            }
        }
        #[doc = "IC_FS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcFsSclHcntSpec;
        impl crate::RegisterSpec for IcFsSclHcntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_fs_scl_hcnt::R`](R) reader structure"]
        impl crate::Readable for IcFsSclHcntSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_fs_scl_hcnt::W`](W) writer structure"]
        impl crate::Writable for IcFsSclHcntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_FS_SCL_HCNT to value 0"]
        impl crate::Resettable for IcFsSclHcntSpec {}
    }
    #[doc = "IC_FS_SCL_LCNT (rw) register accessor: IC_FS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_fs_scl_lcnt`] module"]
    #[doc(alias = "IC_FS_SCL_LCNT")]
    pub type IcFsSclLcnt = crate::Reg<ic_fs_scl_lcnt::IcFsSclLcntSpec>;
    #[doc = "IC_FS_SCL_LCNT"]
    pub mod ic_fs_scl_lcnt {
        #[doc = "Register `IC_FS_SCL_LCNT` reader"]
        pub type R = crate::R<IcFsSclLcntSpec>;
        #[doc = "Register `IC_FS_SCL_LCNT` writer"]
        pub type W = crate::W<IcFsSclLcntSpec>;
        #[doc = "Field `cnt` reader - "]
        pub type CntR = crate::FieldReader<u16>;
        #[doc = "Field `cnt` writer - "]
        pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&self) -> CntR {
                CntR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&mut self) -> CntW<'_, IcFsSclLcntSpec> {
                CntW::new(self, 0)
            }
        }
        #[doc = "IC_FS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcFsSclLcntSpec;
        impl crate::RegisterSpec for IcFsSclLcntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_fs_scl_lcnt::R`](R) reader structure"]
        impl crate::Readable for IcFsSclLcntSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_fs_scl_lcnt::W`](W) writer structure"]
        impl crate::Writable for IcFsSclLcntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_FS_SCL_LCNT to value 0"]
        impl crate::Resettable for IcFsSclLcntSpec {}
    }
    #[doc = "IC_HS_SCL_HCNT (rw) register accessor: IC_HS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_hs_scl_hcnt`] module"]
    #[doc(alias = "IC_HS_SCL_HCNT")]
    pub type IcHsSclHcnt = crate::Reg<ic_hs_scl_hcnt::IcHsSclHcntSpec>;
    #[doc = "IC_HS_SCL_HCNT"]
    pub mod ic_hs_scl_hcnt {
        #[doc = "Register `IC_HS_SCL_HCNT` reader"]
        pub type R = crate::R<IcHsSclHcntSpec>;
        #[doc = "Register `IC_HS_SCL_HCNT` writer"]
        pub type W = crate::W<IcHsSclHcntSpec>;
        #[doc = "Field `cnt` reader - "]
        pub type CntR = crate::FieldReader<u16>;
        #[doc = "Field `cnt` writer - "]
        pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&self) -> CntR {
                CntR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&mut self) -> CntW<'_, IcHsSclHcntSpec> {
                CntW::new(self, 0)
            }
        }
        #[doc = "IC_HS_SCL_HCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcHsSclHcntSpec;
        impl crate::RegisterSpec for IcHsSclHcntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_hs_scl_hcnt::R`](R) reader structure"]
        impl crate::Readable for IcHsSclHcntSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_hs_scl_hcnt::W`](W) writer structure"]
        impl crate::Writable for IcHsSclHcntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_HS_SCL_HCNT to value 0"]
        impl crate::Resettable for IcHsSclHcntSpec {}
    }
    #[doc = "IC_HS_SCL_LCNT (rw) register accessor: IC_HS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_hs_scl_lcnt`] module"]
    #[doc(alias = "IC_HS_SCL_LCNT")]
    pub type IcHsSclLcnt = crate::Reg<ic_hs_scl_lcnt::IcHsSclLcntSpec>;
    #[doc = "IC_HS_SCL_LCNT"]
    pub mod ic_hs_scl_lcnt {
        #[doc = "Register `IC_HS_SCL_LCNT` reader"]
        pub type R = crate::R<IcHsSclLcntSpec>;
        #[doc = "Register `IC_HS_SCL_LCNT` writer"]
        pub type W = crate::W<IcHsSclLcntSpec>;
        #[doc = "Field `cnt` reader - "]
        pub type CntR = crate::FieldReader<u16>;
        #[doc = "Field `cnt` writer - "]
        pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&self) -> CntR {
                CntR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&mut self) -> CntW<'_, IcHsSclLcntSpec> {
                CntW::new(self, 0)
            }
        }
        #[doc = "IC_HS_SCL_LCNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_hs_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_hs_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcHsSclLcntSpec;
        impl crate::RegisterSpec for IcHsSclLcntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_hs_scl_lcnt::R`](R) reader structure"]
        impl crate::Readable for IcHsSclLcntSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_hs_scl_lcnt::W`](W) writer structure"]
        impl crate::Writable for IcHsSclLcntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_HS_SCL_LCNT to value 0"]
        impl crate::Resettable for IcHsSclLcntSpec {}
    }
    #[doc = "IC_RX_TL (rw) register accessor: IC_RX_TL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_rx_tl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rx_tl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_rx_tl`] module"]
    #[doc(alias = "IC_RX_TL")]
    pub type IcRxTl = crate::Reg<ic_rx_tl::IcRxTlSpec>;
    #[doc = "IC_RX_TL"]
    pub mod ic_rx_tl {
        #[doc = "Register `IC_RX_TL` reader"]
        pub type R = crate::R<IcRxTlSpec>;
        #[doc = "Register `IC_RX_TL` writer"]
        pub type W = crate::W<IcRxTlSpec>;
        #[doc = "Field `rx_tl` reader - "]
        pub type RxTlR = crate::FieldReader;
        #[doc = "Field `rx_tl` writer - "]
        pub type RxTlW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn rx_tl(&self) -> RxTlR {
                RxTlR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn rx_tl(&mut self) -> RxTlW<'_, IcRxTlSpec> {
                RxTlW::new(self, 0)
            }
        }
        #[doc = "IC_RX_TL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_rx_tl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rx_tl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcRxTlSpec;
        impl crate::RegisterSpec for IcRxTlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_rx_tl::R`](R) reader structure"]
        impl crate::Readable for IcRxTlSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_rx_tl::W`](W) writer structure"]
        impl crate::Writable for IcRxTlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_RX_TL to value 0"]
        impl crate::Resettable for IcRxTlSpec {}
    }
    #[doc = "IC_TX_TL (rw) register accessor: IC_TX_TL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_tl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_tl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tx_tl`] module"]
    #[doc(alias = "IC_TX_TL")]
    pub type IcTxTl = crate::Reg<ic_tx_tl::IcTxTlSpec>;
    #[doc = "IC_TX_TL"]
    pub mod ic_tx_tl {
        #[doc = "Register `IC_TX_TL` reader"]
        pub type R = crate::R<IcTxTlSpec>;
        #[doc = "Register `IC_TX_TL` writer"]
        pub type W = crate::W<IcTxTlSpec>;
        #[doc = "Field `tx_tl` reader - "]
        pub type TxTlR = crate::FieldReader;
        #[doc = "Field `tx_tl` writer - "]
        pub type TxTlW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn tx_tl(&self) -> TxTlR {
                TxTlR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn tx_tl(&mut self) -> TxTlW<'_, IcTxTlSpec> {
                TxTlW::new(self, 0)
            }
        }
        #[doc = "IC_TX_TL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_tl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_tl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcTxTlSpec;
        impl crate::RegisterSpec for IcTxTlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_tx_tl::R`](R) reader structure"]
        impl crate::Readable for IcTxTlSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_tx_tl::W`](W) writer structure"]
        impl crate::Writable for IcTxTlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_TX_TL to value 0"]
        impl crate::Resettable for IcTxTlSpec {}
    }
    #[doc = "IC_SLV_DATA_NACK_ONLY (rw) register accessor: IC_SLV_DATA_NACK_ONLY\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_slv_data_nack_only::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_slv_data_nack_only`] module"]
    #[doc(alias = "IC_SLV_DATA_NACK_ONLY")]
    pub type IcSlvDataNackOnly = crate::Reg<ic_slv_data_nack_only::IcSlvDataNackOnlySpec>;
    #[doc = "IC_SLV_DATA_NACK_ONLY"]
    pub mod ic_slv_data_nack_only {
        #[doc = "Register `IC_SLV_DATA_NACK_ONLY` reader"]
        pub type R = crate::R<IcSlvDataNackOnlySpec>;
        #[doc = "Register `IC_SLV_DATA_NACK_ONLY` writer"]
        pub type W = crate::W<IcSlvDataNackOnlySpec>;
        #[doc = "Field `nack` reader - "]
        pub type NackR = crate::BitReader;
        #[doc = "Field `nack` writer - "]
        pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn nack(&self) -> NackR {
                NackR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn nack(&mut self) -> NackW<'_, IcSlvDataNackOnlySpec> {
                NackW::new(self, 0)
            }
        }
        #[doc = "IC_SLV_DATA_NACK_ONLY\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_slv_data_nack_only::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcSlvDataNackOnlySpec;
        impl crate::RegisterSpec for IcSlvDataNackOnlySpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_slv_data_nack_only::R`](R) reader structure"]
        impl crate::Readable for IcSlvDataNackOnlySpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_slv_data_nack_only::W`](W) writer structure"]
        impl crate::Writable for IcSlvDataNackOnlySpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_SLV_DATA_NACK_ONLY to value 0"]
        impl crate::Resettable for IcSlvDataNackOnlySpec {}
    }
    #[doc = "IC_STATUS (r) register accessor: IC_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_status`] module"]
    #[doc(alias = "IC_STATUS")]
    pub type IcStatus = crate::Reg<ic_status::IcStatusSpec>;
    #[doc = "IC_STATUS"]
    pub mod ic_status {
        #[doc = "Register `IC_STATUS` reader"]
        pub type R = crate::R<IcStatusSpec>;
        #[doc = "Field `activity` reader - "]
        pub type ActivityR = crate::BitReader;
        #[doc = "Field `tfnf` reader - TX not full"]
        pub type TfnfR = crate::BitReader;
        #[doc = "Field `tfe` reader - TX empty"]
        pub type TfeR = crate::BitReader;
        #[doc = "Field `rfne` reader - RX not empty"]
        pub type RfneR = crate::BitReader;
        #[doc = "Field `rff` reader - RX full"]
        pub type RffR = crate::BitReader;
        #[doc = "Field `mst_activity` reader - "]
        pub type MstActivityR = crate::BitReader;
        #[doc = "Field `slv_activity` reader - "]
        pub type SlvActivityR = crate::BitReader;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn activity(&self) -> ActivityR {
                ActivityR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TX not full"]
            #[inline(always)]
            pub fn tfnf(&self) -> TfnfR {
                TfnfR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - TX empty"]
            #[inline(always)]
            pub fn tfe(&self) -> TfeR {
                TfeR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - RX not empty"]
            #[inline(always)]
            pub fn rfne(&self) -> RfneR {
                RfneR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - RX full"]
            #[inline(always)]
            pub fn rff(&self) -> RffR {
                RffR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn mst_activity(&self) -> MstActivityR {
                MstActivityR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn slv_activity(&self) -> SlvActivityR {
                SlvActivityR::new(((self.bits >> 6) & 1) != 0)
            }
        }
        #[doc = "IC_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcStatusSpec;
        impl crate::RegisterSpec for IcStatusSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_status::R`](R) reader structure"]
        impl crate::Readable for IcStatusSpec {}
        #[doc = "`reset()` method sets IC_STATUS to value 0"]
        impl crate::Resettable for IcStatusSpec {}
    }
    #[doc = "IC_TXFLR (r) register accessor: IC_TXFLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_txflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_txflr`] module"]
    #[doc(alias = "IC_TXFLR")]
    pub type IcTxflr = crate::Reg<ic_txflr::IcTxflrSpec>;
    #[doc = "IC_TXFLR"]
    pub mod ic_txflr {
        #[doc = "Register `IC_TXFLR` reader"]
        pub type R = crate::R<IcTxflrSpec>;
        #[doc = "Field `txflr` reader - "]
        pub type TxflrR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:5"]
            #[inline(always)]
            pub fn txflr(&self) -> TxflrR {
                TxflrR::new((self.bits & 0x3f) as u8)
            }
        }
        #[doc = "IC_TXFLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_txflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcTxflrSpec;
        impl crate::RegisterSpec for IcTxflrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_txflr::R`](R) reader structure"]
        impl crate::Readable for IcTxflrSpec {}
        #[doc = "`reset()` method sets IC_TXFLR to value 0"]
        impl crate::Resettable for IcTxflrSpec {}
    }
    #[doc = "IC_RXFLR (r) register accessor: IC_RXFLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_rxflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_rxflr`] module"]
    #[doc(alias = "IC_RXFLR")]
    pub type IcRxflr = crate::Reg<ic_rxflr::IcRxflrSpec>;
    #[doc = "IC_RXFLR"]
    pub mod ic_rxflr {
        #[doc = "Register `IC_RXFLR` reader"]
        pub type R = crate::R<IcRxflrSpec>;
        #[doc = "Field `rxflr` reader - "]
        pub type RxflrR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:5"]
            #[inline(always)]
            pub fn rxflr(&self) -> RxflrR {
                RxflrR::new((self.bits & 0x3f) as u8)
            }
        }
        #[doc = "IC_RXFLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_rxflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcRxflrSpec;
        impl crate::RegisterSpec for IcRxflrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_rxflr::R`](R) reader structure"]
        impl crate::Readable for IcRxflrSpec {}
        #[doc = "`reset()` method sets IC_RXFLR to value 0"]
        impl crate::Resettable for IcRxflrSpec {}
    }
    #[doc = "IC_SDA_HOLD (rw) register accessor: IC_SDA_HOLD\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_sda_hold`] module"]
    #[doc(alias = "IC_SDA_HOLD")]
    pub type IcSdaHold = crate::Reg<ic_sda_hold::IcSdaHoldSpec>;
    #[doc = "IC_SDA_HOLD"]
    pub mod ic_sda_hold {
        #[doc = "Register `IC_SDA_HOLD` reader"]
        pub type R = crate::R<IcSdaHoldSpec>;
        #[doc = "Register `IC_SDA_HOLD` writer"]
        pub type W = crate::W<IcSdaHoldSpec>;
        #[doc = "Field `sda_rx_hold` reader - "]
        pub type SdaRxHoldR = crate::FieldReader;
        #[doc = "Field `sda_rx_hold` writer - "]
        pub type SdaRxHoldW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn sda_rx_hold(&self) -> SdaRxHoldR {
                SdaRxHoldR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn sda_rx_hold(&mut self) -> SdaRxHoldW<'_, IcSdaHoldSpec> {
                SdaRxHoldW::new(self, 0)
            }
        }
        #[doc = "IC_SDA_HOLD\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcSdaHoldSpec;
        impl crate::RegisterSpec for IcSdaHoldSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_sda_hold::R`](R) reader structure"]
        impl crate::Readable for IcSdaHoldSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_sda_hold::W`](W) writer structure"]
        impl crate::Writable for IcSdaHoldSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_SDA_HOLD to value 0"]
        impl crate::Resettable for IcSdaHoldSpec {}
    }
    #[doc = "IC_SDA_HOLD_TX (rw) register accessor: IC_SDA_HOLD_TX\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_hold_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_sda_hold_tx`] module"]
    #[doc(alias = "IC_SDA_HOLD_TX")]
    pub type IcSdaHoldTx = crate::Reg<ic_sda_hold_tx::IcSdaHoldTxSpec>;
    #[doc = "IC_SDA_HOLD_TX"]
    pub mod ic_sda_hold_tx {
        #[doc = "Register `IC_SDA_HOLD_TX` reader"]
        pub type R = crate::R<IcSdaHoldTxSpec>;
        #[doc = "Register `IC_SDA_HOLD_TX` writer"]
        pub type W = crate::W<IcSdaHoldTxSpec>;
        #[doc = "Field `sda_tx_hold` reader - "]
        pub type SdaTxHoldR = crate::FieldReader<u16>;
        #[doc = "Field `sda_tx_hold` writer - "]
        pub type SdaTxHoldW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn sda_tx_hold(&self) -> SdaTxHoldR {
                SdaTxHoldR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn sda_tx_hold(&mut self) -> SdaTxHoldW<'_, IcSdaHoldTxSpec> {
                SdaTxHoldW::new(self, 0)
            }
        }
        #[doc = "IC_SDA_HOLD_TX\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_hold_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcSdaHoldTxSpec;
        impl crate::RegisterSpec for IcSdaHoldTxSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_sda_hold_tx::R`](R) reader structure"]
        impl crate::Readable for IcSdaHoldTxSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_sda_hold_tx::W`](W) writer structure"]
        impl crate::Writable for IcSdaHoldTxSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_SDA_HOLD_TX to value 0"]
        impl crate::Resettable for IcSdaHoldTxSpec {}
    }
    #[doc = "IC_TX_FLUSH_CNT (r) register accessor: IC_TX_FLUSH_CNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_flush_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tx_flush_cnt`] module"]
    #[doc(alias = "IC_TX_FLUSH_CNT")]
    pub type IcTxFlushCnt = crate::Reg<ic_tx_flush_cnt::IcTxFlushCntSpec>;
    #[doc = "IC_TX_FLUSH_CNT"]
    pub mod ic_tx_flush_cnt {
        #[doc = "Register `IC_TX_FLUSH_CNT` reader"]
        pub type R = crate::R<IcTxFlushCntSpec>;
        #[doc = "Field `cnt` reader - "]
        pub type CntR = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn cnt(&self) -> CntR {
                CntR::new((self.bits & 0xffff) as u16)
            }
        }
        #[doc = "IC_TX_FLUSH_CNT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_flush_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcTxFlushCntSpec;
        impl crate::RegisterSpec for IcTxFlushCntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_tx_flush_cnt::R`](R) reader structure"]
        impl crate::Readable for IcTxFlushCntSpec {}
        #[doc = "`reset()` method sets IC_TX_FLUSH_CNT to value 0"]
        impl crate::Resettable for IcTxFlushCntSpec {}
    }
    #[doc = "IC_TX_ABRT_SOURCE (r) register accessor: IC_TX_ABRT_SOURCE\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_source::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tx_abrt_source`] module"]
    #[doc(alias = "IC_TX_ABRT_SOURCE")]
    pub type IcTxAbrtSource = crate::Reg<ic_tx_abrt_source::IcTxAbrtSourceSpec>;
    #[doc = "IC_TX_ABRT_SOURCE"]
    pub mod ic_tx_abrt_source {
        #[doc = "Register `IC_TX_ABRT_SOURCE` reader"]
        pub type R = crate::R<IcTxAbrtSourceSpec>;
        #[doc = "Field `user_abrt` reader - "]
        pub type UserAbrtR = crate::BitReader;
        #[doc = "Field `sda_stuck_at_low` reader - "]
        pub type SdaStuckAtLowR = crate::BitReader;
        #[doc = "Field `device_noack` reader - "]
        pub type DeviceNoackR = crate::BitReader;
        #[doc = "Field `device_slvaddr_noack` reader - "]
        pub type DeviceSlvaddrNoackR = crate::BitReader;
        #[doc = "Field `abrt_device_write` reader - "]
        pub type AbrtDeviceWriteR = crate::BitReader;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn user_abrt(&self) -> UserAbrtR {
                UserAbrtR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn sda_stuck_at_low(&self) -> SdaStuckAtLowR {
                SdaStuckAtLowR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn device_noack(&self) -> DeviceNoackR {
                DeviceNoackR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn device_slvaddr_noack(&self) -> DeviceSlvaddrNoackR {
                DeviceSlvaddrNoackR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn abrt_device_write(&self) -> AbrtDeviceWriteR {
                AbrtDeviceWriteR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        #[doc = "IC_TX_ABRT_SOURCE\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_source::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcTxAbrtSourceSpec;
        impl crate::RegisterSpec for IcTxAbrtSourceSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_tx_abrt_source::R`](R) reader structure"]
        impl crate::Readable for IcTxAbrtSourceSpec {}
        #[doc = "`reset()` method sets IC_TX_ABRT_SOURCE to value 0"]
        impl crate::Resettable for IcTxAbrtSourceSpec {}
    }
    #[doc = "IC_TX_ABRT_SLV_INTX (r) register accessor: IC_TX_ABRT_SLV_INTX\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_slv_intx::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_tx_abrt_slv_intx`] module"]
    #[doc(alias = "IC_TX_ABRT_SLV_INTX")]
    pub type IcTxAbrtSlvIntx = crate::Reg<ic_tx_abrt_slv_intx::IcTxAbrtSlvIntxSpec>;
    #[doc = "IC_TX_ABRT_SLV_INTX"]
    pub mod ic_tx_abrt_slv_intx {
        #[doc = "Register `IC_TX_ABRT_SLV_INTX` reader"]
        pub type R = crate::R<IcTxAbrtSlvIntxSpec>;
        #[doc = "Field `addr_7b_noack` reader - 7-bit address NACK (bus scan)"]
        pub type Addr7bNoackR = crate::BitReader;
        #[doc = "Field `addr1_10b_noack` reader - "]
        pub type Addr1_10bNoackR = crate::BitReader;
        #[doc = "Field `addr2_10b_noack` reader - "]
        pub type Addr2_10bNoackR = crate::BitReader;
        #[doc = "Field `txdata_noack` reader - "]
        pub type TxdataNoackR = crate::BitReader;
        #[doc = "Field `gcall_noack` reader - "]
        pub type GcallNoackR = crate::BitReader;
        #[doc = "Field `lost` reader - arbitration lost"]
        pub type LostR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - 7-bit address NACK (bus scan)"]
            #[inline(always)]
            pub fn addr_7b_noack(&self) -> Addr7bNoackR {
                Addr7bNoackR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn addr1_10b_noack(&self) -> Addr1_10bNoackR {
                Addr1_10bNoackR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn addr2_10b_noack(&self) -> Addr2_10bNoackR {
                Addr2_10bNoackR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn txdata_noack(&self) -> TxdataNoackR {
                TxdataNoackR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn gcall_noack(&self) -> GcallNoackR {
                GcallNoackR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 12 - arbitration lost"]
            #[inline(always)]
            pub fn lost(&self) -> LostR {
                LostR::new(((self.bits >> 12) & 1) != 0)
            }
        }
        #[doc = "IC_TX_ABRT_SLV_INTX\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_slv_intx::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcTxAbrtSlvIntxSpec;
        impl crate::RegisterSpec for IcTxAbrtSlvIntxSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_tx_abrt_slv_intx::R`](R) reader structure"]
        impl crate::Readable for IcTxAbrtSlvIntxSpec {}
        #[doc = "`reset()` method sets IC_TX_ABRT_SLV_INTX to value 0"]
        impl crate::Resettable for IcTxAbrtSlvIntxSpec {}
    }
    #[doc = "IC_ACK_GENERAL_CALL (rw) register accessor: IC_ACK_GENERAL_CALL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ack_general_call::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ack_general_call::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_ack_general_call`] module"]
    #[doc(alias = "IC_ACK_GENERAL_CALL")]
    pub type IcAckGeneralCall = crate::Reg<ic_ack_general_call::IcAckGeneralCallSpec>;
    #[doc = "IC_ACK_GENERAL_CALL"]
    pub mod ic_ack_general_call {
        #[doc = "Register `IC_ACK_GENERAL_CALL` reader"]
        pub type R = crate::R<IcAckGeneralCallSpec>;
        #[doc = "Register `IC_ACK_GENERAL_CALL` writer"]
        pub type W = crate::W<IcAckGeneralCallSpec>;
        #[doc = "Field `ack_gen_call` reader - "]
        pub type AckGenCallR = crate::BitReader;
        #[doc = "Field `ack_gen_call` writer - "]
        pub type AckGenCallW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn ack_gen_call(&self) -> AckGenCallR {
                AckGenCallR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn ack_gen_call(&mut self) -> AckGenCallW<'_, IcAckGeneralCallSpec> {
                AckGenCallW::new(self, 0)
            }
        }
        #[doc = "IC_ACK_GENERAL_CALL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_ack_general_call::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ack_general_call::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcAckGeneralCallSpec;
        impl crate::RegisterSpec for IcAckGeneralCallSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_ack_general_call::R`](R) reader structure"]
        impl crate::Readable for IcAckGeneralCallSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_ack_general_call::W`](W) writer structure"]
        impl crate::Writable for IcAckGeneralCallSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_ACK_GENERAL_CALL to value 0"]
        impl crate::Resettable for IcAckGeneralCallSpec {}
    }
    #[doc = "IC_ENABLE_STATUS (r) register accessor: IC_ENABLE_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_enable_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_enable_status`] module"]
    #[doc(alias = "IC_ENABLE_STATUS")]
    pub type IcEnableStatus = crate::Reg<ic_enable_status::IcEnableStatusSpec>;
    #[doc = "IC_ENABLE_STATUS"]
    pub mod ic_enable_status {
        #[doc = "Register `IC_ENABLE_STATUS` reader"]
        pub type R = crate::R<IcEnableStatusSpec>;
        #[doc = "Field `ic_en` reader - "]
        pub type IcEnR = crate::BitReader;
        #[doc = "Field `slv_disable_while_busy` reader - "]
        pub type SlvDisableWhileBusyR = crate::BitReader;
        #[doc = "Field `slv_rx_data_lost` reader - "]
        pub type SlvRxDataLostR = crate::BitReader;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn ic_en(&self) -> IcEnR {
                IcEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn slv_disable_while_busy(&self) -> SlvDisableWhileBusyR {
                SlvDisableWhileBusyR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn slv_rx_data_lost(&self) -> SlvRxDataLostR {
                SlvRxDataLostR::new(((self.bits >> 2) & 1) != 0)
            }
        }
        #[doc = "IC_ENABLE_STATUS\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_enable_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcEnableStatusSpec;
        impl crate::RegisterSpec for IcEnableStatusSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_enable_status::R`](R) reader structure"]
        impl crate::Readable for IcEnableStatusSpec {}
        #[doc = "`reset()` method sets IC_ENABLE_STATUS to value 0"]
        impl crate::Resettable for IcEnableStatusSpec {}
    }
    #[doc = "IC_DMA_CR (rw) register accessor: IC_DMA_CR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_dma_cr`] module"]
    #[doc(alias = "IC_DMA_CR")]
    pub type IcDmaCr = crate::Reg<ic_dma_cr::IcDmaCrSpec>;
    #[doc = "IC_DMA_CR"]
    pub mod ic_dma_cr {
        #[doc = "Register `IC_DMA_CR` reader"]
        pub type R = crate::R<IcDmaCrSpec>;
        #[doc = "Register `IC_DMA_CR` writer"]
        pub type W = crate::W<IcDmaCrSpec>;
        #[doc = "Field `rdmae` reader - "]
        pub type RdmaeR = crate::BitReader;
        #[doc = "Field `rdmae` writer - "]
        pub type RdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tdmae` reader - "]
        pub type TdmaeR = crate::BitReader;
        #[doc = "Field `tdmae` writer - "]
        pub type TdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rdmae(&self) -> RdmaeR {
                RdmaeR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn tdmae(&self) -> TdmaeR {
                TdmaeR::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rdmae(&mut self) -> RdmaeW<'_, IcDmaCrSpec> {
                RdmaeW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn tdmae(&mut self) -> TdmaeW<'_, IcDmaCrSpec> {
                TdmaeW::new(self, 1)
            }
        }
        #[doc = "IC_DMA_CR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcDmaCrSpec;
        impl crate::RegisterSpec for IcDmaCrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_dma_cr::R`](R) reader structure"]
        impl crate::Readable for IcDmaCrSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_dma_cr::W`](W) writer structure"]
        impl crate::Writable for IcDmaCrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_DMA_CR to value 0"]
        impl crate::Resettable for IcDmaCrSpec {}
    }
    #[doc = "IC_DMA_TDLR (rw) register accessor: IC_DMA_TDLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_tdlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_dma_tdlr`] module"]
    #[doc(alias = "IC_DMA_TDLR")]
    pub type IcDmaTdlr = crate::Reg<ic_dma_tdlr::IcDmaTdlrSpec>;
    #[doc = "IC_DMA_TDLR"]
    pub mod ic_dma_tdlr {
        #[doc = "Register `IC_DMA_TDLR` reader"]
        pub type R = crate::R<IcDmaTdlrSpec>;
        #[doc = "Register `IC_DMA_TDLR` writer"]
        pub type W = crate::W<IcDmaTdlrSpec>;
        #[doc = "Field `dmatdl` reader - "]
        pub type DmatdlR = crate::FieldReader;
        #[doc = "Field `dmatdl` writer - "]
        pub type DmatdlW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 0:5"]
            #[inline(always)]
            pub fn dmatdl(&self) -> DmatdlR {
                DmatdlR::new((self.bits & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:5"]
            #[inline(always)]
            pub fn dmatdl(&mut self) -> DmatdlW<'_, IcDmaTdlrSpec> {
                DmatdlW::new(self, 0)
            }
        }
        #[doc = "IC_DMA_TDLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_tdlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcDmaTdlrSpec;
        impl crate::RegisterSpec for IcDmaTdlrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_dma_tdlr::R`](R) reader structure"]
        impl crate::Readable for IcDmaTdlrSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_dma_tdlr::W`](W) writer structure"]
        impl crate::Writable for IcDmaTdlrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_DMA_TDLR to value 0"]
        impl crate::Resettable for IcDmaTdlrSpec {}
    }
    #[doc = "IC_DMA_RDLR (rw) register accessor: IC_DMA_RDLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_rdlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_dma_rdlr`] module"]
    #[doc(alias = "IC_DMA_RDLR")]
    pub type IcDmaRdlr = crate::Reg<ic_dma_rdlr::IcDmaRdlrSpec>;
    #[doc = "IC_DMA_RDLR"]
    pub mod ic_dma_rdlr {
        #[doc = "Register `IC_DMA_RDLR` reader"]
        pub type R = crate::R<IcDmaRdlrSpec>;
        #[doc = "Register `IC_DMA_RDLR` writer"]
        pub type W = crate::W<IcDmaRdlrSpec>;
        #[doc = "Field `dmardl` reader - "]
        pub type DmardlR = crate::FieldReader;
        #[doc = "Field `dmardl` writer - "]
        pub type DmardlW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 0:5"]
            #[inline(always)]
            pub fn dmardl(&self) -> DmardlR {
                DmardlR::new((self.bits & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:5"]
            #[inline(always)]
            pub fn dmardl(&mut self) -> DmardlW<'_, IcDmaRdlrSpec> {
                DmardlW::new(self, 0)
            }
        }
        #[doc = "IC_DMA_RDLR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_dma_rdlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcDmaRdlrSpec;
        impl crate::RegisterSpec for IcDmaRdlrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_dma_rdlr::R`](R) reader structure"]
        impl crate::Readable for IcDmaRdlrSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_dma_rdlr::W`](W) writer structure"]
        impl crate::Writable for IcDmaRdlrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_DMA_RDLR to value 0"]
        impl crate::Resettable for IcDmaRdlrSpec {}
    }
    #[doc = "IC_SDA_SETUP (rw) register accessor: IC_SDA_SETUP\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_sda_setup`] module"]
    #[doc(alias = "IC_SDA_SETUP")]
    pub type IcSdaSetup = crate::Reg<ic_sda_setup::IcSdaSetupSpec>;
    #[doc = "IC_SDA_SETUP"]
    pub mod ic_sda_setup {
        #[doc = "Register `IC_SDA_SETUP` reader"]
        pub type R = crate::R<IcSdaSetupSpec>;
        #[doc = "Register `IC_SDA_SETUP` writer"]
        pub type W = crate::W<IcSdaSetupSpec>;
        #[doc = "Field `sda_setup` reader - "]
        pub type SdaSetupR = crate::FieldReader;
        #[doc = "Field `sda_setup` writer - "]
        pub type SdaSetupW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn sda_setup(&self) -> SdaSetupR {
                SdaSetupR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn sda_setup(&mut self) -> SdaSetupW<'_, IcSdaSetupSpec> {
                SdaSetupW::new(self, 0)
            }
        }
        #[doc = "IC_SDA_SETUP\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_sda_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcSdaSetupSpec;
        impl crate::RegisterSpec for IcSdaSetupSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_sda_setup::R`](R) reader structure"]
        impl crate::Readable for IcSdaSetupSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_sda_setup::W`](W) writer structure"]
        impl crate::Writable for IcSdaSetupSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_SDA_SETUP to value 0"]
        impl crate::Resettable for IcSdaSetupSpec {}
    }
    #[doc = "IC_INTR_MASK (rw) register accessor: IC_INTR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_intr_mask`] module"]
    #[doc(alias = "IC_INTR_MASK")]
    pub type IcIntrMask = crate::Reg<ic_intr_mask::IcIntrMaskSpec>;
    #[doc = "IC_INTR_MASK"]
    pub mod ic_intr_mask {
        #[doc = "Register `IC_INTR_MASK` reader"]
        pub type R = crate::R<IcIntrMaskSpec>;
        #[doc = "Register `IC_INTR_MASK` writer"]
        pub type W = crate::W<IcIntrMaskSpec>;
        #[doc = "Field `rx_under` reader - "]
        pub type RxUnderR = crate::BitReader;
        #[doc = "Field `rx_under` writer - "]
        pub type RxUnderW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rx_over` reader - "]
        pub type RxOverR = crate::BitReader;
        #[doc = "Field `rx_over` writer - "]
        pub type RxOverW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rx_full` reader - "]
        pub type RxFullR = crate::BitReader;
        #[doc = "Field `rx_full` writer - "]
        pub type RxFullW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tx_over` reader - "]
        pub type TxOverR = crate::BitReader;
        #[doc = "Field `tx_over` writer - "]
        pub type TxOverW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tx_empty` reader - "]
        pub type TxEmptyR = crate::BitReader;
        #[doc = "Field `tx_empty` writer - "]
        pub type TxEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rd_req` reader - "]
        pub type RdReqR = crate::BitReader;
        #[doc = "Field `rd_req` writer - "]
        pub type RdReqW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tx_abrt` reader - "]
        pub type TxAbrtR = crate::BitReader;
        #[doc = "Field `tx_abrt` writer - "]
        pub type TxAbrtW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rx_done` reader - "]
        pub type RxDoneR = crate::BitReader;
        #[doc = "Field `rx_done` writer - "]
        pub type RxDoneW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `activity` reader - "]
        pub type ActivityR = crate::BitReader;
        #[doc = "Field `activity` writer - "]
        pub type ActivityW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `stop_det` reader - "]
        pub type StopDetR = crate::BitReader;
        #[doc = "Field `stop_det` writer - "]
        pub type StopDetW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `start_det` reader - "]
        pub type StartDetR = crate::BitReader;
        #[doc = "Field `start_det` writer - "]
        pub type StartDetW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `gen_call` reader - "]
        pub type GenCallR = crate::BitReader;
        #[doc = "Field `gen_call` writer - "]
        pub type GenCallW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `restart_det` reader - "]
        pub type RestartDetR = crate::BitReader;
        #[doc = "Field `restart_det` writer - "]
        pub type RestartDetW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rx_under(&self) -> RxUnderR {
                RxUnderR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn rx_over(&self) -> RxOverR {
                RxOverR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn rx_full(&self) -> RxFullR {
                RxFullR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn tx_over(&self) -> TxOverR {
                TxOverR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn tx_empty(&self) -> TxEmptyR {
                TxEmptyR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn rd_req(&self) -> RdReqR {
                RdReqR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn tx_abrt(&self) -> TxAbrtR {
                TxAbrtR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn rx_done(&self) -> RxDoneR {
                RxDoneR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn activity(&self) -> ActivityR {
                ActivityR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn stop_det(&self) -> StopDetR {
                StopDetR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn start_det(&self) -> StartDetR {
                StartDetR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn gen_call(&self) -> GenCallR {
                GenCallR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn restart_det(&self) -> RestartDetR {
                RestartDetR::new(((self.bits >> 12) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rx_under(&mut self) -> RxUnderW<'_, IcIntrMaskSpec> {
                RxUnderW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn rx_over(&mut self) -> RxOverW<'_, IcIntrMaskSpec> {
                RxOverW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn rx_full(&mut self) -> RxFullW<'_, IcIntrMaskSpec> {
                RxFullW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn tx_over(&mut self) -> TxOverW<'_, IcIntrMaskSpec> {
                TxOverW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn tx_empty(&mut self) -> TxEmptyW<'_, IcIntrMaskSpec> {
                TxEmptyW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn rd_req(&mut self) -> RdReqW<'_, IcIntrMaskSpec> {
                RdReqW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn tx_abrt(&mut self) -> TxAbrtW<'_, IcIntrMaskSpec> {
                TxAbrtW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn rx_done(&mut self) -> RxDoneW<'_, IcIntrMaskSpec> {
                RxDoneW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn activity(&mut self) -> ActivityW<'_, IcIntrMaskSpec> {
                ActivityW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn stop_det(&mut self) -> StopDetW<'_, IcIntrMaskSpec> {
                StopDetW::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn start_det(&mut self) -> StartDetW<'_, IcIntrMaskSpec> {
                StartDetW::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn gen_call(&mut self) -> GenCallW<'_, IcIntrMaskSpec> {
                GenCallW::new(self, 11)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn restart_det(&mut self) -> RestartDetW<'_, IcIntrMaskSpec> {
                RestartDetW::new(self, 12)
            }
        }
        #[doc = "IC_INTR_MASK\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcIntrMaskSpec;
        impl crate::RegisterSpec for IcIntrMaskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_intr_mask::R`](R) reader structure"]
        impl crate::Readable for IcIntrMaskSpec {}
        #[doc = "`write(|w| ..)` method takes [`ic_intr_mask::W`](W) writer structure"]
        impl crate::Writable for IcIntrMaskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets IC_INTR_MASK to value 0"]
        impl crate::Resettable for IcIntrMaskSpec {}
    }
    #[doc = "IC_INTR_STAT (r) register accessor: IC_INTR_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_intr_stat`] module"]
    #[doc(alias = "IC_INTR_STAT")]
    pub type IcIntrStat = crate::Reg<ic_intr_stat::IcIntrStatSpec>;
    #[doc = "IC_INTR_STAT"]
    pub mod ic_intr_stat {
        #[doc = "Register `IC_INTR_STAT` reader"]
        pub type R = crate::R<IcIntrStatSpec>;
        #[doc = "Field `rx_under` reader - "]
        pub type RxUnderR = crate::BitReader;
        #[doc = "Field `rx_over` reader - "]
        pub type RxOverR = crate::BitReader;
        #[doc = "Field `rx_full` reader - "]
        pub type RxFullR = crate::BitReader;
        #[doc = "Field `tx_over` reader - "]
        pub type TxOverR = crate::BitReader;
        #[doc = "Field `tx_empty` reader - "]
        pub type TxEmptyR = crate::BitReader;
        #[doc = "Field `rd_req` reader - "]
        pub type RdReqR = crate::BitReader;
        #[doc = "Field `tx_abrt` reader - "]
        pub type TxAbrtR = crate::BitReader;
        #[doc = "Field `rx_done` reader - "]
        pub type RxDoneR = crate::BitReader;
        #[doc = "Field `activity` reader - "]
        pub type ActivityR = crate::BitReader;
        #[doc = "Field `stop_det` reader - "]
        pub type StopDetR = crate::BitReader;
        #[doc = "Field `start_det` reader - "]
        pub type StartDetR = crate::BitReader;
        #[doc = "Field `gen_call` reader - "]
        pub type GenCallR = crate::BitReader;
        #[doc = "Field `restart_det` reader - "]
        pub type RestartDetR = crate::BitReader;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rx_under(&self) -> RxUnderR {
                RxUnderR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn rx_over(&self) -> RxOverR {
                RxOverR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn rx_full(&self) -> RxFullR {
                RxFullR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn tx_over(&self) -> TxOverR {
                TxOverR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn tx_empty(&self) -> TxEmptyR {
                TxEmptyR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn rd_req(&self) -> RdReqR {
                RdReqR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn tx_abrt(&self) -> TxAbrtR {
                TxAbrtR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn rx_done(&self) -> RxDoneR {
                RxDoneR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn activity(&self) -> ActivityR {
                ActivityR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn stop_det(&self) -> StopDetR {
                StopDetR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn start_det(&self) -> StartDetR {
                StartDetR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn gen_call(&self) -> GenCallR {
                GenCallR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn restart_det(&self) -> RestartDetR {
                RestartDetR::new(((self.bits >> 12) & 1) != 0)
            }
        }
        #[doc = "IC_INTR_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcIntrStatSpec;
        impl crate::RegisterSpec for IcIntrStatSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_intr_stat::R`](R) reader structure"]
        impl crate::Readable for IcIntrStatSpec {}
        #[doc = "`reset()` method sets IC_INTR_STAT to value 0"]
        impl crate::Resettable for IcIntrStatSpec {}
    }
    #[doc = "IC_RAW_INTR_STAT (r) register accessor: IC_RAW_INTR_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_raw_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_raw_intr_stat`] module"]
    #[doc(alias = "IC_RAW_INTR_STAT")]
    pub type IcRawIntrStat = crate::Reg<ic_raw_intr_stat::IcRawIntrStatSpec>;
    #[doc = "IC_RAW_INTR_STAT"]
    pub mod ic_raw_intr_stat {
        #[doc = "Register `IC_RAW_INTR_STAT` reader"]
        pub type R = crate::R<IcRawIntrStatSpec>;
        #[doc = "Field `rx_under` reader - "]
        pub type RxUnderR = crate::BitReader;
        #[doc = "Field `rx_over` reader - "]
        pub type RxOverR = crate::BitReader;
        #[doc = "Field `rx_full` reader - "]
        pub type RxFullR = crate::BitReader;
        #[doc = "Field `tx_over` reader - "]
        pub type TxOverR = crate::BitReader;
        #[doc = "Field `tx_empty` reader - "]
        pub type TxEmptyR = crate::BitReader;
        #[doc = "Field `rd_req` reader - "]
        pub type RdReqR = crate::BitReader;
        #[doc = "Field `tx_abrt` reader - "]
        pub type TxAbrtR = crate::BitReader;
        #[doc = "Field `rx_done` reader - "]
        pub type RxDoneR = crate::BitReader;
        #[doc = "Field `activity` reader - "]
        pub type ActivityR = crate::BitReader;
        #[doc = "Field `stop_det` reader - "]
        pub type StopDetR = crate::BitReader;
        #[doc = "Field `start_det` reader - "]
        pub type StartDetR = crate::BitReader;
        #[doc = "Field `gen_call` reader - "]
        pub type GenCallR = crate::BitReader;
        #[doc = "Field `restart_det` reader - "]
        pub type RestartDetR = crate::BitReader;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rx_under(&self) -> RxUnderR {
                RxUnderR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn rx_over(&self) -> RxOverR {
                RxOverR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn rx_full(&self) -> RxFullR {
                RxFullR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn tx_over(&self) -> TxOverR {
                TxOverR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn tx_empty(&self) -> TxEmptyR {
                TxEmptyR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn rd_req(&self) -> RdReqR {
                RdReqR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn tx_abrt(&self) -> TxAbrtR {
                TxAbrtR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn rx_done(&self) -> RxDoneR {
                RxDoneR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn activity(&self) -> ActivityR {
                ActivityR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn stop_det(&self) -> StopDetR {
                StopDetR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn start_det(&self) -> StartDetR {
                StartDetR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn gen_call(&self) -> GenCallR {
                GenCallR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn restart_det(&self) -> RestartDetR {
                RestartDetR::new(((self.bits >> 12) & 1) != 0)
            }
        }
        #[doc = "IC_RAW_INTR_STAT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_raw_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcRawIntrStatSpec;
        impl crate::RegisterSpec for IcRawIntrStatSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_raw_intr_stat::R`](R) reader structure"]
        impl crate::Readable for IcRawIntrStatSpec {}
        #[doc = "`reset()` method sets IC_RAW_INTR_STAT to value 0"]
        impl crate::Resettable for IcRawIntrStatSpec {}
    }
    #[doc = "IC_INTR_STAT_ALL (r) register accessor: IC_INTR_STAT_ALL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_stat_all::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_intr_stat_all`] module"]
    #[doc(alias = "IC_INTR_STAT_ALL")]
    pub type IcIntrStatAll = crate::Reg<ic_intr_stat_all::IcIntrStatAllSpec>;
    #[doc = "IC_INTR_STAT_ALL"]
    pub mod ic_intr_stat_all {
        #[doc = "Register `IC_INTR_STAT_ALL` reader"]
        pub type R = crate::R<IcIntrStatAllSpec>;
        #[doc = "Field `stat` reader - "]
        pub type StatR = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:12"]
            #[inline(always)]
            pub fn stat(&self) -> StatR {
                StatR::new((self.bits & 0x1fff) as u16)
            }
        }
        #[doc = "IC_INTR_STAT_ALL\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_intr_stat_all::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcIntrStatAllSpec;
        impl crate::RegisterSpec for IcIntrStatAllSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_intr_stat_all::R`](R) reader structure"]
        impl crate::Readable for IcIntrStatAllSpec {}
        #[doc = "`reset()` method sets IC_INTR_STAT_ALL to value 0"]
        impl crate::Resettable for IcIntrStatAllSpec {}
    }
    #[doc = "IC_CLR_INTR (r) register accessor: IC_CLR_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_clr_intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_clr_intr`] module"]
    #[doc(alias = "IC_CLR_INTR")]
    pub type IcClrIntr = crate::Reg<ic_clr_intr::IcClrIntrSpec>;
    #[doc = "IC_CLR_INTR"]
    pub mod ic_clr_intr {
        #[doc = "Register `IC_CLR_INTR` reader"]
        pub type R = crate::R<IcClrIntrSpec>;
        #[doc = "Field `clr` reader - read-to-clear all"]
        pub type ClrR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - read-to-clear all"]
            #[inline(always)]
            pub fn clr(&self) -> ClrR {
                ClrR::new((self.bits & 1) != 0)
            }
        }
        #[doc = "IC_CLR_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_clr_intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcClrIntrSpec;
        impl crate::RegisterSpec for IcClrIntrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_clr_intr::R`](R) reader structure"]
        impl crate::Readable for IcClrIntrSpec {}
        #[doc = "`reset()` method sets IC_CLR_INTR to value 0"]
        impl crate::Resettable for IcClrIntrSpec {}
    }
    #[doc = "IC_CLR_INT (r) register accessor: IC_CLR_INT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_clr_int::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_clr_int`] module"]
    #[doc(alias = "IC_CLR_INT")]
    pub type IcClrInt = crate::Reg<ic_clr_int::IcClrIntSpec>;
    #[doc = "IC_CLR_INT"]
    pub mod ic_clr_int {
        #[doc = "Register `IC_CLR_INT` reader"]
        pub type R = crate::R<IcClrIntSpec>;
        #[doc = "Field `clr` reader - read-to-clear combined"]
        pub type ClrR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - read-to-clear combined"]
            #[inline(always)]
            pub fn clr(&self) -> ClrR {
                ClrR::new((self.bits & 1) != 0)
            }
        }
        #[doc = "IC_CLR_INT\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_clr_int::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IcClrIntSpec;
        impl crate::RegisterSpec for IcClrIntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ic_clr_int::R`](R) reader structure"]
        impl crate::Readable for IcClrIntSpec {}
        #[doc = "`reset()` method sets IC_CLR_INT to value 0"]
        impl crate::Resettable for IcClrIntSpec {}
    }
}
#[doc = "SPI0 master/slave controller (SSI v151)"]
pub type Spi0 = crate::Periph<spi0::RegisterBlock, 0x5208_7000>;
impl core::fmt::Debug for Spi0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Spi0").finish()
    }
}
#[doc = "SPI0 master/slave controller (SSI v151)"]
pub mod spi0 {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        spi_er: SpiEr,
        spi_ctra: SpiCtra,
        spi_ctrb: SpiCtrb,
        spi_enhctl: SpiEnhctl,
        _reserved4: [u8; 0x04],
        spi_brs: SpiBrs,
        spi_dcr: SpiDcr,
        spi_drdl: SpiDrdl,
        spi_dtdl: SpiDtdl,
        _reserved8: [u8; 0x3c],
        spi_dr: SpiDr,
        _reserved9: [u8; 0x58],
        spi_rainsr: SpiRainsr,
        spi_insr: SpiInsr,
        spi_inmar: SpiInmar,
        spi_slenr: SpiSlenr,
        spi_twlr: SpiTwlr,
        spi_tlr: SpiTlr,
        _reserved15: [u8; 0x04],
        spi_rwlr: SpiRwlr,
        spi_rlr: SpiRlr,
        _reserved17: [u8; 0x04],
        spi_wsr: SpiWsr,
        _reserved18: [u8; 0x10],
        spi_icr: SpiIcr,
    }
    impl RegisterBlock {
        #[doc = "0x00 - SPI enable register"]
        #[inline(always)]
        pub const fn spi_er(&self) -> &SpiEr {
            &self.spi_er
        }
        #[doc = "0x04 - SPI control register 0"]
        #[inline(always)]
        pub const fn spi_ctra(&self) -> &SpiCtra {
            &self.spi_ctra
        }
        #[doc = "0x08 - SPI control register 1 (master only)"]
        #[inline(always)]
        pub const fn spi_ctrb(&self) -> &SpiCtrb {
            &self.spi_ctrb
        }
        #[doc = "0x0c - Enhanced control register (Dual/Quad/Octal)"]
        #[inline(always)]
        pub const fn spi_enhctl(&self) -> &SpiEnhctl {
            &self.spi_enhctl
        }
        #[doc = "0x14 - Baud rate select register"]
        #[inline(always)]
        pub const fn spi_brs(&self) -> &SpiBrs {
            &self.spi_brs
        }
        #[doc = "0x18 - DMA control register"]
        #[inline(always)]
        pub const fn spi_dcr(&self) -> &SpiDcr {
            &self.spi_dcr
        }
        #[doc = "0x1c - DMA RX data level"]
        #[inline(always)]
        pub const fn spi_drdl(&self) -> &SpiDrdl {
            &self.spi_drdl
        }
        #[doc = "0x20 - DMA TX data level"]
        #[inline(always)]
        pub const fn spi_dtdl(&self) -> &SpiDtdl {
            &self.spi_dtdl
        }
        #[doc = "0x60 - Data register (FIFO read/write)"]
        #[inline(always)]
        pub const fn spi_dr(&self) -> &SpiDr {
            &self.spi_dr
        }
        #[doc = "0xbc - Raw interrupt status register"]
        #[inline(always)]
        pub const fn spi_rainsr(&self) -> &SpiRainsr {
            &self.spi_rainsr
        }
        #[doc = "0xc0 - Interrupt status register (masked)"]
        #[inline(always)]
        pub const fn spi_insr(&self) -> &SpiInsr {
            &self.spi_insr
        }
        #[doc = "0xc4 - Interrupt mask register"]
        #[inline(always)]
        pub const fn spi_inmar(&self) -> &SpiInmar {
            &self.spi_inmar
        }
        #[doc = "0xc8 - Slave enable register (master only)"]
        #[inline(always)]
        pub const fn spi_slenr(&self) -> &SpiSlenr {
            &self.spi_slenr
        }
        #[doc = "0xcc - TX FIFO threshold level"]
        #[inline(always)]
        pub const fn spi_twlr(&self) -> &SpiTwlr {
            &self.spi_twlr
        }
        #[doc = "0xd0 - TX FIFO level register"]
        #[inline(always)]
        pub const fn spi_tlr(&self) -> &SpiTlr {
            &self.spi_tlr
        }
        #[doc = "0xd8 - RX FIFO threshold level"]
        #[inline(always)]
        pub const fn spi_rwlr(&self) -> &SpiRwlr {
            &self.spi_rwlr
        }
        #[doc = "0xdc - RX FIFO level register"]
        #[inline(always)]
        pub const fn spi_rlr(&self) -> &SpiRlr {
            &self.spi_rlr
        }
        #[doc = "0xe4 - Status register"]
        #[inline(always)]
        pub const fn spi_wsr(&self) -> &SpiWsr {
            &self.spi_wsr
        }
        #[doc = "0xf8 - Interrupt clear register"]
        #[inline(always)]
        pub const fn spi_icr(&self) -> &SpiIcr {
            &self.spi_icr
        }
    }
    #[doc = "SPI_ER (rw) register accessor: SPI enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_er::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_er::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_er`] module"]
    #[doc(alias = "SPI_ER")]
    pub type SpiEr = crate::Reg<spi_er::SpiErSpec>;
    #[doc = "SPI enable register"]
    pub mod spi_er {
        #[doc = "Register `SPI_ER` reader"]
        pub type R = crate::R<SpiErSpec>;
        #[doc = "Register `SPI_ER` writer"]
        pub type W = crate::W<SpiErSpec>;
        #[doc = "Field `spi_en` reader - SPI enable: 0=disabled; 1=enabled"]
        pub type SpiEnR = crate::BitReader;
        #[doc = "Field `spi_en` writer - SPI enable: 0=disabled; 1=enabled"]
        pub type SpiEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - SPI enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn spi_en(&self) -> SpiEnR {
                SpiEnR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - SPI enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn spi_en(&mut self) -> SpiEnW<'_, SpiErSpec> {
                SpiEnW::new(self, 0)
            }
        }
        #[doc = "SPI enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_er::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_er::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiErSpec;
        impl crate::RegisterSpec for SpiErSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_er::R`](R) reader structure"]
        impl crate::Readable for SpiErSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_er::W`](W) writer structure"]
        impl crate::Writable for SpiErSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_ER to value 0"]
        impl crate::Resettable for SpiErSpec {}
    }
    #[doc = "SPI_CTRA (rw) register accessor: SPI control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctra::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctra::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctra`] module"]
    #[doc(alias = "SPI_CTRA")]
    pub type SpiCtra = crate::Reg<spi_ctra::SpiCtraSpec>;
    #[doc = "SPI control register 0"]
    pub mod spi_ctra {
        #[doc = "Register `SPI_CTRA` reader"]
        pub type R = crate::R<SpiCtraSpec>;
        #[doc = "Register `SPI_CTRA` writer"]
        pub type W = crate::W<SpiCtraSpec>;
        #[doc = "Field `soe` reader - Shift register loop test: 0=normal; 1=loopback"]
        pub type SoeR = crate::BitReader;
        #[doc = "Field `soe` writer - Shift register loop test: 0=normal; 1=loopback"]
        pub type SoeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Clock phase: 0=first edge sample; 1=second edge sample\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum Scph {
            #[doc = "0: Sample on first clock edge"]
            FirstEdge = 0,
            #[doc = "1: Sample on second clock edge"]
            SecondEdge = 1,
        }
        impl From<Scph> for bool {
            #[inline(always)]
            fn from(variant: Scph) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `scph` reader - Clock phase: 0=first edge sample; 1=second edge sample"]
        pub type ScphR = crate::BitReader<Scph>;
        impl ScphR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Scph {
                match self.bits {
                    false => Scph::FirstEdge,
                    true => Scph::SecondEdge,
                }
            }
            #[doc = "Sample on first clock edge"]
            #[inline(always)]
            pub fn is_first_edge(&self) -> bool {
                *self == Scph::FirstEdge
            }
            #[doc = "Sample on second clock edge"]
            #[inline(always)]
            pub fn is_second_edge(&self) -> bool {
                *self == Scph::SecondEdge
            }
        }
        #[doc = "Field `scph` writer - Clock phase: 0=first edge sample; 1=second edge sample"]
        pub type ScphW<'a, REG> = crate::BitWriter<'a, REG, Scph>;
        impl<'a, REG> ScphW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Sample on first clock edge"]
            #[inline(always)]
            pub fn first_edge(self) -> &'a mut crate::W<REG> {
                self.variant(Scph::FirstEdge)
            }
            #[doc = "Sample on second clock edge"]
            #[inline(always)]
            pub fn second_edge(self) -> &'a mut crate::W<REG> {
                self.variant(Scph::SecondEdge)
            }
        }
        #[doc = "Clock polarity: 0=low idle; 1=high idle\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum Scpol {
            #[doc = "0: SCK idle low"]
            LowIdle = 0,
            #[doc = "1: SCK idle high"]
            HighIdle = 1,
        }
        impl From<Scpol> for bool {
            #[inline(always)]
            fn from(variant: Scpol) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `scpol` reader - Clock polarity: 0=low idle; 1=high idle"]
        pub type ScpolR = crate::BitReader<Scpol>;
        impl ScpolR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Scpol {
                match self.bits {
                    false => Scpol::LowIdle,
                    true => Scpol::HighIdle,
                }
            }
            #[doc = "SCK idle low"]
            #[inline(always)]
            pub fn is_low_idle(&self) -> bool {
                *self == Scpol::LowIdle
            }
            #[doc = "SCK idle high"]
            #[inline(always)]
            pub fn is_high_idle(&self) -> bool {
                *self == Scpol::HighIdle
            }
        }
        #[doc = "Field `scpol` writer - Clock polarity: 0=low idle; 1=high idle"]
        pub type ScpolW<'a, REG> = crate::BitWriter<'a, REG, Scpol>;
        impl<'a, REG> ScpolW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "SCK idle low"]
            #[inline(always)]
            pub fn low_idle(self) -> &'a mut crate::W<REG> {
                self.variant(Scpol::LowIdle)
            }
            #[doc = "SCK idle high"]
            #[inline(always)]
            pub fn high_idle(self) -> &'a mut crate::W<REG> {
                self.variant(Scpol::HighIdle)
            }
        }
        #[doc = "Field `dfs32` reader - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
        pub type Dfs32R = crate::FieldReader;
        #[doc = "Field `dfs32` writer - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
        pub type Dfs32W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Transfer mode: 00=TX/RX; 01=TX only; 10=RX only\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum Trsm {
            #[doc = "0: Transmit and Receive"]
            TxRx = 0,
            #[doc = "1: Transmit Only"]
            TxOnly = 1,
            #[doc = "2: Receive Only"]
            RxOnly = 2,
        }
        impl From<Trsm> for u8 {
            #[inline(always)]
            fn from(variant: Trsm) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for Trsm {
            type Ux = u8;
        }
        impl crate::IsEnum for Trsm {}
        #[doc = "Field `trsm` reader - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
        pub type TrsmR = crate::FieldReader<Trsm>;
        impl TrsmR {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Option<Trsm> {
                match self.bits {
                    0 => Some(Trsm::TxRx),
                    1 => Some(Trsm::TxOnly),
                    2 => Some(Trsm::RxOnly),
                    _ => None,
                }
            }
            #[doc = "Transmit and Receive"]
            #[inline(always)]
            pub fn is_tx_rx(&self) -> bool {
                *self == Trsm::TxRx
            }
            #[doc = "Transmit Only"]
            #[inline(always)]
            pub fn is_tx_only(&self) -> bool {
                *self == Trsm::TxOnly
            }
            #[doc = "Receive Only"]
            #[inline(always)]
            pub fn is_rx_only(&self) -> bool {
                *self == Trsm::RxOnly
            }
        }
        #[doc = "Field `trsm` writer - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
        pub type TrsmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trsm>;
        impl<'a, REG> TrsmW<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "Transmit and Receive"]
            #[inline(always)]
            pub fn tx_rx(self) -> &'a mut crate::W<REG> {
                self.variant(Trsm::TxRx)
            }
            #[doc = "Transmit Only"]
            #[inline(always)]
            pub fn tx_only(self) -> &'a mut crate::W<REG> {
                self.variant(Trsm::TxOnly)
            }
            #[doc = "Receive Only"]
            #[inline(always)]
            pub fn rx_only(self) -> &'a mut crate::W<REG> {
                self.variant(Trsm::RxOnly)
            }
        }
        impl R {
            #[doc = "Bit 0 - Shift register loop test: 0=normal; 1=loopback"]
            #[inline(always)]
            pub fn soe(&self) -> SoeR {
                SoeR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 3 - Clock phase: 0=first edge sample; 1=second edge sample"]
            #[inline(always)]
            pub fn scph(&self) -> ScphR {
                ScphR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Clock polarity: 0=low idle; 1=high idle"]
            #[inline(always)]
            pub fn scpol(&self) -> ScpolR {
                ScpolR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bits 13:17 - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
            #[inline(always)]
            pub fn dfs32(&self) -> Dfs32R {
                Dfs32R::new(((self.bits >> 13) & 0x1f) as u8)
            }
            #[doc = "Bits 18:19 - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
            #[inline(always)]
            pub fn trsm(&self) -> TrsmR {
                TrsmR::new(((self.bits >> 18) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - Shift register loop test: 0=normal; 1=loopback"]
            #[inline(always)]
            pub fn soe(&mut self) -> SoeW<'_, SpiCtraSpec> {
                SoeW::new(self, 0)
            }
            #[doc = "Bit 3 - Clock phase: 0=first edge sample; 1=second edge sample"]
            #[inline(always)]
            pub fn scph(&mut self) -> ScphW<'_, SpiCtraSpec> {
                ScphW::new(self, 3)
            }
            #[doc = "Bit 4 - Clock polarity: 0=low idle; 1=high idle"]
            #[inline(always)]
            pub fn scpol(&mut self) -> ScpolW<'_, SpiCtraSpec> {
                ScpolW::new(self, 4)
            }
            #[doc = "Bits 13:17 - Data frame size in 32-bit mode (0=4bit; up to 31=35bit)"]
            #[inline(always)]
            pub fn dfs32(&mut self) -> Dfs32W<'_, SpiCtraSpec> {
                Dfs32W::new(self, 13)
            }
            #[doc = "Bits 18:19 - Transfer mode: 00=TX/RX; 01=TX only; 10=RX only"]
            #[inline(always)]
            pub fn trsm(&mut self) -> TrsmW<'_, SpiCtraSpec> {
                TrsmW::new(self, 18)
            }
        }
        #[doc = "SPI control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctra::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctra::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiCtraSpec;
        impl crate::RegisterSpec for SpiCtraSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_ctra::R`](R) reader structure"]
        impl crate::Readable for SpiCtraSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_ctra::W`](W) writer structure"]
        impl crate::Writable for SpiCtraSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_CTRA to value 0"]
        impl crate::Resettable for SpiCtraSpec {}
    }
    #[doc = "SPI_CTRB (rw) register accessor: SPI control register 1 (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctrb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrb`] module"]
    #[doc(alias = "SPI_CTRB")]
    pub type SpiCtrb = crate::Reg<spi_ctrb::SpiCtrbSpec>;
    #[doc = "SPI control register 1 (master only)"]
    pub mod spi_ctrb {
        #[doc = "Register `SPI_CTRB` reader"]
        pub type R = crate::R<SpiCtrbSpec>;
        #[doc = "Register `SPI_CTRB` writer"]
        pub type W = crate::W<SpiCtrbSpec>;
        #[doc = "Field `ndf` reader - Number of data frames (master TX only mode)"]
        pub type NdfR = crate::FieldReader<u16>;
        #[doc = "Field `ndf` writer - Number of data frames (master TX only mode)"]
        pub type NdfW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `ssi_clk_stretch_en` reader - Clock stretch enable"]
        pub type SsiClkStretchEnR = crate::BitReader;
        #[doc = "Field `ssi_clk_stretch_en` writer - Clock stretch enable"]
        pub type SsiClkStretchEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:15 - Number of data frames (master TX only mode)"]
            #[inline(always)]
            pub fn ndf(&self) -> NdfR {
                NdfR::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bit 27 - Clock stretch enable"]
            #[inline(always)]
            pub fn ssi_clk_stretch_en(&self) -> SsiClkStretchEnR {
                SsiClkStretchEnR::new(((self.bits >> 27) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Number of data frames (master TX only mode)"]
            #[inline(always)]
            pub fn ndf(&mut self) -> NdfW<'_, SpiCtrbSpec> {
                NdfW::new(self, 0)
            }
            #[doc = "Bit 27 - Clock stretch enable"]
            #[inline(always)]
            pub fn ssi_clk_stretch_en(&mut self) -> SsiClkStretchEnW<'_, SpiCtrbSpec> {
                SsiClkStretchEnW::new(self, 27)
            }
        }
        #[doc = "SPI control register 1 (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_ctrb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_ctrb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiCtrbSpec;
        impl crate::RegisterSpec for SpiCtrbSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_ctrb::R`](R) reader structure"]
        impl crate::Readable for SpiCtrbSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_ctrb::W`](W) writer structure"]
        impl crate::Writable for SpiCtrbSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_CTRB to value 0"]
        impl crate::Resettable for SpiCtrbSpec {}
    }
    #[doc = "SPI_ENHCTL (rw) register accessor: Enhanced control register (Dual/Quad/Octal)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_enhctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_enhctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_enhctl`] module"]
    #[doc(alias = "SPI_ENHCTL")]
    pub type SpiEnhctl = crate::Reg<spi_enhctl::SpiEnhctlSpec>;
    #[doc = "Enhanced control register (Dual/Quad/Octal)"]
    pub mod spi_enhctl {
        #[doc = "Register `SPI_ENHCTL` reader"]
        pub type R = crate::R<SpiEnhctlSpec>;
        #[doc = "Register `SPI_ENHCTL` writer"]
        pub type W = crate::W<SpiEnhctlSpec>;
        #[doc = "Field `spi_dual_en` reader - Dual SPI mode enable"]
        pub type SpiDualEnR = crate::BitReader;
        #[doc = "Field `spi_dual_en` writer - Dual SPI mode enable"]
        pub type SpiDualEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `spi_quad_en` reader - Quad SPI mode enable"]
        pub type SpiQuadEnR = crate::BitReader;
        #[doc = "Field `spi_quad_en` writer - Quad SPI mode enable"]
        pub type SpiQuadEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `spi_oct_en` reader - Octal SPI mode enable"]
        pub type SpiOctEnR = crate::BitReader;
        #[doc = "Field `spi_oct_en` writer - Octal SPI mode enable"]
        pub type SpiOctEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Dual SPI mode enable"]
            #[inline(always)]
            pub fn spi_dual_en(&self) -> SpiDualEnR {
                SpiDualEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Quad SPI mode enable"]
            #[inline(always)]
            pub fn spi_quad_en(&self) -> SpiQuadEnR {
                SpiQuadEnR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Octal SPI mode enable"]
            #[inline(always)]
            pub fn spi_oct_en(&self) -> SpiOctEnR {
                SpiOctEnR::new(((self.bits >> 2) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Dual SPI mode enable"]
            #[inline(always)]
            pub fn spi_dual_en(&mut self) -> SpiDualEnW<'_, SpiEnhctlSpec> {
                SpiDualEnW::new(self, 0)
            }
            #[doc = "Bit 1 - Quad SPI mode enable"]
            #[inline(always)]
            pub fn spi_quad_en(&mut self) -> SpiQuadEnW<'_, SpiEnhctlSpec> {
                SpiQuadEnW::new(self, 1)
            }
            #[doc = "Bit 2 - Octal SPI mode enable"]
            #[inline(always)]
            pub fn spi_oct_en(&mut self) -> SpiOctEnW<'_, SpiEnhctlSpec> {
                SpiOctEnW::new(self, 2)
            }
        }
        #[doc = "Enhanced control register (Dual/Quad/Octal)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_enhctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_enhctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiEnhctlSpec;
        impl crate::RegisterSpec for SpiEnhctlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_enhctl::R`](R) reader structure"]
        impl crate::Readable for SpiEnhctlSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_enhctl::W`](W) writer structure"]
        impl crate::Writable for SpiEnhctlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_ENHCTL to value 0"]
        impl crate::Resettable for SpiEnhctlSpec {}
    }
    #[doc = "SPI_BRS (rw) register accessor: Baud rate select register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_brs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_brs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_brs`] module"]
    #[doc(alias = "SPI_BRS")]
    pub type SpiBrs = crate::Reg<spi_brs::SpiBrsSpec>;
    #[doc = "Baud rate select register"]
    pub mod spi_brs {
        #[doc = "Register `SPI_BRS` reader"]
        pub type R = crate::R<SpiBrsSpec>;
        #[doc = "Register `SPI_BRS` writer"]
        pub type W = crate::W<SpiBrsSpec>;
        #[doc = "Field `clk_div` reader - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
        pub type ClkDivR = crate::FieldReader<u16>;
        #[doc = "Field `clk_div` writer - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
        pub type ClkDivW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
            #[inline(always)]
            pub fn clk_div(&self) -> ClkDivR {
                ClkDivR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Clock divider (master): SCK = SSI_CLK / (2 * (1 + CLK_DIV))"]
            #[inline(always)]
            pub fn clk_div(&mut self) -> ClkDivW<'_, SpiBrsSpec> {
                ClkDivW::new(self, 0)
            }
        }
        #[doc = "Baud rate select register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_brs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_brs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiBrsSpec;
        impl crate::RegisterSpec for SpiBrsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_brs::R`](R) reader structure"]
        impl crate::Readable for SpiBrsSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_brs::W`](W) writer structure"]
        impl crate::Writable for SpiBrsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_BRS to value 0"]
        impl crate::Resettable for SpiBrsSpec {}
    }
    #[doc = "SPI_DCR (rw) register accessor: DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dcr`] module"]
    #[doc(alias = "SPI_DCR")]
    pub type SpiDcr = crate::Reg<spi_dcr::SpiDcrSpec>;
    #[doc = "DMA control register"]
    pub mod spi_dcr {
        #[doc = "Register `SPI_DCR` reader"]
        pub type R = crate::R<SpiDcrSpec>;
        #[doc = "Register `SPI_DCR` writer"]
        pub type W = crate::W<SpiDcrSpec>;
        #[doc = "Field `tdmae` reader - TX DMA enable"]
        pub type TdmaeR = crate::BitReader;
        #[doc = "Field `tdmae` writer - TX DMA enable"]
        pub type TdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rdmae` reader - RX DMA enable"]
        pub type RdmaeR = crate::BitReader;
        #[doc = "Field `rdmae` writer - RX DMA enable"]
        pub type RdmaeW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - TX DMA enable"]
            #[inline(always)]
            pub fn tdmae(&self) -> TdmaeR {
                TdmaeR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - RX DMA enable"]
            #[inline(always)]
            pub fn rdmae(&self) -> RdmaeR {
                RdmaeR::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - TX DMA enable"]
            #[inline(always)]
            pub fn tdmae(&mut self) -> TdmaeW<'_, SpiDcrSpec> {
                TdmaeW::new(self, 0)
            }
            #[doc = "Bit 1 - RX DMA enable"]
            #[inline(always)]
            pub fn rdmae(&mut self) -> RdmaeW<'_, SpiDcrSpec> {
                RdmaeW::new(self, 1)
            }
        }
        #[doc = "DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiDcrSpec;
        impl crate::RegisterSpec for SpiDcrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_dcr::R`](R) reader structure"]
        impl crate::Readable for SpiDcrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_dcr::W`](W) writer structure"]
        impl crate::Writable for SpiDcrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_DCR to value 0"]
        impl crate::Resettable for SpiDcrSpec {}
    }
    #[doc = "SPI_DRDL (rw) register accessor: DMA RX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_drdl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_drdl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_drdl`] module"]
    #[doc(alias = "SPI_DRDL")]
    pub type SpiDrdl = crate::Reg<spi_drdl::SpiDrdlSpec>;
    #[doc = "DMA RX data level"]
    pub mod spi_drdl {
        #[doc = "Register `SPI_DRDL` reader"]
        pub type R = crate::R<SpiDrdlSpec>;
        #[doc = "Register `SPI_DRDL` writer"]
        pub type W = crate::W<SpiDrdlSpec>;
        #[doc = "Field `dma_rx_data_level` reader - DMA RX FIFO threshold"]
        pub type DmaRxDataLevelR = crate::FieldReader;
        #[doc = "Field `dma_rx_data_level` writer - DMA RX FIFO threshold"]
        pub type DmaRxDataLevelW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - DMA RX FIFO threshold"]
            #[inline(always)]
            pub fn dma_rx_data_level(&self) -> DmaRxDataLevelR {
                DmaRxDataLevelR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - DMA RX FIFO threshold"]
            #[inline(always)]
            pub fn dma_rx_data_level(&mut self) -> DmaRxDataLevelW<'_, SpiDrdlSpec> {
                DmaRxDataLevelW::new(self, 0)
            }
        }
        #[doc = "DMA RX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_drdl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_drdl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiDrdlSpec;
        impl crate::RegisterSpec for SpiDrdlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_drdl::R`](R) reader structure"]
        impl crate::Readable for SpiDrdlSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_drdl::W`](W) writer structure"]
        impl crate::Writable for SpiDrdlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_DRDL to value 0"]
        impl crate::Resettable for SpiDrdlSpec {}
    }
    #[doc = "SPI_DTDL (rw) register accessor: DMA TX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dtdl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dtdl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dtdl`] module"]
    #[doc(alias = "SPI_DTDL")]
    pub type SpiDtdl = crate::Reg<spi_dtdl::SpiDtdlSpec>;
    #[doc = "DMA TX data level"]
    pub mod spi_dtdl {
        #[doc = "Register `SPI_DTDL` reader"]
        pub type R = crate::R<SpiDtdlSpec>;
        #[doc = "Register `SPI_DTDL` writer"]
        pub type W = crate::W<SpiDtdlSpec>;
        #[doc = "Field `dma_tx_data_level` reader - DMA TX FIFO threshold"]
        pub type DmaTxDataLevelR = crate::FieldReader;
        #[doc = "Field `dma_tx_data_level` writer - DMA TX FIFO threshold"]
        pub type DmaTxDataLevelW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - DMA TX FIFO threshold"]
            #[inline(always)]
            pub fn dma_tx_data_level(&self) -> DmaTxDataLevelR {
                DmaTxDataLevelR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - DMA TX FIFO threshold"]
            #[inline(always)]
            pub fn dma_tx_data_level(&mut self) -> DmaTxDataLevelW<'_, SpiDtdlSpec> {
                DmaTxDataLevelW::new(self, 0)
            }
        }
        #[doc = "DMA TX data level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dtdl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dtdl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiDtdlSpec;
        impl crate::RegisterSpec for SpiDtdlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_dtdl::R`](R) reader structure"]
        impl crate::Readable for SpiDtdlSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_dtdl::W`](W) writer structure"]
        impl crate::Writable for SpiDtdlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_DTDL to value 0"]
        impl crate::Resettable for SpiDtdlSpec {}
    }
    #[doc = "SPI_DR (rw) register accessor: Data register (FIFO read/write)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dr`] module"]
    #[doc(alias = "SPI_DR")]
    pub type SpiDr = crate::Reg<spi_dr::SpiDrSpec>;
    #[doc = "Data register (FIFO read/write)"]
    pub mod spi_dr {
        #[doc = "Register `SPI_DR` reader"]
        pub type R = crate::R<SpiDrSpec>;
        #[doc = "Register `SPI_DR` writer"]
        pub type W = crate::W<SpiDrSpec>;
        #[doc = "Field `dr` reader - Write: push to TX FIFO; Read: pop from RX FIFO"]
        pub type DrR = crate::FieldReader<u32>;
        #[doc = "Field `dr` writer - Write: push to TX FIFO; Read: pop from RX FIFO"]
        pub type DrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Write: push to TX FIFO; Read: pop from RX FIFO"]
            #[inline(always)]
            pub fn dr(&self) -> DrR {
                DrR::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Write: push to TX FIFO; Read: pop from RX FIFO"]
            #[inline(always)]
            pub fn dr(&mut self) -> DrW<'_, SpiDrSpec> {
                DrW::new(self, 0)
            }
        }
        #[doc = "Data register (FIFO read/write)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_dr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_dr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiDrSpec;
        impl crate::RegisterSpec for SpiDrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_dr::R`](R) reader structure"]
        impl crate::Readable for SpiDrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_dr::W`](W) writer structure"]
        impl crate::Writable for SpiDrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_DR to value 0"]
        impl crate::Resettable for SpiDrSpec {}
    }
    #[doc = "SPI_RAINSR (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rainsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rainsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rainsr`] module"]
    #[doc(alias = "SPI_RAINSR")]
    pub type SpiRainsr = crate::Reg<spi_rainsr::SpiRainsrSpec>;
    #[doc = "Raw interrupt status register"]
    pub mod spi_rainsr {
        #[doc = "Register `SPI_RAINSR` reader"]
        pub type R = crate::R<SpiRainsrSpec>;
        #[doc = "Register `SPI_RAINSR` writer"]
        pub type W = crate::W<SpiRainsrSpec>;
        #[doc = "Field `txe_irq` reader - TX FIFO empty raw status"]
        pub type TxeIrqR = crate::BitReader;
        #[doc = "Field `txo_irq` reader - TX FIFO overflow raw status"]
        pub type TxoIrqR = crate::BitReader;
        #[doc = "Field `rxu_irq` reader - RX FIFO underflow raw status"]
        pub type RxuIrqR = crate::BitReader;
        #[doc = "Field `rxo_irq` reader - RX FIFO overflow raw status"]
        pub type RxoIrqR = crate::BitReader;
        #[doc = "Field `rxf_irq` reader - RX FIFO full raw status"]
        pub type RxfIrqR = crate::BitReader;
        #[doc = "Field `mst_irq` reader - Multi-master contention raw status"]
        pub type MstIrqR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - TX FIFO empty raw status"]
            #[inline(always)]
            pub fn txe_irq(&self) -> TxeIrqR {
                TxeIrqR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TX FIFO overflow raw status"]
            #[inline(always)]
            pub fn txo_irq(&self) -> TxoIrqR {
                TxoIrqR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - RX FIFO underflow raw status"]
            #[inline(always)]
            pub fn rxu_irq(&self) -> RxuIrqR {
                RxuIrqR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - RX FIFO overflow raw status"]
            #[inline(always)]
            pub fn rxo_irq(&self) -> RxoIrqR {
                RxoIrqR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - RX FIFO full raw status"]
            #[inline(always)]
            pub fn rxf_irq(&self) -> RxfIrqR {
                RxfIrqR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Multi-master contention raw status"]
            #[inline(always)]
            pub fn mst_irq(&self) -> MstIrqR {
                MstIrqR::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rainsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rainsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiRainsrSpec;
        impl crate::RegisterSpec for SpiRainsrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_rainsr::R`](R) reader structure"]
        impl crate::Readable for SpiRainsrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_rainsr::W`](W) writer structure"]
        impl crate::Writable for SpiRainsrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_RAINSR to value 0"]
        impl crate::Resettable for SpiRainsrSpec {}
    }
    #[doc = "SPI_INSR (rw) register accessor: Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_insr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_insr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_insr`] module"]
    #[doc(alias = "SPI_INSR")]
    pub type SpiInsr = crate::Reg<spi_insr::SpiInsrSpec>;
    #[doc = "Interrupt status register (masked)"]
    pub mod spi_insr {
        #[doc = "Register `SPI_INSR` reader"]
        pub type R = crate::R<SpiInsrSpec>;
        #[doc = "Register `SPI_INSR` writer"]
        pub type W = crate::W<SpiInsrSpec>;
        #[doc = "Field `txe_is` reader - TX empty interrupt status"]
        pub type TxeIsR = crate::BitReader;
        #[doc = "Field `txo_is` reader - TX overflow interrupt status"]
        pub type TxoIsR = crate::BitReader;
        #[doc = "Field `rxu_is` reader - RX underflow interrupt status"]
        pub type RxuIsR = crate::BitReader;
        #[doc = "Field `rxo_is` reader - RX overflow interrupt status"]
        pub type RxoIsR = crate::BitReader;
        #[doc = "Field `rxf_is` reader - RX full interrupt status"]
        pub type RxfIsR = crate::BitReader;
        #[doc = "Field `mst_is` reader - Multi-master interrupt status"]
        pub type MstIsR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - TX empty interrupt status"]
            #[inline(always)]
            pub fn txe_is(&self) -> TxeIsR {
                TxeIsR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TX overflow interrupt status"]
            #[inline(always)]
            pub fn txo_is(&self) -> TxoIsR {
                TxoIsR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - RX underflow interrupt status"]
            #[inline(always)]
            pub fn rxu_is(&self) -> RxuIsR {
                RxuIsR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - RX overflow interrupt status"]
            #[inline(always)]
            pub fn rxo_is(&self) -> RxoIsR {
                RxoIsR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - RX full interrupt status"]
            #[inline(always)]
            pub fn rxf_is(&self) -> RxfIsR {
                RxfIsR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Multi-master interrupt status"]
            #[inline(always)]
            pub fn mst_is(&self) -> MstIsR {
                MstIsR::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Interrupt status register (masked)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_insr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_insr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiInsrSpec;
        impl crate::RegisterSpec for SpiInsrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_insr::R`](R) reader structure"]
        impl crate::Readable for SpiInsrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_insr::W`](W) writer structure"]
        impl crate::Writable for SpiInsrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_INSR to value 0"]
        impl crate::Resettable for SpiInsrSpec {}
    }
    #[doc = "SPI_INMAR (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_inmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_inmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_inmar`] module"]
    #[doc(alias = "SPI_INMAR")]
    pub type SpiInmar = crate::Reg<spi_inmar::SpiInmarSpec>;
    #[doc = "Interrupt mask register"]
    pub mod spi_inmar {
        #[doc = "Register `SPI_INMAR` reader"]
        pub type R = crate::R<SpiInmarSpec>;
        #[doc = "Register `SPI_INMAR` writer"]
        pub type W = crate::W<SpiInmarSpec>;
        #[doc = "Field `txe_im` reader - TX empty interrupt mask"]
        pub type TxeImR = crate::BitReader;
        #[doc = "Field `txe_im` writer - TX empty interrupt mask"]
        pub type TxeImW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `txo_im` reader - TX overflow interrupt mask"]
        pub type TxoImR = crate::BitReader;
        #[doc = "Field `txo_im` writer - TX overflow interrupt mask"]
        pub type TxoImW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rxu_im` reader - RX underflow interrupt mask"]
        pub type RxuImR = crate::BitReader;
        #[doc = "Field `rxu_im` writer - RX underflow interrupt mask"]
        pub type RxuImW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rxo_im` reader - RX overflow interrupt mask"]
        pub type RxoImR = crate::BitReader;
        #[doc = "Field `rxo_im` writer - RX overflow interrupt mask"]
        pub type RxoImW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rxf_im` reader - RX full interrupt mask"]
        pub type RxfImR = crate::BitReader;
        #[doc = "Field `rxf_im` writer - RX full interrupt mask"]
        pub type RxfImW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `mst_im` reader - Multi-master interrupt mask"]
        pub type MstImR = crate::BitReader;
        #[doc = "Field `mst_im` writer - Multi-master interrupt mask"]
        pub type MstImW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - TX empty interrupt mask"]
            #[inline(always)]
            pub fn txe_im(&self) -> TxeImR {
                TxeImR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TX overflow interrupt mask"]
            #[inline(always)]
            pub fn txo_im(&self) -> TxoImR {
                TxoImR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - RX underflow interrupt mask"]
            #[inline(always)]
            pub fn rxu_im(&self) -> RxuImR {
                RxuImR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - RX overflow interrupt mask"]
            #[inline(always)]
            pub fn rxo_im(&self) -> RxoImR {
                RxoImR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - RX full interrupt mask"]
            #[inline(always)]
            pub fn rxf_im(&self) -> RxfImR {
                RxfImR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Multi-master interrupt mask"]
            #[inline(always)]
            pub fn mst_im(&self) -> MstImR {
                MstImR::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - TX empty interrupt mask"]
            #[inline(always)]
            pub fn txe_im(&mut self) -> TxeImW<'_, SpiInmarSpec> {
                TxeImW::new(self, 0)
            }
            #[doc = "Bit 1 - TX overflow interrupt mask"]
            #[inline(always)]
            pub fn txo_im(&mut self) -> TxoImW<'_, SpiInmarSpec> {
                TxoImW::new(self, 1)
            }
            #[doc = "Bit 2 - RX underflow interrupt mask"]
            #[inline(always)]
            pub fn rxu_im(&mut self) -> RxuImW<'_, SpiInmarSpec> {
                RxuImW::new(self, 2)
            }
            #[doc = "Bit 3 - RX overflow interrupt mask"]
            #[inline(always)]
            pub fn rxo_im(&mut self) -> RxoImW<'_, SpiInmarSpec> {
                RxoImW::new(self, 3)
            }
            #[doc = "Bit 4 - RX full interrupt mask"]
            #[inline(always)]
            pub fn rxf_im(&mut self) -> RxfImW<'_, SpiInmarSpec> {
                RxfImW::new(self, 4)
            }
            #[doc = "Bit 5 - Multi-master interrupt mask"]
            #[inline(always)]
            pub fn mst_im(&mut self) -> MstImW<'_, SpiInmarSpec> {
                MstImW::new(self, 5)
            }
        }
        #[doc = "Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_inmar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_inmar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiInmarSpec;
        impl crate::RegisterSpec for SpiInmarSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_inmar::R`](R) reader structure"]
        impl crate::Readable for SpiInmarSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_inmar::W`](W) writer structure"]
        impl crate::Writable for SpiInmarSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_INMAR to value 0"]
        impl crate::Resettable for SpiInmarSpec {}
    }
    #[doc = "SPI_SLENR (rw) register accessor: Slave enable register (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_slenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_slenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slenr`] module"]
    #[doc(alias = "SPI_SLENR")]
    pub type SpiSlenr = crate::Reg<spi_slenr::SpiSlenrSpec>;
    #[doc = "Slave enable register (master only)"]
    pub mod spi_slenr {
        #[doc = "Register `SPI_SLENR` reader"]
        pub type R = crate::R<SpiSlenrSpec>;
        #[doc = "Register `SPI_SLENR` writer"]
        pub type W = crate::W<SpiSlenrSpec>;
        #[doc = "Field `slave_enable` reader - Slave select enable"]
        pub type SlaveEnableR = crate::BitReader;
        #[doc = "Field `slave_enable` writer - Slave select enable"]
        pub type SlaveEnableW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Slave select enable"]
            #[inline(always)]
            pub fn slave_enable(&self) -> SlaveEnableR {
                SlaveEnableR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Slave select enable"]
            #[inline(always)]
            pub fn slave_enable(&mut self) -> SlaveEnableW<'_, SpiSlenrSpec> {
                SlaveEnableW::new(self, 0)
            }
        }
        #[doc = "Slave enable register (master only)\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_slenr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_slenr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiSlenrSpec;
        impl crate::RegisterSpec for SpiSlenrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_slenr::R`](R) reader structure"]
        impl crate::Readable for SpiSlenrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_slenr::W`](W) writer structure"]
        impl crate::Writable for SpiSlenrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_SLENR to value 0"]
        impl crate::Resettable for SpiSlenrSpec {}
    }
    #[doc = "SPI_TWLR (rw) register accessor: TX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_twlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_twlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_twlr`] module"]
    #[doc(alias = "SPI_TWLR")]
    pub type SpiTwlr = crate::Reg<spi_twlr::SpiTwlrSpec>;
    #[doc = "TX FIFO threshold level"]
    pub mod spi_twlr {
        #[doc = "Register `SPI_TWLR` reader"]
        pub type R = crate::R<SpiTwlrSpec>;
        #[doc = "Register `SPI_TWLR` writer"]
        pub type W = crate::W<SpiTwlrSpec>;
        #[doc = "Field `tx_fifo_threshold` reader - TX FIFO threshold level"]
        pub type TxFifoThresholdR = crate::FieldReader;
        #[doc = "Field `tx_fifo_threshold` writer - TX FIFO threshold level"]
        pub type TxFifoThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - TX FIFO threshold level"]
            #[inline(always)]
            pub fn tx_fifo_threshold(&self) -> TxFifoThresholdR {
                TxFifoThresholdR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - TX FIFO threshold level"]
            #[inline(always)]
            pub fn tx_fifo_threshold(&mut self) -> TxFifoThresholdW<'_, SpiTwlrSpec> {
                TxFifoThresholdW::new(self, 0)
            }
        }
        #[doc = "TX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_twlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_twlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiTwlrSpec;
        impl crate::RegisterSpec for SpiTwlrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_twlr::R`](R) reader structure"]
        impl crate::Readable for SpiTwlrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_twlr::W`](W) writer structure"]
        impl crate::Writable for SpiTwlrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_TWLR to value 0"]
        impl crate::Resettable for SpiTwlrSpec {}
    }
    #[doc = "SPI_TLR (rw) register accessor: TX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_tlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_tlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_tlr`] module"]
    #[doc(alias = "SPI_TLR")]
    pub type SpiTlr = crate::Reg<spi_tlr::SpiTlrSpec>;
    #[doc = "TX FIFO level register"]
    pub mod spi_tlr {
        #[doc = "Register `SPI_TLR` reader"]
        pub type R = crate::R<SpiTlrSpec>;
        #[doc = "Register `SPI_TLR` writer"]
        pub type W = crate::W<SpiTlrSpec>;
        #[doc = "Field `tx_fifo_level` reader - TX FIFO data level"]
        pub type TxFifoLevelR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - TX FIFO data level"]
            #[inline(always)]
            pub fn tx_fifo_level(&self) -> TxFifoLevelR {
                TxFifoLevelR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {}
        #[doc = "TX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_tlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_tlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiTlrSpec;
        impl crate::RegisterSpec for SpiTlrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_tlr::R`](R) reader structure"]
        impl crate::Readable for SpiTlrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_tlr::W`](W) writer structure"]
        impl crate::Writable for SpiTlrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_TLR to value 0"]
        impl crate::Resettable for SpiTlrSpec {}
    }
    #[doc = "SPI_RWLR (rw) register accessor: RX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rwlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rwlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rwlr`] module"]
    #[doc(alias = "SPI_RWLR")]
    pub type SpiRwlr = crate::Reg<spi_rwlr::SpiRwlrSpec>;
    #[doc = "RX FIFO threshold level"]
    pub mod spi_rwlr {
        #[doc = "Register `SPI_RWLR` reader"]
        pub type R = crate::R<SpiRwlrSpec>;
        #[doc = "Register `SPI_RWLR` writer"]
        pub type W = crate::W<SpiRwlrSpec>;
        #[doc = "Field `rx_fifo_threshold` reader - RX FIFO threshold level"]
        pub type RxFifoThresholdR = crate::FieldReader;
        #[doc = "Field `rx_fifo_threshold` writer - RX FIFO threshold level"]
        pub type RxFifoThresholdW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - RX FIFO threshold level"]
            #[inline(always)]
            pub fn rx_fifo_threshold(&self) -> RxFifoThresholdR {
                RxFifoThresholdR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - RX FIFO threshold level"]
            #[inline(always)]
            pub fn rx_fifo_threshold(&mut self) -> RxFifoThresholdW<'_, SpiRwlrSpec> {
                RxFifoThresholdW::new(self, 0)
            }
        }
        #[doc = "RX FIFO threshold level\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rwlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rwlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiRwlrSpec;
        impl crate::RegisterSpec for SpiRwlrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_rwlr::R`](R) reader structure"]
        impl crate::Readable for SpiRwlrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_rwlr::W`](W) writer structure"]
        impl crate::Writable for SpiRwlrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_RWLR to value 0"]
        impl crate::Resettable for SpiRwlrSpec {}
    }
    #[doc = "SPI_RLR (rw) register accessor: RX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_rlr`] module"]
    #[doc(alias = "SPI_RLR")]
    pub type SpiRlr = crate::Reg<spi_rlr::SpiRlrSpec>;
    #[doc = "RX FIFO level register"]
    pub mod spi_rlr {
        #[doc = "Register `SPI_RLR` reader"]
        pub type R = crate::R<SpiRlrSpec>;
        #[doc = "Register `SPI_RLR` writer"]
        pub type W = crate::W<SpiRlrSpec>;
        #[doc = "Field `rx_fifo_level` reader - RX FIFO data level"]
        pub type RxFifoLevelR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - RX FIFO data level"]
            #[inline(always)]
            pub fn rx_fifo_level(&self) -> RxFifoLevelR {
                RxFifoLevelR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {}
        #[doc = "RX FIFO level register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_rlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_rlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiRlrSpec;
        impl crate::RegisterSpec for SpiRlrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_rlr::R`](R) reader structure"]
        impl crate::Readable for SpiRlrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_rlr::W`](W) writer structure"]
        impl crate::Writable for SpiRlrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_RLR to value 0"]
        impl crate::Resettable for SpiRlrSpec {}
    }
    #[doc = "SPI_WSR (rw) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_wsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_wsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_wsr`] module"]
    #[doc(alias = "SPI_WSR")]
    pub type SpiWsr = crate::Reg<spi_wsr::SpiWsrSpec>;
    #[doc = "Status register"]
    pub mod spi_wsr {
        #[doc = "Register `SPI_WSR` reader"]
        pub type R = crate::R<SpiWsrSpec>;
        #[doc = "Register `SPI_WSR` writer"]
        pub type W = crate::W<SpiWsrSpec>;
        #[doc = "Field `busy` reader - SPI busy flag"]
        pub type BusyR = crate::BitReader;
        #[doc = "Field `txfnf` reader - TX FIFO not full"]
        pub type TxfnfR = crate::BitReader;
        #[doc = "Field `txfe` reader - TX FIFO empty"]
        pub type TxfeR = crate::BitReader;
        #[doc = "Field `rxfne` reader - RX FIFO not empty"]
        pub type RxfneR = crate::BitReader;
        #[doc = "Field `rxfo` reader - RX FIFO overflow"]
        pub type RxfoR = crate::BitReader;
        #[doc = "Field `txfo` reader - TX FIFO overflow"]
        pub type TxfoR = crate::BitReader;
        #[doc = "Field `dcm` reader - Data conflict mask"]
        pub type DcmR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - SPI busy flag"]
            #[inline(always)]
            pub fn busy(&self) -> BusyR {
                BusyR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TX FIFO not full"]
            #[inline(always)]
            pub fn txfnf(&self) -> TxfnfR {
                TxfnfR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - TX FIFO empty"]
            #[inline(always)]
            pub fn txfe(&self) -> TxfeR {
                TxfeR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - RX FIFO not empty"]
            #[inline(always)]
            pub fn rxfne(&self) -> RxfneR {
                RxfneR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - RX FIFO overflow"]
            #[inline(always)]
            pub fn rxfo(&self) -> RxfoR {
                RxfoR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - TX FIFO overflow"]
            #[inline(always)]
            pub fn txfo(&self) -> TxfoR {
                TxfoR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Data conflict mask"]
            #[inline(always)]
            pub fn dcm(&self) -> DcmR {
                DcmR::new(((self.bits >> 6) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_wsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_wsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiWsrSpec;
        impl crate::RegisterSpec for SpiWsrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_wsr::R`](R) reader structure"]
        impl crate::Readable for SpiWsrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_wsr::W`](W) writer structure"]
        impl crate::Writable for SpiWsrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_WSR to value 0x06"]
        impl crate::Resettable for SpiWsrSpec {
            const RESET_VALUE: u32 = 0x06;
        }
    }
    #[doc = "SPI_ICR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_icr`] module"]
    #[doc(alias = "SPI_ICR")]
    pub type SpiIcr = crate::Reg<spi_icr::SpiIcrSpec>;
    #[doc = "Interrupt clear register"]
    pub mod spi_icr {
        #[doc = "Register `SPI_ICR` reader"]
        pub type R = crate::R<SpiIcrSpec>;
        #[doc = "Register `SPI_ICR` writer"]
        pub type W = crate::W<SpiIcrSpec>;
        #[doc = "Field `txo_ic` writer - TX overflow interrupt clear"]
        pub type TxoIcW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rxu_ic` writer - RX underflow interrupt clear"]
        pub type RxuIcW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rxo_ic` writer - RX overflow interrupt clear"]
        pub type RxoIcW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `mst_ic` writer - Multi-master interrupt clear"]
        pub type MstIcW<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - TX overflow interrupt clear"]
            #[inline(always)]
            pub fn txo_ic(&mut self) -> TxoIcW<'_, SpiIcrSpec> {
                TxoIcW::new(self, 0)
            }
            #[doc = "Bit 1 - RX underflow interrupt clear"]
            #[inline(always)]
            pub fn rxu_ic(&mut self) -> RxuIcW<'_, SpiIcrSpec> {
                RxuIcW::new(self, 1)
            }
            #[doc = "Bit 2 - RX overflow interrupt clear"]
            #[inline(always)]
            pub fn rxo_ic(&mut self) -> RxoIcW<'_, SpiIcrSpec> {
                RxoIcW::new(self, 2)
            }
            #[doc = "Bit 3 - Multi-master interrupt clear"]
            #[inline(always)]
            pub fn mst_ic(&mut self) -> MstIcW<'_, SpiIcrSpec> {
                MstIcW::new(self, 3)
            }
        }
        #[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SpiIcrSpec;
        impl crate::RegisterSpec for SpiIcrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spi_icr::R`](R) reader structure"]
        impl crate::Readable for SpiIcrSpec {}
        #[doc = "`write(|w| ..)` method takes [`spi_icr::W`](W) writer structure"]
        impl crate::Writable for SpiIcrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SPI_ICR to value 0"]
        impl crate::Resettable for SpiIcrSpec {}
    }
}
#[doc = "PWM controller with 8 channels"]
pub type Pwm = crate::Periph<pwm::RegisterBlock, 0x5209_0000>;
impl core::fmt::Debug for Pwm {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Pwm").finish()
    }
}
#[doc = "PWM controller with 8 channels"]
pub mod pwm {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        pwm_sel0: PwmSel0,
        pwm_startclrcnt_en0: PwmStartclrcntEn0,
        pwm_start0: PwmStart0,
        _reserved3: [u8; 0x04],
        pwm_sel1: PwmSel1,
        pwm_startclrcnt_en1: PwmStartclrcntEn1,
        pwm_start1: PwmStart1,
        _reserved6: [u8; 0x04],
        pwm_sel2: PwmSel2,
        pwm_startclrcnt_en2: PwmStartclrcntEn2,
        pwm_start2: PwmStart2,
        _reserved9: [u8; 0x04],
        pwm_sel3: PwmSel3,
        pwm_startclrcnt_en3: PwmStartclrcntEn3,
        pwm_start3: PwmStart3,
        _reserved12: [u8; 0xc4],
        pwm_en0: PwmEn0,
        pwm_portity0: PwmPortity0,
        pwm_oen_cfg0: PwmOenCfg0,
        pwm_offset_l0: PwmOffsetL0,
        pwm_offset_h0: PwmOffsetH0,
        pwm_freq_l0: PwmFreqL0,
        pwm_freq_h0: PwmFreqH0,
        pwm_duty_l0: PwmDutyL0,
        pwm_duty_h0: PwmDutyH0,
        pwm_periodload_flag0: PwmPeriodloadFlag0,
        pwm_period_val0: PwmPeriodVal0,
        pwm_periodcnt0: PwmPeriodcnt0,
        _reserved24: [u8; 0x10],
        pwm_en1: PwmEn1,
        pwm_portity1: PwmPortity1,
        pwm_oen_cfg1: PwmOenCfg1,
        pwm_offset_l1: PwmOffsetL1,
        pwm_offset_h1: PwmOffsetH1,
        pwm_freq_l1: PwmFreqL1,
        pwm_freq_h1: PwmFreqH1,
        pwm_duty_l1: PwmDutyL1,
        pwm_duty_h1: PwmDutyH1,
        pwm_periodload_flag1: PwmPeriodloadFlag1,
        pwm_period_val1: PwmPeriodVal1,
        pwm_periodcnt1: PwmPeriodcnt1,
        _reserved36: [u8; 0x10],
        pwm_en2: PwmEn2,
        pwm_portity2: PwmPortity2,
        pwm_oen_cfg2: PwmOenCfg2,
        pwm_offset_l2: PwmOffsetL2,
        pwm_offset_h2: PwmOffsetH2,
        pwm_freq_l2: PwmFreqL2,
        pwm_freq_h2: PwmFreqH2,
        pwm_duty_l2: PwmDutyL2,
        pwm_duty_h2: PwmDutyH2,
        pwm_periodload_flag2: PwmPeriodloadFlag2,
        pwm_period_val2: PwmPeriodVal2,
        pwm_periodcnt2: PwmPeriodcnt2,
        _reserved48: [u8; 0x10],
        pwm_en3: PwmEn3,
        pwm_portity3: PwmPortity3,
        pwm_oen_cfg3: PwmOenCfg3,
        pwm_offset_l3: PwmOffsetL3,
        pwm_offset_h3: PwmOffsetH3,
        pwm_freq_l3: PwmFreqL3,
        pwm_freq_h3: PwmFreqH3,
        pwm_duty_l3: PwmDutyL3,
        pwm_duty_h3: PwmDutyH3,
        pwm_periodload_flag3: PwmPeriodloadFlag3,
        pwm_period_val3: PwmPeriodVal3,
        pwm_periodcnt3: PwmPeriodcnt3,
        _reserved60: [u8; 0x10],
        pwm_en4: PwmEn4,
        pwm_portity4: PwmPortity4,
        pwm_oen_cfg4: PwmOenCfg4,
        pwm_offset_l4: PwmOffsetL4,
        pwm_offset_h4: PwmOffsetH4,
        pwm_freq_l4: PwmFreqL4,
        pwm_freq_h4: PwmFreqH4,
        pwm_duty_l4: PwmDutyL4,
        pwm_duty_h4: PwmDutyH4,
        pwm_periodload_flag4: PwmPeriodloadFlag4,
        pwm_period_val4: PwmPeriodVal4,
        pwm_periodcnt4: PwmPeriodcnt4,
        _reserved72: [u8; 0x10],
        pwm_en5: PwmEn5,
        pwm_portity5: PwmPortity5,
        pwm_oen_cfg5: PwmOenCfg5,
        pwm_offset_l5: PwmOffsetL5,
        pwm_offset_h5: PwmOffsetH5,
        pwm_freq_l5: PwmFreqL5,
        pwm_freq_h5: PwmFreqH5,
        pwm_duty_l5: PwmDutyL5,
        pwm_duty_h5: PwmDutyH5,
        pwm_periodload_flag5: PwmPeriodloadFlag5,
        pwm_period_val5: PwmPeriodVal5,
        pwm_periodcnt5: PwmPeriodcnt5,
        _reserved84: [u8; 0x10],
        pwm_en6: PwmEn6,
        pwm_portity6: PwmPortity6,
        pwm_oen_cfg6: PwmOenCfg6,
        pwm_offset_l6: PwmOffsetL6,
        pwm_offset_h6: PwmOffsetH6,
        pwm_freq_l6: PwmFreqL6,
        pwm_freq_h6: PwmFreqH6,
        pwm_duty_l6: PwmDutyL6,
        pwm_duty_h6: PwmDutyH6,
        pwm_periodload_flag6: PwmPeriodloadFlag6,
        pwm_period_val6: PwmPeriodVal6,
        pwm_periodcnt6: PwmPeriodcnt6,
        _reserved96: [u8; 0x10],
        pwm_en7: PwmEn7,
        pwm_portity7: PwmPortity7,
        pwm_oen_cfg7: PwmOenCfg7,
        pwm_offset_l7: PwmOffsetL7,
        pwm_offset_h7: PwmOffsetH7,
        pwm_freq_l7: PwmFreqL7,
        pwm_freq_h7: PwmFreqH7,
        pwm_duty_l7: PwmDutyL7,
        pwm_duty_h7: PwmDutyH7,
        pwm_periodload_flag7: PwmPeriodloadFlag7,
        pwm_period_val7: PwmPeriodVal7,
        pwm_periodcnt7: PwmPeriodcnt7,
        _reserved108: [u8; 0x0210],
        pwm_abnor_state0: PwmAbnorState0,
        pwm_abnor_state1: PwmAbnorState1,
        pwm_abnor_state_clr0: PwmAbnorStateClr0,
        pwm_abnor_state_clr1: PwmAbnorStateClr1,
        pwm_int_mask: PwmIntMask,
        pwm_dma_en: PwmDmaEn,
        pwm_cfg_int_clr0: PwmCfgIntClr0,
    }
    impl RegisterBlock {
        #[doc = "0x00 - PWM group 0 select"]
        #[inline(always)]
        pub const fn pwm_sel0(&self) -> &PwmSel0 {
            &self.pwm_sel0
        }
        #[doc = "0x04 - PWM group 0 start clear counter enable"]
        #[inline(always)]
        pub const fn pwm_startclrcnt_en0(&self) -> &PwmStartclrcntEn0 {
            &self.pwm_startclrcnt_en0
        }
        #[doc = "0x08 - PWM group 0 start"]
        #[inline(always)]
        pub const fn pwm_start0(&self) -> &PwmStart0 {
            &self.pwm_start0
        }
        #[doc = "0x10 - PWM group 1 select"]
        #[inline(always)]
        pub const fn pwm_sel1(&self) -> &PwmSel1 {
            &self.pwm_sel1
        }
        #[doc = "0x14 - PWM group 1 start clear counter enable"]
        #[inline(always)]
        pub const fn pwm_startclrcnt_en1(&self) -> &PwmStartclrcntEn1 {
            &self.pwm_startclrcnt_en1
        }
        #[doc = "0x18 - PWM group 1 start"]
        #[inline(always)]
        pub const fn pwm_start1(&self) -> &PwmStart1 {
            &self.pwm_start1
        }
        #[doc = "0x20 - PWM group 2 select"]
        #[inline(always)]
        pub const fn pwm_sel2(&self) -> &PwmSel2 {
            &self.pwm_sel2
        }
        #[doc = "0x24 - PWM group 2 start clear counter enable"]
        #[inline(always)]
        pub const fn pwm_startclrcnt_en2(&self) -> &PwmStartclrcntEn2 {
            &self.pwm_startclrcnt_en2
        }
        #[doc = "0x28 - PWM group 2 start"]
        #[inline(always)]
        pub const fn pwm_start2(&self) -> &PwmStart2 {
            &self.pwm_start2
        }
        #[doc = "0x30 - PWM group 3 select"]
        #[inline(always)]
        pub const fn pwm_sel3(&self) -> &PwmSel3 {
            &self.pwm_sel3
        }
        #[doc = "0x34 - PWM group 3 start clear counter enable"]
        #[inline(always)]
        pub const fn pwm_startclrcnt_en3(&self) -> &PwmStartclrcntEn3 {
            &self.pwm_startclrcnt_en3
        }
        #[doc = "0x38 - PWM group 3 start"]
        #[inline(always)]
        pub const fn pwm_start3(&self) -> &PwmStart3 {
            &self.pwm_start3
        }
        #[doc = "0x100 - PWM0 enable"]
        #[inline(always)]
        pub const fn pwm_en0(&self) -> &PwmEn0 {
            &self.pwm_en0
        }
        #[doc = "0x104 - PWM0 polarity"]
        #[inline(always)]
        pub const fn pwm_portity0(&self) -> &PwmPortity0 {
            &self.pwm_portity0
        }
        #[doc = "0x108 - PWM0 high-impedance config"]
        #[inline(always)]
        pub const fn pwm_oen_cfg0(&self) -> &PwmOenCfg0 {
            &self.pwm_oen_cfg0
        }
        #[doc = "0x10c - PWM0 phase offset low 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_l0(&self) -> &PwmOffsetL0 {
            &self.pwm_offset_l0
        }
        #[doc = "0x110 - PWM0 phase offset high 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_h0(&self) -> &PwmOffsetH0 {
            &self.pwm_offset_h0
        }
        #[doc = "0x114 - PWM0 frequency low 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_l0(&self) -> &PwmFreqL0 {
            &self.pwm_freq_l0
        }
        #[doc = "0x118 - PWM0 frequency high 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_h0(&self) -> &PwmFreqH0 {
            &self.pwm_freq_h0
        }
        #[doc = "0x11c - PWM0 duty cycle low 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_l0(&self) -> &PwmDutyL0 {
            &self.pwm_duty_l0
        }
        #[doc = "0x120 - PWM0 duty cycle high 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_h0(&self) -> &PwmDutyH0 {
            &self.pwm_duty_h0
        }
        #[doc = "0x124 - PWM0 period load flag"]
        #[inline(always)]
        pub const fn pwm_periodload_flag0(&self) -> &PwmPeriodloadFlag0 {
            &self.pwm_periodload_flag0
        }
        #[doc = "0x128 - PWM0 pulse count value"]
        #[inline(always)]
        pub const fn pwm_period_val0(&self) -> &PwmPeriodVal0 {
            &self.pwm_period_val0
        }
        #[doc = "0x12c - PWM0 pulse count current value"]
        #[inline(always)]
        pub const fn pwm_periodcnt0(&self) -> &PwmPeriodcnt0 {
            &self.pwm_periodcnt0
        }
        #[doc = "0x140 - PWM1 enable"]
        #[inline(always)]
        pub const fn pwm_en1(&self) -> &PwmEn1 {
            &self.pwm_en1
        }
        #[doc = "0x144 - PWM1 polarity"]
        #[inline(always)]
        pub const fn pwm_portity1(&self) -> &PwmPortity1 {
            &self.pwm_portity1
        }
        #[doc = "0x148 - PWM1 high-impedance config"]
        #[inline(always)]
        pub const fn pwm_oen_cfg1(&self) -> &PwmOenCfg1 {
            &self.pwm_oen_cfg1
        }
        #[doc = "0x14c - PWM1 phase offset low"]
        #[inline(always)]
        pub const fn pwm_offset_l1(&self) -> &PwmOffsetL1 {
            &self.pwm_offset_l1
        }
        #[doc = "0x150 - PWM1 phase offset high"]
        #[inline(always)]
        pub const fn pwm_offset_h1(&self) -> &PwmOffsetH1 {
            &self.pwm_offset_h1
        }
        #[doc = "0x154 - PWM1 frequency low"]
        #[inline(always)]
        pub const fn pwm_freq_l1(&self) -> &PwmFreqL1 {
            &self.pwm_freq_l1
        }
        #[doc = "0x158 - PWM1 frequency high"]
        #[inline(always)]
        pub const fn pwm_freq_h1(&self) -> &PwmFreqH1 {
            &self.pwm_freq_h1
        }
        #[doc = "0x15c - PWM1 duty cycle low"]
        #[inline(always)]
        pub const fn pwm_duty_l1(&self) -> &PwmDutyL1 {
            &self.pwm_duty_l1
        }
        #[doc = "0x160 - PWM1 duty cycle high"]
        #[inline(always)]
        pub const fn pwm_duty_h1(&self) -> &PwmDutyH1 {
            &self.pwm_duty_h1
        }
        #[doc = "0x164 - PWM1 period load flag"]
        #[inline(always)]
        pub const fn pwm_periodload_flag1(&self) -> &PwmPeriodloadFlag1 {
            &self.pwm_periodload_flag1
        }
        #[doc = "0x168 - PWM1 pulse count"]
        #[inline(always)]
        pub const fn pwm_period_val1(&self) -> &PwmPeriodVal1 {
            &self.pwm_period_val1
        }
        #[doc = "0x16c - PWM1 pulse count current"]
        #[inline(always)]
        pub const fn pwm_periodcnt1(&self) -> &PwmPeriodcnt1 {
            &self.pwm_periodcnt1
        }
        #[doc = "0x180 - PWM2 enable"]
        #[inline(always)]
        pub const fn pwm_en2(&self) -> &PwmEn2 {
            &self.pwm_en2
        }
        #[doc = "0x184 - PWM2 polarity"]
        #[inline(always)]
        pub const fn pwm_portity2(&self) -> &PwmPortity2 {
            &self.pwm_portity2
        }
        #[doc = "0x188 - PWM2 high-impedance config"]
        #[inline(always)]
        pub const fn pwm_oen_cfg2(&self) -> &PwmOenCfg2 {
            &self.pwm_oen_cfg2
        }
        #[doc = "0x18c - PWM2 phase offset low 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_l2(&self) -> &PwmOffsetL2 {
            &self.pwm_offset_l2
        }
        #[doc = "0x190 - PWM2 phase offset high 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_h2(&self) -> &PwmOffsetH2 {
            &self.pwm_offset_h2
        }
        #[doc = "0x194 - PWM2 frequency low 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_l2(&self) -> &PwmFreqL2 {
            &self.pwm_freq_l2
        }
        #[doc = "0x198 - PWM2 frequency high 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_h2(&self) -> &PwmFreqH2 {
            &self.pwm_freq_h2
        }
        #[doc = "0x19c - PWM2 duty cycle low 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_l2(&self) -> &PwmDutyL2 {
            &self.pwm_duty_l2
        }
        #[doc = "0x1a0 - PWM2 duty cycle high 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_h2(&self) -> &PwmDutyH2 {
            &self.pwm_duty_h2
        }
        #[doc = "0x1a4 - PWM2 period load flag"]
        #[inline(always)]
        pub const fn pwm_periodload_flag2(&self) -> &PwmPeriodloadFlag2 {
            &self.pwm_periodload_flag2
        }
        #[doc = "0x1a8 - PWM2 pulse count value"]
        #[inline(always)]
        pub const fn pwm_period_val2(&self) -> &PwmPeriodVal2 {
            &self.pwm_period_val2
        }
        #[doc = "0x1ac - PWM2 pulse count current value"]
        #[inline(always)]
        pub const fn pwm_periodcnt2(&self) -> &PwmPeriodcnt2 {
            &self.pwm_periodcnt2
        }
        #[doc = "0x1c0 - PWM3 enable"]
        #[inline(always)]
        pub const fn pwm_en3(&self) -> &PwmEn3 {
            &self.pwm_en3
        }
        #[doc = "0x1c4 - PWM3 polarity"]
        #[inline(always)]
        pub const fn pwm_portity3(&self) -> &PwmPortity3 {
            &self.pwm_portity3
        }
        #[doc = "0x1c8 - PWM3 high-impedance config"]
        #[inline(always)]
        pub const fn pwm_oen_cfg3(&self) -> &PwmOenCfg3 {
            &self.pwm_oen_cfg3
        }
        #[doc = "0x1cc - PWM3 phase offset low 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_l3(&self) -> &PwmOffsetL3 {
            &self.pwm_offset_l3
        }
        #[doc = "0x1d0 - PWM3 phase offset high 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_h3(&self) -> &PwmOffsetH3 {
            &self.pwm_offset_h3
        }
        #[doc = "0x1d4 - PWM3 frequency low 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_l3(&self) -> &PwmFreqL3 {
            &self.pwm_freq_l3
        }
        #[doc = "0x1d8 - PWM3 frequency high 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_h3(&self) -> &PwmFreqH3 {
            &self.pwm_freq_h3
        }
        #[doc = "0x1dc - PWM3 duty cycle low 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_l3(&self) -> &PwmDutyL3 {
            &self.pwm_duty_l3
        }
        #[doc = "0x1e0 - PWM3 duty cycle high 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_h3(&self) -> &PwmDutyH3 {
            &self.pwm_duty_h3
        }
        #[doc = "0x1e4 - PWM3 period load flag"]
        #[inline(always)]
        pub const fn pwm_periodload_flag3(&self) -> &PwmPeriodloadFlag3 {
            &self.pwm_periodload_flag3
        }
        #[doc = "0x1e8 - PWM3 pulse count value"]
        #[inline(always)]
        pub const fn pwm_period_val3(&self) -> &PwmPeriodVal3 {
            &self.pwm_period_val3
        }
        #[doc = "0x1ec - PWM3 pulse count current value"]
        #[inline(always)]
        pub const fn pwm_periodcnt3(&self) -> &PwmPeriodcnt3 {
            &self.pwm_periodcnt3
        }
        #[doc = "0x200 - PWM4 enable"]
        #[inline(always)]
        pub const fn pwm_en4(&self) -> &PwmEn4 {
            &self.pwm_en4
        }
        #[doc = "0x204 - PWM4 polarity"]
        #[inline(always)]
        pub const fn pwm_portity4(&self) -> &PwmPortity4 {
            &self.pwm_portity4
        }
        #[doc = "0x208 - PWM4 high-impedance config"]
        #[inline(always)]
        pub const fn pwm_oen_cfg4(&self) -> &PwmOenCfg4 {
            &self.pwm_oen_cfg4
        }
        #[doc = "0x20c - PWM4 phase offset low 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_l4(&self) -> &PwmOffsetL4 {
            &self.pwm_offset_l4
        }
        #[doc = "0x210 - PWM4 phase offset high 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_h4(&self) -> &PwmOffsetH4 {
            &self.pwm_offset_h4
        }
        #[doc = "0x214 - PWM4 frequency low 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_l4(&self) -> &PwmFreqL4 {
            &self.pwm_freq_l4
        }
        #[doc = "0x218 - PWM4 frequency high 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_h4(&self) -> &PwmFreqH4 {
            &self.pwm_freq_h4
        }
        #[doc = "0x21c - PWM4 duty cycle low 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_l4(&self) -> &PwmDutyL4 {
            &self.pwm_duty_l4
        }
        #[doc = "0x220 - PWM4 duty cycle high 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_h4(&self) -> &PwmDutyH4 {
            &self.pwm_duty_h4
        }
        #[doc = "0x224 - PWM4 period load flag"]
        #[inline(always)]
        pub const fn pwm_periodload_flag4(&self) -> &PwmPeriodloadFlag4 {
            &self.pwm_periodload_flag4
        }
        #[doc = "0x228 - PWM4 pulse count value"]
        #[inline(always)]
        pub const fn pwm_period_val4(&self) -> &PwmPeriodVal4 {
            &self.pwm_period_val4
        }
        #[doc = "0x22c - PWM4 pulse count current value"]
        #[inline(always)]
        pub const fn pwm_periodcnt4(&self) -> &PwmPeriodcnt4 {
            &self.pwm_periodcnt4
        }
        #[doc = "0x240 - PWM5 enable"]
        #[inline(always)]
        pub const fn pwm_en5(&self) -> &PwmEn5 {
            &self.pwm_en5
        }
        #[doc = "0x244 - PWM5 polarity"]
        #[inline(always)]
        pub const fn pwm_portity5(&self) -> &PwmPortity5 {
            &self.pwm_portity5
        }
        #[doc = "0x248 - PWM5 high-impedance config"]
        #[inline(always)]
        pub const fn pwm_oen_cfg5(&self) -> &PwmOenCfg5 {
            &self.pwm_oen_cfg5
        }
        #[doc = "0x24c - PWM5 phase offset low 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_l5(&self) -> &PwmOffsetL5 {
            &self.pwm_offset_l5
        }
        #[doc = "0x250 - PWM5 phase offset high 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_h5(&self) -> &PwmOffsetH5 {
            &self.pwm_offset_h5
        }
        #[doc = "0x254 - PWM5 frequency low 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_l5(&self) -> &PwmFreqL5 {
            &self.pwm_freq_l5
        }
        #[doc = "0x258 - PWM5 frequency high 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_h5(&self) -> &PwmFreqH5 {
            &self.pwm_freq_h5
        }
        #[doc = "0x25c - PWM5 duty cycle low 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_l5(&self) -> &PwmDutyL5 {
            &self.pwm_duty_l5
        }
        #[doc = "0x260 - PWM5 duty cycle high 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_h5(&self) -> &PwmDutyH5 {
            &self.pwm_duty_h5
        }
        #[doc = "0x264 - PWM5 period load flag"]
        #[inline(always)]
        pub const fn pwm_periodload_flag5(&self) -> &PwmPeriodloadFlag5 {
            &self.pwm_periodload_flag5
        }
        #[doc = "0x268 - PWM5 pulse count value"]
        #[inline(always)]
        pub const fn pwm_period_val5(&self) -> &PwmPeriodVal5 {
            &self.pwm_period_val5
        }
        #[doc = "0x26c - PWM5 pulse count current value"]
        #[inline(always)]
        pub const fn pwm_periodcnt5(&self) -> &PwmPeriodcnt5 {
            &self.pwm_periodcnt5
        }
        #[doc = "0x280 - PWM6 enable"]
        #[inline(always)]
        pub const fn pwm_en6(&self) -> &PwmEn6 {
            &self.pwm_en6
        }
        #[doc = "0x284 - PWM6 polarity"]
        #[inline(always)]
        pub const fn pwm_portity6(&self) -> &PwmPortity6 {
            &self.pwm_portity6
        }
        #[doc = "0x288 - PWM6 high-impedance config"]
        #[inline(always)]
        pub const fn pwm_oen_cfg6(&self) -> &PwmOenCfg6 {
            &self.pwm_oen_cfg6
        }
        #[doc = "0x28c - PWM6 phase offset low 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_l6(&self) -> &PwmOffsetL6 {
            &self.pwm_offset_l6
        }
        #[doc = "0x290 - PWM6 phase offset high 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_h6(&self) -> &PwmOffsetH6 {
            &self.pwm_offset_h6
        }
        #[doc = "0x294 - PWM6 frequency low 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_l6(&self) -> &PwmFreqL6 {
            &self.pwm_freq_l6
        }
        #[doc = "0x298 - PWM6 frequency high 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_h6(&self) -> &PwmFreqH6 {
            &self.pwm_freq_h6
        }
        #[doc = "0x29c - PWM6 duty cycle low 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_l6(&self) -> &PwmDutyL6 {
            &self.pwm_duty_l6
        }
        #[doc = "0x2a0 - PWM6 duty cycle high 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_h6(&self) -> &PwmDutyH6 {
            &self.pwm_duty_h6
        }
        #[doc = "0x2a4 - PWM6 period load flag"]
        #[inline(always)]
        pub const fn pwm_periodload_flag6(&self) -> &PwmPeriodloadFlag6 {
            &self.pwm_periodload_flag6
        }
        #[doc = "0x2a8 - PWM6 pulse count value"]
        #[inline(always)]
        pub const fn pwm_period_val6(&self) -> &PwmPeriodVal6 {
            &self.pwm_period_val6
        }
        #[doc = "0x2ac - PWM6 pulse count current value"]
        #[inline(always)]
        pub const fn pwm_periodcnt6(&self) -> &PwmPeriodcnt6 {
            &self.pwm_periodcnt6
        }
        #[doc = "0x2c0 - PWM7 enable"]
        #[inline(always)]
        pub const fn pwm_en7(&self) -> &PwmEn7 {
            &self.pwm_en7
        }
        #[doc = "0x2c4 - PWM7 polarity"]
        #[inline(always)]
        pub const fn pwm_portity7(&self) -> &PwmPortity7 {
            &self.pwm_portity7
        }
        #[doc = "0x2c8 - PWM7 high-impedance config"]
        #[inline(always)]
        pub const fn pwm_oen_cfg7(&self) -> &PwmOenCfg7 {
            &self.pwm_oen_cfg7
        }
        #[doc = "0x2cc - PWM7 phase offset low 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_l7(&self) -> &PwmOffsetL7 {
            &self.pwm_offset_l7
        }
        #[doc = "0x2d0 - PWM7 phase offset high 16 bits"]
        #[inline(always)]
        pub const fn pwm_offset_h7(&self) -> &PwmOffsetH7 {
            &self.pwm_offset_h7
        }
        #[doc = "0x2d4 - PWM7 frequency low 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_l7(&self) -> &PwmFreqL7 {
            &self.pwm_freq_l7
        }
        #[doc = "0x2d8 - PWM7 frequency high 16 bits"]
        #[inline(always)]
        pub const fn pwm_freq_h7(&self) -> &PwmFreqH7 {
            &self.pwm_freq_h7
        }
        #[doc = "0x2dc - PWM7 duty cycle low 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_l7(&self) -> &PwmDutyL7 {
            &self.pwm_duty_l7
        }
        #[doc = "0x2e0 - PWM7 duty cycle high 16 bits"]
        #[inline(always)]
        pub const fn pwm_duty_h7(&self) -> &PwmDutyH7 {
            &self.pwm_duty_h7
        }
        #[doc = "0x2e4 - PWM7 period load flag"]
        #[inline(always)]
        pub const fn pwm_periodload_flag7(&self) -> &PwmPeriodloadFlag7 {
            &self.pwm_periodload_flag7
        }
        #[doc = "0x2e8 - PWM7 pulse count value"]
        #[inline(always)]
        pub const fn pwm_period_val7(&self) -> &PwmPeriodVal7 {
            &self.pwm_period_val7
        }
        #[doc = "0x2ec - PWM7 pulse count current value"]
        #[inline(always)]
        pub const fn pwm_periodcnt7(&self) -> &PwmPeriodcnt7 {
            &self.pwm_periodcnt7
        }
        #[doc = "0x500 - PWM abnormal state register 0"]
        #[inline(always)]
        pub const fn pwm_abnor_state0(&self) -> &PwmAbnorState0 {
            &self.pwm_abnor_state0
        }
        #[doc = "0x504 - PWM abnormal state register 1"]
        #[inline(always)]
        pub const fn pwm_abnor_state1(&self) -> &PwmAbnorState1 {
            &self.pwm_abnor_state1
        }
        #[doc = "0x508 - PWM abnormal state clear 0"]
        #[inline(always)]
        pub const fn pwm_abnor_state_clr0(&self) -> &PwmAbnorStateClr0 {
            &self.pwm_abnor_state_clr0
        }
        #[doc = "0x50c - PWM abnormal state clear 1"]
        #[inline(always)]
        pub const fn pwm_abnor_state_clr1(&self) -> &PwmAbnorStateClr1 {
            &self.pwm_abnor_state_clr1
        }
        #[doc = "0x510 - PWM interrupt mask"]
        #[inline(always)]
        pub const fn pwm_int_mask(&self) -> &PwmIntMask {
            &self.pwm_int_mask
        }
        #[doc = "0x514 - PWM DMA enable"]
        #[inline(always)]
        pub const fn pwm_dma_en(&self) -> &PwmDmaEn {
            &self.pwm_dma_en
        }
        #[doc = "0x518 - PWM stepping cycle end interrupt clear"]
        #[inline(always)]
        pub const fn pwm_cfg_int_clr0(&self) -> &PwmCfgIntClr0 {
            &self.pwm_cfg_int_clr0
        }
    }
    #[doc = "PWM_SEL0 (rw) register accessor: PWM group 0 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel0`] module"]
    #[doc(alias = "PWM_SEL0")]
    pub type PwmSel0 = crate::Reg<pwm_sel0::PwmSel0Spec>;
    #[doc = "PWM group 0 select"]
    pub mod pwm_sel0 {
        #[doc = "Register `PWM_SEL0` reader"]
        pub type R = crate::R<PwmSel0Spec>;
        #[doc = "Register `PWM_SEL0` writer"]
        pub type W = crate::W<PwmSel0Spec>;
        #[doc = "Field `pwm_sel_0` reader - Group 0 PWM select, each bit corresponds to one PWM channel"]
        pub type PwmSel0R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_sel_0` writer - Group 0 PWM select, each bit corresponds to one PWM channel"]
        pub type PwmSel0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Group 0 PWM select, each bit corresponds to one PWM channel"]
            #[inline(always)]
            pub fn pwm_sel_0(&self) -> PwmSel0R {
                PwmSel0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Group 0 PWM select, each bit corresponds to one PWM channel"]
            #[inline(always)]
            pub fn pwm_sel_0(&mut self) -> PwmSel0W<'_, PwmSel0Spec> {
                PwmSel0W::new(self, 0)
            }
        }
        #[doc = "PWM group 0 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmSel0Spec;
        impl crate::RegisterSpec for PwmSel0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_sel0::R`](R) reader structure"]
        impl crate::Readable for PwmSel0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_sel0::W`](W) writer structure"]
        impl crate::Writable for PwmSel0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_SEL0 to value 0"]
        impl crate::Resettable for PwmSel0Spec {}
    }
    #[doc = "PWM_STARTCLRCNT_EN0 (rw) register accessor: PWM group 0 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en0`] module"]
    #[doc(alias = "PWM_STARTCLRCNT_EN0")]
    pub type PwmStartclrcntEn0 = crate::Reg<pwm_startclrcnt_en0::PwmStartclrcntEn0Spec>;
    #[doc = "PWM group 0 start clear counter enable"]
    pub mod pwm_startclrcnt_en0 {
        #[doc = "Register `PWM_STARTCLRCNT_EN0` reader"]
        pub type R = crate::R<PwmStartclrcntEn0Spec>;
        #[doc = "Register `PWM_STARTCLRCNT_EN0` writer"]
        pub type W = crate::W<PwmStartclrcntEn0Spec>;
        #[doc = "Field `pwm_startclrcnt_en_0` reader - Start clear counter enable for group 0"]
        pub type PwmStartclrcntEn0R = crate::BitReader;
        #[doc = "Field `pwm_startclrcnt_en_0` writer - Start clear counter enable for group 0"]
        pub type PwmStartclrcntEn0W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Start clear counter enable for group 0"]
            #[inline(always)]
            pub fn pwm_startclrcnt_en_0(&self) -> PwmStartclrcntEn0R {
                PwmStartclrcntEn0R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Start clear counter enable for group 0"]
            #[inline(always)]
            pub fn pwm_startclrcnt_en_0(
                &mut self,
            ) -> PwmStartclrcntEn0W<'_, PwmStartclrcntEn0Spec> {
                PwmStartclrcntEn0W::new(self, 0)
            }
        }
        #[doc = "PWM group 0 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmStartclrcntEn0Spec;
        impl crate::RegisterSpec for PwmStartclrcntEn0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_startclrcnt_en0::R`](R) reader structure"]
        impl crate::Readable for PwmStartclrcntEn0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en0::W`](W) writer structure"]
        impl crate::Writable for PwmStartclrcntEn0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN0 to value 0"]
        impl crate::Resettable for PwmStartclrcntEn0Spec {}
    }
    #[doc = "PWM_START0 (rw) register accessor: PWM group 0 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start0`] module"]
    #[doc(alias = "PWM_START0")]
    pub type PwmStart0 = crate::Reg<pwm_start0::PwmStart0Spec>;
    #[doc = "PWM group 0 start"]
    pub mod pwm_start0 {
        #[doc = "Register `PWM_START0` reader"]
        pub type R = crate::R<PwmStart0Spec>;
        #[doc = "Register `PWM_START0` writer"]
        pub type W = crate::W<PwmStart0Spec>;
        #[doc = "Field `pwm_start_0` writer - Start group 0 (self-clearing)"]
        pub type PwmStart0W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - Start group 0 (self-clearing)"]
            #[inline(always)]
            pub fn pwm_start_0(&mut self) -> PwmStart0W<'_, PwmStart0Spec> {
                PwmStart0W::new(self, 0)
            }
        }
        #[doc = "PWM group 0 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmStart0Spec;
        impl crate::RegisterSpec for PwmStart0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_start0::R`](R) reader structure"]
        impl crate::Readable for PwmStart0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_start0::W`](W) writer structure"]
        impl crate::Writable for PwmStart0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_START0 to value 0"]
        impl crate::Resettable for PwmStart0Spec {}
    }
    #[doc = "PWM_SEL1 (rw) register accessor: PWM group 1 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel1`] module"]
    #[doc(alias = "PWM_SEL1")]
    pub type PwmSel1 = crate::Reg<pwm_sel1::PwmSel1Spec>;
    #[doc = "PWM group 1 select"]
    pub mod pwm_sel1 {
        #[doc = "Register `PWM_SEL1` reader"]
        pub type R = crate::R<PwmSel1Spec>;
        #[doc = "Register `PWM_SEL1` writer"]
        pub type W = crate::W<PwmSel1Spec>;
        #[doc = "Field `pwm_sel_1` reader - Group 1 PWM select"]
        pub type PwmSel1R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_sel_1` writer - Group 1 PWM select"]
        pub type PwmSel1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Group 1 PWM select"]
            #[inline(always)]
            pub fn pwm_sel_1(&self) -> PwmSel1R {
                PwmSel1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Group 1 PWM select"]
            #[inline(always)]
            pub fn pwm_sel_1(&mut self) -> PwmSel1W<'_, PwmSel1Spec> {
                PwmSel1W::new(self, 0)
            }
        }
        #[doc = "PWM group 1 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmSel1Spec;
        impl crate::RegisterSpec for PwmSel1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_sel1::R`](R) reader structure"]
        impl crate::Readable for PwmSel1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_sel1::W`](W) writer structure"]
        impl crate::Writable for PwmSel1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_SEL1 to value 0"]
        impl crate::Resettable for PwmSel1Spec {}
    }
    #[doc = "PWM_STARTCLRCNT_EN1 (rw) register accessor: PWM group 1 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en1`] module"]
    #[doc(alias = "PWM_STARTCLRCNT_EN1")]
    pub type PwmStartclrcntEn1 = crate::Reg<pwm_startclrcnt_en1::PwmStartclrcntEn1Spec>;
    #[doc = "PWM group 1 start clear counter enable"]
    pub mod pwm_startclrcnt_en1 {
        #[doc = "Register `PWM_STARTCLRCNT_EN1` reader"]
        pub type R = crate::R<PwmStartclrcntEn1Spec>;
        #[doc = "Register `PWM_STARTCLRCNT_EN1` writer"]
        pub type W = crate::W<PwmStartclrcntEn1Spec>;
        #[doc = "Field `pwm_startclrcnt_en_1` reader - Start clear counter enable for group 1"]
        pub type PwmStartclrcntEn1R = crate::BitReader;
        #[doc = "Field `pwm_startclrcnt_en_1` writer - Start clear counter enable for group 1"]
        pub type PwmStartclrcntEn1W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Start clear counter enable for group 1"]
            #[inline(always)]
            pub fn pwm_startclrcnt_en_1(&self) -> PwmStartclrcntEn1R {
                PwmStartclrcntEn1R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Start clear counter enable for group 1"]
            #[inline(always)]
            pub fn pwm_startclrcnt_en_1(
                &mut self,
            ) -> PwmStartclrcntEn1W<'_, PwmStartclrcntEn1Spec> {
                PwmStartclrcntEn1W::new(self, 0)
            }
        }
        #[doc = "PWM group 1 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmStartclrcntEn1Spec;
        impl crate::RegisterSpec for PwmStartclrcntEn1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_startclrcnt_en1::R`](R) reader structure"]
        impl crate::Readable for PwmStartclrcntEn1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en1::W`](W) writer structure"]
        impl crate::Writable for PwmStartclrcntEn1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN1 to value 0"]
        impl crate::Resettable for PwmStartclrcntEn1Spec {}
    }
    #[doc = "PWM_START1 (rw) register accessor: PWM group 1 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start1`] module"]
    #[doc(alias = "PWM_START1")]
    pub type PwmStart1 = crate::Reg<pwm_start1::PwmStart1Spec>;
    #[doc = "PWM group 1 start"]
    pub mod pwm_start1 {
        #[doc = "Register `PWM_START1` reader"]
        pub type R = crate::R<PwmStart1Spec>;
        #[doc = "Register `PWM_START1` writer"]
        pub type W = crate::W<PwmStart1Spec>;
        #[doc = "Field `pwm_start_1` writer - Start group 1 (self-clearing)"]
        pub type PwmStart1W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - Start group 1 (self-clearing)"]
            #[inline(always)]
            pub fn pwm_start_1(&mut self) -> PwmStart1W<'_, PwmStart1Spec> {
                PwmStart1W::new(self, 0)
            }
        }
        #[doc = "PWM group 1 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmStart1Spec;
        impl crate::RegisterSpec for PwmStart1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_start1::R`](R) reader structure"]
        impl crate::Readable for PwmStart1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_start1::W`](W) writer structure"]
        impl crate::Writable for PwmStart1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_START1 to value 0"]
        impl crate::Resettable for PwmStart1Spec {}
    }
    #[doc = "PWM_SEL2 (rw) register accessor: PWM group 2 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel2`] module"]
    #[doc(alias = "PWM_SEL2")]
    pub type PwmSel2 = crate::Reg<pwm_sel2::PwmSel2Spec>;
    #[doc = "PWM group 2 select"]
    pub mod pwm_sel2 {
        #[doc = "Register `PWM_SEL2` reader"]
        pub type R = crate::R<PwmSel2Spec>;
        #[doc = "Register `PWM_SEL2` writer"]
        pub type W = crate::W<PwmSel2Spec>;
        #[doc = "Field `pwm_sel_2` reader - Group 2 PWM select"]
        pub type PwmSel2R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_sel_2` writer - Group 2 PWM select"]
        pub type PwmSel2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Group 2 PWM select"]
            #[inline(always)]
            pub fn pwm_sel_2(&self) -> PwmSel2R {
                PwmSel2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Group 2 PWM select"]
            #[inline(always)]
            pub fn pwm_sel_2(&mut self) -> PwmSel2W<'_, PwmSel2Spec> {
                PwmSel2W::new(self, 0)
            }
        }
        #[doc = "PWM group 2 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmSel2Spec;
        impl crate::RegisterSpec for PwmSel2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_sel2::R`](R) reader structure"]
        impl crate::Readable for PwmSel2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_sel2::W`](W) writer structure"]
        impl crate::Writable for PwmSel2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_SEL2 to value 0"]
        impl crate::Resettable for PwmSel2Spec {}
    }
    #[doc = "PWM_STARTCLRCNT_EN2 (rw) register accessor: PWM group 2 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en2`] module"]
    #[doc(alias = "PWM_STARTCLRCNT_EN2")]
    pub type PwmStartclrcntEn2 = crate::Reg<pwm_startclrcnt_en2::PwmStartclrcntEn2Spec>;
    #[doc = "PWM group 2 start clear counter enable"]
    pub mod pwm_startclrcnt_en2 {
        #[doc = "Register `PWM_STARTCLRCNT_EN2` reader"]
        pub type R = crate::R<PwmStartclrcntEn2Spec>;
        #[doc = "Register `PWM_STARTCLRCNT_EN2` writer"]
        pub type W = crate::W<PwmStartclrcntEn2Spec>;
        #[doc = "Field `pwm_startclrcnt_en_2` reader - Start clear counter enable for group 2"]
        pub type PwmStartclrcntEn2R = crate::BitReader;
        #[doc = "Field `pwm_startclrcnt_en_2` writer - Start clear counter enable for group 2"]
        pub type PwmStartclrcntEn2W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Start clear counter enable for group 2"]
            #[inline(always)]
            pub fn pwm_startclrcnt_en_2(&self) -> PwmStartclrcntEn2R {
                PwmStartclrcntEn2R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Start clear counter enable for group 2"]
            #[inline(always)]
            pub fn pwm_startclrcnt_en_2(
                &mut self,
            ) -> PwmStartclrcntEn2W<'_, PwmStartclrcntEn2Spec> {
                PwmStartclrcntEn2W::new(self, 0)
            }
        }
        #[doc = "PWM group 2 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmStartclrcntEn2Spec;
        impl crate::RegisterSpec for PwmStartclrcntEn2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_startclrcnt_en2::R`](R) reader structure"]
        impl crate::Readable for PwmStartclrcntEn2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en2::W`](W) writer structure"]
        impl crate::Writable for PwmStartclrcntEn2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN2 to value 0"]
        impl crate::Resettable for PwmStartclrcntEn2Spec {}
    }
    #[doc = "PWM_START2 (rw) register accessor: PWM group 2 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start2`] module"]
    #[doc(alias = "PWM_START2")]
    pub type PwmStart2 = crate::Reg<pwm_start2::PwmStart2Spec>;
    #[doc = "PWM group 2 start"]
    pub mod pwm_start2 {
        #[doc = "Register `PWM_START2` reader"]
        pub type R = crate::R<PwmStart2Spec>;
        #[doc = "Register `PWM_START2` writer"]
        pub type W = crate::W<PwmStart2Spec>;
        #[doc = "Field `pwm_start_2` writer - Start group 2 (self-clearing)"]
        pub type PwmStart2W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - Start group 2 (self-clearing)"]
            #[inline(always)]
            pub fn pwm_start_2(&mut self) -> PwmStart2W<'_, PwmStart2Spec> {
                PwmStart2W::new(self, 0)
            }
        }
        #[doc = "PWM group 2 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmStart2Spec;
        impl crate::RegisterSpec for PwmStart2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_start2::R`](R) reader structure"]
        impl crate::Readable for PwmStart2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_start2::W`](W) writer structure"]
        impl crate::Writable for PwmStart2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_START2 to value 0"]
        impl crate::Resettable for PwmStart2Spec {}
    }
    #[doc = "PWM_SEL3 (rw) register accessor: PWM group 3 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_sel3`] module"]
    #[doc(alias = "PWM_SEL3")]
    pub type PwmSel3 = crate::Reg<pwm_sel3::PwmSel3Spec>;
    #[doc = "PWM group 3 select"]
    pub mod pwm_sel3 {
        #[doc = "Register `PWM_SEL3` reader"]
        pub type R = crate::R<PwmSel3Spec>;
        #[doc = "Register `PWM_SEL3` writer"]
        pub type W = crate::W<PwmSel3Spec>;
        #[doc = "Field `pwm_sel_3` reader - Group 3 PWM select"]
        pub type PwmSel3R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_sel_3` writer - Group 3 PWM select"]
        pub type PwmSel3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Group 3 PWM select"]
            #[inline(always)]
            pub fn pwm_sel_3(&self) -> PwmSel3R {
                PwmSel3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Group 3 PWM select"]
            #[inline(always)]
            pub fn pwm_sel_3(&mut self) -> PwmSel3W<'_, PwmSel3Spec> {
                PwmSel3W::new(self, 0)
            }
        }
        #[doc = "PWM group 3 select\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_sel3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_sel3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmSel3Spec;
        impl crate::RegisterSpec for PwmSel3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_sel3::R`](R) reader structure"]
        impl crate::Readable for PwmSel3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_sel3::W`](W) writer structure"]
        impl crate::Writable for PwmSel3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_SEL3 to value 0"]
        impl crate::Resettable for PwmSel3Spec {}
    }
    #[doc = "PWM_STARTCLRCNT_EN3 (rw) register accessor: PWM group 3 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_startclrcnt_en3`] module"]
    #[doc(alias = "PWM_STARTCLRCNT_EN3")]
    pub type PwmStartclrcntEn3 = crate::Reg<pwm_startclrcnt_en3::PwmStartclrcntEn3Spec>;
    #[doc = "PWM group 3 start clear counter enable"]
    pub mod pwm_startclrcnt_en3 {
        #[doc = "Register `PWM_STARTCLRCNT_EN3` reader"]
        pub type R = crate::R<PwmStartclrcntEn3Spec>;
        #[doc = "Register `PWM_STARTCLRCNT_EN3` writer"]
        pub type W = crate::W<PwmStartclrcntEn3Spec>;
        #[doc = "Field `pwm_startclrcnt_en_3` reader - Start clear counter enable for group 3"]
        pub type PwmStartclrcntEn3R = crate::BitReader;
        #[doc = "Field `pwm_startclrcnt_en_3` writer - Start clear counter enable for group 3"]
        pub type PwmStartclrcntEn3W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Start clear counter enable for group 3"]
            #[inline(always)]
            pub fn pwm_startclrcnt_en_3(&self) -> PwmStartclrcntEn3R {
                PwmStartclrcntEn3R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Start clear counter enable for group 3"]
            #[inline(always)]
            pub fn pwm_startclrcnt_en_3(
                &mut self,
            ) -> PwmStartclrcntEn3W<'_, PwmStartclrcntEn3Spec> {
                PwmStartclrcntEn3W::new(self, 0)
            }
        }
        #[doc = "PWM group 3 start clear counter enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_startclrcnt_en3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_startclrcnt_en3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmStartclrcntEn3Spec;
        impl crate::RegisterSpec for PwmStartclrcntEn3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_startclrcnt_en3::R`](R) reader structure"]
        impl crate::Readable for PwmStartclrcntEn3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_startclrcnt_en3::W`](W) writer structure"]
        impl crate::Writable for PwmStartclrcntEn3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_STARTCLRCNT_EN3 to value 0"]
        impl crate::Resettable for PwmStartclrcntEn3Spec {}
    }
    #[doc = "PWM_START3 (rw) register accessor: PWM group 3 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_start3`] module"]
    #[doc(alias = "PWM_START3")]
    pub type PwmStart3 = crate::Reg<pwm_start3::PwmStart3Spec>;
    #[doc = "PWM group 3 start"]
    pub mod pwm_start3 {
        #[doc = "Register `PWM_START3` reader"]
        pub type R = crate::R<PwmStart3Spec>;
        #[doc = "Register `PWM_START3` writer"]
        pub type W = crate::W<PwmStart3Spec>;
        #[doc = "Field `pwm_start_3` writer - Start group 3 (self-clearing)"]
        pub type PwmStart3W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - Start group 3 (self-clearing)"]
            #[inline(always)]
            pub fn pwm_start_3(&mut self) -> PwmStart3W<'_, PwmStart3Spec> {
                PwmStart3W::new(self, 0)
            }
        }
        #[doc = "PWM group 3 start\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_start3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_start3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmStart3Spec;
        impl crate::RegisterSpec for PwmStart3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_start3::R`](R) reader structure"]
        impl crate::Readable for PwmStart3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_start3::W`](W) writer structure"]
        impl crate::Writable for PwmStart3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_START3 to value 0"]
        impl crate::Resettable for PwmStart3Spec {}
    }
    #[doc = "PWM_EN0 (rw) register accessor: PWM0 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en0`] module"]
    #[doc(alias = "PWM_EN0")]
    pub type PwmEn0 = crate::Reg<pwm_en0::PwmEn0Spec>;
    #[doc = "PWM0 enable"]
    pub mod pwm_en0 {
        #[doc = "Register `PWM_EN0` reader"]
        pub type R = crate::R<PwmEn0Spec>;
        #[doc = "Register `PWM_EN0` writer"]
        pub type W = crate::W<PwmEn0Spec>;
        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmEn0 {
            #[doc = "0: PWM disabled, output low"]
            Off = 0,
            #[doc = "1: PWM enabled"]
            On = 1,
        }
        impl From<PwmEn0> for bool {
            #[inline(always)]
            fn from(variant: PwmEn0) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_en_0` reader - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn0R = crate::BitReader<PwmEn0>;
        impl PwmEn0R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmEn0 {
                match self.bits {
                    false => PwmEn0::Off,
                    true => PwmEn0::On,
                }
            }
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn is_off(&self) -> bool {
                *self == PwmEn0::Off
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn is_on(&self) -> bool {
                *self == PwmEn0::On
            }
        }
        #[doc = "Field `pwm_en_0` writer - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn0W<'a, REG> = crate::BitWriter<'a, REG, PwmEn0>;
        impl<'a, REG> PwmEn0W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn off(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn0::Off)
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn on(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn0::On)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_0(&self) -> PwmEn0R {
                PwmEn0R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_0(&mut self) -> PwmEn0W<'_, PwmEn0Spec> {
                PwmEn0W::new(self, 0)
            }
        }
        #[doc = "PWM0 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmEn0Spec;
        impl crate::RegisterSpec for PwmEn0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_en0::R`](R) reader structure"]
        impl crate::Readable for PwmEn0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_en0::W`](W) writer structure"]
        impl crate::Writable for PwmEn0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_EN0 to value 0"]
        impl crate::Resettable for PwmEn0Spec {}
    }
    #[doc = "PWM_PORTITY0 (rw) register accessor: PWM0 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity0`] module"]
    #[doc(alias = "PWM_PORTITY0")]
    pub type PwmPortity0 = crate::Reg<pwm_portity0::PwmPortity0Spec>;
    #[doc = "PWM0 polarity"]
    pub mod pwm_portity0 {
        #[doc = "Register `PWM_PORTITY0` reader"]
        pub type R = crate::R<PwmPortity0Spec>;
        #[doc = "Register `PWM_PORTITY0` writer"]
        pub type W = crate::W<PwmPortity0Spec>;
        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmPoarity0 {
            #[doc = "0: Normal polarity"]
            Normal = 0,
            #[doc = "1: Inverted polarity"]
            Inverted = 1,
        }
        impl From<PwmPoarity0> for bool {
            #[inline(always)]
            fn from(variant: PwmPoarity0) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_poarity_0` reader - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity0R = crate::BitReader<PwmPoarity0>;
        impl PwmPoarity0R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmPoarity0 {
                match self.bits {
                    false => PwmPoarity0::Normal,
                    true => PwmPoarity0::Inverted,
                }
            }
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn is_normal(&self) -> bool {
                *self == PwmPoarity0::Normal
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn is_inverted(&self) -> bool {
                *self == PwmPoarity0::Inverted
            }
        }
        #[doc = "Field `pwm_poarity_0` writer - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity0W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity0>;
        impl<'a, REG> PwmPoarity0W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn normal(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity0::Normal)
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn inverted(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity0::Inverted)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_0(&self) -> PwmPoarity0R {
                PwmPoarity0R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_0(&mut self) -> PwmPoarity0W<'_, PwmPortity0Spec> {
                PwmPoarity0W::new(self, 0)
            }
        }
        #[doc = "PWM0 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPortity0Spec;
        impl crate::RegisterSpec for PwmPortity0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_portity0::R`](R) reader structure"]
        impl crate::Readable for PwmPortity0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_portity0::W`](W) writer structure"]
        impl crate::Writable for PwmPortity0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PORTITY0 to value 0"]
        impl crate::Resettable for PwmPortity0Spec {}
    }
    #[doc = "PWM_OEN_CFG0 (rw) register accessor: PWM0 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg0`] module"]
    #[doc(alias = "PWM_OEN_CFG0")]
    pub type PwmOenCfg0 = crate::Reg<pwm_oen_cfg0::PwmOenCfg0Spec>;
    #[doc = "PWM0 high-impedance config"]
    pub mod pwm_oen_cfg0 {
        #[doc = "Register `PWM_OEN_CFG0` reader"]
        pub type R = crate::R<PwmOenCfg0Spec>;
        #[doc = "Register `PWM_OEN_CFG0` writer"]
        pub type W = crate::W<PwmOenCfg0Spec>;
        #[doc = "Field `pwm_oen_cfg_0` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg0R = crate::BitReader;
        #[doc = "Field `pwm_oen_cfg_0` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg0W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_0(&self) -> PwmOenCfg0R {
                PwmOenCfg0R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_0(&mut self) -> PwmOenCfg0W<'_, PwmOenCfg0Spec> {
                PwmOenCfg0W::new(self, 0)
            }
        }
        #[doc = "PWM0 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOenCfg0Spec;
        impl crate::RegisterSpec for PwmOenCfg0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_oen_cfg0::R`](R) reader structure"]
        impl crate::Readable for PwmOenCfg0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg0::W`](W) writer structure"]
        impl crate::Writable for PwmOenCfg0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OEN_CFG0 to value 0"]
        impl crate::Resettable for PwmOenCfg0Spec {}
    }
    #[doc = "PWM_OFFSET_L0 (rw) register accessor: PWM0 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l0`] module"]
    #[doc(alias = "PWM_OFFSET_L0")]
    pub type PwmOffsetL0 = crate::Reg<pwm_offset_l0::PwmOffsetL0Spec>;
    #[doc = "PWM0 phase offset low 16 bits"]
    pub mod pwm_offset_l0 {
        #[doc = "Register `PWM_OFFSET_L0` reader"]
        pub type R = crate::R<PwmOffsetL0Spec>;
        #[doc = "Register `PWM_OFFSET_L0` writer"]
        pub type W = crate::W<PwmOffsetL0Spec>;
        #[doc = "Field `pwm_offset_l_0` reader - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL0R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_l_0` writer - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_0(&self) -> PwmOffsetL0R {
                PwmOffsetL0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_0(&mut self) -> PwmOffsetL0W<'_, PwmOffsetL0Spec> {
                PwmOffsetL0W::new(self, 0)
            }
        }
        #[doc = "PWM0 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetL0Spec;
        impl crate::RegisterSpec for PwmOffsetL0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_l0::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetL0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l0::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetL0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_L0 to value 0"]
        impl crate::Resettable for PwmOffsetL0Spec {}
    }
    #[doc = "PWM_OFFSET_H0 (rw) register accessor: PWM0 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h0`] module"]
    #[doc(alias = "PWM_OFFSET_H0")]
    pub type PwmOffsetH0 = crate::Reg<pwm_offset_h0::PwmOffsetH0Spec>;
    #[doc = "PWM0 phase offset high 16 bits"]
    pub mod pwm_offset_h0 {
        #[doc = "Register `PWM_OFFSET_H0` reader"]
        pub type R = crate::R<PwmOffsetH0Spec>;
        #[doc = "Register `PWM_OFFSET_H0` writer"]
        pub type W = crate::W<PwmOffsetH0Spec>;
        #[doc = "Field `pwm_offset_h_0` reader - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH0R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_h_0` writer - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_0(&self) -> PwmOffsetH0R {
                PwmOffsetH0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_0(&mut self) -> PwmOffsetH0W<'_, PwmOffsetH0Spec> {
                PwmOffsetH0W::new(self, 0)
            }
        }
        #[doc = "PWM0 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetH0Spec;
        impl crate::RegisterSpec for PwmOffsetH0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_h0::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetH0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h0::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetH0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_H0 to value 0"]
        impl crate::Resettable for PwmOffsetH0Spec {}
    }
    #[doc = "PWM_FREQ_L0 (rw) register accessor: PWM0 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l0`] module"]
    #[doc(alias = "PWM_FREQ_L0")]
    pub type PwmFreqL0 = crate::Reg<pwm_freq_l0::PwmFreqL0Spec>;
    #[doc = "PWM0 frequency low 16 bits"]
    pub mod pwm_freq_l0 {
        #[doc = "Register `PWM_FREQ_L0` reader"]
        pub type R = crate::R<PwmFreqL0Spec>;
        #[doc = "Register `PWM_FREQ_L0` writer"]
        pub type W = crate::W<PwmFreqL0Spec>;
        #[doc = "Field `pwm_freq_l_0` reader - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL0R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_l_0` writer - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_0(&self) -> PwmFreqL0R {
                PwmFreqL0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_0(&mut self) -> PwmFreqL0W<'_, PwmFreqL0Spec> {
                PwmFreqL0W::new(self, 0)
            }
        }
        #[doc = "PWM0 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqL0Spec;
        impl crate::RegisterSpec for PwmFreqL0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_l0::R`](R) reader structure"]
        impl crate::Readable for PwmFreqL0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l0::W`](W) writer structure"]
        impl crate::Writable for PwmFreqL0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_L0 to value 0"]
        impl crate::Resettable for PwmFreqL0Spec {}
    }
    #[doc = "PWM_FREQ_H0 (rw) register accessor: PWM0 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h0`] module"]
    #[doc(alias = "PWM_FREQ_H0")]
    pub type PwmFreqH0 = crate::Reg<pwm_freq_h0::PwmFreqH0Spec>;
    #[doc = "PWM0 frequency high 16 bits"]
    pub mod pwm_freq_h0 {
        #[doc = "Register `PWM_FREQ_H0` reader"]
        pub type R = crate::R<PwmFreqH0Spec>;
        #[doc = "Register `PWM_FREQ_H0` writer"]
        pub type W = crate::W<PwmFreqH0Spec>;
        #[doc = "Field `pwm_freq_h_0` reader - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH0R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_h_0` writer - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_0(&self) -> PwmFreqH0R {
                PwmFreqH0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_0(&mut self) -> PwmFreqH0W<'_, PwmFreqH0Spec> {
                PwmFreqH0W::new(self, 0)
            }
        }
        #[doc = "PWM0 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqH0Spec;
        impl crate::RegisterSpec for PwmFreqH0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_h0::R`](R) reader structure"]
        impl crate::Readable for PwmFreqH0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h0::W`](W) writer structure"]
        impl crate::Writable for PwmFreqH0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_H0 to value 0"]
        impl crate::Resettable for PwmFreqH0Spec {}
    }
    #[doc = "PWM_DUTY_L0 (rw) register accessor: PWM0 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l0`] module"]
    #[doc(alias = "PWM_DUTY_L0")]
    pub type PwmDutyL0 = crate::Reg<pwm_duty_l0::PwmDutyL0Spec>;
    #[doc = "PWM0 duty cycle low 16 bits"]
    pub mod pwm_duty_l0 {
        #[doc = "Register `PWM_DUTY_L0` reader"]
        pub type R = crate::R<PwmDutyL0Spec>;
        #[doc = "Register `PWM_DUTY_L0` writer"]
        pub type W = crate::W<PwmDutyL0Spec>;
        #[doc = "Field `pwm_duty_l_0` reader - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL0R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_l_0` writer - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_0(&self) -> PwmDutyL0R {
                PwmDutyL0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_0(&mut self) -> PwmDutyL0W<'_, PwmDutyL0Spec> {
                PwmDutyL0W::new(self, 0)
            }
        }
        #[doc = "PWM0 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyL0Spec;
        impl crate::RegisterSpec for PwmDutyL0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_l0::R`](R) reader structure"]
        impl crate::Readable for PwmDutyL0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l0::W`](W) writer structure"]
        impl crate::Writable for PwmDutyL0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_L0 to value 0"]
        impl crate::Resettable for PwmDutyL0Spec {}
    }
    #[doc = "PWM_DUTY_H0 (rw) register accessor: PWM0 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h0`] module"]
    #[doc(alias = "PWM_DUTY_H0")]
    pub type PwmDutyH0 = crate::Reg<pwm_duty_h0::PwmDutyH0Spec>;
    #[doc = "PWM0 duty cycle high 16 bits"]
    pub mod pwm_duty_h0 {
        #[doc = "Register `PWM_DUTY_H0` reader"]
        pub type R = crate::R<PwmDutyH0Spec>;
        #[doc = "Register `PWM_DUTY_H0` writer"]
        pub type W = crate::W<PwmDutyH0Spec>;
        #[doc = "Field `pwm_duty_h_0` reader - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH0R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_h_0` writer - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_0(&self) -> PwmDutyH0R {
                PwmDutyH0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_0(&mut self) -> PwmDutyH0W<'_, PwmDutyH0Spec> {
                PwmDutyH0W::new(self, 0)
            }
        }
        #[doc = "PWM0 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyH0Spec;
        impl crate::RegisterSpec for PwmDutyH0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_h0::R`](R) reader structure"]
        impl crate::Readable for PwmDutyH0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h0::W`](W) writer structure"]
        impl crate::Writable for PwmDutyH0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_H0 to value 0"]
        impl crate::Resettable for PwmDutyH0Spec {}
    }
    #[doc = "PWM_PERIODLOAD_FLAG0 (rw) register accessor: PWM0 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag0`] module"]
    #[doc(alias = "PWM_PERIODLOAD_FLAG0")]
    pub type PwmPeriodloadFlag0 = crate::Reg<pwm_periodload_flag0::PwmPeriodloadFlag0Spec>;
    #[doc = "PWM0 period load flag"]
    pub mod pwm_periodload_flag0 {
        #[doc = "Register `PWM_PERIODLOAD_FLAG0` reader"]
        pub type R = crate::R<PwmPeriodloadFlag0Spec>;
        #[doc = "Register `PWM_PERIODLOAD_FLAG0` writer"]
        pub type W = crate::W<PwmPeriodloadFlag0Spec>;
        #[doc = "Field `pwm_periodload_flag_0` reader - Period load complete flag"]
        pub type PwmPeriodloadFlag0R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Period load complete flag"]
            #[inline(always)]
            pub fn pwm_periodload_flag_0(&self) -> PwmPeriodloadFlag0R {
                PwmPeriodloadFlag0R::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "PWM0 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodloadFlag0Spec;
        impl crate::RegisterSpec for PwmPeriodloadFlag0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodload_flag0::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodloadFlag0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag0::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodloadFlag0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG0 to value 0"]
        impl crate::Resettable for PwmPeriodloadFlag0Spec {}
    }
    #[doc = "PWM_PERIOD_VAL0 (rw) register accessor: PWM0 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val0`] module"]
    #[doc(alias = "PWM_PERIOD_VAL0")]
    pub type PwmPeriodVal0 = crate::Reg<pwm_period_val0::PwmPeriodVal0Spec>;
    #[doc = "PWM0 pulse count value"]
    pub mod pwm_period_val0 {
        #[doc = "Register `PWM_PERIOD_VAL0` reader"]
        pub type R = crate::R<PwmPeriodVal0Spec>;
        #[doc = "Register `PWM_PERIOD_VAL0` writer"]
        pub type W = crate::W<PwmPeriodVal0Spec>;
        #[doc = "Field `pwm_period_val_0` reader - Pulse count for stepping mode"]
        pub type PwmPeriodVal0R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_period_val_0` writer - Pulse count for stepping mode"]
        pub type PwmPeriodVal0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_0(&self) -> PwmPeriodVal0R {
                PwmPeriodVal0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_0(&mut self) -> PwmPeriodVal0W<'_, PwmPeriodVal0Spec> {
                PwmPeriodVal0W::new(self, 0)
            }
        }
        #[doc = "PWM0 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodVal0Spec;
        impl crate::RegisterSpec for PwmPeriodVal0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_period_val0::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodVal0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_period_val0::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodVal0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIOD_VAL0 to value 0"]
        impl crate::Resettable for PwmPeriodVal0Spec {}
    }
    #[doc = "PWM_PERIODCNT0 (rw) register accessor: PWM0 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt0`] module"]
    #[doc(alias = "PWM_PERIODCNT0")]
    pub type PwmPeriodcnt0 = crate::Reg<pwm_periodcnt0::PwmPeriodcnt0Spec>;
    #[doc = "PWM0 pulse count current value"]
    pub mod pwm_periodcnt0 {
        #[doc = "Register `PWM_PERIODCNT0` reader"]
        pub type R = crate::R<PwmPeriodcnt0Spec>;
        #[doc = "Register `PWM_PERIODCNT0` writer"]
        pub type W = crate::W<PwmPeriodcnt0Spec>;
        #[doc = "Field `pwm_periodcnt_0` reader - Current pulse count"]
        pub type PwmPeriodcnt0R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Current pulse count"]
            #[inline(always)]
            pub fn pwm_periodcnt_0(&self) -> PwmPeriodcnt0R {
                PwmPeriodcnt0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM0 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodcnt0Spec;
        impl crate::RegisterSpec for PwmPeriodcnt0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodcnt0::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodcnt0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt0::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodcnt0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODCNT0 to value 0"]
        impl crate::Resettable for PwmPeriodcnt0Spec {}
    }
    #[doc = "PWM_EN1 (rw) register accessor: PWM1 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en1`] module"]
    #[doc(alias = "PWM_EN1")]
    pub type PwmEn1 = crate::Reg<pwm_en1::PwmEn1Spec>;
    #[doc = "PWM1 enable"]
    pub mod pwm_en1 {
        #[doc = "Register `PWM_EN1` reader"]
        pub type R = crate::R<PwmEn1Spec>;
        #[doc = "Register `PWM_EN1` writer"]
        pub type W = crate::W<PwmEn1Spec>;
        #[doc = "Field `pwm_en_1` reader - PWM1 enable"]
        pub type PwmEn1R = crate::BitReader;
        #[doc = "Field `pwm_en_1` writer - PWM1 enable"]
        pub type PwmEn1W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM1 enable"]
            #[inline(always)]
            pub fn pwm_en_1(&self) -> PwmEn1R {
                PwmEn1R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM1 enable"]
            #[inline(always)]
            pub fn pwm_en_1(&mut self) -> PwmEn1W<'_, PwmEn1Spec> {
                PwmEn1W::new(self, 0)
            }
        }
        #[doc = "PWM1 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmEn1Spec;
        impl crate::RegisterSpec for PwmEn1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_en1::R`](R) reader structure"]
        impl crate::Readable for PwmEn1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_en1::W`](W) writer structure"]
        impl crate::Writable for PwmEn1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_EN1 to value 0"]
        impl crate::Resettable for PwmEn1Spec {}
    }
    #[doc = "PWM_PORTITY1 (rw) register accessor: PWM1 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity1`] module"]
    #[doc(alias = "PWM_PORTITY1")]
    pub type PwmPortity1 = crate::Reg<pwm_portity1::PwmPortity1Spec>;
    #[doc = "PWM1 polarity"]
    pub mod pwm_portity1 {
        #[doc = "Register `PWM_PORTITY1` reader"]
        pub type R = crate::R<PwmPortity1Spec>;
        #[doc = "Register `PWM_PORTITY1` writer"]
        pub type W = crate::W<PwmPortity1Spec>;
        #[doc = "Field `pwm_poarity_1` reader - PWM1 polarity"]
        pub type PwmPoarity1R = crate::BitReader;
        #[doc = "Field `pwm_poarity_1` writer - PWM1 polarity"]
        pub type PwmPoarity1W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM1 polarity"]
            #[inline(always)]
            pub fn pwm_poarity_1(&self) -> PwmPoarity1R {
                PwmPoarity1R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM1 polarity"]
            #[inline(always)]
            pub fn pwm_poarity_1(&mut self) -> PwmPoarity1W<'_, PwmPortity1Spec> {
                PwmPoarity1W::new(self, 0)
            }
        }
        #[doc = "PWM1 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPortity1Spec;
        impl crate::RegisterSpec for PwmPortity1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_portity1::R`](R) reader structure"]
        impl crate::Readable for PwmPortity1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_portity1::W`](W) writer structure"]
        impl crate::Writable for PwmPortity1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PORTITY1 to value 0"]
        impl crate::Resettable for PwmPortity1Spec {}
    }
    #[doc = "PWM_OEN_CFG1 (rw) register accessor: PWM1 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg1`] module"]
    #[doc(alias = "PWM_OEN_CFG1")]
    pub type PwmOenCfg1 = crate::Reg<pwm_oen_cfg1::PwmOenCfg1Spec>;
    #[doc = "PWM1 high-impedance config"]
    pub mod pwm_oen_cfg1 {
        #[doc = "Register `PWM_OEN_CFG1` reader"]
        pub type R = crate::R<PwmOenCfg1Spec>;
        #[doc = "Register `PWM_OEN_CFG1` writer"]
        pub type W = crate::W<PwmOenCfg1Spec>;
        #[doc = "Field `pwm_oen_cfg_1` reader - PWM1 high-Z enable"]
        pub type PwmOenCfg1R = crate::BitReader;
        #[doc = "Field `pwm_oen_cfg_1` writer - PWM1 high-Z enable"]
        pub type PwmOenCfg1W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM1 high-Z enable"]
            #[inline(always)]
            pub fn pwm_oen_cfg_1(&self) -> PwmOenCfg1R {
                PwmOenCfg1R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM1 high-Z enable"]
            #[inline(always)]
            pub fn pwm_oen_cfg_1(&mut self) -> PwmOenCfg1W<'_, PwmOenCfg1Spec> {
                PwmOenCfg1W::new(self, 0)
            }
        }
        #[doc = "PWM1 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOenCfg1Spec;
        impl crate::RegisterSpec for PwmOenCfg1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_oen_cfg1::R`](R) reader structure"]
        impl crate::Readable for PwmOenCfg1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg1::W`](W) writer structure"]
        impl crate::Writable for PwmOenCfg1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OEN_CFG1 to value 0"]
        impl crate::Resettable for PwmOenCfg1Spec {}
    }
    #[doc = "PWM_OFFSET_L1 (rw) register accessor: PWM1 phase offset low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l1`] module"]
    #[doc(alias = "PWM_OFFSET_L1")]
    pub type PwmOffsetL1 = crate::Reg<pwm_offset_l1::PwmOffsetL1Spec>;
    #[doc = "PWM1 phase offset low"]
    pub mod pwm_offset_l1 {
        #[doc = "Register `PWM_OFFSET_L1` reader"]
        pub type R = crate::R<PwmOffsetL1Spec>;
        #[doc = "Register `PWM_OFFSET_L1` writer"]
        pub type W = crate::W<PwmOffsetL1Spec>;
        #[doc = "Field `pwm_offset_l_1` reader - PWM1 phase offset low 16 bits"]
        pub type PwmOffsetL1R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_l_1` writer - PWM1 phase offset low 16 bits"]
        pub type PwmOffsetL1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM1 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_1(&self) -> PwmOffsetL1R {
                PwmOffsetL1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM1 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_1(&mut self) -> PwmOffsetL1W<'_, PwmOffsetL1Spec> {
                PwmOffsetL1W::new(self, 0)
            }
        }
        #[doc = "PWM1 phase offset low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetL1Spec;
        impl crate::RegisterSpec for PwmOffsetL1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_l1::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetL1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l1::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetL1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_L1 to value 0"]
        impl crate::Resettable for PwmOffsetL1Spec {}
    }
    #[doc = "PWM_OFFSET_H1 (rw) register accessor: PWM1 phase offset high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h1`] module"]
    #[doc(alias = "PWM_OFFSET_H1")]
    pub type PwmOffsetH1 = crate::Reg<pwm_offset_h1::PwmOffsetH1Spec>;
    #[doc = "PWM1 phase offset high"]
    pub mod pwm_offset_h1 {
        #[doc = "Register `PWM_OFFSET_H1` reader"]
        pub type R = crate::R<PwmOffsetH1Spec>;
        #[doc = "Register `PWM_OFFSET_H1` writer"]
        pub type W = crate::W<PwmOffsetH1Spec>;
        #[doc = "Field `pwm_offset_h_1` reader - PWM1 phase offset high 16 bits"]
        pub type PwmOffsetH1R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_h_1` writer - PWM1 phase offset high 16 bits"]
        pub type PwmOffsetH1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM1 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_1(&self) -> PwmOffsetH1R {
                PwmOffsetH1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM1 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_1(&mut self) -> PwmOffsetH1W<'_, PwmOffsetH1Spec> {
                PwmOffsetH1W::new(self, 0)
            }
        }
        #[doc = "PWM1 phase offset high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetH1Spec;
        impl crate::RegisterSpec for PwmOffsetH1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_h1::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetH1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h1::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetH1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_H1 to value 0"]
        impl crate::Resettable for PwmOffsetH1Spec {}
    }
    #[doc = "PWM_FREQ_L1 (rw) register accessor: PWM1 frequency low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l1`] module"]
    #[doc(alias = "PWM_FREQ_L1")]
    pub type PwmFreqL1 = crate::Reg<pwm_freq_l1::PwmFreqL1Spec>;
    #[doc = "PWM1 frequency low"]
    pub mod pwm_freq_l1 {
        #[doc = "Register `PWM_FREQ_L1` reader"]
        pub type R = crate::R<PwmFreqL1Spec>;
        #[doc = "Register `PWM_FREQ_L1` writer"]
        pub type W = crate::W<PwmFreqL1Spec>;
        #[doc = "Field `pwm_freq_l_1` reader - PWM1 clock divider low 16 bits"]
        pub type PwmFreqL1R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_l_1` writer - PWM1 clock divider low 16 bits"]
        pub type PwmFreqL1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM1 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_1(&self) -> PwmFreqL1R {
                PwmFreqL1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM1 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_1(&mut self) -> PwmFreqL1W<'_, PwmFreqL1Spec> {
                PwmFreqL1W::new(self, 0)
            }
        }
        #[doc = "PWM1 frequency low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqL1Spec;
        impl crate::RegisterSpec for PwmFreqL1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_l1::R`](R) reader structure"]
        impl crate::Readable for PwmFreqL1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l1::W`](W) writer structure"]
        impl crate::Writable for PwmFreqL1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_L1 to value 0"]
        impl crate::Resettable for PwmFreqL1Spec {}
    }
    #[doc = "PWM_FREQ_H1 (rw) register accessor: PWM1 frequency high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h1`] module"]
    #[doc(alias = "PWM_FREQ_H1")]
    pub type PwmFreqH1 = crate::Reg<pwm_freq_h1::PwmFreqH1Spec>;
    #[doc = "PWM1 frequency high"]
    pub mod pwm_freq_h1 {
        #[doc = "Register `PWM_FREQ_H1` reader"]
        pub type R = crate::R<PwmFreqH1Spec>;
        #[doc = "Register `PWM_FREQ_H1` writer"]
        pub type W = crate::W<PwmFreqH1Spec>;
        #[doc = "Field `pwm_freq_h_1` reader - PWM1 clock divider high 16 bits"]
        pub type PwmFreqH1R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_h_1` writer - PWM1 clock divider high 16 bits"]
        pub type PwmFreqH1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM1 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_1(&self) -> PwmFreqH1R {
                PwmFreqH1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM1 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_1(&mut self) -> PwmFreqH1W<'_, PwmFreqH1Spec> {
                PwmFreqH1W::new(self, 0)
            }
        }
        #[doc = "PWM1 frequency high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqH1Spec;
        impl crate::RegisterSpec for PwmFreqH1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_h1::R`](R) reader structure"]
        impl crate::Readable for PwmFreqH1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h1::W`](W) writer structure"]
        impl crate::Writable for PwmFreqH1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_H1 to value 0"]
        impl crate::Resettable for PwmFreqH1Spec {}
    }
    #[doc = "PWM_DUTY_L1 (rw) register accessor: PWM1 duty cycle low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l1`] module"]
    #[doc(alias = "PWM_DUTY_L1")]
    pub type PwmDutyL1 = crate::Reg<pwm_duty_l1::PwmDutyL1Spec>;
    #[doc = "PWM1 duty cycle low"]
    pub mod pwm_duty_l1 {
        #[doc = "Register `PWM_DUTY_L1` reader"]
        pub type R = crate::R<PwmDutyL1Spec>;
        #[doc = "Register `PWM_DUTY_L1` writer"]
        pub type W = crate::W<PwmDutyL1Spec>;
        #[doc = "Field `pwm_duty_l_1` reader - PWM1 duty low 16 bits"]
        pub type PwmDutyL1R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_l_1` writer - PWM1 duty low 16 bits"]
        pub type PwmDutyL1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM1 duty low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_1(&self) -> PwmDutyL1R {
                PwmDutyL1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM1 duty low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_1(&mut self) -> PwmDutyL1W<'_, PwmDutyL1Spec> {
                PwmDutyL1W::new(self, 0)
            }
        }
        #[doc = "PWM1 duty cycle low\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyL1Spec;
        impl crate::RegisterSpec for PwmDutyL1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_l1::R`](R) reader structure"]
        impl crate::Readable for PwmDutyL1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l1::W`](W) writer structure"]
        impl crate::Writable for PwmDutyL1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_L1 to value 0"]
        impl crate::Resettable for PwmDutyL1Spec {}
    }
    #[doc = "PWM_DUTY_H1 (rw) register accessor: PWM1 duty cycle high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h1`] module"]
    #[doc(alias = "PWM_DUTY_H1")]
    pub type PwmDutyH1 = crate::Reg<pwm_duty_h1::PwmDutyH1Spec>;
    #[doc = "PWM1 duty cycle high"]
    pub mod pwm_duty_h1 {
        #[doc = "Register `PWM_DUTY_H1` reader"]
        pub type R = crate::R<PwmDutyH1Spec>;
        #[doc = "Register `PWM_DUTY_H1` writer"]
        pub type W = crate::W<PwmDutyH1Spec>;
        #[doc = "Field `pwm_duty_h_1` reader - PWM1 duty high 16 bits"]
        pub type PwmDutyH1R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_h_1` writer - PWM1 duty high 16 bits"]
        pub type PwmDutyH1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM1 duty high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_1(&self) -> PwmDutyH1R {
                PwmDutyH1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM1 duty high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_1(&mut self) -> PwmDutyH1W<'_, PwmDutyH1Spec> {
                PwmDutyH1W::new(self, 0)
            }
        }
        #[doc = "PWM1 duty cycle high\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyH1Spec;
        impl crate::RegisterSpec for PwmDutyH1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_h1::R`](R) reader structure"]
        impl crate::Readable for PwmDutyH1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h1::W`](W) writer structure"]
        impl crate::Writable for PwmDutyH1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_H1 to value 0"]
        impl crate::Resettable for PwmDutyH1Spec {}
    }
    #[doc = "PWM_PERIODLOAD_FLAG1 (rw) register accessor: PWM1 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag1`] module"]
    #[doc(alias = "PWM_PERIODLOAD_FLAG1")]
    pub type PwmPeriodloadFlag1 = crate::Reg<pwm_periodload_flag1::PwmPeriodloadFlag1Spec>;
    #[doc = "PWM1 period load flag"]
    pub mod pwm_periodload_flag1 {
        #[doc = "Register `PWM_PERIODLOAD_FLAG1` reader"]
        pub type R = crate::R<PwmPeriodloadFlag1Spec>;
        #[doc = "Register `PWM_PERIODLOAD_FLAG1` writer"]
        pub type W = crate::W<PwmPeriodloadFlag1Spec>;
        #[doc = "Field `pwm_periodload_flag_1` reader - Period load flag"]
        pub type PwmPeriodloadFlag1R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Period load flag"]
            #[inline(always)]
            pub fn pwm_periodload_flag_1(&self) -> PwmPeriodloadFlag1R {
                PwmPeriodloadFlag1R::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "PWM1 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodloadFlag1Spec;
        impl crate::RegisterSpec for PwmPeriodloadFlag1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodload_flag1::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodloadFlag1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag1::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodloadFlag1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG1 to value 0"]
        impl crate::Resettable for PwmPeriodloadFlag1Spec {}
    }
    #[doc = "PWM_PERIOD_VAL1 (rw) register accessor: PWM1 pulse count\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val1`] module"]
    #[doc(alias = "PWM_PERIOD_VAL1")]
    pub type PwmPeriodVal1 = crate::Reg<pwm_period_val1::PwmPeriodVal1Spec>;
    #[doc = "PWM1 pulse count"]
    pub mod pwm_period_val1 {
        #[doc = "Register `PWM_PERIOD_VAL1` reader"]
        pub type R = crate::R<PwmPeriodVal1Spec>;
        #[doc = "Register `PWM_PERIOD_VAL1` writer"]
        pub type W = crate::W<PwmPeriodVal1Spec>;
        #[doc = "Field `pwm_period_val_1` reader - Pulse count"]
        pub type PwmPeriodVal1R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_period_val_1` writer - Pulse count"]
        pub type PwmPeriodVal1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Pulse count"]
            #[inline(always)]
            pub fn pwm_period_val_1(&self) -> PwmPeriodVal1R {
                PwmPeriodVal1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Pulse count"]
            #[inline(always)]
            pub fn pwm_period_val_1(&mut self) -> PwmPeriodVal1W<'_, PwmPeriodVal1Spec> {
                PwmPeriodVal1W::new(self, 0)
            }
        }
        #[doc = "PWM1 pulse count\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodVal1Spec;
        impl crate::RegisterSpec for PwmPeriodVal1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_period_val1::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodVal1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_period_val1::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodVal1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIOD_VAL1 to value 0"]
        impl crate::Resettable for PwmPeriodVal1Spec {}
    }
    #[doc = "PWM_PERIODCNT1 (rw) register accessor: PWM1 pulse count current\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt1`] module"]
    #[doc(alias = "PWM_PERIODCNT1")]
    pub type PwmPeriodcnt1 = crate::Reg<pwm_periodcnt1::PwmPeriodcnt1Spec>;
    #[doc = "PWM1 pulse count current"]
    pub mod pwm_periodcnt1 {
        #[doc = "Register `PWM_PERIODCNT1` reader"]
        pub type R = crate::R<PwmPeriodcnt1Spec>;
        #[doc = "Register `PWM_PERIODCNT1` writer"]
        pub type W = crate::W<PwmPeriodcnt1Spec>;
        #[doc = "Field `pwm_periodcnt_1` reader - Current pulse count"]
        pub type PwmPeriodcnt1R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Current pulse count"]
            #[inline(always)]
            pub fn pwm_periodcnt_1(&self) -> PwmPeriodcnt1R {
                PwmPeriodcnt1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM1 pulse count current\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodcnt1Spec;
        impl crate::RegisterSpec for PwmPeriodcnt1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodcnt1::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodcnt1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt1::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodcnt1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODCNT1 to value 0"]
        impl crate::Resettable for PwmPeriodcnt1Spec {}
    }
    #[doc = "PWM_ABNOR_STATE0 (rw) register accessor: PWM abnormal state register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state0`] module"]
    #[doc(alias = "PWM_ABNOR_STATE0")]
    pub type PwmAbnorState0 = crate::Reg<pwm_abnor_state0::PwmAbnorState0Spec>;
    #[doc = "PWM abnormal state register 0"]
    pub mod pwm_abnor_state0 {
        #[doc = "Register `PWM_ABNOR_STATE0` reader"]
        pub type R = crate::R<PwmAbnorState0Spec>;
        #[doc = "Register `PWM_ABNOR_STATE0` writer"]
        pub type W = crate::W<PwmAbnorState0Spec>;
        #[doc = "Field `pwm_abnor_state0` reader - Multi-channel config abnormal state, each bit per PWM"]
        pub type PwmAbnorState0R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Multi-channel config abnormal state, each bit per PWM"]
            #[inline(always)]
            pub fn pwm_abnor_state0(&self) -> PwmAbnorState0R {
                PwmAbnorState0R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM abnormal state register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmAbnorState0Spec;
        impl crate::RegisterSpec for PwmAbnorState0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_abnor_state0::R`](R) reader structure"]
        impl crate::Readable for PwmAbnorState0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state0::W`](W) writer structure"]
        impl crate::Writable for PwmAbnorState0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_ABNOR_STATE0 to value 0"]
        impl crate::Resettable for PwmAbnorState0Spec {}
    }
    #[doc = "PWM_ABNOR_STATE1 (rw) register accessor: PWM abnormal state register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state1`] module"]
    #[doc(alias = "PWM_ABNOR_STATE1")]
    pub type PwmAbnorState1 = crate::Reg<pwm_abnor_state1::PwmAbnorState1Spec>;
    #[doc = "PWM abnormal state register 1"]
    pub mod pwm_abnor_state1 {
        #[doc = "Register `PWM_ABNOR_STATE1` reader"]
        pub type R = crate::R<PwmAbnorState1Spec>;
        #[doc = "Register `PWM_ABNOR_STATE1` writer"]
        pub type W = crate::W<PwmAbnorState1Spec>;
        #[doc = "Field `pwm_abnor_state1` reader - Counter config abnormal state, each bit per PWM"]
        pub type PwmAbnorState1R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Counter config abnormal state, each bit per PWM"]
            #[inline(always)]
            pub fn pwm_abnor_state1(&self) -> PwmAbnorState1R {
                PwmAbnorState1R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM abnormal state register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmAbnorState1Spec;
        impl crate::RegisterSpec for PwmAbnorState1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_abnor_state1::R`](R) reader structure"]
        impl crate::Readable for PwmAbnorState1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state1::W`](W) writer structure"]
        impl crate::Writable for PwmAbnorState1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_ABNOR_STATE1 to value 0"]
        impl crate::Resettable for PwmAbnorState1Spec {}
    }
    #[doc = "PWM_ABNOR_STATE_CLR0 (rw) register accessor: PWM abnormal state clear 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state_clr0`] module"]
    #[doc(alias = "PWM_ABNOR_STATE_CLR0")]
    pub type PwmAbnorStateClr0 = crate::Reg<pwm_abnor_state_clr0::PwmAbnorStateClr0Spec>;
    #[doc = "PWM abnormal state clear 0"]
    pub mod pwm_abnor_state_clr0 {
        #[doc = "Register `PWM_ABNOR_STATE_CLR0` reader"]
        pub type R = crate::R<PwmAbnorStateClr0Spec>;
        #[doc = "Register `PWM_ABNOR_STATE_CLR0` writer"]
        pub type W = crate::W<PwmAbnorStateClr0Spec>;
        #[doc = "Field `pwm_abnor_state_clr0` writer - Clear abnormal state 0 (self-clearing)"]
        pub type PwmAbnorStateClr0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl W {
            #[doc = "Bits 0:15 - Clear abnormal state 0 (self-clearing)"]
            #[inline(always)]
            pub fn pwm_abnor_state_clr0(
                &mut self,
            ) -> PwmAbnorStateClr0W<'_, PwmAbnorStateClr0Spec> {
                PwmAbnorStateClr0W::new(self, 0)
            }
        }
        #[doc = "PWM abnormal state clear 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmAbnorStateClr0Spec;
        impl crate::RegisterSpec for PwmAbnorStateClr0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_abnor_state_clr0::R`](R) reader structure"]
        impl crate::Readable for PwmAbnorStateClr0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state_clr0::W`](W) writer structure"]
        impl crate::Writable for PwmAbnorStateClr0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_ABNOR_STATE_CLR0 to value 0"]
        impl crate::Resettable for PwmAbnorStateClr0Spec {}
    }
    #[doc = "PWM_ABNOR_STATE_CLR1 (rw) register accessor: PWM abnormal state clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_abnor_state_clr1`] module"]
    #[doc(alias = "PWM_ABNOR_STATE_CLR1")]
    pub type PwmAbnorStateClr1 = crate::Reg<pwm_abnor_state_clr1::PwmAbnorStateClr1Spec>;
    #[doc = "PWM abnormal state clear 1"]
    pub mod pwm_abnor_state_clr1 {
        #[doc = "Register `PWM_ABNOR_STATE_CLR1` reader"]
        pub type R = crate::R<PwmAbnorStateClr1Spec>;
        #[doc = "Register `PWM_ABNOR_STATE_CLR1` writer"]
        pub type W = crate::W<PwmAbnorStateClr1Spec>;
        #[doc = "Field `pwm_abnor_state_clr1` writer - Clear abnormal state 1 (self-clearing)"]
        pub type PwmAbnorStateClr1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl W {
            #[doc = "Bits 0:15 - Clear abnormal state 1 (self-clearing)"]
            #[inline(always)]
            pub fn pwm_abnor_state_clr1(
                &mut self,
            ) -> PwmAbnorStateClr1W<'_, PwmAbnorStateClr1Spec> {
                PwmAbnorStateClr1W::new(self, 0)
            }
        }
        #[doc = "PWM abnormal state clear 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_abnor_state_clr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_abnor_state_clr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmAbnorStateClr1Spec;
        impl crate::RegisterSpec for PwmAbnorStateClr1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_abnor_state_clr1::R`](R) reader structure"]
        impl crate::Readable for PwmAbnorStateClr1Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_abnor_state_clr1::W`](W) writer structure"]
        impl crate::Writable for PwmAbnorStateClr1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_ABNOR_STATE_CLR1 to value 0"]
        impl crate::Resettable for PwmAbnorStateClr1Spec {}
    }
    #[doc = "PWM_INT_MASK (rw) register accessor: PWM interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_int_mask`] module"]
    #[doc(alias = "PWM_INT_MASK")]
    pub type PwmIntMask = crate::Reg<pwm_int_mask::PwmIntMaskSpec>;
    #[doc = "PWM interrupt mask"]
    pub mod pwm_int_mask {
        #[doc = "Register `PWM_INT_MASK` reader"]
        pub type R = crate::R<PwmIntMaskSpec>;
        #[doc = "Register `PWM_INT_MASK` writer"]
        pub type W = crate::W<PwmIntMaskSpec>;
        #[doc = "Field `pwm_int_mask` reader - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
        pub type PwmIntMaskR = crate::FieldReader;
        #[doc = "Field `pwm_int_mask` writer - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
        pub type PwmIntMaskW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bits 0:1 - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
            #[inline(always)]
            pub fn pwm_int_mask(&self) -> PwmIntMaskR {
                PwmIntMaskR::new((self.bits & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - Interrupt mask: bit\\[0\\]=abnormal; bit\\[1\\]=stepping cycle end"]
            #[inline(always)]
            pub fn pwm_int_mask(&mut self) -> PwmIntMaskW<'_, PwmIntMaskSpec> {
                PwmIntMaskW::new(self, 0)
            }
        }
        #[doc = "PWM interrupt mask\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmIntMaskSpec;
        impl crate::RegisterSpec for PwmIntMaskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_int_mask::R`](R) reader structure"]
        impl crate::Readable for PwmIntMaskSpec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_int_mask::W`](W) writer structure"]
        impl crate::Writable for PwmIntMaskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_INT_MASK to value 0"]
        impl crate::Resettable for PwmIntMaskSpec {}
    }
    #[doc = "PWM_DMA_EN (rw) register accessor: PWM DMA enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_dma_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_dma_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_dma_en`] module"]
    #[doc(alias = "PWM_DMA_EN")]
    pub type PwmDmaEn = crate::Reg<pwm_dma_en::PwmDmaEnSpec>;
    #[doc = "PWM DMA enable"]
    pub mod pwm_dma_en {
        #[doc = "Register `PWM_DMA_EN` reader"]
        pub type R = crate::R<PwmDmaEnSpec>;
        #[doc = "Register `PWM_DMA_EN` writer"]
        pub type W = crate::W<PwmDmaEnSpec>;
        #[doc = "Field `pwm_dma_en` reader - DMA enable: 0=disabled; 1=enabled"]
        pub type PwmDmaEnR = crate::BitReader;
        #[doc = "Field `pwm_dma_en` writer - DMA enable: 0=disabled; 1=enabled"]
        pub type PwmDmaEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - DMA enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn pwm_dma_en(&self) -> PwmDmaEnR {
                PwmDmaEnR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - DMA enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn pwm_dma_en(&mut self) -> PwmDmaEnW<'_, PwmDmaEnSpec> {
                PwmDmaEnW::new(self, 0)
            }
        }
        #[doc = "PWM DMA enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_dma_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_dma_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDmaEnSpec;
        impl crate::RegisterSpec for PwmDmaEnSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_dma_en::R`](R) reader structure"]
        impl crate::Readable for PwmDmaEnSpec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_dma_en::W`](W) writer structure"]
        impl crate::Writable for PwmDmaEnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DMA_EN to value 0"]
        impl crate::Resettable for PwmDmaEnSpec {}
    }
    #[doc = "PWM_CFG_INT_CLR0 (rw) register accessor: PWM stepping cycle end interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_cfg_int_clr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_cfg_int_clr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_cfg_int_clr0`] module"]
    #[doc(alias = "PWM_CFG_INT_CLR0")]
    pub type PwmCfgIntClr0 = crate::Reg<pwm_cfg_int_clr0::PwmCfgIntClr0Spec>;
    #[doc = "PWM stepping cycle end interrupt clear"]
    pub mod pwm_cfg_int_clr0 {
        #[doc = "Register `PWM_CFG_INT_CLR0` reader"]
        pub type R = crate::R<PwmCfgIntClr0Spec>;
        #[doc = "Register `PWM_CFG_INT_CLR0` writer"]
        pub type W = crate::W<PwmCfgIntClr0Spec>;
        #[doc = "Field `pwm_cfg_int_clr0` writer - Stepping cycle end interrupt clear (self-clearing)"]
        pub type PwmCfgIntClr0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl W {
            #[doc = "Bits 0:15 - Stepping cycle end interrupt clear (self-clearing)"]
            #[inline(always)]
            pub fn pwm_cfg_int_clr0(&mut self) -> PwmCfgIntClr0W<'_, PwmCfgIntClr0Spec> {
                PwmCfgIntClr0W::new(self, 0)
            }
        }
        #[doc = "PWM stepping cycle end interrupt clear\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_cfg_int_clr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_cfg_int_clr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmCfgIntClr0Spec;
        impl crate::RegisterSpec for PwmCfgIntClr0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_cfg_int_clr0::R`](R) reader structure"]
        impl crate::Readable for PwmCfgIntClr0Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_cfg_int_clr0::W`](W) writer structure"]
        impl crate::Writable for PwmCfgIntClr0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_CFG_INT_CLR0 to value 0"]
        impl crate::Resettable for PwmCfgIntClr0Spec {}
    }
    #[doc = "PWM_EN2 (rw) register accessor: PWM2 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en2`] module"]
    #[doc(alias = "PWM_EN2")]
    pub type PwmEn2 = crate::Reg<pwm_en2::PwmEn2Spec>;
    #[doc = "PWM2 enable"]
    pub mod pwm_en2 {
        #[doc = "Register `PWM_EN2` reader"]
        pub type R = crate::R<PwmEn2Spec>;
        #[doc = "Register `PWM_EN2` writer"]
        pub type W = crate::W<PwmEn2Spec>;
        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmEn2 {
            #[doc = "0: PWM disabled, output low"]
            Off = 0,
            #[doc = "1: PWM enabled"]
            On = 1,
        }
        impl From<PwmEn2> for bool {
            #[inline(always)]
            fn from(variant: PwmEn2) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_en_2` reader - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn2R = crate::BitReader<PwmEn2>;
        impl PwmEn2R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmEn2 {
                match self.bits {
                    false => PwmEn2::Off,
                    true => PwmEn2::On,
                }
            }
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn is_off(&self) -> bool {
                *self == PwmEn2::Off
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn is_on(&self) -> bool {
                *self == PwmEn2::On
            }
        }
        #[doc = "Field `pwm_en_2` writer - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn2W<'a, REG> = crate::BitWriter<'a, REG, PwmEn2>;
        impl<'a, REG> PwmEn2W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn off(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn2::Off)
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn on(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn2::On)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_2(&self) -> PwmEn2R {
                PwmEn2R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_2(&mut self) -> PwmEn2W<'_, PwmEn2Spec> {
                PwmEn2W::new(self, 0)
            }
        }
        #[doc = "PWM2 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmEn2Spec;
        impl crate::RegisterSpec for PwmEn2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_en2::R`](R) reader structure"]
        impl crate::Readable for PwmEn2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_en2::W`](W) writer structure"]
        impl crate::Writable for PwmEn2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_EN2 to value 0"]
        impl crate::Resettable for PwmEn2Spec {}
    }
    #[doc = "PWM_PORTITY2 (rw) register accessor: PWM2 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity2`] module"]
    #[doc(alias = "PWM_PORTITY2")]
    pub type PwmPortity2 = crate::Reg<pwm_portity2::PwmPortity2Spec>;
    #[doc = "PWM2 polarity"]
    pub mod pwm_portity2 {
        #[doc = "Register `PWM_PORTITY2` reader"]
        pub type R = crate::R<PwmPortity2Spec>;
        #[doc = "Register `PWM_PORTITY2` writer"]
        pub type W = crate::W<PwmPortity2Spec>;
        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmPoarity2 {
            #[doc = "0: Normal polarity"]
            Normal = 0,
            #[doc = "1: Inverted polarity"]
            Inverted = 1,
        }
        impl From<PwmPoarity2> for bool {
            #[inline(always)]
            fn from(variant: PwmPoarity2) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_poarity_2` reader - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity2R = crate::BitReader<PwmPoarity2>;
        impl PwmPoarity2R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmPoarity2 {
                match self.bits {
                    false => PwmPoarity2::Normal,
                    true => PwmPoarity2::Inverted,
                }
            }
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn is_normal(&self) -> bool {
                *self == PwmPoarity2::Normal
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn is_inverted(&self) -> bool {
                *self == PwmPoarity2::Inverted
            }
        }
        #[doc = "Field `pwm_poarity_2` writer - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity2W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity2>;
        impl<'a, REG> PwmPoarity2W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn normal(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity2::Normal)
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn inverted(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity2::Inverted)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_2(&self) -> PwmPoarity2R {
                PwmPoarity2R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_2(&mut self) -> PwmPoarity2W<'_, PwmPortity2Spec> {
                PwmPoarity2W::new(self, 0)
            }
        }
        #[doc = "PWM2 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPortity2Spec;
        impl crate::RegisterSpec for PwmPortity2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_portity2::R`](R) reader structure"]
        impl crate::Readable for PwmPortity2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_portity2::W`](W) writer structure"]
        impl crate::Writable for PwmPortity2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PORTITY2 to value 0"]
        impl crate::Resettable for PwmPortity2Spec {}
    }
    #[doc = "PWM_OEN_CFG2 (rw) register accessor: PWM2 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg2`] module"]
    #[doc(alias = "PWM_OEN_CFG2")]
    pub type PwmOenCfg2 = crate::Reg<pwm_oen_cfg2::PwmOenCfg2Spec>;
    #[doc = "PWM2 high-impedance config"]
    pub mod pwm_oen_cfg2 {
        #[doc = "Register `PWM_OEN_CFG2` reader"]
        pub type R = crate::R<PwmOenCfg2Spec>;
        #[doc = "Register `PWM_OEN_CFG2` writer"]
        pub type W = crate::W<PwmOenCfg2Spec>;
        #[doc = "Field `pwm_oen_cfg_2` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg2R = crate::BitReader;
        #[doc = "Field `pwm_oen_cfg_2` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg2W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_2(&self) -> PwmOenCfg2R {
                PwmOenCfg2R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_2(&mut self) -> PwmOenCfg2W<'_, PwmOenCfg2Spec> {
                PwmOenCfg2W::new(self, 0)
            }
        }
        #[doc = "PWM2 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOenCfg2Spec;
        impl crate::RegisterSpec for PwmOenCfg2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_oen_cfg2::R`](R) reader structure"]
        impl crate::Readable for PwmOenCfg2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg2::W`](W) writer structure"]
        impl crate::Writable for PwmOenCfg2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OEN_CFG2 to value 0"]
        impl crate::Resettable for PwmOenCfg2Spec {}
    }
    #[doc = "PWM_OFFSET_L2 (rw) register accessor: PWM2 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l2`] module"]
    #[doc(alias = "PWM_OFFSET_L2")]
    pub type PwmOffsetL2 = crate::Reg<pwm_offset_l2::PwmOffsetL2Spec>;
    #[doc = "PWM2 phase offset low 16 bits"]
    pub mod pwm_offset_l2 {
        #[doc = "Register `PWM_OFFSET_L2` reader"]
        pub type R = crate::R<PwmOffsetL2Spec>;
        #[doc = "Register `PWM_OFFSET_L2` writer"]
        pub type W = crate::W<PwmOffsetL2Spec>;
        #[doc = "Field `pwm_offset_l_2` reader - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL2R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_l_2` writer - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_2(&self) -> PwmOffsetL2R {
                PwmOffsetL2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_2(&mut self) -> PwmOffsetL2W<'_, PwmOffsetL2Spec> {
                PwmOffsetL2W::new(self, 0)
            }
        }
        #[doc = "PWM2 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetL2Spec;
        impl crate::RegisterSpec for PwmOffsetL2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_l2::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetL2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l2::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetL2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_L2 to value 0"]
        impl crate::Resettable for PwmOffsetL2Spec {}
    }
    #[doc = "PWM_OFFSET_H2 (rw) register accessor: PWM2 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h2`] module"]
    #[doc(alias = "PWM_OFFSET_H2")]
    pub type PwmOffsetH2 = crate::Reg<pwm_offset_h2::PwmOffsetH2Spec>;
    #[doc = "PWM2 phase offset high 16 bits"]
    pub mod pwm_offset_h2 {
        #[doc = "Register `PWM_OFFSET_H2` reader"]
        pub type R = crate::R<PwmOffsetH2Spec>;
        #[doc = "Register `PWM_OFFSET_H2` writer"]
        pub type W = crate::W<PwmOffsetH2Spec>;
        #[doc = "Field `pwm_offset_h_2` reader - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH2R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_h_2` writer - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_2(&self) -> PwmOffsetH2R {
                PwmOffsetH2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_2(&mut self) -> PwmOffsetH2W<'_, PwmOffsetH2Spec> {
                PwmOffsetH2W::new(self, 0)
            }
        }
        #[doc = "PWM2 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetH2Spec;
        impl crate::RegisterSpec for PwmOffsetH2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_h2::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetH2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h2::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetH2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_H2 to value 0"]
        impl crate::Resettable for PwmOffsetH2Spec {}
    }
    #[doc = "PWM_FREQ_L2 (rw) register accessor: PWM2 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l2`] module"]
    #[doc(alias = "PWM_FREQ_L2")]
    pub type PwmFreqL2 = crate::Reg<pwm_freq_l2::PwmFreqL2Spec>;
    #[doc = "PWM2 frequency low 16 bits"]
    pub mod pwm_freq_l2 {
        #[doc = "Register `PWM_FREQ_L2` reader"]
        pub type R = crate::R<PwmFreqL2Spec>;
        #[doc = "Register `PWM_FREQ_L2` writer"]
        pub type W = crate::W<PwmFreqL2Spec>;
        #[doc = "Field `pwm_freq_l_2` reader - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL2R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_l_2` writer - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_2(&self) -> PwmFreqL2R {
                PwmFreqL2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_2(&mut self) -> PwmFreqL2W<'_, PwmFreqL2Spec> {
                PwmFreqL2W::new(self, 0)
            }
        }
        #[doc = "PWM2 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqL2Spec;
        impl crate::RegisterSpec for PwmFreqL2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_l2::R`](R) reader structure"]
        impl crate::Readable for PwmFreqL2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l2::W`](W) writer structure"]
        impl crate::Writable for PwmFreqL2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_L2 to value 0"]
        impl crate::Resettable for PwmFreqL2Spec {}
    }
    #[doc = "PWM_FREQ_H2 (rw) register accessor: PWM2 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h2`] module"]
    #[doc(alias = "PWM_FREQ_H2")]
    pub type PwmFreqH2 = crate::Reg<pwm_freq_h2::PwmFreqH2Spec>;
    #[doc = "PWM2 frequency high 16 bits"]
    pub mod pwm_freq_h2 {
        #[doc = "Register `PWM_FREQ_H2` reader"]
        pub type R = crate::R<PwmFreqH2Spec>;
        #[doc = "Register `PWM_FREQ_H2` writer"]
        pub type W = crate::W<PwmFreqH2Spec>;
        #[doc = "Field `pwm_freq_h_2` reader - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH2R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_h_2` writer - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_2(&self) -> PwmFreqH2R {
                PwmFreqH2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_2(&mut self) -> PwmFreqH2W<'_, PwmFreqH2Spec> {
                PwmFreqH2W::new(self, 0)
            }
        }
        #[doc = "PWM2 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqH2Spec;
        impl crate::RegisterSpec for PwmFreqH2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_h2::R`](R) reader structure"]
        impl crate::Readable for PwmFreqH2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h2::W`](W) writer structure"]
        impl crate::Writable for PwmFreqH2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_H2 to value 0"]
        impl crate::Resettable for PwmFreqH2Spec {}
    }
    #[doc = "PWM_DUTY_L2 (rw) register accessor: PWM2 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l2`] module"]
    #[doc(alias = "PWM_DUTY_L2")]
    pub type PwmDutyL2 = crate::Reg<pwm_duty_l2::PwmDutyL2Spec>;
    #[doc = "PWM2 duty cycle low 16 bits"]
    pub mod pwm_duty_l2 {
        #[doc = "Register `PWM_DUTY_L2` reader"]
        pub type R = crate::R<PwmDutyL2Spec>;
        #[doc = "Register `PWM_DUTY_L2` writer"]
        pub type W = crate::W<PwmDutyL2Spec>;
        #[doc = "Field `pwm_duty_l_2` reader - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL2R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_l_2` writer - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_2(&self) -> PwmDutyL2R {
                PwmDutyL2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_2(&mut self) -> PwmDutyL2W<'_, PwmDutyL2Spec> {
                PwmDutyL2W::new(self, 0)
            }
        }
        #[doc = "PWM2 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyL2Spec;
        impl crate::RegisterSpec for PwmDutyL2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_l2::R`](R) reader structure"]
        impl crate::Readable for PwmDutyL2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l2::W`](W) writer structure"]
        impl crate::Writable for PwmDutyL2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_L2 to value 0"]
        impl crate::Resettable for PwmDutyL2Spec {}
    }
    #[doc = "PWM_DUTY_H2 (rw) register accessor: PWM2 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h2`] module"]
    #[doc(alias = "PWM_DUTY_H2")]
    pub type PwmDutyH2 = crate::Reg<pwm_duty_h2::PwmDutyH2Spec>;
    #[doc = "PWM2 duty cycle high 16 bits"]
    pub mod pwm_duty_h2 {
        #[doc = "Register `PWM_DUTY_H2` reader"]
        pub type R = crate::R<PwmDutyH2Spec>;
        #[doc = "Register `PWM_DUTY_H2` writer"]
        pub type W = crate::W<PwmDutyH2Spec>;
        #[doc = "Field `pwm_duty_h_2` reader - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH2R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_h_2` writer - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_2(&self) -> PwmDutyH2R {
                PwmDutyH2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_2(&mut self) -> PwmDutyH2W<'_, PwmDutyH2Spec> {
                PwmDutyH2W::new(self, 0)
            }
        }
        #[doc = "PWM2 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyH2Spec;
        impl crate::RegisterSpec for PwmDutyH2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_h2::R`](R) reader structure"]
        impl crate::Readable for PwmDutyH2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h2::W`](W) writer structure"]
        impl crate::Writable for PwmDutyH2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_H2 to value 0"]
        impl crate::Resettable for PwmDutyH2Spec {}
    }
    #[doc = "PWM_PERIODLOAD_FLAG2 (rw) register accessor: PWM2 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag2`] module"]
    #[doc(alias = "PWM_PERIODLOAD_FLAG2")]
    pub type PwmPeriodloadFlag2 = crate::Reg<pwm_periodload_flag2::PwmPeriodloadFlag2Spec>;
    #[doc = "PWM2 period load flag"]
    pub mod pwm_periodload_flag2 {
        #[doc = "Register `PWM_PERIODLOAD_FLAG2` reader"]
        pub type R = crate::R<PwmPeriodloadFlag2Spec>;
        #[doc = "Register `PWM_PERIODLOAD_FLAG2` writer"]
        pub type W = crate::W<PwmPeriodloadFlag2Spec>;
        #[doc = "Field `pwm_periodload_flag_2` reader - Period load complete flag"]
        pub type PwmPeriodloadFlag2R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Period load complete flag"]
            #[inline(always)]
            pub fn pwm_periodload_flag_2(&self) -> PwmPeriodloadFlag2R {
                PwmPeriodloadFlag2R::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "PWM2 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodloadFlag2Spec;
        impl crate::RegisterSpec for PwmPeriodloadFlag2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodload_flag2::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodloadFlag2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag2::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodloadFlag2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG2 to value 0"]
        impl crate::Resettable for PwmPeriodloadFlag2Spec {}
    }
    #[doc = "PWM_PERIOD_VAL2 (rw) register accessor: PWM2 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val2`] module"]
    #[doc(alias = "PWM_PERIOD_VAL2")]
    pub type PwmPeriodVal2 = crate::Reg<pwm_period_val2::PwmPeriodVal2Spec>;
    #[doc = "PWM2 pulse count value"]
    pub mod pwm_period_val2 {
        #[doc = "Register `PWM_PERIOD_VAL2` reader"]
        pub type R = crate::R<PwmPeriodVal2Spec>;
        #[doc = "Register `PWM_PERIOD_VAL2` writer"]
        pub type W = crate::W<PwmPeriodVal2Spec>;
        #[doc = "Field `pwm_period_val_2` reader - Pulse count for stepping mode"]
        pub type PwmPeriodVal2R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_period_val_2` writer - Pulse count for stepping mode"]
        pub type PwmPeriodVal2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_2(&self) -> PwmPeriodVal2R {
                PwmPeriodVal2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_2(&mut self) -> PwmPeriodVal2W<'_, PwmPeriodVal2Spec> {
                PwmPeriodVal2W::new(self, 0)
            }
        }
        #[doc = "PWM2 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodVal2Spec;
        impl crate::RegisterSpec for PwmPeriodVal2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_period_val2::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodVal2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_period_val2::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodVal2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIOD_VAL2 to value 0"]
        impl crate::Resettable for PwmPeriodVal2Spec {}
    }
    #[doc = "PWM_PERIODCNT2 (rw) register accessor: PWM2 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt2`] module"]
    #[doc(alias = "PWM_PERIODCNT2")]
    pub type PwmPeriodcnt2 = crate::Reg<pwm_periodcnt2::PwmPeriodcnt2Spec>;
    #[doc = "PWM2 pulse count current value"]
    pub mod pwm_periodcnt2 {
        #[doc = "Register `PWM_PERIODCNT2` reader"]
        pub type R = crate::R<PwmPeriodcnt2Spec>;
        #[doc = "Register `PWM_PERIODCNT2` writer"]
        pub type W = crate::W<PwmPeriodcnt2Spec>;
        #[doc = "Field `pwm_periodcnt_2` reader - Current pulse count"]
        pub type PwmPeriodcnt2R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Current pulse count"]
            #[inline(always)]
            pub fn pwm_periodcnt_2(&self) -> PwmPeriodcnt2R {
                PwmPeriodcnt2R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM2 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodcnt2Spec;
        impl crate::RegisterSpec for PwmPeriodcnt2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodcnt2::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodcnt2Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt2::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodcnt2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODCNT2 to value 0"]
        impl crate::Resettable for PwmPeriodcnt2Spec {}
    }
    #[doc = "PWM_EN3 (rw) register accessor: PWM3 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en3`] module"]
    #[doc(alias = "PWM_EN3")]
    pub type PwmEn3 = crate::Reg<pwm_en3::PwmEn3Spec>;
    #[doc = "PWM3 enable"]
    pub mod pwm_en3 {
        #[doc = "Register `PWM_EN3` reader"]
        pub type R = crate::R<PwmEn3Spec>;
        #[doc = "Register `PWM_EN3` writer"]
        pub type W = crate::W<PwmEn3Spec>;
        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmEn3 {
            #[doc = "0: PWM disabled, output low"]
            Off = 0,
            #[doc = "1: PWM enabled"]
            On = 1,
        }
        impl From<PwmEn3> for bool {
            #[inline(always)]
            fn from(variant: PwmEn3) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_en_3` reader - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn3R = crate::BitReader<PwmEn3>;
        impl PwmEn3R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmEn3 {
                match self.bits {
                    false => PwmEn3::Off,
                    true => PwmEn3::On,
                }
            }
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn is_off(&self) -> bool {
                *self == PwmEn3::Off
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn is_on(&self) -> bool {
                *self == PwmEn3::On
            }
        }
        #[doc = "Field `pwm_en_3` writer - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn3W<'a, REG> = crate::BitWriter<'a, REG, PwmEn3>;
        impl<'a, REG> PwmEn3W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn off(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn3::Off)
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn on(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn3::On)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_3(&self) -> PwmEn3R {
                PwmEn3R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_3(&mut self) -> PwmEn3W<'_, PwmEn3Spec> {
                PwmEn3W::new(self, 0)
            }
        }
        #[doc = "PWM3 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmEn3Spec;
        impl crate::RegisterSpec for PwmEn3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_en3::R`](R) reader structure"]
        impl crate::Readable for PwmEn3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_en3::W`](W) writer structure"]
        impl crate::Writable for PwmEn3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_EN3 to value 0"]
        impl crate::Resettable for PwmEn3Spec {}
    }
    #[doc = "PWM_PORTITY3 (rw) register accessor: PWM3 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity3`] module"]
    #[doc(alias = "PWM_PORTITY3")]
    pub type PwmPortity3 = crate::Reg<pwm_portity3::PwmPortity3Spec>;
    #[doc = "PWM3 polarity"]
    pub mod pwm_portity3 {
        #[doc = "Register `PWM_PORTITY3` reader"]
        pub type R = crate::R<PwmPortity3Spec>;
        #[doc = "Register `PWM_PORTITY3` writer"]
        pub type W = crate::W<PwmPortity3Spec>;
        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmPoarity3 {
            #[doc = "0: Normal polarity"]
            Normal = 0,
            #[doc = "1: Inverted polarity"]
            Inverted = 1,
        }
        impl From<PwmPoarity3> for bool {
            #[inline(always)]
            fn from(variant: PwmPoarity3) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_poarity_3` reader - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity3R = crate::BitReader<PwmPoarity3>;
        impl PwmPoarity3R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmPoarity3 {
                match self.bits {
                    false => PwmPoarity3::Normal,
                    true => PwmPoarity3::Inverted,
                }
            }
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn is_normal(&self) -> bool {
                *self == PwmPoarity3::Normal
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn is_inverted(&self) -> bool {
                *self == PwmPoarity3::Inverted
            }
        }
        #[doc = "Field `pwm_poarity_3` writer - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity3W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity3>;
        impl<'a, REG> PwmPoarity3W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn normal(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity3::Normal)
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn inverted(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity3::Inverted)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_3(&self) -> PwmPoarity3R {
                PwmPoarity3R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_3(&mut self) -> PwmPoarity3W<'_, PwmPortity3Spec> {
                PwmPoarity3W::new(self, 0)
            }
        }
        #[doc = "PWM3 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPortity3Spec;
        impl crate::RegisterSpec for PwmPortity3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_portity3::R`](R) reader structure"]
        impl crate::Readable for PwmPortity3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_portity3::W`](W) writer structure"]
        impl crate::Writable for PwmPortity3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PORTITY3 to value 0"]
        impl crate::Resettable for PwmPortity3Spec {}
    }
    #[doc = "PWM_OEN_CFG3 (rw) register accessor: PWM3 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg3`] module"]
    #[doc(alias = "PWM_OEN_CFG3")]
    pub type PwmOenCfg3 = crate::Reg<pwm_oen_cfg3::PwmOenCfg3Spec>;
    #[doc = "PWM3 high-impedance config"]
    pub mod pwm_oen_cfg3 {
        #[doc = "Register `PWM_OEN_CFG3` reader"]
        pub type R = crate::R<PwmOenCfg3Spec>;
        #[doc = "Register `PWM_OEN_CFG3` writer"]
        pub type W = crate::W<PwmOenCfg3Spec>;
        #[doc = "Field `pwm_oen_cfg_3` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg3R = crate::BitReader;
        #[doc = "Field `pwm_oen_cfg_3` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg3W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_3(&self) -> PwmOenCfg3R {
                PwmOenCfg3R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_3(&mut self) -> PwmOenCfg3W<'_, PwmOenCfg3Spec> {
                PwmOenCfg3W::new(self, 0)
            }
        }
        #[doc = "PWM3 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOenCfg3Spec;
        impl crate::RegisterSpec for PwmOenCfg3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_oen_cfg3::R`](R) reader structure"]
        impl crate::Readable for PwmOenCfg3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg3::W`](W) writer structure"]
        impl crate::Writable for PwmOenCfg3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OEN_CFG3 to value 0"]
        impl crate::Resettable for PwmOenCfg3Spec {}
    }
    #[doc = "PWM_OFFSET_L3 (rw) register accessor: PWM3 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l3`] module"]
    #[doc(alias = "PWM_OFFSET_L3")]
    pub type PwmOffsetL3 = crate::Reg<pwm_offset_l3::PwmOffsetL3Spec>;
    #[doc = "PWM3 phase offset low 16 bits"]
    pub mod pwm_offset_l3 {
        #[doc = "Register `PWM_OFFSET_L3` reader"]
        pub type R = crate::R<PwmOffsetL3Spec>;
        #[doc = "Register `PWM_OFFSET_L3` writer"]
        pub type W = crate::W<PwmOffsetL3Spec>;
        #[doc = "Field `pwm_offset_l_3` reader - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL3R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_l_3` writer - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_3(&self) -> PwmOffsetL3R {
                PwmOffsetL3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_3(&mut self) -> PwmOffsetL3W<'_, PwmOffsetL3Spec> {
                PwmOffsetL3W::new(self, 0)
            }
        }
        #[doc = "PWM3 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetL3Spec;
        impl crate::RegisterSpec for PwmOffsetL3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_l3::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetL3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l3::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetL3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_L3 to value 0"]
        impl crate::Resettable for PwmOffsetL3Spec {}
    }
    #[doc = "PWM_OFFSET_H3 (rw) register accessor: PWM3 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h3`] module"]
    #[doc(alias = "PWM_OFFSET_H3")]
    pub type PwmOffsetH3 = crate::Reg<pwm_offset_h3::PwmOffsetH3Spec>;
    #[doc = "PWM3 phase offset high 16 bits"]
    pub mod pwm_offset_h3 {
        #[doc = "Register `PWM_OFFSET_H3` reader"]
        pub type R = crate::R<PwmOffsetH3Spec>;
        #[doc = "Register `PWM_OFFSET_H3` writer"]
        pub type W = crate::W<PwmOffsetH3Spec>;
        #[doc = "Field `pwm_offset_h_3` reader - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH3R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_h_3` writer - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_3(&self) -> PwmOffsetH3R {
                PwmOffsetH3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_3(&mut self) -> PwmOffsetH3W<'_, PwmOffsetH3Spec> {
                PwmOffsetH3W::new(self, 0)
            }
        }
        #[doc = "PWM3 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetH3Spec;
        impl crate::RegisterSpec for PwmOffsetH3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_h3::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetH3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h3::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetH3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_H3 to value 0"]
        impl crate::Resettable for PwmOffsetH3Spec {}
    }
    #[doc = "PWM_FREQ_L3 (rw) register accessor: PWM3 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l3`] module"]
    #[doc(alias = "PWM_FREQ_L3")]
    pub type PwmFreqL3 = crate::Reg<pwm_freq_l3::PwmFreqL3Spec>;
    #[doc = "PWM3 frequency low 16 bits"]
    pub mod pwm_freq_l3 {
        #[doc = "Register `PWM_FREQ_L3` reader"]
        pub type R = crate::R<PwmFreqL3Spec>;
        #[doc = "Register `PWM_FREQ_L3` writer"]
        pub type W = crate::W<PwmFreqL3Spec>;
        #[doc = "Field `pwm_freq_l_3` reader - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL3R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_l_3` writer - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_3(&self) -> PwmFreqL3R {
                PwmFreqL3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_3(&mut self) -> PwmFreqL3W<'_, PwmFreqL3Spec> {
                PwmFreqL3W::new(self, 0)
            }
        }
        #[doc = "PWM3 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqL3Spec;
        impl crate::RegisterSpec for PwmFreqL3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_l3::R`](R) reader structure"]
        impl crate::Readable for PwmFreqL3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l3::W`](W) writer structure"]
        impl crate::Writable for PwmFreqL3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_L3 to value 0"]
        impl crate::Resettable for PwmFreqL3Spec {}
    }
    #[doc = "PWM_FREQ_H3 (rw) register accessor: PWM3 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h3`] module"]
    #[doc(alias = "PWM_FREQ_H3")]
    pub type PwmFreqH3 = crate::Reg<pwm_freq_h3::PwmFreqH3Spec>;
    #[doc = "PWM3 frequency high 16 bits"]
    pub mod pwm_freq_h3 {
        #[doc = "Register `PWM_FREQ_H3` reader"]
        pub type R = crate::R<PwmFreqH3Spec>;
        #[doc = "Register `PWM_FREQ_H3` writer"]
        pub type W = crate::W<PwmFreqH3Spec>;
        #[doc = "Field `pwm_freq_h_3` reader - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH3R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_h_3` writer - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_3(&self) -> PwmFreqH3R {
                PwmFreqH3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_3(&mut self) -> PwmFreqH3W<'_, PwmFreqH3Spec> {
                PwmFreqH3W::new(self, 0)
            }
        }
        #[doc = "PWM3 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqH3Spec;
        impl crate::RegisterSpec for PwmFreqH3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_h3::R`](R) reader structure"]
        impl crate::Readable for PwmFreqH3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h3::W`](W) writer structure"]
        impl crate::Writable for PwmFreqH3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_H3 to value 0"]
        impl crate::Resettable for PwmFreqH3Spec {}
    }
    #[doc = "PWM_DUTY_L3 (rw) register accessor: PWM3 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l3`] module"]
    #[doc(alias = "PWM_DUTY_L3")]
    pub type PwmDutyL3 = crate::Reg<pwm_duty_l3::PwmDutyL3Spec>;
    #[doc = "PWM3 duty cycle low 16 bits"]
    pub mod pwm_duty_l3 {
        #[doc = "Register `PWM_DUTY_L3` reader"]
        pub type R = crate::R<PwmDutyL3Spec>;
        #[doc = "Register `PWM_DUTY_L3` writer"]
        pub type W = crate::W<PwmDutyL3Spec>;
        #[doc = "Field `pwm_duty_l_3` reader - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL3R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_l_3` writer - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_3(&self) -> PwmDutyL3R {
                PwmDutyL3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_3(&mut self) -> PwmDutyL3W<'_, PwmDutyL3Spec> {
                PwmDutyL3W::new(self, 0)
            }
        }
        #[doc = "PWM3 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyL3Spec;
        impl crate::RegisterSpec for PwmDutyL3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_l3::R`](R) reader structure"]
        impl crate::Readable for PwmDutyL3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l3::W`](W) writer structure"]
        impl crate::Writable for PwmDutyL3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_L3 to value 0"]
        impl crate::Resettable for PwmDutyL3Spec {}
    }
    #[doc = "PWM_DUTY_H3 (rw) register accessor: PWM3 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h3`] module"]
    #[doc(alias = "PWM_DUTY_H3")]
    pub type PwmDutyH3 = crate::Reg<pwm_duty_h3::PwmDutyH3Spec>;
    #[doc = "PWM3 duty cycle high 16 bits"]
    pub mod pwm_duty_h3 {
        #[doc = "Register `PWM_DUTY_H3` reader"]
        pub type R = crate::R<PwmDutyH3Spec>;
        #[doc = "Register `PWM_DUTY_H3` writer"]
        pub type W = crate::W<PwmDutyH3Spec>;
        #[doc = "Field `pwm_duty_h_3` reader - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH3R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_h_3` writer - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_3(&self) -> PwmDutyH3R {
                PwmDutyH3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_3(&mut self) -> PwmDutyH3W<'_, PwmDutyH3Spec> {
                PwmDutyH3W::new(self, 0)
            }
        }
        #[doc = "PWM3 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyH3Spec;
        impl crate::RegisterSpec for PwmDutyH3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_h3::R`](R) reader structure"]
        impl crate::Readable for PwmDutyH3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h3::W`](W) writer structure"]
        impl crate::Writable for PwmDutyH3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_H3 to value 0"]
        impl crate::Resettable for PwmDutyH3Spec {}
    }
    #[doc = "PWM_PERIODLOAD_FLAG3 (rw) register accessor: PWM3 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag3`] module"]
    #[doc(alias = "PWM_PERIODLOAD_FLAG3")]
    pub type PwmPeriodloadFlag3 = crate::Reg<pwm_periodload_flag3::PwmPeriodloadFlag3Spec>;
    #[doc = "PWM3 period load flag"]
    pub mod pwm_periodload_flag3 {
        #[doc = "Register `PWM_PERIODLOAD_FLAG3` reader"]
        pub type R = crate::R<PwmPeriodloadFlag3Spec>;
        #[doc = "Register `PWM_PERIODLOAD_FLAG3` writer"]
        pub type W = crate::W<PwmPeriodloadFlag3Spec>;
        #[doc = "Field `pwm_periodload_flag_3` reader - Period load complete flag"]
        pub type PwmPeriodloadFlag3R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Period load complete flag"]
            #[inline(always)]
            pub fn pwm_periodload_flag_3(&self) -> PwmPeriodloadFlag3R {
                PwmPeriodloadFlag3R::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "PWM3 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodloadFlag3Spec;
        impl crate::RegisterSpec for PwmPeriodloadFlag3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodload_flag3::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodloadFlag3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag3::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodloadFlag3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG3 to value 0"]
        impl crate::Resettable for PwmPeriodloadFlag3Spec {}
    }
    #[doc = "PWM_PERIOD_VAL3 (rw) register accessor: PWM3 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val3`] module"]
    #[doc(alias = "PWM_PERIOD_VAL3")]
    pub type PwmPeriodVal3 = crate::Reg<pwm_period_val3::PwmPeriodVal3Spec>;
    #[doc = "PWM3 pulse count value"]
    pub mod pwm_period_val3 {
        #[doc = "Register `PWM_PERIOD_VAL3` reader"]
        pub type R = crate::R<PwmPeriodVal3Spec>;
        #[doc = "Register `PWM_PERIOD_VAL3` writer"]
        pub type W = crate::W<PwmPeriodVal3Spec>;
        #[doc = "Field `pwm_period_val_3` reader - Pulse count for stepping mode"]
        pub type PwmPeriodVal3R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_period_val_3` writer - Pulse count for stepping mode"]
        pub type PwmPeriodVal3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_3(&self) -> PwmPeriodVal3R {
                PwmPeriodVal3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_3(&mut self) -> PwmPeriodVal3W<'_, PwmPeriodVal3Spec> {
                PwmPeriodVal3W::new(self, 0)
            }
        }
        #[doc = "PWM3 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodVal3Spec;
        impl crate::RegisterSpec for PwmPeriodVal3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_period_val3::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodVal3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_period_val3::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodVal3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIOD_VAL3 to value 0"]
        impl crate::Resettable for PwmPeriodVal3Spec {}
    }
    #[doc = "PWM_PERIODCNT3 (rw) register accessor: PWM3 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt3`] module"]
    #[doc(alias = "PWM_PERIODCNT3")]
    pub type PwmPeriodcnt3 = crate::Reg<pwm_periodcnt3::PwmPeriodcnt3Spec>;
    #[doc = "PWM3 pulse count current value"]
    pub mod pwm_periodcnt3 {
        #[doc = "Register `PWM_PERIODCNT3` reader"]
        pub type R = crate::R<PwmPeriodcnt3Spec>;
        #[doc = "Register `PWM_PERIODCNT3` writer"]
        pub type W = crate::W<PwmPeriodcnt3Spec>;
        #[doc = "Field `pwm_periodcnt_3` reader - Current pulse count"]
        pub type PwmPeriodcnt3R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Current pulse count"]
            #[inline(always)]
            pub fn pwm_periodcnt_3(&self) -> PwmPeriodcnt3R {
                PwmPeriodcnt3R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM3 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodcnt3Spec;
        impl crate::RegisterSpec for PwmPeriodcnt3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodcnt3::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodcnt3Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt3::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodcnt3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODCNT3 to value 0"]
        impl crate::Resettable for PwmPeriodcnt3Spec {}
    }
    #[doc = "PWM_EN4 (rw) register accessor: PWM4 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en4`] module"]
    #[doc(alias = "PWM_EN4")]
    pub type PwmEn4 = crate::Reg<pwm_en4::PwmEn4Spec>;
    #[doc = "PWM4 enable"]
    pub mod pwm_en4 {
        #[doc = "Register `PWM_EN4` reader"]
        pub type R = crate::R<PwmEn4Spec>;
        #[doc = "Register `PWM_EN4` writer"]
        pub type W = crate::W<PwmEn4Spec>;
        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmEn4 {
            #[doc = "0: PWM disabled, output low"]
            Off = 0,
            #[doc = "1: PWM enabled"]
            On = 1,
        }
        impl From<PwmEn4> for bool {
            #[inline(always)]
            fn from(variant: PwmEn4) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_en_4` reader - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn4R = crate::BitReader<PwmEn4>;
        impl PwmEn4R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmEn4 {
                match self.bits {
                    false => PwmEn4::Off,
                    true => PwmEn4::On,
                }
            }
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn is_off(&self) -> bool {
                *self == PwmEn4::Off
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn is_on(&self) -> bool {
                *self == PwmEn4::On
            }
        }
        #[doc = "Field `pwm_en_4` writer - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn4W<'a, REG> = crate::BitWriter<'a, REG, PwmEn4>;
        impl<'a, REG> PwmEn4W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn off(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn4::Off)
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn on(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn4::On)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_4(&self) -> PwmEn4R {
                PwmEn4R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_4(&mut self) -> PwmEn4W<'_, PwmEn4Spec> {
                PwmEn4W::new(self, 0)
            }
        }
        #[doc = "PWM4 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmEn4Spec;
        impl crate::RegisterSpec for PwmEn4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_en4::R`](R) reader structure"]
        impl crate::Readable for PwmEn4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_en4::W`](W) writer structure"]
        impl crate::Writable for PwmEn4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_EN4 to value 0"]
        impl crate::Resettable for PwmEn4Spec {}
    }
    #[doc = "PWM_PORTITY4 (rw) register accessor: PWM4 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity4`] module"]
    #[doc(alias = "PWM_PORTITY4")]
    pub type PwmPortity4 = crate::Reg<pwm_portity4::PwmPortity4Spec>;
    #[doc = "PWM4 polarity"]
    pub mod pwm_portity4 {
        #[doc = "Register `PWM_PORTITY4` reader"]
        pub type R = crate::R<PwmPortity4Spec>;
        #[doc = "Register `PWM_PORTITY4` writer"]
        pub type W = crate::W<PwmPortity4Spec>;
        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmPoarity4 {
            #[doc = "0: Normal polarity"]
            Normal = 0,
            #[doc = "1: Inverted polarity"]
            Inverted = 1,
        }
        impl From<PwmPoarity4> for bool {
            #[inline(always)]
            fn from(variant: PwmPoarity4) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_poarity_4` reader - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity4R = crate::BitReader<PwmPoarity4>;
        impl PwmPoarity4R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmPoarity4 {
                match self.bits {
                    false => PwmPoarity4::Normal,
                    true => PwmPoarity4::Inverted,
                }
            }
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn is_normal(&self) -> bool {
                *self == PwmPoarity4::Normal
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn is_inverted(&self) -> bool {
                *self == PwmPoarity4::Inverted
            }
        }
        #[doc = "Field `pwm_poarity_4` writer - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity4W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity4>;
        impl<'a, REG> PwmPoarity4W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn normal(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity4::Normal)
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn inverted(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity4::Inverted)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_4(&self) -> PwmPoarity4R {
                PwmPoarity4R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_4(&mut self) -> PwmPoarity4W<'_, PwmPortity4Spec> {
                PwmPoarity4W::new(self, 0)
            }
        }
        #[doc = "PWM4 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPortity4Spec;
        impl crate::RegisterSpec for PwmPortity4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_portity4::R`](R) reader structure"]
        impl crate::Readable for PwmPortity4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_portity4::W`](W) writer structure"]
        impl crate::Writable for PwmPortity4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PORTITY4 to value 0"]
        impl crate::Resettable for PwmPortity4Spec {}
    }
    #[doc = "PWM_OEN_CFG4 (rw) register accessor: PWM4 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg4`] module"]
    #[doc(alias = "PWM_OEN_CFG4")]
    pub type PwmOenCfg4 = crate::Reg<pwm_oen_cfg4::PwmOenCfg4Spec>;
    #[doc = "PWM4 high-impedance config"]
    pub mod pwm_oen_cfg4 {
        #[doc = "Register `PWM_OEN_CFG4` reader"]
        pub type R = crate::R<PwmOenCfg4Spec>;
        #[doc = "Register `PWM_OEN_CFG4` writer"]
        pub type W = crate::W<PwmOenCfg4Spec>;
        #[doc = "Field `pwm_oen_cfg_4` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg4R = crate::BitReader;
        #[doc = "Field `pwm_oen_cfg_4` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg4W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_4(&self) -> PwmOenCfg4R {
                PwmOenCfg4R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_4(&mut self) -> PwmOenCfg4W<'_, PwmOenCfg4Spec> {
                PwmOenCfg4W::new(self, 0)
            }
        }
        #[doc = "PWM4 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOenCfg4Spec;
        impl crate::RegisterSpec for PwmOenCfg4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_oen_cfg4::R`](R) reader structure"]
        impl crate::Readable for PwmOenCfg4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg4::W`](W) writer structure"]
        impl crate::Writable for PwmOenCfg4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OEN_CFG4 to value 0"]
        impl crate::Resettable for PwmOenCfg4Spec {}
    }
    #[doc = "PWM_OFFSET_L4 (rw) register accessor: PWM4 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l4`] module"]
    #[doc(alias = "PWM_OFFSET_L4")]
    pub type PwmOffsetL4 = crate::Reg<pwm_offset_l4::PwmOffsetL4Spec>;
    #[doc = "PWM4 phase offset low 16 bits"]
    pub mod pwm_offset_l4 {
        #[doc = "Register `PWM_OFFSET_L4` reader"]
        pub type R = crate::R<PwmOffsetL4Spec>;
        #[doc = "Register `PWM_OFFSET_L4` writer"]
        pub type W = crate::W<PwmOffsetL4Spec>;
        #[doc = "Field `pwm_offset_l_4` reader - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL4R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_l_4` writer - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_4(&self) -> PwmOffsetL4R {
                PwmOffsetL4R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_4(&mut self) -> PwmOffsetL4W<'_, PwmOffsetL4Spec> {
                PwmOffsetL4W::new(self, 0)
            }
        }
        #[doc = "PWM4 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetL4Spec;
        impl crate::RegisterSpec for PwmOffsetL4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_l4::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetL4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l4::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetL4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_L4 to value 0"]
        impl crate::Resettable for PwmOffsetL4Spec {}
    }
    #[doc = "PWM_OFFSET_H4 (rw) register accessor: PWM4 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h4`] module"]
    #[doc(alias = "PWM_OFFSET_H4")]
    pub type PwmOffsetH4 = crate::Reg<pwm_offset_h4::PwmOffsetH4Spec>;
    #[doc = "PWM4 phase offset high 16 bits"]
    pub mod pwm_offset_h4 {
        #[doc = "Register `PWM_OFFSET_H4` reader"]
        pub type R = crate::R<PwmOffsetH4Spec>;
        #[doc = "Register `PWM_OFFSET_H4` writer"]
        pub type W = crate::W<PwmOffsetH4Spec>;
        #[doc = "Field `pwm_offset_h_4` reader - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH4R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_h_4` writer - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_4(&self) -> PwmOffsetH4R {
                PwmOffsetH4R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_4(&mut self) -> PwmOffsetH4W<'_, PwmOffsetH4Spec> {
                PwmOffsetH4W::new(self, 0)
            }
        }
        #[doc = "PWM4 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetH4Spec;
        impl crate::RegisterSpec for PwmOffsetH4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_h4::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetH4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h4::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetH4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_H4 to value 0"]
        impl crate::Resettable for PwmOffsetH4Spec {}
    }
    #[doc = "PWM_FREQ_L4 (rw) register accessor: PWM4 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l4`] module"]
    #[doc(alias = "PWM_FREQ_L4")]
    pub type PwmFreqL4 = crate::Reg<pwm_freq_l4::PwmFreqL4Spec>;
    #[doc = "PWM4 frequency low 16 bits"]
    pub mod pwm_freq_l4 {
        #[doc = "Register `PWM_FREQ_L4` reader"]
        pub type R = crate::R<PwmFreqL4Spec>;
        #[doc = "Register `PWM_FREQ_L4` writer"]
        pub type W = crate::W<PwmFreqL4Spec>;
        #[doc = "Field `pwm_freq_l_4` reader - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL4R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_l_4` writer - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_4(&self) -> PwmFreqL4R {
                PwmFreqL4R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_4(&mut self) -> PwmFreqL4W<'_, PwmFreqL4Spec> {
                PwmFreqL4W::new(self, 0)
            }
        }
        #[doc = "PWM4 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqL4Spec;
        impl crate::RegisterSpec for PwmFreqL4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_l4::R`](R) reader structure"]
        impl crate::Readable for PwmFreqL4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l4::W`](W) writer structure"]
        impl crate::Writable for PwmFreqL4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_L4 to value 0"]
        impl crate::Resettable for PwmFreqL4Spec {}
    }
    #[doc = "PWM_FREQ_H4 (rw) register accessor: PWM4 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h4`] module"]
    #[doc(alias = "PWM_FREQ_H4")]
    pub type PwmFreqH4 = crate::Reg<pwm_freq_h4::PwmFreqH4Spec>;
    #[doc = "PWM4 frequency high 16 bits"]
    pub mod pwm_freq_h4 {
        #[doc = "Register `PWM_FREQ_H4` reader"]
        pub type R = crate::R<PwmFreqH4Spec>;
        #[doc = "Register `PWM_FREQ_H4` writer"]
        pub type W = crate::W<PwmFreqH4Spec>;
        #[doc = "Field `pwm_freq_h_4` reader - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH4R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_h_4` writer - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_4(&self) -> PwmFreqH4R {
                PwmFreqH4R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_4(&mut self) -> PwmFreqH4W<'_, PwmFreqH4Spec> {
                PwmFreqH4W::new(self, 0)
            }
        }
        #[doc = "PWM4 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqH4Spec;
        impl crate::RegisterSpec for PwmFreqH4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_h4::R`](R) reader structure"]
        impl crate::Readable for PwmFreqH4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h4::W`](W) writer structure"]
        impl crate::Writable for PwmFreqH4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_H4 to value 0"]
        impl crate::Resettable for PwmFreqH4Spec {}
    }
    #[doc = "PWM_DUTY_L4 (rw) register accessor: PWM4 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l4`] module"]
    #[doc(alias = "PWM_DUTY_L4")]
    pub type PwmDutyL4 = crate::Reg<pwm_duty_l4::PwmDutyL4Spec>;
    #[doc = "PWM4 duty cycle low 16 bits"]
    pub mod pwm_duty_l4 {
        #[doc = "Register `PWM_DUTY_L4` reader"]
        pub type R = crate::R<PwmDutyL4Spec>;
        #[doc = "Register `PWM_DUTY_L4` writer"]
        pub type W = crate::W<PwmDutyL4Spec>;
        #[doc = "Field `pwm_duty_l_4` reader - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL4R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_l_4` writer - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_4(&self) -> PwmDutyL4R {
                PwmDutyL4R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_4(&mut self) -> PwmDutyL4W<'_, PwmDutyL4Spec> {
                PwmDutyL4W::new(self, 0)
            }
        }
        #[doc = "PWM4 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyL4Spec;
        impl crate::RegisterSpec for PwmDutyL4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_l4::R`](R) reader structure"]
        impl crate::Readable for PwmDutyL4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l4::W`](W) writer structure"]
        impl crate::Writable for PwmDutyL4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_L4 to value 0"]
        impl crate::Resettable for PwmDutyL4Spec {}
    }
    #[doc = "PWM_DUTY_H4 (rw) register accessor: PWM4 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h4`] module"]
    #[doc(alias = "PWM_DUTY_H4")]
    pub type PwmDutyH4 = crate::Reg<pwm_duty_h4::PwmDutyH4Spec>;
    #[doc = "PWM4 duty cycle high 16 bits"]
    pub mod pwm_duty_h4 {
        #[doc = "Register `PWM_DUTY_H4` reader"]
        pub type R = crate::R<PwmDutyH4Spec>;
        #[doc = "Register `PWM_DUTY_H4` writer"]
        pub type W = crate::W<PwmDutyH4Spec>;
        #[doc = "Field `pwm_duty_h_4` reader - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH4R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_h_4` writer - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_4(&self) -> PwmDutyH4R {
                PwmDutyH4R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_4(&mut self) -> PwmDutyH4W<'_, PwmDutyH4Spec> {
                PwmDutyH4W::new(self, 0)
            }
        }
        #[doc = "PWM4 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyH4Spec;
        impl crate::RegisterSpec for PwmDutyH4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_h4::R`](R) reader structure"]
        impl crate::Readable for PwmDutyH4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h4::W`](W) writer structure"]
        impl crate::Writable for PwmDutyH4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_H4 to value 0"]
        impl crate::Resettable for PwmDutyH4Spec {}
    }
    #[doc = "PWM_PERIODLOAD_FLAG4 (rw) register accessor: PWM4 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag4`] module"]
    #[doc(alias = "PWM_PERIODLOAD_FLAG4")]
    pub type PwmPeriodloadFlag4 = crate::Reg<pwm_periodload_flag4::PwmPeriodloadFlag4Spec>;
    #[doc = "PWM4 period load flag"]
    pub mod pwm_periodload_flag4 {
        #[doc = "Register `PWM_PERIODLOAD_FLAG4` reader"]
        pub type R = crate::R<PwmPeriodloadFlag4Spec>;
        #[doc = "Register `PWM_PERIODLOAD_FLAG4` writer"]
        pub type W = crate::W<PwmPeriodloadFlag4Spec>;
        #[doc = "Field `pwm_periodload_flag_4` reader - Period load complete flag"]
        pub type PwmPeriodloadFlag4R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Period load complete flag"]
            #[inline(always)]
            pub fn pwm_periodload_flag_4(&self) -> PwmPeriodloadFlag4R {
                PwmPeriodloadFlag4R::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "PWM4 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodloadFlag4Spec;
        impl crate::RegisterSpec for PwmPeriodloadFlag4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodload_flag4::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodloadFlag4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag4::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodloadFlag4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG4 to value 0"]
        impl crate::Resettable for PwmPeriodloadFlag4Spec {}
    }
    #[doc = "PWM_PERIOD_VAL4 (rw) register accessor: PWM4 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val4`] module"]
    #[doc(alias = "PWM_PERIOD_VAL4")]
    pub type PwmPeriodVal4 = crate::Reg<pwm_period_val4::PwmPeriodVal4Spec>;
    #[doc = "PWM4 pulse count value"]
    pub mod pwm_period_val4 {
        #[doc = "Register `PWM_PERIOD_VAL4` reader"]
        pub type R = crate::R<PwmPeriodVal4Spec>;
        #[doc = "Register `PWM_PERIOD_VAL4` writer"]
        pub type W = crate::W<PwmPeriodVal4Spec>;
        #[doc = "Field `pwm_period_val_4` reader - Pulse count for stepping mode"]
        pub type PwmPeriodVal4R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_period_val_4` writer - Pulse count for stepping mode"]
        pub type PwmPeriodVal4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_4(&self) -> PwmPeriodVal4R {
                PwmPeriodVal4R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_4(&mut self) -> PwmPeriodVal4W<'_, PwmPeriodVal4Spec> {
                PwmPeriodVal4W::new(self, 0)
            }
        }
        #[doc = "PWM4 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodVal4Spec;
        impl crate::RegisterSpec for PwmPeriodVal4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_period_val4::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodVal4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_period_val4::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodVal4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIOD_VAL4 to value 0"]
        impl crate::Resettable for PwmPeriodVal4Spec {}
    }
    #[doc = "PWM_PERIODCNT4 (rw) register accessor: PWM4 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt4`] module"]
    #[doc(alias = "PWM_PERIODCNT4")]
    pub type PwmPeriodcnt4 = crate::Reg<pwm_periodcnt4::PwmPeriodcnt4Spec>;
    #[doc = "PWM4 pulse count current value"]
    pub mod pwm_periodcnt4 {
        #[doc = "Register `PWM_PERIODCNT4` reader"]
        pub type R = crate::R<PwmPeriodcnt4Spec>;
        #[doc = "Register `PWM_PERIODCNT4` writer"]
        pub type W = crate::W<PwmPeriodcnt4Spec>;
        #[doc = "Field `pwm_periodcnt_4` reader - Current pulse count"]
        pub type PwmPeriodcnt4R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Current pulse count"]
            #[inline(always)]
            pub fn pwm_periodcnt_4(&self) -> PwmPeriodcnt4R {
                PwmPeriodcnt4R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM4 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodcnt4Spec;
        impl crate::RegisterSpec for PwmPeriodcnt4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodcnt4::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodcnt4Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt4::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodcnt4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODCNT4 to value 0"]
        impl crate::Resettable for PwmPeriodcnt4Spec {}
    }
    #[doc = "PWM_EN5 (rw) register accessor: PWM5 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en5`] module"]
    #[doc(alias = "PWM_EN5")]
    pub type PwmEn5 = crate::Reg<pwm_en5::PwmEn5Spec>;
    #[doc = "PWM5 enable"]
    pub mod pwm_en5 {
        #[doc = "Register `PWM_EN5` reader"]
        pub type R = crate::R<PwmEn5Spec>;
        #[doc = "Register `PWM_EN5` writer"]
        pub type W = crate::W<PwmEn5Spec>;
        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmEn5 {
            #[doc = "0: PWM disabled, output low"]
            Off = 0,
            #[doc = "1: PWM enabled"]
            On = 1,
        }
        impl From<PwmEn5> for bool {
            #[inline(always)]
            fn from(variant: PwmEn5) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_en_5` reader - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn5R = crate::BitReader<PwmEn5>;
        impl PwmEn5R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmEn5 {
                match self.bits {
                    false => PwmEn5::Off,
                    true => PwmEn5::On,
                }
            }
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn is_off(&self) -> bool {
                *self == PwmEn5::Off
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn is_on(&self) -> bool {
                *self == PwmEn5::On
            }
        }
        #[doc = "Field `pwm_en_5` writer - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn5W<'a, REG> = crate::BitWriter<'a, REG, PwmEn5>;
        impl<'a, REG> PwmEn5W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn off(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn5::Off)
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn on(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn5::On)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_5(&self) -> PwmEn5R {
                PwmEn5R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_5(&mut self) -> PwmEn5W<'_, PwmEn5Spec> {
                PwmEn5W::new(self, 0)
            }
        }
        #[doc = "PWM5 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmEn5Spec;
        impl crate::RegisterSpec for PwmEn5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_en5::R`](R) reader structure"]
        impl crate::Readable for PwmEn5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_en5::W`](W) writer structure"]
        impl crate::Writable for PwmEn5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_EN5 to value 0"]
        impl crate::Resettable for PwmEn5Spec {}
    }
    #[doc = "PWM_PORTITY5 (rw) register accessor: PWM5 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity5`] module"]
    #[doc(alias = "PWM_PORTITY5")]
    pub type PwmPortity5 = crate::Reg<pwm_portity5::PwmPortity5Spec>;
    #[doc = "PWM5 polarity"]
    pub mod pwm_portity5 {
        #[doc = "Register `PWM_PORTITY5` reader"]
        pub type R = crate::R<PwmPortity5Spec>;
        #[doc = "Register `PWM_PORTITY5` writer"]
        pub type W = crate::W<PwmPortity5Spec>;
        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmPoarity5 {
            #[doc = "0: Normal polarity"]
            Normal = 0,
            #[doc = "1: Inverted polarity"]
            Inverted = 1,
        }
        impl From<PwmPoarity5> for bool {
            #[inline(always)]
            fn from(variant: PwmPoarity5) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_poarity_5` reader - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity5R = crate::BitReader<PwmPoarity5>;
        impl PwmPoarity5R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmPoarity5 {
                match self.bits {
                    false => PwmPoarity5::Normal,
                    true => PwmPoarity5::Inverted,
                }
            }
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn is_normal(&self) -> bool {
                *self == PwmPoarity5::Normal
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn is_inverted(&self) -> bool {
                *self == PwmPoarity5::Inverted
            }
        }
        #[doc = "Field `pwm_poarity_5` writer - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity5W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity5>;
        impl<'a, REG> PwmPoarity5W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn normal(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity5::Normal)
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn inverted(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity5::Inverted)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_5(&self) -> PwmPoarity5R {
                PwmPoarity5R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_5(&mut self) -> PwmPoarity5W<'_, PwmPortity5Spec> {
                PwmPoarity5W::new(self, 0)
            }
        }
        #[doc = "PWM5 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPortity5Spec;
        impl crate::RegisterSpec for PwmPortity5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_portity5::R`](R) reader structure"]
        impl crate::Readable for PwmPortity5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_portity5::W`](W) writer structure"]
        impl crate::Writable for PwmPortity5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PORTITY5 to value 0"]
        impl crate::Resettable for PwmPortity5Spec {}
    }
    #[doc = "PWM_OEN_CFG5 (rw) register accessor: PWM5 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg5`] module"]
    #[doc(alias = "PWM_OEN_CFG5")]
    pub type PwmOenCfg5 = crate::Reg<pwm_oen_cfg5::PwmOenCfg5Spec>;
    #[doc = "PWM5 high-impedance config"]
    pub mod pwm_oen_cfg5 {
        #[doc = "Register `PWM_OEN_CFG5` reader"]
        pub type R = crate::R<PwmOenCfg5Spec>;
        #[doc = "Register `PWM_OEN_CFG5` writer"]
        pub type W = crate::W<PwmOenCfg5Spec>;
        #[doc = "Field `pwm_oen_cfg_5` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg5R = crate::BitReader;
        #[doc = "Field `pwm_oen_cfg_5` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg5W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_5(&self) -> PwmOenCfg5R {
                PwmOenCfg5R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_5(&mut self) -> PwmOenCfg5W<'_, PwmOenCfg5Spec> {
                PwmOenCfg5W::new(self, 0)
            }
        }
        #[doc = "PWM5 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOenCfg5Spec;
        impl crate::RegisterSpec for PwmOenCfg5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_oen_cfg5::R`](R) reader structure"]
        impl crate::Readable for PwmOenCfg5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg5::W`](W) writer structure"]
        impl crate::Writable for PwmOenCfg5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OEN_CFG5 to value 0"]
        impl crate::Resettable for PwmOenCfg5Spec {}
    }
    #[doc = "PWM_OFFSET_L5 (rw) register accessor: PWM5 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l5`] module"]
    #[doc(alias = "PWM_OFFSET_L5")]
    pub type PwmOffsetL5 = crate::Reg<pwm_offset_l5::PwmOffsetL5Spec>;
    #[doc = "PWM5 phase offset low 16 bits"]
    pub mod pwm_offset_l5 {
        #[doc = "Register `PWM_OFFSET_L5` reader"]
        pub type R = crate::R<PwmOffsetL5Spec>;
        #[doc = "Register `PWM_OFFSET_L5` writer"]
        pub type W = crate::W<PwmOffsetL5Spec>;
        #[doc = "Field `pwm_offset_l_5` reader - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL5R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_l_5` writer - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_5(&self) -> PwmOffsetL5R {
                PwmOffsetL5R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_5(&mut self) -> PwmOffsetL5W<'_, PwmOffsetL5Spec> {
                PwmOffsetL5W::new(self, 0)
            }
        }
        #[doc = "PWM5 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetL5Spec;
        impl crate::RegisterSpec for PwmOffsetL5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_l5::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetL5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l5::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetL5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_L5 to value 0"]
        impl crate::Resettable for PwmOffsetL5Spec {}
    }
    #[doc = "PWM_OFFSET_H5 (rw) register accessor: PWM5 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h5`] module"]
    #[doc(alias = "PWM_OFFSET_H5")]
    pub type PwmOffsetH5 = crate::Reg<pwm_offset_h5::PwmOffsetH5Spec>;
    #[doc = "PWM5 phase offset high 16 bits"]
    pub mod pwm_offset_h5 {
        #[doc = "Register `PWM_OFFSET_H5` reader"]
        pub type R = crate::R<PwmOffsetH5Spec>;
        #[doc = "Register `PWM_OFFSET_H5` writer"]
        pub type W = crate::W<PwmOffsetH5Spec>;
        #[doc = "Field `pwm_offset_h_5` reader - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH5R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_h_5` writer - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_5(&self) -> PwmOffsetH5R {
                PwmOffsetH5R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_5(&mut self) -> PwmOffsetH5W<'_, PwmOffsetH5Spec> {
                PwmOffsetH5W::new(self, 0)
            }
        }
        #[doc = "PWM5 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetH5Spec;
        impl crate::RegisterSpec for PwmOffsetH5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_h5::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetH5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h5::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetH5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_H5 to value 0"]
        impl crate::Resettable for PwmOffsetH5Spec {}
    }
    #[doc = "PWM_FREQ_L5 (rw) register accessor: PWM5 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l5`] module"]
    #[doc(alias = "PWM_FREQ_L5")]
    pub type PwmFreqL5 = crate::Reg<pwm_freq_l5::PwmFreqL5Spec>;
    #[doc = "PWM5 frequency low 16 bits"]
    pub mod pwm_freq_l5 {
        #[doc = "Register `PWM_FREQ_L5` reader"]
        pub type R = crate::R<PwmFreqL5Spec>;
        #[doc = "Register `PWM_FREQ_L5` writer"]
        pub type W = crate::W<PwmFreqL5Spec>;
        #[doc = "Field `pwm_freq_l_5` reader - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL5R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_l_5` writer - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_5(&self) -> PwmFreqL5R {
                PwmFreqL5R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_5(&mut self) -> PwmFreqL5W<'_, PwmFreqL5Spec> {
                PwmFreqL5W::new(self, 0)
            }
        }
        #[doc = "PWM5 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqL5Spec;
        impl crate::RegisterSpec for PwmFreqL5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_l5::R`](R) reader structure"]
        impl crate::Readable for PwmFreqL5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l5::W`](W) writer structure"]
        impl crate::Writable for PwmFreqL5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_L5 to value 0"]
        impl crate::Resettable for PwmFreqL5Spec {}
    }
    #[doc = "PWM_FREQ_H5 (rw) register accessor: PWM5 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h5`] module"]
    #[doc(alias = "PWM_FREQ_H5")]
    pub type PwmFreqH5 = crate::Reg<pwm_freq_h5::PwmFreqH5Spec>;
    #[doc = "PWM5 frequency high 16 bits"]
    pub mod pwm_freq_h5 {
        #[doc = "Register `PWM_FREQ_H5` reader"]
        pub type R = crate::R<PwmFreqH5Spec>;
        #[doc = "Register `PWM_FREQ_H5` writer"]
        pub type W = crate::W<PwmFreqH5Spec>;
        #[doc = "Field `pwm_freq_h_5` reader - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH5R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_h_5` writer - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_5(&self) -> PwmFreqH5R {
                PwmFreqH5R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_5(&mut self) -> PwmFreqH5W<'_, PwmFreqH5Spec> {
                PwmFreqH5W::new(self, 0)
            }
        }
        #[doc = "PWM5 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqH5Spec;
        impl crate::RegisterSpec for PwmFreqH5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_h5::R`](R) reader structure"]
        impl crate::Readable for PwmFreqH5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h5::W`](W) writer structure"]
        impl crate::Writable for PwmFreqH5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_H5 to value 0"]
        impl crate::Resettable for PwmFreqH5Spec {}
    }
    #[doc = "PWM_DUTY_L5 (rw) register accessor: PWM5 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l5`] module"]
    #[doc(alias = "PWM_DUTY_L5")]
    pub type PwmDutyL5 = crate::Reg<pwm_duty_l5::PwmDutyL5Spec>;
    #[doc = "PWM5 duty cycle low 16 bits"]
    pub mod pwm_duty_l5 {
        #[doc = "Register `PWM_DUTY_L5` reader"]
        pub type R = crate::R<PwmDutyL5Spec>;
        #[doc = "Register `PWM_DUTY_L5` writer"]
        pub type W = crate::W<PwmDutyL5Spec>;
        #[doc = "Field `pwm_duty_l_5` reader - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL5R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_l_5` writer - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_5(&self) -> PwmDutyL5R {
                PwmDutyL5R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_5(&mut self) -> PwmDutyL5W<'_, PwmDutyL5Spec> {
                PwmDutyL5W::new(self, 0)
            }
        }
        #[doc = "PWM5 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyL5Spec;
        impl crate::RegisterSpec for PwmDutyL5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_l5::R`](R) reader structure"]
        impl crate::Readable for PwmDutyL5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l5::W`](W) writer structure"]
        impl crate::Writable for PwmDutyL5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_L5 to value 0"]
        impl crate::Resettable for PwmDutyL5Spec {}
    }
    #[doc = "PWM_DUTY_H5 (rw) register accessor: PWM5 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h5`] module"]
    #[doc(alias = "PWM_DUTY_H5")]
    pub type PwmDutyH5 = crate::Reg<pwm_duty_h5::PwmDutyH5Spec>;
    #[doc = "PWM5 duty cycle high 16 bits"]
    pub mod pwm_duty_h5 {
        #[doc = "Register `PWM_DUTY_H5` reader"]
        pub type R = crate::R<PwmDutyH5Spec>;
        #[doc = "Register `PWM_DUTY_H5` writer"]
        pub type W = crate::W<PwmDutyH5Spec>;
        #[doc = "Field `pwm_duty_h_5` reader - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH5R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_h_5` writer - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_5(&self) -> PwmDutyH5R {
                PwmDutyH5R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_5(&mut self) -> PwmDutyH5W<'_, PwmDutyH5Spec> {
                PwmDutyH5W::new(self, 0)
            }
        }
        #[doc = "PWM5 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyH5Spec;
        impl crate::RegisterSpec for PwmDutyH5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_h5::R`](R) reader structure"]
        impl crate::Readable for PwmDutyH5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h5::W`](W) writer structure"]
        impl crate::Writable for PwmDutyH5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_H5 to value 0"]
        impl crate::Resettable for PwmDutyH5Spec {}
    }
    #[doc = "PWM_PERIODLOAD_FLAG5 (rw) register accessor: PWM5 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag5`] module"]
    #[doc(alias = "PWM_PERIODLOAD_FLAG5")]
    pub type PwmPeriodloadFlag5 = crate::Reg<pwm_periodload_flag5::PwmPeriodloadFlag5Spec>;
    #[doc = "PWM5 period load flag"]
    pub mod pwm_periodload_flag5 {
        #[doc = "Register `PWM_PERIODLOAD_FLAG5` reader"]
        pub type R = crate::R<PwmPeriodloadFlag5Spec>;
        #[doc = "Register `PWM_PERIODLOAD_FLAG5` writer"]
        pub type W = crate::W<PwmPeriodloadFlag5Spec>;
        #[doc = "Field `pwm_periodload_flag_5` reader - Period load complete flag"]
        pub type PwmPeriodloadFlag5R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Period load complete flag"]
            #[inline(always)]
            pub fn pwm_periodload_flag_5(&self) -> PwmPeriodloadFlag5R {
                PwmPeriodloadFlag5R::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "PWM5 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodloadFlag5Spec;
        impl crate::RegisterSpec for PwmPeriodloadFlag5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodload_flag5::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodloadFlag5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag5::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodloadFlag5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG5 to value 0"]
        impl crate::Resettable for PwmPeriodloadFlag5Spec {}
    }
    #[doc = "PWM_PERIOD_VAL5 (rw) register accessor: PWM5 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val5`] module"]
    #[doc(alias = "PWM_PERIOD_VAL5")]
    pub type PwmPeriodVal5 = crate::Reg<pwm_period_val5::PwmPeriodVal5Spec>;
    #[doc = "PWM5 pulse count value"]
    pub mod pwm_period_val5 {
        #[doc = "Register `PWM_PERIOD_VAL5` reader"]
        pub type R = crate::R<PwmPeriodVal5Spec>;
        #[doc = "Register `PWM_PERIOD_VAL5` writer"]
        pub type W = crate::W<PwmPeriodVal5Spec>;
        #[doc = "Field `pwm_period_val_5` reader - Pulse count for stepping mode"]
        pub type PwmPeriodVal5R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_period_val_5` writer - Pulse count for stepping mode"]
        pub type PwmPeriodVal5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_5(&self) -> PwmPeriodVal5R {
                PwmPeriodVal5R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_5(&mut self) -> PwmPeriodVal5W<'_, PwmPeriodVal5Spec> {
                PwmPeriodVal5W::new(self, 0)
            }
        }
        #[doc = "PWM5 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodVal5Spec;
        impl crate::RegisterSpec for PwmPeriodVal5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_period_val5::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodVal5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_period_val5::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodVal5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIOD_VAL5 to value 0"]
        impl crate::Resettable for PwmPeriodVal5Spec {}
    }
    #[doc = "PWM_PERIODCNT5 (rw) register accessor: PWM5 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt5`] module"]
    #[doc(alias = "PWM_PERIODCNT5")]
    pub type PwmPeriodcnt5 = crate::Reg<pwm_periodcnt5::PwmPeriodcnt5Spec>;
    #[doc = "PWM5 pulse count current value"]
    pub mod pwm_periodcnt5 {
        #[doc = "Register `PWM_PERIODCNT5` reader"]
        pub type R = crate::R<PwmPeriodcnt5Spec>;
        #[doc = "Register `PWM_PERIODCNT5` writer"]
        pub type W = crate::W<PwmPeriodcnt5Spec>;
        #[doc = "Field `pwm_periodcnt_5` reader - Current pulse count"]
        pub type PwmPeriodcnt5R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Current pulse count"]
            #[inline(always)]
            pub fn pwm_periodcnt_5(&self) -> PwmPeriodcnt5R {
                PwmPeriodcnt5R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM5 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodcnt5Spec;
        impl crate::RegisterSpec for PwmPeriodcnt5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodcnt5::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodcnt5Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt5::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodcnt5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODCNT5 to value 0"]
        impl crate::Resettable for PwmPeriodcnt5Spec {}
    }
    #[doc = "PWM_EN6 (rw) register accessor: PWM6 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en6`] module"]
    #[doc(alias = "PWM_EN6")]
    pub type PwmEn6 = crate::Reg<pwm_en6::PwmEn6Spec>;
    #[doc = "PWM6 enable"]
    pub mod pwm_en6 {
        #[doc = "Register `PWM_EN6` reader"]
        pub type R = crate::R<PwmEn6Spec>;
        #[doc = "Register `PWM_EN6` writer"]
        pub type W = crate::W<PwmEn6Spec>;
        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmEn6 {
            #[doc = "0: PWM disabled, output low"]
            Off = 0,
            #[doc = "1: PWM enabled"]
            On = 1,
        }
        impl From<PwmEn6> for bool {
            #[inline(always)]
            fn from(variant: PwmEn6) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_en_6` reader - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn6R = crate::BitReader<PwmEn6>;
        impl PwmEn6R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmEn6 {
                match self.bits {
                    false => PwmEn6::Off,
                    true => PwmEn6::On,
                }
            }
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn is_off(&self) -> bool {
                *self == PwmEn6::Off
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn is_on(&self) -> bool {
                *self == PwmEn6::On
            }
        }
        #[doc = "Field `pwm_en_6` writer - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn6W<'a, REG> = crate::BitWriter<'a, REG, PwmEn6>;
        impl<'a, REG> PwmEn6W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn off(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn6::Off)
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn on(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn6::On)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_6(&self) -> PwmEn6R {
                PwmEn6R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_6(&mut self) -> PwmEn6W<'_, PwmEn6Spec> {
                PwmEn6W::new(self, 0)
            }
        }
        #[doc = "PWM6 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmEn6Spec;
        impl crate::RegisterSpec for PwmEn6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_en6::R`](R) reader structure"]
        impl crate::Readable for PwmEn6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_en6::W`](W) writer structure"]
        impl crate::Writable for PwmEn6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_EN6 to value 0"]
        impl crate::Resettable for PwmEn6Spec {}
    }
    #[doc = "PWM_PORTITY6 (rw) register accessor: PWM6 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity6`] module"]
    #[doc(alias = "PWM_PORTITY6")]
    pub type PwmPortity6 = crate::Reg<pwm_portity6::PwmPortity6Spec>;
    #[doc = "PWM6 polarity"]
    pub mod pwm_portity6 {
        #[doc = "Register `PWM_PORTITY6` reader"]
        pub type R = crate::R<PwmPortity6Spec>;
        #[doc = "Register `PWM_PORTITY6` writer"]
        pub type W = crate::W<PwmPortity6Spec>;
        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmPoarity6 {
            #[doc = "0: Normal polarity"]
            Normal = 0,
            #[doc = "1: Inverted polarity"]
            Inverted = 1,
        }
        impl From<PwmPoarity6> for bool {
            #[inline(always)]
            fn from(variant: PwmPoarity6) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_poarity_6` reader - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity6R = crate::BitReader<PwmPoarity6>;
        impl PwmPoarity6R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmPoarity6 {
                match self.bits {
                    false => PwmPoarity6::Normal,
                    true => PwmPoarity6::Inverted,
                }
            }
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn is_normal(&self) -> bool {
                *self == PwmPoarity6::Normal
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn is_inverted(&self) -> bool {
                *self == PwmPoarity6::Inverted
            }
        }
        #[doc = "Field `pwm_poarity_6` writer - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity6W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity6>;
        impl<'a, REG> PwmPoarity6W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn normal(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity6::Normal)
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn inverted(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity6::Inverted)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_6(&self) -> PwmPoarity6R {
                PwmPoarity6R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_6(&mut self) -> PwmPoarity6W<'_, PwmPortity6Spec> {
                PwmPoarity6W::new(self, 0)
            }
        }
        #[doc = "PWM6 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPortity6Spec;
        impl crate::RegisterSpec for PwmPortity6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_portity6::R`](R) reader structure"]
        impl crate::Readable for PwmPortity6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_portity6::W`](W) writer structure"]
        impl crate::Writable for PwmPortity6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PORTITY6 to value 0"]
        impl crate::Resettable for PwmPortity6Spec {}
    }
    #[doc = "PWM_OEN_CFG6 (rw) register accessor: PWM6 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg6`] module"]
    #[doc(alias = "PWM_OEN_CFG6")]
    pub type PwmOenCfg6 = crate::Reg<pwm_oen_cfg6::PwmOenCfg6Spec>;
    #[doc = "PWM6 high-impedance config"]
    pub mod pwm_oen_cfg6 {
        #[doc = "Register `PWM_OEN_CFG6` reader"]
        pub type R = crate::R<PwmOenCfg6Spec>;
        #[doc = "Register `PWM_OEN_CFG6` writer"]
        pub type W = crate::W<PwmOenCfg6Spec>;
        #[doc = "Field `pwm_oen_cfg_6` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg6R = crate::BitReader;
        #[doc = "Field `pwm_oen_cfg_6` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg6W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_6(&self) -> PwmOenCfg6R {
                PwmOenCfg6R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_6(&mut self) -> PwmOenCfg6W<'_, PwmOenCfg6Spec> {
                PwmOenCfg6W::new(self, 0)
            }
        }
        #[doc = "PWM6 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOenCfg6Spec;
        impl crate::RegisterSpec for PwmOenCfg6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_oen_cfg6::R`](R) reader structure"]
        impl crate::Readable for PwmOenCfg6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg6::W`](W) writer structure"]
        impl crate::Writable for PwmOenCfg6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OEN_CFG6 to value 0"]
        impl crate::Resettable for PwmOenCfg6Spec {}
    }
    #[doc = "PWM_OFFSET_L6 (rw) register accessor: PWM6 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l6`] module"]
    #[doc(alias = "PWM_OFFSET_L6")]
    pub type PwmOffsetL6 = crate::Reg<pwm_offset_l6::PwmOffsetL6Spec>;
    #[doc = "PWM6 phase offset low 16 bits"]
    pub mod pwm_offset_l6 {
        #[doc = "Register `PWM_OFFSET_L6` reader"]
        pub type R = crate::R<PwmOffsetL6Spec>;
        #[doc = "Register `PWM_OFFSET_L6` writer"]
        pub type W = crate::W<PwmOffsetL6Spec>;
        #[doc = "Field `pwm_offset_l_6` reader - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL6R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_l_6` writer - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_6(&self) -> PwmOffsetL6R {
                PwmOffsetL6R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_6(&mut self) -> PwmOffsetL6W<'_, PwmOffsetL6Spec> {
                PwmOffsetL6W::new(self, 0)
            }
        }
        #[doc = "PWM6 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetL6Spec;
        impl crate::RegisterSpec for PwmOffsetL6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_l6::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetL6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l6::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetL6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_L6 to value 0"]
        impl crate::Resettable for PwmOffsetL6Spec {}
    }
    #[doc = "PWM_OFFSET_H6 (rw) register accessor: PWM6 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h6`] module"]
    #[doc(alias = "PWM_OFFSET_H6")]
    pub type PwmOffsetH6 = crate::Reg<pwm_offset_h6::PwmOffsetH6Spec>;
    #[doc = "PWM6 phase offset high 16 bits"]
    pub mod pwm_offset_h6 {
        #[doc = "Register `PWM_OFFSET_H6` reader"]
        pub type R = crate::R<PwmOffsetH6Spec>;
        #[doc = "Register `PWM_OFFSET_H6` writer"]
        pub type W = crate::W<PwmOffsetH6Spec>;
        #[doc = "Field `pwm_offset_h_6` reader - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH6R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_h_6` writer - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_6(&self) -> PwmOffsetH6R {
                PwmOffsetH6R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_6(&mut self) -> PwmOffsetH6W<'_, PwmOffsetH6Spec> {
                PwmOffsetH6W::new(self, 0)
            }
        }
        #[doc = "PWM6 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetH6Spec;
        impl crate::RegisterSpec for PwmOffsetH6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_h6::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetH6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h6::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetH6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_H6 to value 0"]
        impl crate::Resettable for PwmOffsetH6Spec {}
    }
    #[doc = "PWM_FREQ_L6 (rw) register accessor: PWM6 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l6`] module"]
    #[doc(alias = "PWM_FREQ_L6")]
    pub type PwmFreqL6 = crate::Reg<pwm_freq_l6::PwmFreqL6Spec>;
    #[doc = "PWM6 frequency low 16 bits"]
    pub mod pwm_freq_l6 {
        #[doc = "Register `PWM_FREQ_L6` reader"]
        pub type R = crate::R<PwmFreqL6Spec>;
        #[doc = "Register `PWM_FREQ_L6` writer"]
        pub type W = crate::W<PwmFreqL6Spec>;
        #[doc = "Field `pwm_freq_l_6` reader - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL6R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_l_6` writer - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_6(&self) -> PwmFreqL6R {
                PwmFreqL6R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_6(&mut self) -> PwmFreqL6W<'_, PwmFreqL6Spec> {
                PwmFreqL6W::new(self, 0)
            }
        }
        #[doc = "PWM6 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqL6Spec;
        impl crate::RegisterSpec for PwmFreqL6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_l6::R`](R) reader structure"]
        impl crate::Readable for PwmFreqL6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l6::W`](W) writer structure"]
        impl crate::Writable for PwmFreqL6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_L6 to value 0"]
        impl crate::Resettable for PwmFreqL6Spec {}
    }
    #[doc = "PWM_FREQ_H6 (rw) register accessor: PWM6 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h6`] module"]
    #[doc(alias = "PWM_FREQ_H6")]
    pub type PwmFreqH6 = crate::Reg<pwm_freq_h6::PwmFreqH6Spec>;
    #[doc = "PWM6 frequency high 16 bits"]
    pub mod pwm_freq_h6 {
        #[doc = "Register `PWM_FREQ_H6` reader"]
        pub type R = crate::R<PwmFreqH6Spec>;
        #[doc = "Register `PWM_FREQ_H6` writer"]
        pub type W = crate::W<PwmFreqH6Spec>;
        #[doc = "Field `pwm_freq_h_6` reader - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH6R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_h_6` writer - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_6(&self) -> PwmFreqH6R {
                PwmFreqH6R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_6(&mut self) -> PwmFreqH6W<'_, PwmFreqH6Spec> {
                PwmFreqH6W::new(self, 0)
            }
        }
        #[doc = "PWM6 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqH6Spec;
        impl crate::RegisterSpec for PwmFreqH6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_h6::R`](R) reader structure"]
        impl crate::Readable for PwmFreqH6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h6::W`](W) writer structure"]
        impl crate::Writable for PwmFreqH6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_H6 to value 0"]
        impl crate::Resettable for PwmFreqH6Spec {}
    }
    #[doc = "PWM_DUTY_L6 (rw) register accessor: PWM6 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l6`] module"]
    #[doc(alias = "PWM_DUTY_L6")]
    pub type PwmDutyL6 = crate::Reg<pwm_duty_l6::PwmDutyL6Spec>;
    #[doc = "PWM6 duty cycle low 16 bits"]
    pub mod pwm_duty_l6 {
        #[doc = "Register `PWM_DUTY_L6` reader"]
        pub type R = crate::R<PwmDutyL6Spec>;
        #[doc = "Register `PWM_DUTY_L6` writer"]
        pub type W = crate::W<PwmDutyL6Spec>;
        #[doc = "Field `pwm_duty_l_6` reader - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL6R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_l_6` writer - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_6(&self) -> PwmDutyL6R {
                PwmDutyL6R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_6(&mut self) -> PwmDutyL6W<'_, PwmDutyL6Spec> {
                PwmDutyL6W::new(self, 0)
            }
        }
        #[doc = "PWM6 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyL6Spec;
        impl crate::RegisterSpec for PwmDutyL6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_l6::R`](R) reader structure"]
        impl crate::Readable for PwmDutyL6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l6::W`](W) writer structure"]
        impl crate::Writable for PwmDutyL6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_L6 to value 0"]
        impl crate::Resettable for PwmDutyL6Spec {}
    }
    #[doc = "PWM_DUTY_H6 (rw) register accessor: PWM6 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h6`] module"]
    #[doc(alias = "PWM_DUTY_H6")]
    pub type PwmDutyH6 = crate::Reg<pwm_duty_h6::PwmDutyH6Spec>;
    #[doc = "PWM6 duty cycle high 16 bits"]
    pub mod pwm_duty_h6 {
        #[doc = "Register `PWM_DUTY_H6` reader"]
        pub type R = crate::R<PwmDutyH6Spec>;
        #[doc = "Register `PWM_DUTY_H6` writer"]
        pub type W = crate::W<PwmDutyH6Spec>;
        #[doc = "Field `pwm_duty_h_6` reader - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH6R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_h_6` writer - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_6(&self) -> PwmDutyH6R {
                PwmDutyH6R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_6(&mut self) -> PwmDutyH6W<'_, PwmDutyH6Spec> {
                PwmDutyH6W::new(self, 0)
            }
        }
        #[doc = "PWM6 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyH6Spec;
        impl crate::RegisterSpec for PwmDutyH6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_h6::R`](R) reader structure"]
        impl crate::Readable for PwmDutyH6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h6::W`](W) writer structure"]
        impl crate::Writable for PwmDutyH6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_H6 to value 0"]
        impl crate::Resettable for PwmDutyH6Spec {}
    }
    #[doc = "PWM_PERIODLOAD_FLAG6 (rw) register accessor: PWM6 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag6`] module"]
    #[doc(alias = "PWM_PERIODLOAD_FLAG6")]
    pub type PwmPeriodloadFlag6 = crate::Reg<pwm_periodload_flag6::PwmPeriodloadFlag6Spec>;
    #[doc = "PWM6 period load flag"]
    pub mod pwm_periodload_flag6 {
        #[doc = "Register `PWM_PERIODLOAD_FLAG6` reader"]
        pub type R = crate::R<PwmPeriodloadFlag6Spec>;
        #[doc = "Register `PWM_PERIODLOAD_FLAG6` writer"]
        pub type W = crate::W<PwmPeriodloadFlag6Spec>;
        #[doc = "Field `pwm_periodload_flag_6` reader - Period load complete flag"]
        pub type PwmPeriodloadFlag6R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Period load complete flag"]
            #[inline(always)]
            pub fn pwm_periodload_flag_6(&self) -> PwmPeriodloadFlag6R {
                PwmPeriodloadFlag6R::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "PWM6 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodloadFlag6Spec;
        impl crate::RegisterSpec for PwmPeriodloadFlag6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodload_flag6::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodloadFlag6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag6::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodloadFlag6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG6 to value 0"]
        impl crate::Resettable for PwmPeriodloadFlag6Spec {}
    }
    #[doc = "PWM_PERIOD_VAL6 (rw) register accessor: PWM6 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val6`] module"]
    #[doc(alias = "PWM_PERIOD_VAL6")]
    pub type PwmPeriodVal6 = crate::Reg<pwm_period_val6::PwmPeriodVal6Spec>;
    #[doc = "PWM6 pulse count value"]
    pub mod pwm_period_val6 {
        #[doc = "Register `PWM_PERIOD_VAL6` reader"]
        pub type R = crate::R<PwmPeriodVal6Spec>;
        #[doc = "Register `PWM_PERIOD_VAL6` writer"]
        pub type W = crate::W<PwmPeriodVal6Spec>;
        #[doc = "Field `pwm_period_val_6` reader - Pulse count for stepping mode"]
        pub type PwmPeriodVal6R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_period_val_6` writer - Pulse count for stepping mode"]
        pub type PwmPeriodVal6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_6(&self) -> PwmPeriodVal6R {
                PwmPeriodVal6R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_6(&mut self) -> PwmPeriodVal6W<'_, PwmPeriodVal6Spec> {
                PwmPeriodVal6W::new(self, 0)
            }
        }
        #[doc = "PWM6 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodVal6Spec;
        impl crate::RegisterSpec for PwmPeriodVal6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_period_val6::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodVal6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_period_val6::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodVal6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIOD_VAL6 to value 0"]
        impl crate::Resettable for PwmPeriodVal6Spec {}
    }
    #[doc = "PWM_PERIODCNT6 (rw) register accessor: PWM6 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt6`] module"]
    #[doc(alias = "PWM_PERIODCNT6")]
    pub type PwmPeriodcnt6 = crate::Reg<pwm_periodcnt6::PwmPeriodcnt6Spec>;
    #[doc = "PWM6 pulse count current value"]
    pub mod pwm_periodcnt6 {
        #[doc = "Register `PWM_PERIODCNT6` reader"]
        pub type R = crate::R<PwmPeriodcnt6Spec>;
        #[doc = "Register `PWM_PERIODCNT6` writer"]
        pub type W = crate::W<PwmPeriodcnt6Spec>;
        #[doc = "Field `pwm_periodcnt_6` reader - Current pulse count"]
        pub type PwmPeriodcnt6R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Current pulse count"]
            #[inline(always)]
            pub fn pwm_periodcnt_6(&self) -> PwmPeriodcnt6R {
                PwmPeriodcnt6R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM6 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodcnt6Spec;
        impl crate::RegisterSpec for PwmPeriodcnt6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodcnt6::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodcnt6Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt6::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodcnt6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODCNT6 to value 0"]
        impl crate::Resettable for PwmPeriodcnt6Spec {}
    }
    #[doc = "PWM_EN7 (rw) register accessor: PWM7 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_en7`] module"]
    #[doc(alias = "PWM_EN7")]
    pub type PwmEn7 = crate::Reg<pwm_en7::PwmEn7Spec>;
    #[doc = "PWM7 enable"]
    pub mod pwm_en7 {
        #[doc = "Register `PWM_EN7` reader"]
        pub type R = crate::R<PwmEn7Spec>;
        #[doc = "Register `PWM_EN7` writer"]
        pub type W = crate::W<PwmEn7Spec>;
        #[doc = "PWM0 enable: 0=off; 1=on\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmEn7 {
            #[doc = "0: PWM disabled, output low"]
            Off = 0,
            #[doc = "1: PWM enabled"]
            On = 1,
        }
        impl From<PwmEn7> for bool {
            #[inline(always)]
            fn from(variant: PwmEn7) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_en_7` reader - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn7R = crate::BitReader<PwmEn7>;
        impl PwmEn7R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmEn7 {
                match self.bits {
                    false => PwmEn7::Off,
                    true => PwmEn7::On,
                }
            }
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn is_off(&self) -> bool {
                *self == PwmEn7::Off
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn is_on(&self) -> bool {
                *self == PwmEn7::On
            }
        }
        #[doc = "Field `pwm_en_7` writer - PWM0 enable: 0=off; 1=on"]
        pub type PwmEn7W<'a, REG> = crate::BitWriter<'a, REG, PwmEn7>;
        impl<'a, REG> PwmEn7W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "PWM disabled, output low"]
            #[inline(always)]
            pub fn off(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn7::Off)
            }
            #[doc = "PWM enabled"]
            #[inline(always)]
            pub fn on(self) -> &'a mut crate::W<REG> {
                self.variant(PwmEn7::On)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_7(&self) -> PwmEn7R {
                PwmEn7R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 enable: 0=off; 1=on"]
            #[inline(always)]
            pub fn pwm_en_7(&mut self) -> PwmEn7W<'_, PwmEn7Spec> {
                PwmEn7W::new(self, 0)
            }
        }
        #[doc = "PWM7 enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_en7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_en7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmEn7Spec;
        impl crate::RegisterSpec for PwmEn7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_en7::R`](R) reader structure"]
        impl crate::Readable for PwmEn7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_en7::W`](W) writer structure"]
        impl crate::Writable for PwmEn7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_EN7 to value 0"]
        impl crate::Resettable for PwmEn7Spec {}
    }
    #[doc = "PWM_PORTITY7 (rw) register accessor: PWM7 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_portity7`] module"]
    #[doc(alias = "PWM_PORTITY7")]
    pub type PwmPortity7 = crate::Reg<pwm_portity7::PwmPortity7Spec>;
    #[doc = "PWM7 polarity"]
    pub mod pwm_portity7 {
        #[doc = "Register `PWM_PORTITY7` reader"]
        pub type R = crate::R<PwmPortity7Spec>;
        #[doc = "Register `PWM_PORTITY7` writer"]
        pub type W = crate::W<PwmPortity7Spec>;
        #[doc = "PWM0 polarity: 0=normal; 1=inverted\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        pub enum PwmPoarity7 {
            #[doc = "0: Normal polarity"]
            Normal = 0,
            #[doc = "1: Inverted polarity"]
            Inverted = 1,
        }
        impl From<PwmPoarity7> for bool {
            #[inline(always)]
            fn from(variant: PwmPoarity7) -> Self {
                variant as u8 != 0
            }
        }
        #[doc = "Field `pwm_poarity_7` reader - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity7R = crate::BitReader<PwmPoarity7>;
        impl PwmPoarity7R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> PwmPoarity7 {
                match self.bits {
                    false => PwmPoarity7::Normal,
                    true => PwmPoarity7::Inverted,
                }
            }
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn is_normal(&self) -> bool {
                *self == PwmPoarity7::Normal
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn is_inverted(&self) -> bool {
                *self == PwmPoarity7::Inverted
            }
        }
        #[doc = "Field `pwm_poarity_7` writer - PWM0 polarity: 0=normal; 1=inverted"]
        pub type PwmPoarity7W<'a, REG> = crate::BitWriter<'a, REG, PwmPoarity7>;
        impl<'a, REG> PwmPoarity7W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
        {
            #[doc = "Normal polarity"]
            #[inline(always)]
            pub fn normal(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity7::Normal)
            }
            #[doc = "Inverted polarity"]
            #[inline(always)]
            pub fn inverted(self) -> &'a mut crate::W<REG> {
                self.variant(PwmPoarity7::Inverted)
            }
        }
        impl R {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_7(&self) -> PwmPoarity7R {
                PwmPoarity7R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 polarity: 0=normal; 1=inverted"]
            #[inline(always)]
            pub fn pwm_poarity_7(&mut self) -> PwmPoarity7W<'_, PwmPortity7Spec> {
                PwmPoarity7W::new(self, 0)
            }
        }
        #[doc = "PWM7 polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_portity7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_portity7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPortity7Spec;
        impl crate::RegisterSpec for PwmPortity7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_portity7::R`](R) reader structure"]
        impl crate::Readable for PwmPortity7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_portity7::W`](W) writer structure"]
        impl crate::Writable for PwmPortity7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PORTITY7 to value 0"]
        impl crate::Resettable for PwmPortity7Spec {}
    }
    #[doc = "PWM_OEN_CFG7 (rw) register accessor: PWM7 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_oen_cfg7`] module"]
    #[doc(alias = "PWM_OEN_CFG7")]
    pub type PwmOenCfg7 = crate::Reg<pwm_oen_cfg7::PwmOenCfg7Spec>;
    #[doc = "PWM7 high-impedance config"]
    pub mod pwm_oen_cfg7 {
        #[doc = "Register `PWM_OEN_CFG7` reader"]
        pub type R = crate::R<PwmOenCfg7Spec>;
        #[doc = "Register `PWM_OEN_CFG7` writer"]
        pub type W = crate::W<PwmOenCfg7Spec>;
        #[doc = "Field `pwm_oen_cfg_7` reader - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg7R = crate::BitReader;
        #[doc = "Field `pwm_oen_cfg_7` writer - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
        pub type PwmOenCfg7W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_7(&self) -> PwmOenCfg7R {
                PwmOenCfg7R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - PWM0 high-Z enable: 0=follow polarity; 1=high-Z when inactive"]
            #[inline(always)]
            pub fn pwm_oen_cfg_7(&mut self) -> PwmOenCfg7W<'_, PwmOenCfg7Spec> {
                PwmOenCfg7W::new(self, 0)
            }
        }
        #[doc = "PWM7 high-impedance config\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_oen_cfg7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_oen_cfg7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOenCfg7Spec;
        impl crate::RegisterSpec for PwmOenCfg7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_oen_cfg7::R`](R) reader structure"]
        impl crate::Readable for PwmOenCfg7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_oen_cfg7::W`](W) writer structure"]
        impl crate::Writable for PwmOenCfg7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OEN_CFG7 to value 0"]
        impl crate::Resettable for PwmOenCfg7Spec {}
    }
    #[doc = "PWM_OFFSET_L7 (rw) register accessor: PWM7 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_l7`] module"]
    #[doc(alias = "PWM_OFFSET_L7")]
    pub type PwmOffsetL7 = crate::Reg<pwm_offset_l7::PwmOffsetL7Spec>;
    #[doc = "PWM7 phase offset low 16 bits"]
    pub mod pwm_offset_l7 {
        #[doc = "Register `PWM_OFFSET_L7` reader"]
        pub type R = crate::R<PwmOffsetL7Spec>;
        #[doc = "Register `PWM_OFFSET_L7` writer"]
        pub type W = crate::W<PwmOffsetL7Spec>;
        #[doc = "Field `pwm_offset_l_7` reader - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL7R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_l_7` writer - PWM0 phase offset low 16 bits"]
        pub type PwmOffsetL7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_7(&self) -> PwmOffsetL7R {
                PwmOffsetL7R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset low 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_l_7(&mut self) -> PwmOffsetL7W<'_, PwmOffsetL7Spec> {
                PwmOffsetL7W::new(self, 0)
            }
        }
        #[doc = "PWM7 phase offset low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetL7Spec;
        impl crate::RegisterSpec for PwmOffsetL7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_l7::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetL7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_l7::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetL7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_L7 to value 0"]
        impl crate::Resettable for PwmOffsetL7Spec {}
    }
    #[doc = "PWM_OFFSET_H7 (rw) register accessor: PWM7 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset_h7`] module"]
    #[doc(alias = "PWM_OFFSET_H7")]
    pub type PwmOffsetH7 = crate::Reg<pwm_offset_h7::PwmOffsetH7Spec>;
    #[doc = "PWM7 phase offset high 16 bits"]
    pub mod pwm_offset_h7 {
        #[doc = "Register `PWM_OFFSET_H7` reader"]
        pub type R = crate::R<PwmOffsetH7Spec>;
        #[doc = "Register `PWM_OFFSET_H7` writer"]
        pub type W = crate::W<PwmOffsetH7Spec>;
        #[doc = "Field `pwm_offset_h_7` reader - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH7R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_offset_h_7` writer - PWM0 phase offset high 16 bits"]
        pub type PwmOffsetH7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_7(&self) -> PwmOffsetH7R {
                PwmOffsetH7R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 phase offset high 16 bits"]
            #[inline(always)]
            pub fn pwm_offset_h_7(&mut self) -> PwmOffsetH7W<'_, PwmOffsetH7Spec> {
                PwmOffsetH7W::new(self, 0)
            }
        }
        #[doc = "PWM7 phase offset high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_offset_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_offset_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmOffsetH7Spec;
        impl crate::RegisterSpec for PwmOffsetH7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset_h7::R`](R) reader structure"]
        impl crate::Readable for PwmOffsetH7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset_h7::W`](W) writer structure"]
        impl crate::Writable for PwmOffsetH7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_OFFSET_H7 to value 0"]
        impl crate::Resettable for PwmOffsetH7Spec {}
    }
    #[doc = "PWM_FREQ_L7 (rw) register accessor: PWM7 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_l7`] module"]
    #[doc(alias = "PWM_FREQ_L7")]
    pub type PwmFreqL7 = crate::Reg<pwm_freq_l7::PwmFreqL7Spec>;
    #[doc = "PWM7 frequency low 16 bits"]
    pub mod pwm_freq_l7 {
        #[doc = "Register `PWM_FREQ_L7` reader"]
        pub type R = crate::R<PwmFreqL7Spec>;
        #[doc = "Register `PWM_FREQ_L7` writer"]
        pub type W = crate::W<PwmFreqL7Spec>;
        #[doc = "Field `pwm_freq_l_7` reader - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL7R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_l_7` writer - PWM0 clock divider low 16 bits"]
        pub type PwmFreqL7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_7(&self) -> PwmFreqL7R {
                PwmFreqL7R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider low 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_l_7(&mut self) -> PwmFreqL7W<'_, PwmFreqL7Spec> {
                PwmFreqL7W::new(self, 0)
            }
        }
        #[doc = "PWM7 frequency low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqL7Spec;
        impl crate::RegisterSpec for PwmFreqL7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_l7::R`](R) reader structure"]
        impl crate::Readable for PwmFreqL7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_l7::W`](W) writer structure"]
        impl crate::Writable for PwmFreqL7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_L7 to value 0"]
        impl crate::Resettable for PwmFreqL7Spec {}
    }
    #[doc = "PWM_FREQ_H7 (rw) register accessor: PWM7 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_freq_h7`] module"]
    #[doc(alias = "PWM_FREQ_H7")]
    pub type PwmFreqH7 = crate::Reg<pwm_freq_h7::PwmFreqH7Spec>;
    #[doc = "PWM7 frequency high 16 bits"]
    pub mod pwm_freq_h7 {
        #[doc = "Register `PWM_FREQ_H7` reader"]
        pub type R = crate::R<PwmFreqH7Spec>;
        #[doc = "Register `PWM_FREQ_H7` writer"]
        pub type W = crate::W<PwmFreqH7Spec>;
        #[doc = "Field `pwm_freq_h_7` reader - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH7R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_freq_h_7` writer - PWM0 clock divider high 16 bits"]
        pub type PwmFreqH7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_7(&self) -> PwmFreqH7R {
                PwmFreqH7R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 clock divider high 16 bits"]
            #[inline(always)]
            pub fn pwm_freq_h_7(&mut self) -> PwmFreqH7W<'_, PwmFreqH7Spec> {
                PwmFreqH7W::new(self, 0)
            }
        }
        #[doc = "PWM7 frequency high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_freq_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_freq_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmFreqH7Spec;
        impl crate::RegisterSpec for PwmFreqH7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_freq_h7::R`](R) reader structure"]
        impl crate::Readable for PwmFreqH7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_freq_h7::W`](W) writer structure"]
        impl crate::Writable for PwmFreqH7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_FREQ_H7 to value 0"]
        impl crate::Resettable for PwmFreqH7Spec {}
    }
    #[doc = "PWM_DUTY_L7 (rw) register accessor: PWM7 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_l7`] module"]
    #[doc(alias = "PWM_DUTY_L7")]
    pub type PwmDutyL7 = crate::Reg<pwm_duty_l7::PwmDutyL7Spec>;
    #[doc = "PWM7 duty cycle low 16 bits"]
    pub mod pwm_duty_l7 {
        #[doc = "Register `PWM_DUTY_L7` reader"]
        pub type R = crate::R<PwmDutyL7Spec>;
        #[doc = "Register `PWM_DUTY_L7` writer"]
        pub type W = crate::W<PwmDutyL7Spec>;
        #[doc = "Field `pwm_duty_l_7` reader - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL7R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_l_7` writer - PWM0 duty cycle low 16 bits"]
        pub type PwmDutyL7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_7(&self) -> PwmDutyL7R {
                PwmDutyL7R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle low 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_l_7(&mut self) -> PwmDutyL7W<'_, PwmDutyL7Spec> {
                PwmDutyL7W::new(self, 0)
            }
        }
        #[doc = "PWM7 duty cycle low 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_l7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_l7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyL7Spec;
        impl crate::RegisterSpec for PwmDutyL7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_l7::R`](R) reader structure"]
        impl crate::Readable for PwmDutyL7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_l7::W`](W) writer structure"]
        impl crate::Writable for PwmDutyL7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_L7 to value 0"]
        impl crate::Resettable for PwmDutyL7Spec {}
    }
    #[doc = "PWM_DUTY_H7 (rw) register accessor: PWM7 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_duty_h7`] module"]
    #[doc(alias = "PWM_DUTY_H7")]
    pub type PwmDutyH7 = crate::Reg<pwm_duty_h7::PwmDutyH7Spec>;
    #[doc = "PWM7 duty cycle high 16 bits"]
    pub mod pwm_duty_h7 {
        #[doc = "Register `PWM_DUTY_H7` reader"]
        pub type R = crate::R<PwmDutyH7Spec>;
        #[doc = "Register `PWM_DUTY_H7` writer"]
        pub type W = crate::W<PwmDutyH7Spec>;
        #[doc = "Field `pwm_duty_h_7` reader - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH7R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_duty_h_7` writer - PWM0 duty cycle high 16 bits"]
        pub type PwmDutyH7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_7(&self) -> PwmDutyH7R {
                PwmDutyH7R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - PWM0 duty cycle high 16 bits"]
            #[inline(always)]
            pub fn pwm_duty_h_7(&mut self) -> PwmDutyH7W<'_, PwmDutyH7Spec> {
                PwmDutyH7W::new(self, 0)
            }
        }
        #[doc = "PWM7 duty cycle high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_duty_h7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_duty_h7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmDutyH7Spec;
        impl crate::RegisterSpec for PwmDutyH7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_duty_h7::R`](R) reader structure"]
        impl crate::Readable for PwmDutyH7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_duty_h7::W`](W) writer structure"]
        impl crate::Writable for PwmDutyH7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_DUTY_H7 to value 0"]
        impl crate::Resettable for PwmDutyH7Spec {}
    }
    #[doc = "PWM_PERIODLOAD_FLAG7 (rw) register accessor: PWM7 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodload_flag7`] module"]
    #[doc(alias = "PWM_PERIODLOAD_FLAG7")]
    pub type PwmPeriodloadFlag7 = crate::Reg<pwm_periodload_flag7::PwmPeriodloadFlag7Spec>;
    #[doc = "PWM7 period load flag"]
    pub mod pwm_periodload_flag7 {
        #[doc = "Register `PWM_PERIODLOAD_FLAG7` reader"]
        pub type R = crate::R<PwmPeriodloadFlag7Spec>;
        #[doc = "Register `PWM_PERIODLOAD_FLAG7` writer"]
        pub type W = crate::W<PwmPeriodloadFlag7Spec>;
        #[doc = "Field `pwm_periodload_flag_7` reader - Period load complete flag"]
        pub type PwmPeriodloadFlag7R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Period load complete flag"]
            #[inline(always)]
            pub fn pwm_periodload_flag_7(&self) -> PwmPeriodloadFlag7R {
                PwmPeriodloadFlag7R::new((self.bits & 1) != 0)
            }
        }
        impl W {}
        #[doc = "PWM7 period load flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodload_flag7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodload_flag7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodloadFlag7Spec;
        impl crate::RegisterSpec for PwmPeriodloadFlag7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodload_flag7::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodloadFlag7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodload_flag7::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodloadFlag7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODLOAD_FLAG7 to value 0"]
        impl crate::Resettable for PwmPeriodloadFlag7Spec {}
    }
    #[doc = "PWM_PERIOD_VAL7 (rw) register accessor: PWM7 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_period_val7`] module"]
    #[doc(alias = "PWM_PERIOD_VAL7")]
    pub type PwmPeriodVal7 = crate::Reg<pwm_period_val7::PwmPeriodVal7Spec>;
    #[doc = "PWM7 pulse count value"]
    pub mod pwm_period_val7 {
        #[doc = "Register `PWM_PERIOD_VAL7` reader"]
        pub type R = crate::R<PwmPeriodVal7Spec>;
        #[doc = "Register `PWM_PERIOD_VAL7` writer"]
        pub type W = crate::W<PwmPeriodVal7Spec>;
        #[doc = "Field `pwm_period_val_7` reader - Pulse count for stepping mode"]
        pub type PwmPeriodVal7R = crate::FieldReader<u16>;
        #[doc = "Field `pwm_period_val_7` writer - Pulse count for stepping mode"]
        pub type PwmPeriodVal7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_7(&self) -> PwmPeriodVal7R {
                PwmPeriodVal7R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Pulse count for stepping mode"]
            #[inline(always)]
            pub fn pwm_period_val_7(&mut self) -> PwmPeriodVal7W<'_, PwmPeriodVal7Spec> {
                PwmPeriodVal7W::new(self, 0)
            }
        }
        #[doc = "PWM7 pulse count value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_period_val7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_period_val7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodVal7Spec;
        impl crate::RegisterSpec for PwmPeriodVal7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_period_val7::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodVal7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_period_val7::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodVal7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIOD_VAL7 to value 0"]
        impl crate::Resettable for PwmPeriodVal7Spec {}
    }
    #[doc = "PWM_PERIODCNT7 (rw) register accessor: PWM7 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_periodcnt7`] module"]
    #[doc(alias = "PWM_PERIODCNT7")]
    pub type PwmPeriodcnt7 = crate::Reg<pwm_periodcnt7::PwmPeriodcnt7Spec>;
    #[doc = "PWM7 pulse count current value"]
    pub mod pwm_periodcnt7 {
        #[doc = "Register `PWM_PERIODCNT7` reader"]
        pub type R = crate::R<PwmPeriodcnt7Spec>;
        #[doc = "Register `PWM_PERIODCNT7` writer"]
        pub type W = crate::W<PwmPeriodcnt7Spec>;
        #[doc = "Field `pwm_periodcnt_7` reader - Current pulse count"]
        pub type PwmPeriodcnt7R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Current pulse count"]
            #[inline(always)]
            pub fn pwm_periodcnt_7(&self) -> PwmPeriodcnt7R {
                PwmPeriodcnt7R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {}
        #[doc = "PWM7 pulse count current value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_periodcnt7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_periodcnt7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PwmPeriodcnt7Spec;
        impl crate::RegisterSpec for PwmPeriodcnt7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_periodcnt7::R`](R) reader structure"]
        impl crate::Readable for PwmPeriodcnt7Spec {}
        #[doc = "`write(|w| ..)` method takes [`pwm_periodcnt7::W`](W) writer structure"]
        impl crate::Writable for PwmPeriodcnt7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PWM_PERIODCNT7 to value 0"]
        impl crate::Resettable for PwmPeriodcnt7Spec {}
    }
}
#[doc = "DMA controller with 4 channels"]
pub type Dma = crate::Periph<dma::RegisterBlock, 0x5207_0000>;
impl core::fmt::Debug for Dma {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Dma").finish()
    }
}
#[doc = "DMA controller with 4 channels"]
pub mod dma {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x04],
        dmac_int_st: DmacIntSt,
        dmac_int_clr: DmacIntClr,
        dmac_ori_int_st: DmacOriIntSt,
        dmac_en_chns: DmacEnChns,
        dmac_burst_req: DmacBurstReq,
        dmac_single_req: DmacSingleReq,
        dmac_config: DmacConfig,
        dmac_sync: DmacSync,
        _reserved8: [u8; 0xdc],
        dmac_lli_0: (),
        _reserved9: [u8; 0x04],
        dmac_d_addr_0: (),
        _reserved10: [u8; 0x04],
        dmac_chn_config_0: (),
        _reserved11: [u8; 0x08],
        dmac_s_addr_0: (),
        _reserved12: [u8; 0x04],
        dmac_chn_control_0: (),
    }
    impl RegisterBlock {
        #[doc = "0x04 - Interrupt status register"]
        #[inline(always)]
        pub const fn dmac_int_st(&self) -> &DmacIntSt {
            &self.dmac_int_st
        }
        #[doc = "0x08 - Interrupt clear register"]
        #[inline(always)]
        pub const fn dmac_int_clr(&self) -> &DmacIntClr {
            &self.dmac_int_clr
        }
        #[doc = "0x0c - Raw interrupt status register"]
        #[inline(always)]
        pub const fn dmac_ori_int_st(&self) -> &DmacOriIntSt {
            &self.dmac_ori_int_st
        }
        #[doc = "0x10 - Channel enable query register"]
        #[inline(always)]
        pub const fn dmac_en_chns(&self) -> &DmacEnChns {
            &self.dmac_en_chns
        }
        #[doc = "0x14 - Burst software request register"]
        #[inline(always)]
        pub const fn dmac_burst_req(&self) -> &DmacBurstReq {
            &self.dmac_burst_req
        }
        #[doc = "0x18 - Single software request register"]
        #[inline(always)]
        pub const fn dmac_single_req(&self) -> &DmacSingleReq {
            &self.dmac_single_req
        }
        #[doc = "0x1c - DMA configuration register"]
        #[inline(always)]
        pub const fn dmac_config(&self) -> &DmacConfig {
            &self.dmac_config
        }
        #[doc = "0x20 - DMA sync register"]
        #[inline(always)]
        pub const fn dmac_sync(&self) -> &DmacSync {
            &self.dmac_sync
        }
        #[doc = "0x100..0x110 - Channel %s \\[dim=4\\] linked list register"]
        #[inline(always)]
        pub const fn dmac_lli_0(&self, n: usize) -> &DmacLli_ {
            #[allow(clippy::no_effect)]
            [(); 4][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(256)
                    .add(32 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x100..0x110 - Channel %s \\[dim=4\\] linked list register"]
        #[inline(always)]
        pub fn dmac_lli_0_iter(&self) -> impl Iterator<Item = &DmacLli_> {
            (0..4).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(256)
                    .add(32 * n)
                    .cast()
            })
        }
        #[doc = "0x104..0x114 - Channel %s \\[dim=4\\] destination address"]
        #[inline(always)]
        pub const fn dmac_d_addr_0(&self, n: usize) -> &DmacDAddr_ {
            #[allow(clippy::no_effect)]
            [(); 4][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(260)
                    .add(32 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x104..0x114 - Channel %s \\[dim=4\\] destination address"]
        #[inline(always)]
        pub fn dmac_d_addr_0_iter(&self) -> impl Iterator<Item = &DmacDAddr_> {
            (0..4).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(260)
                    .add(32 * n)
                    .cast()
            })
        }
        #[doc = "0x108..0x118 - Channel %s \\[dim=4\\] configuration register"]
        #[inline(always)]
        pub const fn dmac_chn_config_0(&self, n: usize) -> &DmacChnConfig_ {
            #[allow(clippy::no_effect)]
            [(); 4][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(264)
                    .add(32 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x108..0x118 - Channel %s \\[dim=4\\] configuration register"]
        #[inline(always)]
        pub fn dmac_chn_config_0_iter(&self) -> impl Iterator<Item = &DmacChnConfig_> {
            (0..4).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(264)
                    .add(32 * n)
                    .cast()
            })
        }
        #[doc = "0x110..0x120 - Channel %s \\[dim=4\\] source address"]
        #[inline(always)]
        pub const fn dmac_s_addr_0(&self, n: usize) -> &DmacSAddr_ {
            #[allow(clippy::no_effect)]
            [(); 4][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(272)
                    .add(32 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x110..0x120 - Channel %s \\[dim=4\\] source address"]
        #[inline(always)]
        pub fn dmac_s_addr_0_iter(&self) -> impl Iterator<Item = &DmacSAddr_> {
            (0..4).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(272)
                    .add(32 * n)
                    .cast()
            })
        }
        #[doc = "0x114..0x124 - Channel %s \\[dim=4\\] control register"]
        #[inline(always)]
        pub const fn dmac_chn_control_0(&self, n: usize) -> &DmacChnControl_ {
            #[allow(clippy::no_effect)]
            [(); 4][n];
            unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(276)
                    .add(32 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x114..0x124 - Channel %s \\[dim=4\\] control register"]
        #[inline(always)]
        pub fn dmac_chn_control_0_iter(&self) -> impl Iterator<Item = &DmacChnControl_> {
            (0..4).map(move |n| unsafe {
                &*core::ptr::from_ref(self)
                    .cast::<u8>()
                    .add(276)
                    .add(32 * n)
                    .cast()
            })
        }
    }
    #[doc = "DMAC_INT_ST (rw) register accessor: Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_int_st`] module"]
    #[doc(alias = "DMAC_INT_ST")]
    pub type DmacIntSt = crate::Reg<dmac_int_st::DmacIntStSpec>;
    #[doc = "Interrupt status register"]
    pub mod dmac_int_st {
        #[doc = "Register `DMAC_INT_ST` reader"]
        pub type R = crate::R<DmacIntStSpec>;
        #[doc = "Register `DMAC_INT_ST` writer"]
        pub type W = crate::W<DmacIntStSpec>;
        #[doc = "Field `int_st` reader - Channel interrupt status (after mask)"]
        pub type IntStR = crate::FieldReader;
        #[doc = "Field `int_trans_st` reader - Channel transfer interrupt status (after mask)"]
        pub type IntTransStR = crate::FieldReader;
        #[doc = "Field `int_err_st` reader - Channel error interrupt status (after mask)"]
        pub type IntErrStR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - Channel interrupt status (after mask)"]
            #[inline(always)]
            pub fn int_st(&self) -> IntStR {
                IntStR::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - Channel transfer interrupt status (after mask)"]
            #[inline(always)]
            pub fn int_trans_st(&self) -> IntTransStR {
                IntTransStR::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - Channel error interrupt status (after mask)"]
            #[inline(always)]
            pub fn int_err_st(&self) -> IntErrStR {
                IntErrStR::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {}
        #[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacIntStSpec;
        impl crate::RegisterSpec for DmacIntStSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_int_st::R`](R) reader structure"]
        impl crate::Readable for DmacIntStSpec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_int_st::W`](W) writer structure"]
        impl crate::Writable for DmacIntStSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_INT_ST to value 0"]
        impl crate::Resettable for DmacIntStSpec {}
    }
    #[doc = "DMAC_INT_CLR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_int_clr`] module"]
    #[doc(alias = "DMAC_INT_CLR")]
    pub type DmacIntClr = crate::Reg<dmac_int_clr::DmacIntClrSpec>;
    #[doc = "Interrupt clear register"]
    pub mod dmac_int_clr {
        #[doc = "Register `DMAC_INT_CLR` reader"]
        pub type R = crate::R<DmacIntClrSpec>;
        #[doc = "Register `DMAC_INT_CLR` writer"]
        pub type W = crate::W<DmacIntClrSpec>;
        #[doc = "Field `int_trans_clr` reader - Clear channel transfer interrupt"]
        pub type IntTransClrR = crate::FieldReader;
        #[doc = "Field `int_trans_clr` writer - Clear channel transfer interrupt"]
        pub type IntTransClrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `int_err_clr` reader - Clear channel error interrupt"]
        pub type IntErrClrR = crate::FieldReader;
        #[doc = "Field `int_err_clr` writer - Clear channel error interrupt"]
        pub type IntErrClrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Clear channel transfer interrupt"]
            #[inline(always)]
            pub fn int_trans_clr(&self) -> IntTransClrR {
                IntTransClrR::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - Clear channel error interrupt"]
            #[inline(always)]
            pub fn int_err_clr(&self) -> IntErrClrR {
                IntErrClrR::new(((self.bits >> 8) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Clear channel transfer interrupt"]
            #[inline(always)]
            pub fn int_trans_clr(&mut self) -> IntTransClrW<'_, DmacIntClrSpec> {
                IntTransClrW::new(self, 0)
            }
            #[doc = "Bits 8:15 - Clear channel error interrupt"]
            #[inline(always)]
            pub fn int_err_clr(&mut self) -> IntErrClrW<'_, DmacIntClrSpec> {
                IntErrClrW::new(self, 8)
            }
        }
        #[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacIntClrSpec;
        impl crate::RegisterSpec for DmacIntClrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_int_clr::R`](R) reader structure"]
        impl crate::Readable for DmacIntClrSpec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_int_clr::W`](W) writer structure"]
        impl crate::Writable for DmacIntClrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_INT_CLR to value 0"]
        impl crate::Resettable for DmacIntClrSpec {}
    }
    #[doc = "DMAC_ORI_INT_ST (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_ori_int_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_ori_int_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_ori_int_st`] module"]
    #[doc(alias = "DMAC_ORI_INT_ST")]
    pub type DmacOriIntSt = crate::Reg<dmac_ori_int_st::DmacOriIntStSpec>;
    #[doc = "Raw interrupt status register"]
    pub mod dmac_ori_int_st {
        #[doc = "Register `DMAC_ORI_INT_ST` reader"]
        pub type R = crate::R<DmacOriIntStSpec>;
        #[doc = "Register `DMAC_ORI_INT_ST` writer"]
        pub type W = crate::W<DmacOriIntStSpec>;
        #[doc = "Field `ori_int_trans_st` reader - Raw transfer interrupt status (before mask)"]
        pub type OriIntTransStR = crate::FieldReader;
        #[doc = "Field `ori_int_err_st` reader - Raw error interrupt status (before mask)"]
        pub type OriIntErrStR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - Raw transfer interrupt status (before mask)"]
            #[inline(always)]
            pub fn ori_int_trans_st(&self) -> OriIntTransStR {
                OriIntTransStR::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - Raw error interrupt status (before mask)"]
            #[inline(always)]
            pub fn ori_int_err_st(&self) -> OriIntErrStR {
                OriIntErrStR::new(((self.bits >> 8) & 0xff) as u8)
            }
        }
        impl W {}
        #[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_ori_int_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_ori_int_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacOriIntStSpec;
        impl crate::RegisterSpec for DmacOriIntStSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_ori_int_st::R`](R) reader structure"]
        impl crate::Readable for DmacOriIntStSpec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_ori_int_st::W`](W) writer structure"]
        impl crate::Writable for DmacOriIntStSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_ORI_INT_ST to value 0"]
        impl crate::Resettable for DmacOriIntStSpec {}
    }
    #[doc = "DMAC_EN_CHNS (rw) register accessor: Channel enable query register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_en_chns::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_en_chns::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_en_chns`] module"]
    #[doc(alias = "DMAC_EN_CHNS")]
    pub type DmacEnChns = crate::Reg<dmac_en_chns::DmacEnChnsSpec>;
    #[doc = "Channel enable query register"]
    pub mod dmac_en_chns {
        #[doc = "Register `DMAC_EN_CHNS` reader"]
        pub type R = crate::R<DmacEnChnsSpec>;
        #[doc = "Register `DMAC_EN_CHNS` writer"]
        pub type W = crate::W<DmacEnChnsSpec>;
        #[doc = "Field `en_chns` reader - Channel enable status: 0=disabled; 1=enabled"]
        pub type EnChnsR = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - Channel enable status: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn en_chns(&self) -> EnChnsR {
                EnChnsR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {}
        #[doc = "Channel enable query register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_en_chns::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_en_chns::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacEnChnsSpec;
        impl crate::RegisterSpec for DmacEnChnsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_en_chns::R`](R) reader structure"]
        impl crate::Readable for DmacEnChnsSpec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_en_chns::W`](W) writer structure"]
        impl crate::Writable for DmacEnChnsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_EN_CHNS to value 0"]
        impl crate::Resettable for DmacEnChnsSpec {}
    }
    #[doc = "DMAC_BURST_REQ (rw) register accessor: Burst software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_burst_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_burst_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_burst_req`] module"]
    #[doc(alias = "DMAC_BURST_REQ")]
    pub type DmacBurstReq = crate::Reg<dmac_burst_req::DmacBurstReqSpec>;
    #[doc = "Burst software request register"]
    pub mod dmac_burst_req {
        #[doc = "Register `DMAC_BURST_REQ` reader"]
        pub type R = crate::R<DmacBurstReqSpec>;
        #[doc = "Register `DMAC_BURST_REQ` writer"]
        pub type W = crate::W<DmacBurstReqSpec>;
        #[doc = "Field `last_burst_req` reader - Last burst request per peripheral"]
        pub type LastBurstReqR = crate::FieldReader<u16>;
        #[doc = "Field `last_burst_req` writer - Last burst request per peripheral"]
        pub type LastBurstReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `burst_req` reader - Burst request per peripheral"]
        pub type BurstReqR = crate::FieldReader<u16>;
        #[doc = "Field `burst_req` writer - Burst request per peripheral"]
        pub type BurstReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Last burst request per peripheral"]
            #[inline(always)]
            pub fn last_burst_req(&self) -> LastBurstReqR {
                LastBurstReqR::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - Burst request per peripheral"]
            #[inline(always)]
            pub fn burst_req(&self) -> BurstReqR {
                BurstReqR::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Last burst request per peripheral"]
            #[inline(always)]
            pub fn last_burst_req(&mut self) -> LastBurstReqW<'_, DmacBurstReqSpec> {
                LastBurstReqW::new(self, 0)
            }
            #[doc = "Bits 16:31 - Burst request per peripheral"]
            #[inline(always)]
            pub fn burst_req(&mut self) -> BurstReqW<'_, DmacBurstReqSpec> {
                BurstReqW::new(self, 16)
            }
        }
        #[doc = "Burst software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_burst_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_burst_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacBurstReqSpec;
        impl crate::RegisterSpec for DmacBurstReqSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_burst_req::R`](R) reader structure"]
        impl crate::Readable for DmacBurstReqSpec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_burst_req::W`](W) writer structure"]
        impl crate::Writable for DmacBurstReqSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_BURST_REQ to value 0"]
        impl crate::Resettable for DmacBurstReqSpec {}
    }
    #[doc = "DMAC_SINGLE_REQ (rw) register accessor: Single software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_single_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_single_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_single_req`] module"]
    #[doc(alias = "DMAC_SINGLE_REQ")]
    pub type DmacSingleReq = crate::Reg<dmac_single_req::DmacSingleReqSpec>;
    #[doc = "Single software request register"]
    pub mod dmac_single_req {
        #[doc = "Register `DMAC_SINGLE_REQ` reader"]
        pub type R = crate::R<DmacSingleReqSpec>;
        #[doc = "Register `DMAC_SINGLE_REQ` writer"]
        pub type W = crate::W<DmacSingleReqSpec>;
        #[doc = "Field `last_single_req` reader - Last single request per peripheral"]
        pub type LastSingleReqR = crate::FieldReader<u16>;
        #[doc = "Field `last_single_req` writer - Last single request per peripheral"]
        pub type LastSingleReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `single_req` reader - Single request per peripheral"]
        pub type SingleReqR = crate::FieldReader<u16>;
        #[doc = "Field `single_req` writer - Single request per peripheral"]
        pub type SingleReqW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Last single request per peripheral"]
            #[inline(always)]
            pub fn last_single_req(&self) -> LastSingleReqR {
                LastSingleReqR::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - Single request per peripheral"]
            #[inline(always)]
            pub fn single_req(&self) -> SingleReqR {
                SingleReqR::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Last single request per peripheral"]
            #[inline(always)]
            pub fn last_single_req(&mut self) -> LastSingleReqW<'_, DmacSingleReqSpec> {
                LastSingleReqW::new(self, 0)
            }
            #[doc = "Bits 16:31 - Single request per peripheral"]
            #[inline(always)]
            pub fn single_req(&mut self) -> SingleReqW<'_, DmacSingleReqSpec> {
                SingleReqW::new(self, 16)
            }
        }
        #[doc = "Single software request register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_single_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_single_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacSingleReqSpec;
        impl crate::RegisterSpec for DmacSingleReqSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_single_req::R`](R) reader structure"]
        impl crate::Readable for DmacSingleReqSpec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_single_req::W`](W) writer structure"]
        impl crate::Writable for DmacSingleReqSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_SINGLE_REQ to value 0"]
        impl crate::Resettable for DmacSingleReqSpec {}
    }
    #[doc = "DMAC_CONFIG (rw) register accessor: DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_config`] module"]
    #[doc(alias = "DMAC_CONFIG")]
    pub type DmacConfig = crate::Reg<dmac_config::DmacConfigSpec>;
    #[doc = "DMA configuration register"]
    pub mod dmac_config {
        #[doc = "Register `DMAC_CONFIG` reader"]
        pub type R = crate::R<DmacConfigSpec>;
        #[doc = "Register `DMAC_CONFIG` writer"]
        pub type W = crate::W<DmacConfigSpec>;
        #[doc = "Field `dmac_en` reader - DMAC enable: 0=disabled; 1=enabled"]
        pub type DmacEnR = crate::BitReader;
        #[doc = "Field `dmac_en` writer - DMAC enable: 0=disabled; 1=enabled"]
        pub type DmacEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_m1` reader - Master 1 endianness: 0=little; 1=big"]
        pub type DmacM1R = crate::BitReader;
        #[doc = "Field `dmac_m1` writer - Master 1 endianness: 0=little; 1=big"]
        pub type DmacM1W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_m2` reader - Master 2 endianness: 0=little; 1=big"]
        pub type DmacM2R = crate::BitReader;
        #[doc = "Field `dmac_m2` writer - Master 2 endianness: 0=little; 1=big"]
        pub type DmacM2W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - DMAC enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn dmac_en(&self) -> DmacEnR {
                DmacEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Master 1 endianness: 0=little; 1=big"]
            #[inline(always)]
            pub fn dmac_m1(&self) -> DmacM1R {
                DmacM1R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Master 2 endianness: 0=little; 1=big"]
            #[inline(always)]
            pub fn dmac_m2(&self) -> DmacM2R {
                DmacM2R::new(((self.bits >> 2) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - DMAC enable: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn dmac_en(&mut self) -> DmacEnW<'_, DmacConfigSpec> {
                DmacEnW::new(self, 0)
            }
            #[doc = "Bit 1 - Master 1 endianness: 0=little; 1=big"]
            #[inline(always)]
            pub fn dmac_m1(&mut self) -> DmacM1W<'_, DmacConfigSpec> {
                DmacM1W::new(self, 1)
            }
            #[doc = "Bit 2 - Master 2 endianness: 0=little; 1=big"]
            #[inline(always)]
            pub fn dmac_m2(&mut self) -> DmacM2W<'_, DmacConfigSpec> {
                DmacM2W::new(self, 2)
            }
        }
        #[doc = "DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacConfigSpec;
        impl crate::RegisterSpec for DmacConfigSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_config::R`](R) reader structure"]
        impl crate::Readable for DmacConfigSpec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_config::W`](W) writer structure"]
        impl crate::Writable for DmacConfigSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_CONFIG to value 0"]
        impl crate::Resettable for DmacConfigSpec {}
    }
    #[doc = "DMAC_SYNC (rw) register accessor: DMA sync register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_sync`] module"]
    #[doc(alias = "DMAC_SYNC")]
    pub type DmacSync = crate::Reg<dmac_sync::DmacSyncSpec>;
    #[doc = "DMA sync register"]
    pub mod dmac_sync {
        #[doc = "Register `DMAC_SYNC` reader"]
        pub type R = crate::R<DmacSyncSpec>;
        #[doc = "Register `DMAC_SYNC` writer"]
        pub type W = crate::W<DmacSyncSpec>;
        #[doc = "Field `damc_sync` reader - DMA request sync: 0=enable sync; 1=disable sync"]
        pub type DamcSyncR = crate::FieldReader<u16>;
        #[doc = "Field `damc_sync` writer - DMA request sync: 0=enable sync; 1=disable sync"]
        pub type DamcSyncW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - DMA request sync: 0=enable sync; 1=disable sync"]
            #[inline(always)]
            pub fn damc_sync(&self) -> DamcSyncR {
                DamcSyncR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - DMA request sync: 0=enable sync; 1=disable sync"]
            #[inline(always)]
            pub fn damc_sync(&mut self) -> DamcSyncW<'_, DmacSyncSpec> {
                DamcSyncW::new(self, 0)
            }
        }
        #[doc = "DMA sync register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacSyncSpec;
        impl crate::RegisterSpec for DmacSyncSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_sync::R`](R) reader structure"]
        impl crate::Readable for DmacSyncSpec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_sync::W`](W) writer structure"]
        impl crate::Writable for DmacSyncSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_SYNC to value 0"]
        impl crate::Resettable for DmacSyncSpec {}
    }
    #[doc = "DMAC_D_ADDR_ (rw) register accessor: Channel %s \\[dim=4\\] destination address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_d_addr_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_d_addr_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_d_addr_`] module"]
    #[doc(alias = "DMAC_D_ADDR_")]
    pub type DmacDAddr_ = crate::Reg<dmac_d_addr_::DmacDAddr_Spec>;
    #[doc = "Channel %s \\[dim=4\\] destination address"]
    pub mod dmac_d_addr_ {
        #[doc = "Register `DMAC_D_ADDR_%s` reader"]
        pub type R = crate::R<DmacDAddr_Spec>;
        #[doc = "Register `DMAC_D_ADDR_%s` writer"]
        pub type W = crate::W<DmacDAddr_Spec>;
        #[doc = "Field `dmac_d_addr_0` reader - Channel 0 destination address"]
        pub type DmacDAddr0R = crate::FieldReader<u32>;
        #[doc = "Field `dmac_d_addr_0` writer - Channel 0 destination address"]
        pub type DmacDAddr0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Channel 0 destination address"]
            #[inline(always)]
            pub fn dmac_d_addr_0(&self) -> DmacDAddr0R {
                DmacDAddr0R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Channel 0 destination address"]
            #[inline(always)]
            pub fn dmac_d_addr_0(&mut self) -> DmacDAddr0W<'_, DmacDAddr_Spec> {
                DmacDAddr0W::new(self, 0)
            }
        }
        #[doc = "Channel %s \\[dim=4\\] destination address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_d_addr_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_d_addr_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacDAddr_Spec;
        impl crate::RegisterSpec for DmacDAddr_Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_d_addr_::R`](R) reader structure"]
        impl crate::Readable for DmacDAddr_Spec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_d_addr_::W`](W) writer structure"]
        impl crate::Writable for DmacDAddr_Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_D_ADDR_%s to value 0"]
        impl crate::Resettable for DmacDAddr_Spec {}
    }
    #[doc = "DMAC_LLI_ (rw) register accessor: Channel %s \\[dim=4\\] linked list register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_lli_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_lli_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_lli_`] module"]
    #[doc(alias = "DMAC_LLI_")]
    pub type DmacLli_ = crate::Reg<dmac_lli_::DmacLli_Spec>;
    #[doc = "Channel %s \\[dim=4\\] linked list register"]
    pub mod dmac_lli_ {
        #[doc = "Register `DMAC_LLI_%s` reader"]
        pub type R = crate::R<DmacLli_Spec>;
        #[doc = "Register `DMAC_LLI_%s` writer"]
        pub type W = crate::W<DmacLli_Spec>;
        #[doc = "Field `dmac_lm_0` reader - Master for next LLI node: 0=Master1; 1=Master2"]
        pub type DmacLm0R = crate::BitReader;
        #[doc = "Field `dmac_lm_0` writer - Master for next LLI node: 0=Master1; 1=Master2"]
        pub type DmacLm0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_lli_0` reader - Linked list address \\[31:2\\]"]
        pub type DmacLli0R = crate::FieldReader<u32>;
        #[doc = "Field `dmac_lli_0` writer - Linked list address \\[31:2\\]"]
        pub type DmacLli0W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
        impl R {
            #[doc = "Bit 0 - Master for next LLI node: 0=Master1; 1=Master2"]
            #[inline(always)]
            pub fn dmac_lm_0(&self) -> DmacLm0R {
                DmacLm0R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 2:31 - Linked list address \\[31:2\\]"]
            #[inline(always)]
            pub fn dmac_lli_0(&self) -> DmacLli0R {
                DmacLli0R::new((self.bits >> 2) & 0x3fff_ffff)
            }
        }
        impl W {
            #[doc = "Bit 0 - Master for next LLI node: 0=Master1; 1=Master2"]
            #[inline(always)]
            pub fn dmac_lm_0(&mut self) -> DmacLm0W<'_, DmacLli_Spec> {
                DmacLm0W::new(self, 0)
            }
            #[doc = "Bits 2:31 - Linked list address \\[31:2\\]"]
            #[inline(always)]
            pub fn dmac_lli_0(&mut self) -> DmacLli0W<'_, DmacLli_Spec> {
                DmacLli0W::new(self, 2)
            }
        }
        #[doc = "Channel %s \\[dim=4\\] linked list register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_lli_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_lli_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacLli_Spec;
        impl crate::RegisterSpec for DmacLli_Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_lli_::R`](R) reader structure"]
        impl crate::Readable for DmacLli_Spec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_lli_::W`](W) writer structure"]
        impl crate::Writable for DmacLli_Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_LLI_%s to value 0"]
        impl crate::Resettable for DmacLli_Spec {}
    }
    #[doc = "DMAC_S_ADDR_ (rw) register accessor: Channel %s \\[dim=4\\] source address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_s_addr_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_s_addr_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_s_addr_`] module"]
    #[doc(alias = "DMAC_S_ADDR_")]
    pub type DmacSAddr_ = crate::Reg<dmac_s_addr_::DmacSAddr_Spec>;
    #[doc = "Channel %s \\[dim=4\\] source address"]
    pub mod dmac_s_addr_ {
        #[doc = "Register `DMAC_S_ADDR_%s` reader"]
        pub type R = crate::R<DmacSAddr_Spec>;
        #[doc = "Register `DMAC_S_ADDR_%s` writer"]
        pub type W = crate::W<DmacSAddr_Spec>;
        #[doc = "Field `dmac_s_addr_0` reader - Channel 0 source address"]
        pub type DmacSAddr0R = crate::FieldReader<u32>;
        #[doc = "Field `dmac_s_addr_0` writer - Channel 0 source address"]
        pub type DmacSAddr0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Channel 0 source address"]
            #[inline(always)]
            pub fn dmac_s_addr_0(&self) -> DmacSAddr0R {
                DmacSAddr0R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Channel 0 source address"]
            #[inline(always)]
            pub fn dmac_s_addr_0(&mut self) -> DmacSAddr0W<'_, DmacSAddr_Spec> {
                DmacSAddr0W::new(self, 0)
            }
        }
        #[doc = "Channel %s \\[dim=4\\] source address\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_s_addr_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_s_addr_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacSAddr_Spec;
        impl crate::RegisterSpec for DmacSAddr_Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_s_addr_::R`](R) reader structure"]
        impl crate::Readable for DmacSAddr_Spec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_s_addr_::W`](W) writer structure"]
        impl crate::Writable for DmacSAddr_Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_S_ADDR_%s to value 0"]
        impl crate::Resettable for DmacSAddr_Spec {}
    }
    #[doc = "DMAC_CHN_CONTROL_ (rw) register accessor: Channel %s \\[dim=4\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_control_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_control_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_chn_control_`] module"]
    #[doc(alias = "DMAC_CHN_CONTROL_")]
    pub type DmacChnControl_ = crate::Reg<dmac_chn_control_::DmacChnControl_Spec>;
    #[doc = "Channel %s \\[dim=4\\] control register"]
    pub mod dmac_chn_control_ {
        #[doc = "Register `DMAC_CHN_CONTROL_%s` reader"]
        pub type R = crate::R<DmacChnControl_Spec>;
        #[doc = "Register `DMAC_CHN_CONTROL_%s` writer"]
        pub type W = crate::W<DmacChnControl_Spec>;
        #[doc = "Field `dmac_trans_size_0` reader - Transfer size"]
        pub type DmacTransSize0R = crate::FieldReader<u16>;
        #[doc = "Field `dmac_trans_size_0` writer - Transfer size"]
        pub type DmacTransSize0W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum DmacSBsize0 {
            #[doc = "0: Burst size 1"]
            Bs1 = 0,
            #[doc = "1: Burst size 4"]
            Bs4 = 1,
            #[doc = "2: Burst size 8"]
            Bs8 = 2,
            #[doc = "3: Burst size 16"]
            Bs16 = 3,
            #[doc = "4: Burst size 32"]
            Bs32 = 4,
            #[doc = "5: Burst size 64"]
            Bs64 = 5,
            #[doc = "6: Burst size 128"]
            Bs128 = 6,
            #[doc = "7: Burst size 256"]
            Bs256 = 7,
        }
        impl From<DmacSBsize0> for u8 {
            #[inline(always)]
            fn from(variant: DmacSBsize0) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for DmacSBsize0 {
            type Ux = u8;
        }
        impl crate::IsEnum for DmacSBsize0 {}
        #[doc = "Field `dmac_s_bsize_0` reader - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
        pub type DmacSBsize0R = crate::FieldReader<DmacSBsize0>;
        impl DmacSBsize0R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> DmacSBsize0 {
                match self.bits {
                    0 => DmacSBsize0::Bs1,
                    1 => DmacSBsize0::Bs4,
                    2 => DmacSBsize0::Bs8,
                    3 => DmacSBsize0::Bs16,
                    4 => DmacSBsize0::Bs32,
                    5 => DmacSBsize0::Bs64,
                    6 => DmacSBsize0::Bs128,
                    7 => DmacSBsize0::Bs256,
                    _ => unreachable!(),
                }
            }
            #[doc = "Burst size 1"]
            #[inline(always)]
            pub fn is_bs1(&self) -> bool {
                *self == DmacSBsize0::Bs1
            }
            #[doc = "Burst size 4"]
            #[inline(always)]
            pub fn is_bs4(&self) -> bool {
                *self == DmacSBsize0::Bs4
            }
            #[doc = "Burst size 8"]
            #[inline(always)]
            pub fn is_bs8(&self) -> bool {
                *self == DmacSBsize0::Bs8
            }
            #[doc = "Burst size 16"]
            #[inline(always)]
            pub fn is_bs16(&self) -> bool {
                *self == DmacSBsize0::Bs16
            }
            #[doc = "Burst size 32"]
            #[inline(always)]
            pub fn is_bs32(&self) -> bool {
                *self == DmacSBsize0::Bs32
            }
            #[doc = "Burst size 64"]
            #[inline(always)]
            pub fn is_bs64(&self) -> bool {
                *self == DmacSBsize0::Bs64
            }
            #[doc = "Burst size 128"]
            #[inline(always)]
            pub fn is_bs128(&self) -> bool {
                *self == DmacSBsize0::Bs128
            }
            #[doc = "Burst size 256"]
            #[inline(always)]
            pub fn is_bs256(&self) -> bool {
                *self == DmacSBsize0::Bs256
            }
        }
        #[doc = "Field `dmac_s_bsize_0` writer - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
        pub type DmacSBsize0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacSBsize0, crate::Safe>;
        impl<'a, REG> DmacSBsize0W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "Burst size 1"]
            #[inline(always)]
            pub fn bs1(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSBsize0::Bs1)
            }
            #[doc = "Burst size 4"]
            #[inline(always)]
            pub fn bs4(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSBsize0::Bs4)
            }
            #[doc = "Burst size 8"]
            #[inline(always)]
            pub fn bs8(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSBsize0::Bs8)
            }
            #[doc = "Burst size 16"]
            #[inline(always)]
            pub fn bs16(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSBsize0::Bs16)
            }
            #[doc = "Burst size 32"]
            #[inline(always)]
            pub fn bs32(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSBsize0::Bs32)
            }
            #[doc = "Burst size 64"]
            #[inline(always)]
            pub fn bs64(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSBsize0::Bs64)
            }
            #[doc = "Burst size 128"]
            #[inline(always)]
            pub fn bs128(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSBsize0::Bs128)
            }
            #[doc = "Burst size 256"]
            #[inline(always)]
            pub fn bs256(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSBsize0::Bs256)
            }
        }
        #[doc = "Field `dmac_d_bsize_0` reader - Destination burst size"]
        pub type DmacDBsize0R = crate::FieldReader;
        #[doc = "Field `dmac_d_bsize_0` writer - Destination burst size"]
        pub type DmacDBsize0W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Source width: 000=8bit; 001=16bit; 010=32bit\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum DmacSWidth0 {
            #[doc = "0: 8-bit"]
            Byte = 0,
            #[doc = "1: 16-bit"]
            Halfword = 1,
            #[doc = "2: 32-bit"]
            Word = 2,
        }
        impl From<DmacSWidth0> for u8 {
            #[inline(always)]
            fn from(variant: DmacSWidth0) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for DmacSWidth0 {
            type Ux = u8;
        }
        impl crate::IsEnum for DmacSWidth0 {}
        #[doc = "Field `dmac_s_width_0` reader - Source width: 000=8bit; 001=16bit; 010=32bit"]
        pub type DmacSWidth0R = crate::FieldReader<DmacSWidth0>;
        impl DmacSWidth0R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Option<DmacSWidth0> {
                match self.bits {
                    0 => Some(DmacSWidth0::Byte),
                    1 => Some(DmacSWidth0::Halfword),
                    2 => Some(DmacSWidth0::Word),
                    _ => None,
                }
            }
            #[doc = "8-bit"]
            #[inline(always)]
            pub fn is_byte(&self) -> bool {
                *self == DmacSWidth0::Byte
            }
            #[doc = "16-bit"]
            #[inline(always)]
            pub fn is_halfword(&self) -> bool {
                *self == DmacSWidth0::Halfword
            }
            #[doc = "32-bit"]
            #[inline(always)]
            pub fn is_word(&self) -> bool {
                *self == DmacSWidth0::Word
            }
        }
        #[doc = "Field `dmac_s_width_0` writer - Source width: 000=8bit; 001=16bit; 010=32bit"]
        pub type DmacSWidth0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacSWidth0>;
        impl<'a, REG> DmacSWidth0W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "8-bit"]
            #[inline(always)]
            pub fn byte(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSWidth0::Byte)
            }
            #[doc = "16-bit"]
            #[inline(always)]
            pub fn halfword(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSWidth0::Halfword)
            }
            #[doc = "32-bit"]
            #[inline(always)]
            pub fn word(self) -> &'a mut crate::W<REG> {
                self.variant(DmacSWidth0::Word)
            }
        }
        #[doc = "Destination width\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum DmacDWidth0 {
            #[doc = "0: 8-bit"]
            Byte = 0,
            #[doc = "1: 16-bit"]
            Halfword = 1,
            #[doc = "2: 32-bit"]
            Word = 2,
        }
        impl From<DmacDWidth0> for u8 {
            #[inline(always)]
            fn from(variant: DmacDWidth0) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for DmacDWidth0 {
            type Ux = u8;
        }
        impl crate::IsEnum for DmacDWidth0 {}
        #[doc = "Field `dmac_d_width_0` reader - Destination width"]
        pub type DmacDWidth0R = crate::FieldReader<DmacDWidth0>;
        impl DmacDWidth0R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> Option<DmacDWidth0> {
                match self.bits {
                    0 => Some(DmacDWidth0::Byte),
                    1 => Some(DmacDWidth0::Halfword),
                    2 => Some(DmacDWidth0::Word),
                    _ => None,
                }
            }
            #[doc = "8-bit"]
            #[inline(always)]
            pub fn is_byte(&self) -> bool {
                *self == DmacDWidth0::Byte
            }
            #[doc = "16-bit"]
            #[inline(always)]
            pub fn is_halfword(&self) -> bool {
                *self == DmacDWidth0::Halfword
            }
            #[doc = "32-bit"]
            #[inline(always)]
            pub fn is_word(&self) -> bool {
                *self == DmacDWidth0::Word
            }
        }
        #[doc = "Field `dmac_d_width_0` writer - Destination width"]
        pub type DmacDWidth0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacDWidth0>;
        impl<'a, REG> DmacDWidth0W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "8-bit"]
            #[inline(always)]
            pub fn byte(self) -> &'a mut crate::W<REG> {
                self.variant(DmacDWidth0::Byte)
            }
            #[doc = "16-bit"]
            #[inline(always)]
            pub fn halfword(self) -> &'a mut crate::W<REG> {
                self.variant(DmacDWidth0::Halfword)
            }
            #[doc = "32-bit"]
            #[inline(always)]
            pub fn word(self) -> &'a mut crate::W<REG> {
                self.variant(DmacDWidth0::Word)
            }
        }
        #[doc = "Field `dmac_s_master_0` reader - Source master: 0=Master1; 1=Master2"]
        pub type DmacSMaster0R = crate::BitReader;
        #[doc = "Field `dmac_s_master_0` writer - Source master: 0=Master1; 1=Master2"]
        pub type DmacSMaster0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_d_master_0` reader - Destination master"]
        pub type DmacDMaster0R = crate::BitReader;
        #[doc = "Field `dmac_d_master_0` writer - Destination master"]
        pub type DmacDMaster0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_s_inc_0` reader - Source address increment: 0=no; 1=yes"]
        pub type DmacSInc0R = crate::BitReader;
        #[doc = "Field `dmac_s_inc_0` writer - Source address increment: 0=no; 1=yes"]
        pub type DmacSInc0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_d_inc_0` reader - Destination address increment"]
        pub type DmacDInc0R = crate::BitReader;
        #[doc = "Field `dmac_d_inc_0` writer - Destination address increment"]
        pub type DmacDInc0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_prot_0` reader - Protection HPROT\\[2:0\\]"]
        pub type DmacProt0R = crate::FieldReader;
        #[doc = "Field `dmac_prot_0` writer - Protection HPROT\\[2:0\\]"]
        pub type DmacProt0W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `dmac_trans_int_0` reader - Transfer complete interrupt enable"]
        pub type DmacTransInt0R = crate::BitReader;
        #[doc = "Field `dmac_trans_int_0` writer - Transfer complete interrupt enable"]
        pub type DmacTransInt0W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:11 - Transfer size"]
            #[inline(always)]
            pub fn dmac_trans_size_0(&self) -> DmacTransSize0R {
                DmacTransSize0R::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bits 12:14 - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
            #[inline(always)]
            pub fn dmac_s_bsize_0(&self) -> DmacSBsize0R {
                DmacSBsize0R::new(((self.bits >> 12) & 7) as u8)
            }
            #[doc = "Bits 15:17 - Destination burst size"]
            #[inline(always)]
            pub fn dmac_d_bsize_0(&self) -> DmacDBsize0R {
                DmacDBsize0R::new(((self.bits >> 15) & 7) as u8)
            }
            #[doc = "Bits 18:20 - Source width: 000=8bit; 001=16bit; 010=32bit"]
            #[inline(always)]
            pub fn dmac_s_width_0(&self) -> DmacSWidth0R {
                DmacSWidth0R::new(((self.bits >> 18) & 7) as u8)
            }
            #[doc = "Bits 21:23 - Destination width"]
            #[inline(always)]
            pub fn dmac_d_width_0(&self) -> DmacDWidth0R {
                DmacDWidth0R::new(((self.bits >> 21) & 7) as u8)
            }
            #[doc = "Bit 24 - Source master: 0=Master1; 1=Master2"]
            #[inline(always)]
            pub fn dmac_s_master_0(&self) -> DmacSMaster0R {
                DmacSMaster0R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - Destination master"]
            #[inline(always)]
            pub fn dmac_d_master_0(&self) -> DmacDMaster0R {
                DmacDMaster0R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - Source address increment: 0=no; 1=yes"]
            #[inline(always)]
            pub fn dmac_s_inc_0(&self) -> DmacSInc0R {
                DmacSInc0R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - Destination address increment"]
            #[inline(always)]
            pub fn dmac_d_inc_0(&self) -> DmacDInc0R {
                DmacDInc0R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bits 28:30 - Protection HPROT\\[2:0\\]"]
            #[inline(always)]
            pub fn dmac_prot_0(&self) -> DmacProt0R {
                DmacProt0R::new(((self.bits >> 28) & 7) as u8)
            }
            #[doc = "Bit 31 - Transfer complete interrupt enable"]
            #[inline(always)]
            pub fn dmac_trans_int_0(&self) -> DmacTransInt0R {
                DmacTransInt0R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - Transfer size"]
            #[inline(always)]
            pub fn dmac_trans_size_0(&mut self) -> DmacTransSize0W<'_, DmacChnControl_Spec> {
                DmacTransSize0W::new(self, 0)
            }
            #[doc = "Bits 12:14 - Source burst size: 000=1; 001=4; 010=8; 011=16; 100=32; 101=64; 110=128; 111=256"]
            #[inline(always)]
            pub fn dmac_s_bsize_0(&mut self) -> DmacSBsize0W<'_, DmacChnControl_Spec> {
                DmacSBsize0W::new(self, 12)
            }
            #[doc = "Bits 15:17 - Destination burst size"]
            #[inline(always)]
            pub fn dmac_d_bsize_0(&mut self) -> DmacDBsize0W<'_, DmacChnControl_Spec> {
                DmacDBsize0W::new(self, 15)
            }
            #[doc = "Bits 18:20 - Source width: 000=8bit; 001=16bit; 010=32bit"]
            #[inline(always)]
            pub fn dmac_s_width_0(&mut self) -> DmacSWidth0W<'_, DmacChnControl_Spec> {
                DmacSWidth0W::new(self, 18)
            }
            #[doc = "Bits 21:23 - Destination width"]
            #[inline(always)]
            pub fn dmac_d_width_0(&mut self) -> DmacDWidth0W<'_, DmacChnControl_Spec> {
                DmacDWidth0W::new(self, 21)
            }
            #[doc = "Bit 24 - Source master: 0=Master1; 1=Master2"]
            #[inline(always)]
            pub fn dmac_s_master_0(&mut self) -> DmacSMaster0W<'_, DmacChnControl_Spec> {
                DmacSMaster0W::new(self, 24)
            }
            #[doc = "Bit 25 - Destination master"]
            #[inline(always)]
            pub fn dmac_d_master_0(&mut self) -> DmacDMaster0W<'_, DmacChnControl_Spec> {
                DmacDMaster0W::new(self, 25)
            }
            #[doc = "Bit 26 - Source address increment: 0=no; 1=yes"]
            #[inline(always)]
            pub fn dmac_s_inc_0(&mut self) -> DmacSInc0W<'_, DmacChnControl_Spec> {
                DmacSInc0W::new(self, 26)
            }
            #[doc = "Bit 27 - Destination address increment"]
            #[inline(always)]
            pub fn dmac_d_inc_0(&mut self) -> DmacDInc0W<'_, DmacChnControl_Spec> {
                DmacDInc0W::new(self, 27)
            }
            #[doc = "Bits 28:30 - Protection HPROT\\[2:0\\]"]
            #[inline(always)]
            pub fn dmac_prot_0(&mut self) -> DmacProt0W<'_, DmacChnControl_Spec> {
                DmacProt0W::new(self, 28)
            }
            #[doc = "Bit 31 - Transfer complete interrupt enable"]
            #[inline(always)]
            pub fn dmac_trans_int_0(&mut self) -> DmacTransInt0W<'_, DmacChnControl_Spec> {
                DmacTransInt0W::new(self, 31)
            }
        }
        #[doc = "Channel %s \\[dim=4\\] control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_control_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_control_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacChnControl_Spec;
        impl crate::RegisterSpec for DmacChnControl_Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_chn_control_::R`](R) reader structure"]
        impl crate::Readable for DmacChnControl_Spec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_chn_control_::W`](W) writer structure"]
        impl crate::Writable for DmacChnControl_Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_CHN_CONTROL_%s to value 0"]
        impl crate::Resettable for DmacChnControl_Spec {}
    }
    #[doc = "DMAC_CHN_CONFIG_ (rw) register accessor: Channel %s \\[dim=4\\] configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_config_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_config_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_chn_config_`] module"]
    #[doc(alias = "DMAC_CHN_CONFIG_")]
    pub type DmacChnConfig_ = crate::Reg<dmac_chn_config_::DmacChnConfig_Spec>;
    #[doc = "Channel %s \\[dim=4\\] configuration register"]
    pub mod dmac_chn_config_ {
        #[doc = "Register `DMAC_CHN_CONFIG_%s` reader"]
        pub type R = crate::R<DmacChnConfig_Spec>;
        #[doc = "Register `DMAC_CHN_CONFIG_%s` writer"]
        pub type W = crate::W<DmacChnConfig_Spec>;
        #[doc = "Field `dmac_chn_en_0` reader - Channel enable: 0=disable; 1=enable"]
        pub type DmacChnEn0R = crate::BitReader;
        #[doc = "Field `dmac_chn_en_0` writer - Channel enable: 0=disable; 1=enable"]
        pub type DmacChnEn0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_s_peripheral_0` reader - Source peripheral select"]
        pub type DmacSPeripheral0R = crate::FieldReader;
        #[doc = "Field `dmac_s_peripheral_0` writer - Source peripheral select"]
        pub type DmacSPeripheral0W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `dmac_d_peripheral_0` reader - Destination peripheral select"]
        pub type DmacDPeripheral0R = crate::FieldReader;
        #[doc = "Field `dmac_d_peripheral_0` writer - Destination peripheral select"]
        pub type DmacDPeripheral0W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)\n\nValue on reset: 0"]
        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
        #[repr(u8)]
        pub enum DmacFlowCtl0 {
            #[doc = "0: Memory to Memory, DMAC flow control"]
            Mem2memDmac = 0,
            #[doc = "1: Memory to Peripheral, DMAC flow control"]
            Mem2perDmac = 1,
            #[doc = "2: Peripheral to Memory, DMAC flow control"]
            Per2memDmac = 2,
            #[doc = "3: Peripheral to Peripheral, DMAC flow control"]
            Per2perDmac = 3,
            #[doc = "4: Peripheral to Peripheral, Destination flow control"]
            Per2perDst = 4,
            #[doc = "5: Memory to Peripheral, Destination flow control"]
            Mem2perDst = 5,
            #[doc = "6: Peripheral to Memory, Source flow control"]
            Per2memSrc = 6,
            #[doc = "7: Peripheral to Peripheral, Source flow control"]
            Per2perSrc = 7,
        }
        impl From<DmacFlowCtl0> for u8 {
            #[inline(always)]
            fn from(variant: DmacFlowCtl0) -> Self {
                variant as _
            }
        }
        impl crate::FieldSpec for DmacFlowCtl0 {
            type Ux = u8;
        }
        impl crate::IsEnum for DmacFlowCtl0 {}
        #[doc = "Field `dmac_flow_ctl_0` reader - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
        pub type DmacFlowCtl0R = crate::FieldReader<DmacFlowCtl0>;
        impl DmacFlowCtl0R {
            #[doc = "Get enumerated values variant"]
            #[inline(always)]
            pub const fn variant(&self) -> DmacFlowCtl0 {
                match self.bits {
                    0 => DmacFlowCtl0::Mem2memDmac,
                    1 => DmacFlowCtl0::Mem2perDmac,
                    2 => DmacFlowCtl0::Per2memDmac,
                    3 => DmacFlowCtl0::Per2perDmac,
                    4 => DmacFlowCtl0::Per2perDst,
                    5 => DmacFlowCtl0::Mem2perDst,
                    6 => DmacFlowCtl0::Per2memSrc,
                    7 => DmacFlowCtl0::Per2perSrc,
                    _ => unreachable!(),
                }
            }
            #[doc = "Memory to Memory, DMAC flow control"]
            #[inline(always)]
            pub fn is_mem2mem_dmac(&self) -> bool {
                *self == DmacFlowCtl0::Mem2memDmac
            }
            #[doc = "Memory to Peripheral, DMAC flow control"]
            #[inline(always)]
            pub fn is_mem2per_dmac(&self) -> bool {
                *self == DmacFlowCtl0::Mem2perDmac
            }
            #[doc = "Peripheral to Memory, DMAC flow control"]
            #[inline(always)]
            pub fn is_per2mem_dmac(&self) -> bool {
                *self == DmacFlowCtl0::Per2memDmac
            }
            #[doc = "Peripheral to Peripheral, DMAC flow control"]
            #[inline(always)]
            pub fn is_per2per_dmac(&self) -> bool {
                *self == DmacFlowCtl0::Per2perDmac
            }
            #[doc = "Peripheral to Peripheral, Destination flow control"]
            #[inline(always)]
            pub fn is_per2per_dst(&self) -> bool {
                *self == DmacFlowCtl0::Per2perDst
            }
            #[doc = "Memory to Peripheral, Destination flow control"]
            #[inline(always)]
            pub fn is_mem2per_dst(&self) -> bool {
                *self == DmacFlowCtl0::Mem2perDst
            }
            #[doc = "Peripheral to Memory, Source flow control"]
            #[inline(always)]
            pub fn is_per2mem_src(&self) -> bool {
                *self == DmacFlowCtl0::Per2memSrc
            }
            #[doc = "Peripheral to Peripheral, Source flow control"]
            #[inline(always)]
            pub fn is_per2per_src(&self) -> bool {
                *self == DmacFlowCtl0::Per2perSrc
            }
        }
        #[doc = "Field `dmac_flow_ctl_0` writer - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
        pub type DmacFlowCtl0W<'a, REG> = crate::FieldWriter<'a, REG, 3, DmacFlowCtl0, crate::Safe>;
        impl<'a, REG> DmacFlowCtl0W<'a, REG>
        where
            REG: crate::Writable + crate::RegisterSpec,
            REG::Ux: From<u8>,
        {
            #[doc = "Memory to Memory, DMAC flow control"]
            #[inline(always)]
            pub fn mem2mem_dmac(self) -> &'a mut crate::W<REG> {
                self.variant(DmacFlowCtl0::Mem2memDmac)
            }
            #[doc = "Memory to Peripheral, DMAC flow control"]
            #[inline(always)]
            pub fn mem2per_dmac(self) -> &'a mut crate::W<REG> {
                self.variant(DmacFlowCtl0::Mem2perDmac)
            }
            #[doc = "Peripheral to Memory, DMAC flow control"]
            #[inline(always)]
            pub fn per2mem_dmac(self) -> &'a mut crate::W<REG> {
                self.variant(DmacFlowCtl0::Per2memDmac)
            }
            #[doc = "Peripheral to Peripheral, DMAC flow control"]
            #[inline(always)]
            pub fn per2per_dmac(self) -> &'a mut crate::W<REG> {
                self.variant(DmacFlowCtl0::Per2perDmac)
            }
            #[doc = "Peripheral to Peripheral, Destination flow control"]
            #[inline(always)]
            pub fn per2per_dst(self) -> &'a mut crate::W<REG> {
                self.variant(DmacFlowCtl0::Per2perDst)
            }
            #[doc = "Memory to Peripheral, Destination flow control"]
            #[inline(always)]
            pub fn mem2per_dst(self) -> &'a mut crate::W<REG> {
                self.variant(DmacFlowCtl0::Mem2perDst)
            }
            #[doc = "Peripheral to Memory, Source flow control"]
            #[inline(always)]
            pub fn per2mem_src(self) -> &'a mut crate::W<REG> {
                self.variant(DmacFlowCtl0::Per2memSrc)
            }
            #[doc = "Peripheral to Peripheral, Source flow control"]
            #[inline(always)]
            pub fn per2per_src(self) -> &'a mut crate::W<REG> {
                self.variant(DmacFlowCtl0::Per2perSrc)
            }
        }
        #[doc = "Field `dmac_int_en_0` reader - Error interrupt mask: 0=masked; 1=unmasked"]
        pub type DmacIntEn0R = crate::BitReader;
        #[doc = "Field `dmac_int_en_0` writer - Error interrupt mask: 0=masked; 1=unmasked"]
        pub type DmacIntEn0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_int_tc_0` reader - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
        pub type DmacIntTc0R = crate::BitReader;
        #[doc = "Field `dmac_int_tc_0` writer - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
        pub type DmacIntTc0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_lock_0` reader - Bus lock: 0=disabled; 1=enabled"]
        pub type DmacLock0R = crate::BitReader;
        #[doc = "Field `dmac_lock_0` writer - Bus lock: 0=disabled; 1=enabled"]
        pub type DmacLock0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmac_active_0` reader - FIFO has data: 0=no; 1=yes"]
        pub type DmacActive0R = crate::BitReader;
        #[doc = "Field `dmac_halt_0` reader - Halt: 0=allow DMA; 1=ignore DMA requests"]
        pub type DmacHalt0R = crate::BitReader;
        #[doc = "Field `dmac_halt_0` writer - Halt: 0=allow DMA; 1=ignore DMA requests"]
        pub type DmacHalt0W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Channel enable: 0=disable; 1=enable"]
            #[inline(always)]
            pub fn dmac_chn_en_0(&self) -> DmacChnEn0R {
                DmacChnEn0R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 1:4 - Source peripheral select"]
            #[inline(always)]
            pub fn dmac_s_peripheral_0(&self) -> DmacSPeripheral0R {
                DmacSPeripheral0R::new(((self.bits >> 1) & 0x0f) as u8)
            }
            #[doc = "Bits 5:8 - Destination peripheral select"]
            #[inline(always)]
            pub fn dmac_d_peripheral_0(&self) -> DmacDPeripheral0R {
                DmacDPeripheral0R::new(((self.bits >> 5) & 0x0f) as u8)
            }
            #[doc = "Bits 9:11 - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
            #[inline(always)]
            pub fn dmac_flow_ctl_0(&self) -> DmacFlowCtl0R {
                DmacFlowCtl0R::new(((self.bits >> 9) & 7) as u8)
            }
            #[doc = "Bit 12 - Error interrupt mask: 0=masked; 1=unmasked"]
            #[inline(always)]
            pub fn dmac_int_en_0(&self) -> DmacIntEn0R {
                DmacIntEn0R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
            #[inline(always)]
            pub fn dmac_int_tc_0(&self) -> DmacIntTc0R {
                DmacIntTc0R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - Bus lock: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn dmac_lock_0(&self) -> DmacLock0R {
                DmacLock0R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - FIFO has data: 0=no; 1=yes"]
            #[inline(always)]
            pub fn dmac_active_0(&self) -> DmacActive0R {
                DmacActive0R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - Halt: 0=allow DMA; 1=ignore DMA requests"]
            #[inline(always)]
            pub fn dmac_halt_0(&self) -> DmacHalt0R {
                DmacHalt0R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Channel enable: 0=disable; 1=enable"]
            #[inline(always)]
            pub fn dmac_chn_en_0(&mut self) -> DmacChnEn0W<'_, DmacChnConfig_Spec> {
                DmacChnEn0W::new(self, 0)
            }
            #[doc = "Bits 1:4 - Source peripheral select"]
            #[inline(always)]
            pub fn dmac_s_peripheral_0(&mut self) -> DmacSPeripheral0W<'_, DmacChnConfig_Spec> {
                DmacSPeripheral0W::new(self, 1)
            }
            #[doc = "Bits 5:8 - Destination peripheral select"]
            #[inline(always)]
            pub fn dmac_d_peripheral_0(&mut self) -> DmacDPeripheral0W<'_, DmacChnConfig_Spec> {
                DmacDPeripheral0W::new(self, 5)
            }
            #[doc = "Bits 9:11 - Flow control: 000=mem2mem; 001=mem2per; 010=per2mem; 011=per2per(DMAC); 100=per2per(dst); 101=mem2per(dst); 110=per2mem(src); 111=per2per(src)"]
            #[inline(always)]
            pub fn dmac_flow_ctl_0(&mut self) -> DmacFlowCtl0W<'_, DmacChnConfig_Spec> {
                DmacFlowCtl0W::new(self, 9)
            }
            #[doc = "Bit 12 - Error interrupt mask: 0=masked; 1=unmasked"]
            #[inline(always)]
            pub fn dmac_int_en_0(&mut self) -> DmacIntEn0W<'_, DmacChnConfig_Spec> {
                DmacIntEn0W::new(self, 12)
            }
            #[doc = "Bit 13 - Transfer complete interrupt mask: 0=masked; 1=unmasked"]
            #[inline(always)]
            pub fn dmac_int_tc_0(&mut self) -> DmacIntTc0W<'_, DmacChnConfig_Spec> {
                DmacIntTc0W::new(self, 13)
            }
            #[doc = "Bit 14 - Bus lock: 0=disabled; 1=enabled"]
            #[inline(always)]
            pub fn dmac_lock_0(&mut self) -> DmacLock0W<'_, DmacChnConfig_Spec> {
                DmacLock0W::new(self, 14)
            }
            #[doc = "Bit 16 - Halt: 0=allow DMA; 1=ignore DMA requests"]
            #[inline(always)]
            pub fn dmac_halt_0(&mut self) -> DmacHalt0W<'_, DmacChnConfig_Spec> {
                DmacHalt0W::new(self, 16)
            }
        }
        #[doc = "Channel %s \\[dim=4\\] configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_chn_config_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_chn_config_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DmacChnConfig_Spec;
        impl crate::RegisterSpec for DmacChnConfig_Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmac_chn_config_::R`](R) reader structure"]
        impl crate::Readable for DmacChnConfig_Spec {}
        #[doc = "`write(|w| ..)` method takes [`dmac_chn_config_::W`](W) writer structure"]
        impl crate::Writable for DmacChnConfig_Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DMAC_CHN_CONFIG_%s to value 0"]
        impl crate::Resettable for DmacChnConfig_Spec {}
    }
}
#[doc = "RTC instance 0 (rtc_unified IP v150)"]
pub type Rtc = crate::Periph<rtc::RegisterBlock, 0x5702_4100>;
impl core::fmt::Debug for Rtc {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Rtc").finish()
    }
}
#[doc = "RTC instance 0 (rtc_unified IP v150)"]
pub mod rtc {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        load_count0: LoadCount0,
        load_count1: LoadCount1,
        current_value0: CurrentValue0,
        current_value1: CurrentValue1,
        control: Control,
        eoi_ren: EoiRen,
        raw_intr: RawIntr,
        intr: Intr,
    }
    impl RegisterBlock {
        #[doc = "0x00 - LOAD_COUNT0"]
        #[inline(always)]
        pub const fn load_count0(&self) -> &LoadCount0 {
            &self.load_count0
        }
        #[doc = "0x04 - LOAD_COUNT1"]
        #[inline(always)]
        pub const fn load_count1(&self) -> &LoadCount1 {
            &self.load_count1
        }
        #[doc = "0x08 - CURRENT_VALUE0"]
        #[inline(always)]
        pub const fn current_value0(&self) -> &CurrentValue0 {
            &self.current_value0
        }
        #[doc = "0x0c - CURRENT_VALUE1"]
        #[inline(always)]
        pub const fn current_value1(&self) -> &CurrentValue1 {
            &self.current_value1
        }
        #[doc = "0x10 - CONTROL"]
        #[inline(always)]
        pub const fn control(&self) -> &Control {
            &self.control
        }
        #[doc = "0x14 - EOI_REN"]
        #[inline(always)]
        pub const fn eoi_ren(&self) -> &EoiRen {
            &self.eoi_ren
        }
        #[doc = "0x18 - RAW_INTR"]
        #[inline(always)]
        pub const fn raw_intr(&self) -> &RawIntr {
            &self.raw_intr
        }
        #[doc = "0x1c - INTR"]
        #[inline(always)]
        pub const fn intr(&self) -> &Intr {
            &self.intr
        }
    }
    #[doc = "LOAD_COUNT0 (rw) register accessor: LOAD_COUNT0\n\nYou can [`read`](crate::Reg::read) this register and get [`load_count0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load_count0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load_count0`] module"]
    #[doc(alias = "LOAD_COUNT0")]
    pub type LoadCount0 = crate::Reg<load_count0::LoadCount0Spec>;
    #[doc = "LOAD_COUNT0"]
    pub mod load_count0 {
        #[doc = "Register `LOAD_COUNT0` reader"]
        pub type R = crate::R<LoadCount0Spec>;
        #[doc = "Register `LOAD_COUNT0` writer"]
        pub type W = crate::W<LoadCount0Spec>;
        #[doc = "Field `load_count0` reader - "]
        pub type LoadCount0R = crate::FieldReader<u32>;
        #[doc = "Field `load_count0` writer - "]
        pub type LoadCount0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31"]
            #[inline(always)]
            pub fn load_count0(&self) -> LoadCount0R {
                LoadCount0R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31"]
            #[inline(always)]
            pub fn load_count0(&mut self) -> LoadCount0W<'_, LoadCount0Spec> {
                LoadCount0W::new(self, 0)
            }
        }
        #[doc = "LOAD_COUNT0\n\nYou can [`read`](crate::Reg::read) this register and get [`load_count0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load_count0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LoadCount0Spec;
        impl crate::RegisterSpec for LoadCount0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`load_count0::R`](R) reader structure"]
        impl crate::Readable for LoadCount0Spec {}
        #[doc = "`write(|w| ..)` method takes [`load_count0::W`](W) writer structure"]
        impl crate::Writable for LoadCount0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets LOAD_COUNT0 to value 0"]
        impl crate::Resettable for LoadCount0Spec {}
    }
    #[doc = "LOAD_COUNT1 (rw) register accessor: LOAD_COUNT1\n\nYou can [`read`](crate::Reg::read) this register and get [`load_count1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load_count1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load_count1`] module"]
    #[doc(alias = "LOAD_COUNT1")]
    pub type LoadCount1 = crate::Reg<load_count1::LoadCount1Spec>;
    #[doc = "LOAD_COUNT1"]
    pub mod load_count1 {
        #[doc = "Register `LOAD_COUNT1` reader"]
        pub type R = crate::R<LoadCount1Spec>;
        #[doc = "Register `LOAD_COUNT1` writer"]
        pub type W = crate::W<LoadCount1Spec>;
        #[doc = "Field `load_count1` reader - "]
        pub type LoadCount1R = crate::FieldReader<u32>;
        #[doc = "Field `load_count1` writer - "]
        pub type LoadCount1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31"]
            #[inline(always)]
            pub fn load_count1(&self) -> LoadCount1R {
                LoadCount1R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31"]
            #[inline(always)]
            pub fn load_count1(&mut self) -> LoadCount1W<'_, LoadCount1Spec> {
                LoadCount1W::new(self, 0)
            }
        }
        #[doc = "LOAD_COUNT1\n\nYou can [`read`](crate::Reg::read) this register and get [`load_count1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load_count1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LoadCount1Spec;
        impl crate::RegisterSpec for LoadCount1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`load_count1::R`](R) reader structure"]
        impl crate::Readable for LoadCount1Spec {}
        #[doc = "`write(|w| ..)` method takes [`load_count1::W`](W) writer structure"]
        impl crate::Writable for LoadCount1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets LOAD_COUNT1 to value 0"]
        impl crate::Resettable for LoadCount1Spec {}
    }
    #[doc = "CURRENT_VALUE0 (r) register accessor: CURRENT_VALUE0\n\nYou can [`read`](crate::Reg::read) this register and get [`current_value0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@current_value0`] module"]
    #[doc(alias = "CURRENT_VALUE0")]
    pub type CurrentValue0 = crate::Reg<current_value0::CurrentValue0Spec>;
    #[doc = "CURRENT_VALUE0"]
    pub mod current_value0 {
        #[doc = "Register `CURRENT_VALUE0` reader"]
        pub type R = crate::R<CurrentValue0Spec>;
        #[doc = "Field `current_value0` reader - "]
        pub type CurrentValue0R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31"]
            #[inline(always)]
            pub fn current_value0(&self) -> CurrentValue0R {
                CurrentValue0R::new(self.bits)
            }
        }
        #[doc = "CURRENT_VALUE0\n\nYou can [`read`](crate::Reg::read) this register and get [`current_value0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CurrentValue0Spec;
        impl crate::RegisterSpec for CurrentValue0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`current_value0::R`](R) reader structure"]
        impl crate::Readable for CurrentValue0Spec {}
        #[doc = "`reset()` method sets CURRENT_VALUE0 to value 0"]
        impl crate::Resettable for CurrentValue0Spec {}
    }
    #[doc = "CURRENT_VALUE1 (r) register accessor: CURRENT_VALUE1\n\nYou can [`read`](crate::Reg::read) this register and get [`current_value1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@current_value1`] module"]
    #[doc(alias = "CURRENT_VALUE1")]
    pub type CurrentValue1 = crate::Reg<current_value1::CurrentValue1Spec>;
    #[doc = "CURRENT_VALUE1"]
    pub mod current_value1 {
        #[doc = "Register `CURRENT_VALUE1` reader"]
        pub type R = crate::R<CurrentValue1Spec>;
        #[doc = "Field `current_value1` reader - "]
        pub type CurrentValue1R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31"]
            #[inline(always)]
            pub fn current_value1(&self) -> CurrentValue1R {
                CurrentValue1R::new(self.bits)
            }
        }
        #[doc = "CURRENT_VALUE1\n\nYou can [`read`](crate::Reg::read) this register and get [`current_value1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CurrentValue1Spec;
        impl crate::RegisterSpec for CurrentValue1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`current_value1::R`](R) reader structure"]
        impl crate::Readable for CurrentValue1Spec {}
        #[doc = "`reset()` method sets CURRENT_VALUE1 to value 0"]
        impl crate::Resettable for CurrentValue1Spec {}
    }
    #[doc = "CONTROL (rw) register accessor: CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`] module"]
    #[doc(alias = "CONTROL")]
    pub type Control = crate::Reg<control::ControlSpec>;
    #[doc = "CONTROL"]
    pub mod control {
        #[doc = "Register `CONTROL` reader"]
        pub type R = crate::R<ControlSpec>;
        #[doc = "Register `CONTROL` writer"]
        pub type W = crate::W<ControlSpec>;
        #[doc = "Field `enable` reader - "]
        pub type EnableR = crate::BitReader;
        #[doc = "Field `enable` writer - "]
        pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `mode` reader - "]
        pub type ModeR = crate::FieldReader;
        #[doc = "Field `mode` writer - "]
        pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `int_mask` reader - "]
        pub type IntMaskR = crate::BitReader;
        #[doc = "Field `int_mask` writer - "]
        pub type IntMaskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rstfsm` reader - "]
        pub type RstfsmR = crate::BitReader;
        #[doc = "Field `rstfsm` writer - "]
        pub type RstfsmW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cnt_req` reader - "]
        pub type CntReqR = crate::BitReader;
        #[doc = "Field `cnt_req` writer - "]
        pub type CntReqW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cnt_lock` reader - "]
        pub type CntLockR = crate::BitReader;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn enable(&self) -> EnableR {
                EnableR::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 1:2"]
            #[inline(always)]
            pub fn mode(&self) -> ModeR {
                ModeR::new(((self.bits >> 1) & 3) as u8)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn int_mask(&self) -> IntMaskR {
                IntMaskR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn rstfsm(&self) -> RstfsmR {
                RstfsmR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn cnt_req(&self) -> CntReqR {
                CntReqR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn cnt_lock(&self) -> CntLockR {
                CntLockR::new(((self.bits >> 6) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn enable(&mut self) -> EnableW<'_, ControlSpec> {
                EnableW::new(self, 0)
            }
            #[doc = "Bits 1:2"]
            #[inline(always)]
            pub fn mode(&mut self) -> ModeW<'_, ControlSpec> {
                ModeW::new(self, 1)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn int_mask(&mut self) -> IntMaskW<'_, ControlSpec> {
                IntMaskW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn rstfsm(&mut self) -> RstfsmW<'_, ControlSpec> {
                RstfsmW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn cnt_req(&mut self) -> CntReqW<'_, ControlSpec> {
                CntReqW::new(self, 5)
            }
        }
        #[doc = "CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ControlSpec;
        impl crate::RegisterSpec for ControlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`control::R`](R) reader structure"]
        impl crate::Readable for ControlSpec {}
        #[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"]
        impl crate::Writable for ControlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CONTROL to value 0"]
        impl crate::Resettable for ControlSpec {}
    }
    #[doc = "EOI_REN (r) register accessor: EOI_REN\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eoi_ren`] module"]
    #[doc(alias = "EOI_REN")]
    pub type EoiRen = crate::Reg<eoi_ren::EoiRenSpec>;
    #[doc = "EOI_REN"]
    pub mod eoi_ren {
        #[doc = "Register `EOI_REN` reader"]
        pub type R = crate::R<EoiRenSpec>;
        #[doc = "Field `eoi` reader - "]
        pub type EoiR = crate::BitReader;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn eoi(&self) -> EoiR {
                EoiR::new((self.bits & 1) != 0)
            }
        }
        #[doc = "EOI_REN\n\nYou can [`read`](crate::Reg::read) this register and get [`eoi_ren::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct EoiRenSpec;
        impl crate::RegisterSpec for EoiRenSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`eoi_ren::R`](R) reader structure"]
        impl crate::Readable for EoiRenSpec {}
        #[doc = "`reset()` method sets EOI_REN to value 0"]
        impl crate::Resettable for EoiRenSpec {}
    }
    #[doc = "RAW_INTR (r) register accessor: RAW_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_intr`] module"]
    #[doc(alias = "RAW_INTR")]
    pub type RawIntr = crate::Reg<raw_intr::RawIntrSpec>;
    #[doc = "RAW_INTR"]
    pub mod raw_intr {
        #[doc = "Register `RAW_INTR` reader"]
        pub type R = crate::R<RawIntrSpec>;
        #[doc = "Field `int_status` reader - "]
        pub type IntStatusR = crate::BitReader;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn int_status(&self) -> IntStatusR {
                IntStatusR::new((self.bits & 1) != 0)
            }
        }
        #[doc = "RAW_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RawIntrSpec;
        impl crate::RegisterSpec for RawIntrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`raw_intr::R`](R) reader structure"]
        impl crate::Readable for RawIntrSpec {}
        #[doc = "`reset()` method sets RAW_INTR to value 0"]
        impl crate::Resettable for RawIntrSpec {}
    }
    #[doc = "INTR (r) register accessor: INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr`] module"]
    #[doc(alias = "INTR")]
    pub type Intr = crate::Reg<intr::IntrSpec>;
    #[doc = "INTR"]
    pub mod intr {
        #[doc = "Register `INTR` reader"]
        pub type R = crate::R<IntrSpec>;
        #[doc = "Field `int_status` reader - "]
        pub type IntStatusR = crate::BitReader;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn int_status(&self) -> IntStatusR {
                IntStatusR::new((self.bits & 1) != 0)
            }
        }
        #[doc = "INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IntrSpec;
        impl crate::RegisterSpec for IntrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`intr::R`](R) reader structure"]
        impl crate::Readable for IntrSpec {}
        #[doc = "`reset()` method sets INTR to value 0"]
        impl crate::Resettable for IntrSpec {}
    }
}
#[doc = "True Random Number Generator"]
pub type Trng = crate::Periph<trng::RegisterBlock, 0x5200_9000>;
impl core::fmt::Debug for Trng {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Trng").finish()
    }
}
#[doc = "True Random Number Generator"]
pub mod trng {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        trng_ctrl: TrngCtrl,
        _reserved1: [u8; 0x20],
        trng_ring_en: TrngRingEn,
        _reserved2: [u8; 0xd8],
        trng_fifo_data: TrngFifoData,
        trng_fifo_ready: TrngFifoReady,
        trng_data_st: TrngDataSt,
        _reserved5: [u8; 0x68],
        trng_fro_sample_clk_sel: TrngFroSampleClkSel,
        trng_fro_div_cnt: TrngFroDivCnt,
    }
    impl RegisterBlock {
        #[doc = "0x00 - TRNG_CTRL"]
        #[inline(always)]
        pub const fn trng_ctrl(&self) -> &TrngCtrl {
            &self.trng_ctrl
        }
        #[doc = "0x24 - TRNG_RING_EN"]
        #[inline(always)]
        pub const fn trng_ring_en(&self) -> &TrngRingEn {
            &self.trng_ring_en
        }
        #[doc = "0x100 - TRNG FIFO data output register"]
        #[inline(always)]
        pub const fn trng_fifo_data(&self) -> &TrngFifoData {
            &self.trng_fifo_data
        }
        #[doc = "0x104 - TRNG FIFO ready status"]
        #[inline(always)]
        pub const fn trng_fifo_ready(&self) -> &TrngFifoReady {
            &self.trng_fifo_ready
        }
        #[doc = "0x108 - TRNG data status register"]
        #[inline(always)]
        pub const fn trng_data_st(&self) -> &TrngDataSt {
            &self.trng_data_st
        }
        #[doc = "0x174 - TRNG FRO sample clock select"]
        #[inline(always)]
        pub const fn trng_fro_sample_clk_sel(&self) -> &TrngFroSampleClkSel {
            &self.trng_fro_sample_clk_sel
        }
        #[doc = "0x178 - TRNG FRO divider count"]
        #[inline(always)]
        pub const fn trng_fro_div_cnt(&self) -> &TrngFroDivCnt {
            &self.trng_fro_div_cnt
        }
    }
    #[doc = "TRNG_CTRL (rw) register accessor: TRNG_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_ctrl`] module"]
    #[doc(alias = "TRNG_CTRL")]
    pub type TrngCtrl = crate::Reg<trng_ctrl::TrngCtrlSpec>;
    #[doc = "TRNG_CTRL"]
    pub mod trng_ctrl {
        #[doc = "Register `TRNG_CTRL` reader"]
        pub type R = crate::R<TrngCtrlSpec>;
        #[doc = "Register `TRNG_CTRL` writer"]
        pub type W = crate::W<TrngCtrlSpec>;
        #[doc = "Field `health_test_en` reader - "]
        pub type HealthTestEnR = crate::BitReader;
        #[doc = "Field `health_test_en` writer - "]
        pub type HealthTestEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `online_test_en` reader - "]
        pub type OnlineTestEnR = crate::BitReader;
        #[doc = "Field `online_test_en` writer - "]
        pub type OnlineTestEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `post_proc_en` reader - "]
        pub type PostProcEnR = crate::BitReader;
        #[doc = "Field `post_proc_en` writer - "]
        pub type PostProcEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `rnd_chk_en` reader - "]
        pub type RndChkEnR = crate::BitReader;
        #[doc = "Field `rnd_chk_en` writer - "]
        pub type RndChkEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `lfsr_reseed_en` reader - "]
        pub type LfsrReseedEnR = crate::BitReader;
        #[doc = "Field `lfsr_reseed_en` writer - "]
        pub type LfsrReseedEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `private_en` reader - "]
        pub type PrivateEnR = crate::BitReader;
        #[doc = "Field `private_en` writer - "]
        pub type PrivateEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn health_test_en(&self) -> HealthTestEnR {
                HealthTestEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn online_test_en(&self) -> OnlineTestEnR {
                OnlineTestEnR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn post_proc_en(&self) -> PostProcEnR {
                PostProcEnR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn rnd_chk_en(&self) -> RndChkEnR {
                RndChkEnR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn lfsr_reseed_en(&self) -> LfsrReseedEnR {
                LfsrReseedEnR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn private_en(&self) -> PrivateEnR {
                PrivateEnR::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn health_test_en(&mut self) -> HealthTestEnW<'_, TrngCtrlSpec> {
                HealthTestEnW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn online_test_en(&mut self) -> OnlineTestEnW<'_, TrngCtrlSpec> {
                OnlineTestEnW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn post_proc_en(&mut self) -> PostProcEnW<'_, TrngCtrlSpec> {
                PostProcEnW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn rnd_chk_en(&mut self) -> RndChkEnW<'_, TrngCtrlSpec> {
                RndChkEnW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn lfsr_reseed_en(&mut self) -> LfsrReseedEnW<'_, TrngCtrlSpec> {
                LfsrReseedEnW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn private_en(&mut self) -> PrivateEnW<'_, TrngCtrlSpec> {
                PrivateEnW::new(self, 5)
            }
        }
        #[doc = "TRNG_CTRL\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TrngCtrlSpec;
        impl crate::RegisterSpec for TrngCtrlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trng_ctrl::R`](R) reader structure"]
        impl crate::Readable for TrngCtrlSpec {}
        #[doc = "`write(|w| ..)` method takes [`trng_ctrl::W`](W) writer structure"]
        impl crate::Writable for TrngCtrlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TRNG_CTRL to value 0"]
        impl crate::Resettable for TrngCtrlSpec {}
    }
    #[doc = "TRNG_RING_EN (rw) register accessor: TRNG_RING_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_ring_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_ring_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_ring_en`] module"]
    #[doc(alias = "TRNG_RING_EN")]
    pub type TrngRingEn = crate::Reg<trng_ring_en::TrngRingEnSpec>;
    #[doc = "TRNG_RING_EN"]
    pub mod trng_ring_en {
        #[doc = "Register `TRNG_RING_EN` reader"]
        pub type R = crate::R<TrngRingEnSpec>;
        #[doc = "Register `TRNG_RING_EN` writer"]
        pub type W = crate::W<TrngRingEnSpec>;
        #[doc = "Field `ro_en` reader - "]
        pub type RoEnR = crate::BitReader;
        #[doc = "Field `ro_en` writer - "]
        pub type RoEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `tero_en` reader - "]
        pub type TeroEnR = crate::BitReader;
        #[doc = "Field `tero_en` writer - "]
        pub type TeroEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `fro_en` reader - "]
        pub type FroEnR = crate::BitReader;
        #[doc = "Field `fro_en` writer - "]
        pub type FroEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn ro_en(&self) -> RoEnR {
                RoEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn tero_en(&self) -> TeroEnR {
                TeroEnR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn fro_en(&self) -> FroEnR {
                FroEnR::new(((self.bits >> 2) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn ro_en(&mut self) -> RoEnW<'_, TrngRingEnSpec> {
                RoEnW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn tero_en(&mut self) -> TeroEnW<'_, TrngRingEnSpec> {
                TeroEnW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn fro_en(&mut self) -> FroEnW<'_, TrngRingEnSpec> {
                FroEnW::new(self, 2)
            }
        }
        #[doc = "TRNG_RING_EN\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_ring_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_ring_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TrngRingEnSpec;
        impl crate::RegisterSpec for TrngRingEnSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trng_ring_en::R`](R) reader structure"]
        impl crate::Readable for TrngRingEnSpec {}
        #[doc = "`write(|w| ..)` method takes [`trng_ring_en::W`](W) writer structure"]
        impl crate::Writable for TrngRingEnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TRNG_RING_EN to value 0"]
        impl crate::Resettable for TrngRingEnSpec {}
    }
    #[doc = "TRNG_FIFO_DATA (rw) register accessor: TRNG FIFO data output register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fifo_data`] module"]
    #[doc(alias = "TRNG_FIFO_DATA")]
    pub type TrngFifoData = crate::Reg<trng_fifo_data::TrngFifoDataSpec>;
    #[doc = "TRNG FIFO data output register"]
    pub mod trng_fifo_data {
        #[doc = "Register `TRNG_FIFO_DATA` reader"]
        pub type R = crate::R<TrngFifoDataSpec>;
        #[doc = "Register `TRNG_FIFO_DATA` writer"]
        pub type W = crate::W<TrngFifoDataSpec>;
        #[doc = "Field `trng_data` reader - Random data (read to get random number)"]
        pub type TrngDataR = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Random data (read to get random number)"]
            #[inline(always)]
            pub fn trng_data(&self) -> TrngDataR {
                TrngDataR::new(self.bits)
            }
        }
        impl W {}
        #[doc = "TRNG FIFO data output register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TrngFifoDataSpec;
        impl crate::RegisterSpec for TrngFifoDataSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trng_fifo_data::R`](R) reader structure"]
        impl crate::Readable for TrngFifoDataSpec {}
        #[doc = "`write(|w| ..)` method takes [`trng_fifo_data::W`](W) writer structure"]
        impl crate::Writable for TrngFifoDataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TRNG_FIFO_DATA to value 0"]
        impl crate::Resettable for TrngFifoDataSpec {}
    }
    #[doc = "TRNG_FIFO_READY (rw) register accessor: TRNG FIFO ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_ready::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_ready::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fifo_ready`] module"]
    #[doc(alias = "TRNG_FIFO_READY")]
    pub type TrngFifoReady = crate::Reg<trng_fifo_ready::TrngFifoReadySpec>;
    #[doc = "TRNG FIFO ready status"]
    pub mod trng_fifo_ready {
        #[doc = "Register `TRNG_FIFO_READY` reader"]
        pub type R = crate::R<TrngFifoReadySpec>;
        #[doc = "Register `TRNG_FIFO_READY` writer"]
        pub type W = crate::W<TrngFifoReadySpec>;
        #[doc = "Field `trng_data_ready` reader - Data ready: 1=data available in FIFO"]
        pub type TrngDataReadyR = crate::BitReader;
        #[doc = "Field `trng_done` reader - TRNG generation done"]
        pub type TrngDoneR = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Data ready: 1=data available in FIFO"]
            #[inline(always)]
            pub fn trng_data_ready(&self) -> TrngDataReadyR {
                TrngDataReadyR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TRNG generation done"]
            #[inline(always)]
            pub fn trng_done(&self) -> TrngDoneR {
                TrngDoneR::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {}
        #[doc = "TRNG FIFO ready status\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fifo_ready::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fifo_ready::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TrngFifoReadySpec;
        impl crate::RegisterSpec for TrngFifoReadySpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trng_fifo_ready::R`](R) reader structure"]
        impl crate::Readable for TrngFifoReadySpec {}
        #[doc = "`write(|w| ..)` method takes [`trng_fifo_ready::W`](W) writer structure"]
        impl crate::Writable for TrngFifoReadySpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TRNG_FIFO_READY to value 0"]
        impl crate::Resettable for TrngFifoReadySpec {}
    }
    #[doc = "TRNG_DATA_ST (rw) register accessor: TRNG data status register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_data_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_data_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_data_st`] module"]
    #[doc(alias = "TRNG_DATA_ST")]
    pub type TrngDataSt = crate::Reg<trng_data_st::TrngDataStSpec>;
    #[doc = "TRNG data status register"]
    pub mod trng_data_st {
        #[doc = "Register `TRNG_DATA_ST` reader"]
        pub type R = crate::R<TrngDataStSpec>;
        #[doc = "Register `TRNG_DATA_ST` writer"]
        pub type W = crate::W<TrngDataStSpec>;
        #[doc = "Field `data_st` reader - Data status"]
        pub type DataStR = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Data status"]
            #[inline(always)]
            pub fn data_st(&self) -> DataStR {
                DataStR::new(self.bits)
            }
        }
        impl W {}
        #[doc = "TRNG data status register\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_data_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_data_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TrngDataStSpec;
        impl crate::RegisterSpec for TrngDataStSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trng_data_st::R`](R) reader structure"]
        impl crate::Readable for TrngDataStSpec {}
        #[doc = "`write(|w| ..)` method takes [`trng_data_st::W`](W) writer structure"]
        impl crate::Writable for TrngDataStSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TRNG_DATA_ST to value 0"]
        impl crate::Resettable for TrngDataStSpec {}
    }
    #[doc = "TRNG_FRO_SAMPLE_CLK_SEL (rw) register accessor: TRNG FRO sample clock select\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_sample_clk_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_sample_clk_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fro_sample_clk_sel`] module"]
    #[doc(alias = "TRNG_FRO_SAMPLE_CLK_SEL")]
    pub type TrngFroSampleClkSel = crate::Reg<trng_fro_sample_clk_sel::TrngFroSampleClkSelSpec>;
    #[doc = "TRNG FRO sample clock select"]
    pub mod trng_fro_sample_clk_sel {
        #[doc = "Register `TRNG_FRO_SAMPLE_CLK_SEL` reader"]
        pub type R = crate::R<TrngFroSampleClkSelSpec>;
        #[doc = "Register `TRNG_FRO_SAMPLE_CLK_SEL` writer"]
        pub type W = crate::W<TrngFroSampleClkSelSpec>;
        #[doc = "Field `fro_sample_clk_sel` reader - FRO sample clock select: 0=inner; 1=external"]
        pub type FroSampleClkSelR = crate::BitReader;
        #[doc = "Field `fro_sample_clk_sel` writer - FRO sample clock select: 0=inner; 1=external"]
        pub type FroSampleClkSelW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - FRO sample clock select: 0=inner; 1=external"]
            #[inline(always)]
            pub fn fro_sample_clk_sel(&self) -> FroSampleClkSelR {
                FroSampleClkSelR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - FRO sample clock select: 0=inner; 1=external"]
            #[inline(always)]
            pub fn fro_sample_clk_sel(&mut self) -> FroSampleClkSelW<'_, TrngFroSampleClkSelSpec> {
                FroSampleClkSelW::new(self, 0)
            }
        }
        #[doc = "TRNG FRO sample clock select\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_sample_clk_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_sample_clk_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TrngFroSampleClkSelSpec;
        impl crate::RegisterSpec for TrngFroSampleClkSelSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trng_fro_sample_clk_sel::R`](R) reader structure"]
        impl crate::Readable for TrngFroSampleClkSelSpec {}
        #[doc = "`write(|w| ..)` method takes [`trng_fro_sample_clk_sel::W`](W) writer structure"]
        impl crate::Writable for TrngFroSampleClkSelSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TRNG_FRO_SAMPLE_CLK_SEL to value 0"]
        impl crate::Resettable for TrngFroSampleClkSelSpec {}
    }
    #[doc = "TRNG_FRO_DIV_CNT (rw) register accessor: TRNG FRO divider count\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_div_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_div_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trng_fro_div_cnt`] module"]
    #[doc(alias = "TRNG_FRO_DIV_CNT")]
    pub type TrngFroDivCnt = crate::Reg<trng_fro_div_cnt::TrngFroDivCntSpec>;
    #[doc = "TRNG FRO divider count"]
    pub mod trng_fro_div_cnt {
        #[doc = "Register `TRNG_FRO_DIV_CNT` reader"]
        pub type R = crate::R<TrngFroDivCntSpec>;
        #[doc = "Register `TRNG_FRO_DIV_CNT` writer"]
        pub type W = crate::W<TrngFroDivCntSpec>;
        #[doc = "Field `fro_div_cnt` reader - FRO divider count (default 0x1b)"]
        pub type FroDivCntR = crate::FieldReader;
        #[doc = "Field `fro_div_cnt` writer - FRO divider count (default 0x1b)"]
        pub type FroDivCntW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - FRO divider count (default 0x1b)"]
            #[inline(always)]
            pub fn fro_div_cnt(&self) -> FroDivCntR {
                FroDivCntR::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - FRO divider count (default 0x1b)"]
            #[inline(always)]
            pub fn fro_div_cnt(&mut self) -> FroDivCntW<'_, TrngFroDivCntSpec> {
                FroDivCntW::new(self, 0)
            }
        }
        #[doc = "TRNG FRO divider count\n\nYou can [`read`](crate::Reg::read) this register and get [`trng_fro_div_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_fro_div_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TrngFroDivCntSpec;
        impl crate::RegisterSpec for TrngFroDivCntSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trng_fro_div_cnt::R`](R) reader structure"]
        impl crate::Readable for TrngFroDivCntSpec {}
        #[doc = "`write(|w| ..)` method takes [`trng_fro_div_cnt::W`](W) writer structure"]
        impl crate::Writable for TrngFroDivCntSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets TRNG_FRO_DIV_CNT to value 0"]
        impl crate::Resettable for TrngFroDivCntSpec {}
    }
}
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub type Gpio1 = crate::Periph<gpio0::RegisterBlock, 0x5701_4000>;
impl core::fmt::Debug for Gpio1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Gpio1").finish()
    }
}
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub use self::gpio0 as gpio1;
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub type Gpio2 = crate::Periph<gpio0::RegisterBlock, 0x5701_8000>;
impl core::fmt::Debug for Gpio2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Gpio2").finish()
    }
}
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub use self::gpio0 as gpio2;
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub type Gpio3 = crate::Periph<gpio0::RegisterBlock, 0x5701_c000>;
impl core::fmt::Debug for Gpio3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Gpio3").finish()
    }
}
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub use self::gpio0 as gpio3;
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub type Gpio4 = crate::Periph<gpio0::RegisterBlock, 0x5702_0000>;
impl core::fmt::Debug for Gpio4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Gpio4").finish()
    }
}
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub use self::gpio0 as gpio4;
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub type UlpGpio = crate::Periph<gpio0::RegisterBlock, 0x5703_0000>;
impl core::fmt::Debug for UlpGpio {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UlpGpio").finish()
    }
}
#[doc = "GPIO controller for GPIO\\[7:0\\]"]
pub use self::gpio0 as ulp_gpio;
#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
pub type Uart1 = crate::Periph<uart0::RegisterBlock, 0x5208_0000>;
impl core::fmt::Debug for Uart1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Uart1").finish()
    }
}
#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
pub use self::uart0 as uart1;
#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
pub type Uart2 = crate::Periph<uart0::RegisterBlock, 0x5208_2000>;
impl core::fmt::Debug for Uart2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Uart2").finish()
    }
}
#[doc = "UART0 - Universal Asynchronous Receiver/Transmitter"]
pub use self::uart0 as uart2;
#[doc = "I2C0 master controller (DesignWare SSI, IP v151)"]
pub type I2c1 = crate::Periph<i2c0::RegisterBlock, 0x5208_4000>;
impl core::fmt::Debug for I2c1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2c1").finish()
    }
}
#[doc = "I2C0 master controller (DesignWare SSI, IP v151)"]
pub use self::i2c0 as i2c1;
#[doc = "SPI0 master/slave controller (SSI v151)"]
pub type Spi1 = crate::Periph<spi0::RegisterBlock, 0x5208_8000>;
impl core::fmt::Debug for Spi1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Spi1").finish()
    }
}
#[doc = "SPI0 master/slave controller (SSI v151)"]
pub use self::spi0 as spi1;
#[doc = "SPI0 master/slave controller (SSI v151)"]
pub type Spi2 = crate::Periph<spi0::RegisterBlock, 0x5208_9000>;
impl core::fmt::Debug for Spi2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Spi2").finish()
    }
}
#[doc = "SPI0 master/slave controller (SSI v151)"]
pub use self::spi0 as spi2;
#[doc = "DMA controller with 4 channels"]
pub type Sdma = crate::Periph<dma::RegisterBlock, 0x520a_0000>;
impl core::fmt::Debug for Sdma {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Sdma").finish()
    }
}
#[doc = "DMA controller with 4 channels"]
pub use self::dma as sdma;
#[doc = "13-bit GADC (general ADC, v153)"]
pub type Gadc = crate::Periph<gadc::RegisterBlock, 0x5703_6000>;
impl core::fmt::Debug for Gadc {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Gadc").finish()
    }
}
#[doc = "13-bit GADC (general ADC, v153)"]
pub mod gadc {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        cfg_rstn: CfgRstn,
        cfg_clken: CfgClken,
        cfg_prechg_lead: CfgPrechgLead,
        cfg_clk_div_0: CfgClkDiv0,
        cfg_clk_div_1: CfgClkDiv1,
        cfg_manual_clk_0: CfgManualClk0,
        cfg_manual_clk_1: CfgManualClk1,
        cfg_iso: CfgIso,
        _reserved8: [u8; 0x10],
        cfg_gadc_ctrl_0: CfgGadcCtrl0,
        cfg_gadc_ctrl_1: CfgGadcCtrl1,
        cfg_gadc_ctrl_2: CfgGadcCtrl2,
        cfg_gadc_ctrl_3: CfgGadcCtrl3,
        cfg_gadc_ctrl_4: CfgGadcCtrl4,
        rpt_gadc_ctrl_0: RptGadcCtrl0,
        cfg_gadc_ctrl_5: CfgGadcCtrl5,
        cfg_gadc_ctrl_6: CfgGadcCtrl6,
        rpt_gadc_ctrl_1: RptGadcCtrl1,
        cfg_gadc_ctrl_7: CfgGadcCtrl7,
        rpt_gadc_ctrl_2: RptGadcCtrl2,
        cfg_gadc_data_0: CfgGadcData0,
        cfg_gadc_data_1: CfgGadcData1,
        rpt_gadc_data_0: RptGadcData0,
        rpt_gadc_data_1: RptGadcData1,
        rpt_gadc_data_2: RptGadcData2,
        rpt_gadc_data_3: RptGadcData3,
        cfg_gadc_data_3: CfgGadcData3,
        cfg_gadc_data_4: CfgGadcData4,
        rpt_gadc_data_4: RptGadcData4,
        cfg_gadc_data_5: CfgGadcData5,
        cfg_gadc_data_6: CfgGadcData6,
        cfg_gadc_data_7: CfgGadcData7,
        cfg_gadc_data_8: CfgGadcData8,
        cfg_gadc_data_9: CfgGadcData9,
        cfg_gadc_data_10: CfgGadcData10,
        cfg_gadc_data_11: CfgGadcData11,
        cfg_gadc_data_12: CfgGadcData12,
        cfg_gadc_data_13: CfgGadcData13,
        cfg_gadc_data_14: CfgGadcData14,
        cfg_gadc_data_15: CfgGadcData15,
        cfg_gadc_data_16: CfgGadcData16,
        cfg_gadc_data_17: CfgGadcData17,
        cfg_gadc_data_18: CfgGadcData18,
        cfg_gadc_data_19: CfgGadcData19,
        cfg_gadc_data_20: CfgGadcData20,
        cfg_gadc_data_21: CfgGadcData21,
        cfg_gadc_data_22: CfgGadcData22,
        cfg_gadc_data_23: CfgGadcData23,
        cfg_gadc_data_24: CfgGadcData24,
        cfg_gadc_data_25: CfgGadcData25,
        rpt_gadc_data_5: RptGadcData5,
        rpt_gadc_data_6: RptGadcData6,
        rpt_gadc_data_7: RptGadcData7,
        rpt_gadc_data_8: RptGadcData8,
        rpt_gadc_data_9: RptGadcData9,
        rpt_gadc_data_10: RptGadcData10,
        rpt_gadc_data_11: RptGadcData11,
        rpt_gadc_data_12: RptGadcData12,
        rpt_gadc_data_13: RptGadcData13,
        _reserved58: [u8; 0x08],
        cfg_cmp_os_0: CfgCmpOs0,
        cfg_cmp_os_1: CfgCmpOs1,
        cfg_cmp_os_2: CfgCmpOs2,
        cfg_cmp_os_3: CfgCmpOs3,
        cfg_cmp_os_4: CfgCmpOs4,
        cfg_cmp_os_5: CfgCmpOs5,
        cfg_cmp_os_6: CfgCmpOs6,
        cfg_cmp_os_7: CfgCmpOs7,
        cfg_cmp_os_8: CfgCmpOs8,
        cfg_cmp_os_9: CfgCmpOs9,
        cfg_cmp_os_10: CfgCmpOs10,
        rpt_cmp_os_0: RptCmpOs0,
        cfg_cmp_os_11: CfgCmpOs11,
        cfg_cmp_os_12: CfgCmpOs12,
        rpt_cmp_os_2: RptCmpOs2,
        _reserved73: [u8; 0x14],
        cfg_cdac_fc0_0: CfgCdacFc0_0,
        cfg_cdac_fc0_1: CfgCdacFc0_1,
        cfg_cdac_fc0_2: CfgCdacFc0_2,
        cfg_cdac_fc0_3: CfgCdacFc0_3,
        cfg_cdac_fc0_4: CfgCdacFc0_4,
        cfg_cdac_fc0_5: CfgCdacFc0_5,
        rpt_cdac_fc0_0: RptCdacFc0_0,
        cfg_cdac_fc0_6: CfgCdacFc0_6,
        cfg_cdac_fc0_7: CfgCdacFc0_7,
        cfg_cdac_fc0_8: CfgCdacFc0_8,
        cfg_cdac_fc0_9: CfgCdacFc0_9,
        cfg_cdac_fc0_10: CfgCdacFc0_10,
        cfg_cdac_fc0_11: CfgCdacFc0_11,
        cfg_cdac_fc0_12: CfgCdacFc0_12,
        cfg_cdac_fc0_13: CfgCdacFc0_13,
        cfg_cdac_fc0_14: CfgCdacFc0_14,
        cfg_cdac_fc1_0: CfgCdacFc1_0,
        cfg_cdac_fc1_1: CfgCdacFc1_1,
        cfg_cdac_fc1_2: CfgCdacFc1_2,
        cfg_cdac_fc1_3: CfgCdacFc1_3,
        rpt_cdac_fc1_0: RptCdacFc1_0,
        rpt_cdac_fc1_3: RptCdacFc1_3,
        rpt_cdac_fc3_1: RptCdacFc3_1,
        rpt_cdac_fc3_2: RptCdacFc3_2,
        rpt_cdac_fc3_3: RptCdacFc3_3,
        rpt_cdac_fc3_4: RptCdacFc3_4,
        rpt_cdac_fc3_5: RptCdacFc3_5,
        rpt_cdac_fc3_6: RptCdacFc3_6,
        rpt_cdac_fc3_7: RptCdacFc3_7,
        rpt_cdac_fc3_8: RptCdacFc3_8,
        rpt_cdac_fc3_9: RptCdacFc3_9,
        rpt_cdac_fc3_10: RptCdacFc3_10,
        rpt_cdac_fc3_11: RptCdacFc3_11,
        rpt_cdac_fc3_12: RptCdacFc3_12,
        rpt_cdac_fc3_13: RptCdacFc3_13,
        rpt_cdac_fc3_14: RptCdacFc3_14,
        rpt_cdac_fc3_15: RptCdacFc3_15,
        rpt_cdac_fc3_16: RptCdacFc3_16,
        rpt_cdac_fc3_17: RptCdacFc3_17,
        rpt_cdac_fc3_18: RptCdacFc3_18,
        _reserved113: [u8; 0x10],
        cfg_dcoc_cal_0: CfgDcocCal0,
        cfg_dcoc_cal_1: CfgDcocCal1,
        cfg_dcoc_cal_2: CfgDcocCal2,
        cfg_dcoc_cal_3: CfgDcocCal3,
        cfg_dcoc_cal_4: CfgDcocCal4,
        cfg_dcoc_cal_5: CfgDcocCal5,
        cfg_dcoc_cal_6: CfgDcocCal6,
        cfg_dcoc_cal_7: CfgDcocCal7,
        cfg_dcoc_cal_8: CfgDcocCal8,
        rpt_dcoc_cal_0: RptDcocCal0,
        cfg_dcoc_cal_12: CfgDcocCal12,
        cfg_dcoc_cal_13: CfgDcocCal13,
        rpt_dcoc_cal_1: RptDcocCal1,
        _reserved126: [u8; 0x0c],
        cfg_sar_spd_0: CfgSarSpd0,
        cfg_sar_spd_1: CfgSarSpd1,
        cfg_sar_spd_2: CfgSarSpd2,
        cfg_sar_spd_3: CfgSarSpd3,
        cfg_sar_spd_4: CfgSarSpd4,
        rpt_sar_spd_0: RptSarSpd0,
        rpt_sar_spd_1: RptSarSpd1,
        cfg_sar_spd_6: CfgSarSpd6,
        rpt_sar_spd_2: RptSarSpd2,
        _reserved135: [u8; 0x1c],
        cfg_rc_cal_0: CfgRcCal0,
        cfg_rc_cal_1: CfgRcCal1,
        cfg_rc_cal_2: CfgRcCal2,
        cfg_rc_cal_3: CfgRcCal3,
        cfg_rc_cal_4: CfgRcCal4,
        rpt_rc_cal_0: RptRcCal0,
        rpt_rc_cal_1: RptRcCal1,
        cfg_rc_cal_5: CfgRcCal5,
        cfg_rc_cal_6: CfgRcCal6,
        cfg_rc_cal_7: CfgRcCal7,
        cfg_rc_cal_8: CfgRcCal8,
        rpt_rc_cal_2: RptRcCal2,
        rpt_rc_cal_3: RptRcCal3,
        _reserved148: [u8; 0x0c],
        cfg_amux_0: CfgAmux0,
        cfg_amux_1: CfgAmux1,
        cfg_amux_2: CfgAmux2,
        cfg_amux_3: CfgAmux3,
        cfg_amux_4: CfgAmux4,
        cfg_amux_5: CfgAmux5,
        rpt_amux_0: RptAmux0,
        _reserved155: [u8; 0x14],
        cfg_tst_0: CfgTst0,
        cfg_tst_1: CfgTst1,
        cfg_cmp_0: CfgCmp0,
        cfg_cmp_1: CfgCmp1,
        rpt_cmp_0: RptCmp0,
        rpt_cmp_1: RptCmp1,
    }
    impl RegisterBlock {
        #[doc = "0x00 - cfg_rstn"]
        #[inline(always)]
        pub const fn cfg_rstn(&self) -> &CfgRstn {
            &self.cfg_rstn
        }
        #[doc = "0x04 - cfg_clken"]
        #[inline(always)]
        pub const fn cfg_clken(&self) -> &CfgClken {
            &self.cfg_clken
        }
        #[doc = "0x08 - cfg_prechg_lead"]
        #[inline(always)]
        pub const fn cfg_prechg_lead(&self) -> &CfgPrechgLead {
            &self.cfg_prechg_lead
        }
        #[doc = "0x0c - cfg_clk_div_0"]
        #[inline(always)]
        pub const fn cfg_clk_div_0(&self) -> &CfgClkDiv0 {
            &self.cfg_clk_div_0
        }
        #[doc = "0x10 - cfg_clk_div_1"]
        #[inline(always)]
        pub const fn cfg_clk_div_1(&self) -> &CfgClkDiv1 {
            &self.cfg_clk_div_1
        }
        #[doc = "0x14 - cfg_manual_clk_0"]
        #[inline(always)]
        pub const fn cfg_manual_clk_0(&self) -> &CfgManualClk0 {
            &self.cfg_manual_clk_0
        }
        #[doc = "0x18 - cfg_manual_clk_1"]
        #[inline(always)]
        pub const fn cfg_manual_clk_1(&self) -> &CfgManualClk1 {
            &self.cfg_manual_clk_1
        }
        #[doc = "0x1c - cfg_iso"]
        #[inline(always)]
        pub const fn cfg_iso(&self) -> &CfgIso {
            &self.cfg_iso
        }
        #[doc = "0x30 - cfg_gadc_ctrl_0"]
        #[inline(always)]
        pub const fn cfg_gadc_ctrl_0(&self) -> &CfgGadcCtrl0 {
            &self.cfg_gadc_ctrl_0
        }
        #[doc = "0x34 - cfg_gadc_ctrl_1"]
        #[inline(always)]
        pub const fn cfg_gadc_ctrl_1(&self) -> &CfgGadcCtrl1 {
            &self.cfg_gadc_ctrl_1
        }
        #[doc = "0x38 - cfg_gadc_ctrl_2"]
        #[inline(always)]
        pub const fn cfg_gadc_ctrl_2(&self) -> &CfgGadcCtrl2 {
            &self.cfg_gadc_ctrl_2
        }
        #[doc = "0x3c - cfg_gadc_ctrl_3"]
        #[inline(always)]
        pub const fn cfg_gadc_ctrl_3(&self) -> &CfgGadcCtrl3 {
            &self.cfg_gadc_ctrl_3
        }
        #[doc = "0x40 - cfg_gadc_ctrl_4"]
        #[inline(always)]
        pub const fn cfg_gadc_ctrl_4(&self) -> &CfgGadcCtrl4 {
            &self.cfg_gadc_ctrl_4
        }
        #[doc = "0x44 - rpt_gadc_ctrl_0"]
        #[inline(always)]
        pub const fn rpt_gadc_ctrl_0(&self) -> &RptGadcCtrl0 {
            &self.rpt_gadc_ctrl_0
        }
        #[doc = "0x48 - cfg_gadc_ctrl_5"]
        #[inline(always)]
        pub const fn cfg_gadc_ctrl_5(&self) -> &CfgGadcCtrl5 {
            &self.cfg_gadc_ctrl_5
        }
        #[doc = "0x4c - cfg_gadc_ctrl_6"]
        #[inline(always)]
        pub const fn cfg_gadc_ctrl_6(&self) -> &CfgGadcCtrl6 {
            &self.cfg_gadc_ctrl_6
        }
        #[doc = "0x50 - rpt_gadc_ctrl_1"]
        #[inline(always)]
        pub const fn rpt_gadc_ctrl_1(&self) -> &RptGadcCtrl1 {
            &self.rpt_gadc_ctrl_1
        }
        #[doc = "0x54 - cfg_gadc_ctrl_7"]
        #[inline(always)]
        pub const fn cfg_gadc_ctrl_7(&self) -> &CfgGadcCtrl7 {
            &self.cfg_gadc_ctrl_7
        }
        #[doc = "0x58 - rpt_gadc_ctrl_2"]
        #[inline(always)]
        pub const fn rpt_gadc_ctrl_2(&self) -> &RptGadcCtrl2 {
            &self.rpt_gadc_ctrl_2
        }
        #[doc = "0x5c - cfg_gadc_data_0"]
        #[inline(always)]
        pub const fn cfg_gadc_data_0(&self) -> &CfgGadcData0 {
            &self.cfg_gadc_data_0
        }
        #[doc = "0x60 - cfg_gadc_data_1"]
        #[inline(always)]
        pub const fn cfg_gadc_data_1(&self) -> &CfgGadcData1 {
            &self.cfg_gadc_data_1
        }
        #[doc = "0x64 - rpt_gadc_data_0"]
        #[inline(always)]
        pub const fn rpt_gadc_data_0(&self) -> &RptGadcData0 {
            &self.rpt_gadc_data_0
        }
        #[doc = "0x68 - rpt_gadc_data_1"]
        #[inline(always)]
        pub const fn rpt_gadc_data_1(&self) -> &RptGadcData1 {
            &self.rpt_gadc_data_1
        }
        #[doc = "0x6c - rpt_gadc_data_2"]
        #[inline(always)]
        pub const fn rpt_gadc_data_2(&self) -> &RptGadcData2 {
            &self.rpt_gadc_data_2
        }
        #[doc = "0x70 - rpt_gadc_data_3"]
        #[inline(always)]
        pub const fn rpt_gadc_data_3(&self) -> &RptGadcData3 {
            &self.rpt_gadc_data_3
        }
        #[doc = "0x74 - cfg_gadc_data_3"]
        #[inline(always)]
        pub const fn cfg_gadc_data_3(&self) -> &CfgGadcData3 {
            &self.cfg_gadc_data_3
        }
        #[doc = "0x78 - cfg_gadc_data_4"]
        #[inline(always)]
        pub const fn cfg_gadc_data_4(&self) -> &CfgGadcData4 {
            &self.cfg_gadc_data_4
        }
        #[doc = "0x7c - rpt_gadc_data_4"]
        #[inline(always)]
        pub const fn rpt_gadc_data_4(&self) -> &RptGadcData4 {
            &self.rpt_gadc_data_4
        }
        #[doc = "0x80 - cfg_gadc_data_5"]
        #[inline(always)]
        pub const fn cfg_gadc_data_5(&self) -> &CfgGadcData5 {
            &self.cfg_gadc_data_5
        }
        #[doc = "0x84 - cfg_gadc_data_6"]
        #[inline(always)]
        pub const fn cfg_gadc_data_6(&self) -> &CfgGadcData6 {
            &self.cfg_gadc_data_6
        }
        #[doc = "0x88 - cfg_gadc_data_7"]
        #[inline(always)]
        pub const fn cfg_gadc_data_7(&self) -> &CfgGadcData7 {
            &self.cfg_gadc_data_7
        }
        #[doc = "0x8c - cfg_gadc_data_8"]
        #[inline(always)]
        pub const fn cfg_gadc_data_8(&self) -> &CfgGadcData8 {
            &self.cfg_gadc_data_8
        }
        #[doc = "0x90 - cfg_gadc_data_9"]
        #[inline(always)]
        pub const fn cfg_gadc_data_9(&self) -> &CfgGadcData9 {
            &self.cfg_gadc_data_9
        }
        #[doc = "0x94 - cfg_gadc_data_10"]
        #[inline(always)]
        pub const fn cfg_gadc_data_10(&self) -> &CfgGadcData10 {
            &self.cfg_gadc_data_10
        }
        #[doc = "0x98 - cfg_gadc_data_11"]
        #[inline(always)]
        pub const fn cfg_gadc_data_11(&self) -> &CfgGadcData11 {
            &self.cfg_gadc_data_11
        }
        #[doc = "0x9c - cfg_gadc_data_12"]
        #[inline(always)]
        pub const fn cfg_gadc_data_12(&self) -> &CfgGadcData12 {
            &self.cfg_gadc_data_12
        }
        #[doc = "0xa0 - cfg_gadc_data_13"]
        #[inline(always)]
        pub const fn cfg_gadc_data_13(&self) -> &CfgGadcData13 {
            &self.cfg_gadc_data_13
        }
        #[doc = "0xa4 - cfg_gadc_data_14"]
        #[inline(always)]
        pub const fn cfg_gadc_data_14(&self) -> &CfgGadcData14 {
            &self.cfg_gadc_data_14
        }
        #[doc = "0xa8 - cfg_gadc_data_15"]
        #[inline(always)]
        pub const fn cfg_gadc_data_15(&self) -> &CfgGadcData15 {
            &self.cfg_gadc_data_15
        }
        #[doc = "0xac - cfg_gadc_data_16"]
        #[inline(always)]
        pub const fn cfg_gadc_data_16(&self) -> &CfgGadcData16 {
            &self.cfg_gadc_data_16
        }
        #[doc = "0xb0 - cfg_gadc_data_17"]
        #[inline(always)]
        pub const fn cfg_gadc_data_17(&self) -> &CfgGadcData17 {
            &self.cfg_gadc_data_17
        }
        #[doc = "0xb4 - cfg_gadc_data_18"]
        #[inline(always)]
        pub const fn cfg_gadc_data_18(&self) -> &CfgGadcData18 {
            &self.cfg_gadc_data_18
        }
        #[doc = "0xb8 - cfg_gadc_data_19"]
        #[inline(always)]
        pub const fn cfg_gadc_data_19(&self) -> &CfgGadcData19 {
            &self.cfg_gadc_data_19
        }
        #[doc = "0xbc - cfg_gadc_data_20"]
        #[inline(always)]
        pub const fn cfg_gadc_data_20(&self) -> &CfgGadcData20 {
            &self.cfg_gadc_data_20
        }
        #[doc = "0xc0 - cfg_gadc_data_21"]
        #[inline(always)]
        pub const fn cfg_gadc_data_21(&self) -> &CfgGadcData21 {
            &self.cfg_gadc_data_21
        }
        #[doc = "0xc4 - cfg_gadc_data_22"]
        #[inline(always)]
        pub const fn cfg_gadc_data_22(&self) -> &CfgGadcData22 {
            &self.cfg_gadc_data_22
        }
        #[doc = "0xc8 - cfg_gadc_data_23"]
        #[inline(always)]
        pub const fn cfg_gadc_data_23(&self) -> &CfgGadcData23 {
            &self.cfg_gadc_data_23
        }
        #[doc = "0xcc - cfg_gadc_data_24"]
        #[inline(always)]
        pub const fn cfg_gadc_data_24(&self) -> &CfgGadcData24 {
            &self.cfg_gadc_data_24
        }
        #[doc = "0xd0 - cfg_gadc_data_25"]
        #[inline(always)]
        pub const fn cfg_gadc_data_25(&self) -> &CfgGadcData25 {
            &self.cfg_gadc_data_25
        }
        #[doc = "0xd4 - rpt_gadc_data_5"]
        #[inline(always)]
        pub const fn rpt_gadc_data_5(&self) -> &RptGadcData5 {
            &self.rpt_gadc_data_5
        }
        #[doc = "0xd8 - rpt_gadc_data_6"]
        #[inline(always)]
        pub const fn rpt_gadc_data_6(&self) -> &RptGadcData6 {
            &self.rpt_gadc_data_6
        }
        #[doc = "0xdc - rpt_gadc_data_7"]
        #[inline(always)]
        pub const fn rpt_gadc_data_7(&self) -> &RptGadcData7 {
            &self.rpt_gadc_data_7
        }
        #[doc = "0xe0 - rpt_gadc_data_8"]
        #[inline(always)]
        pub const fn rpt_gadc_data_8(&self) -> &RptGadcData8 {
            &self.rpt_gadc_data_8
        }
        #[doc = "0xe4 - rpt_gadc_data_9"]
        #[inline(always)]
        pub const fn rpt_gadc_data_9(&self) -> &RptGadcData9 {
            &self.rpt_gadc_data_9
        }
        #[doc = "0xe8 - rpt_gadc_data_10"]
        #[inline(always)]
        pub const fn rpt_gadc_data_10(&self) -> &RptGadcData10 {
            &self.rpt_gadc_data_10
        }
        #[doc = "0xec - rpt_gadc_data_11"]
        #[inline(always)]
        pub const fn rpt_gadc_data_11(&self) -> &RptGadcData11 {
            &self.rpt_gadc_data_11
        }
        #[doc = "0xf0 - rpt_gadc_data_12"]
        #[inline(always)]
        pub const fn rpt_gadc_data_12(&self) -> &RptGadcData12 {
            &self.rpt_gadc_data_12
        }
        #[doc = "0xf4 - rpt_gadc_data_13"]
        #[inline(always)]
        pub const fn rpt_gadc_data_13(&self) -> &RptGadcData13 {
            &self.rpt_gadc_data_13
        }
        #[doc = "0x100 - cfg_cmp_os_0"]
        #[inline(always)]
        pub const fn cfg_cmp_os_0(&self) -> &CfgCmpOs0 {
            &self.cfg_cmp_os_0
        }
        #[doc = "0x104 - cfg_cmp_os_1"]
        #[inline(always)]
        pub const fn cfg_cmp_os_1(&self) -> &CfgCmpOs1 {
            &self.cfg_cmp_os_1
        }
        #[doc = "0x108 - cfg_cmp_os_2"]
        #[inline(always)]
        pub const fn cfg_cmp_os_2(&self) -> &CfgCmpOs2 {
            &self.cfg_cmp_os_2
        }
        #[doc = "0x10c - cfg_cmp_os_3"]
        #[inline(always)]
        pub const fn cfg_cmp_os_3(&self) -> &CfgCmpOs3 {
            &self.cfg_cmp_os_3
        }
        #[doc = "0x110 - cfg_cmp_os_4"]
        #[inline(always)]
        pub const fn cfg_cmp_os_4(&self) -> &CfgCmpOs4 {
            &self.cfg_cmp_os_4
        }
        #[doc = "0x114 - cfg_cmp_os_5"]
        #[inline(always)]
        pub const fn cfg_cmp_os_5(&self) -> &CfgCmpOs5 {
            &self.cfg_cmp_os_5
        }
        #[doc = "0x118 - cfg_cmp_os_6"]
        #[inline(always)]
        pub const fn cfg_cmp_os_6(&self) -> &CfgCmpOs6 {
            &self.cfg_cmp_os_6
        }
        #[doc = "0x11c - cfg_cmp_os_7"]
        #[inline(always)]
        pub const fn cfg_cmp_os_7(&self) -> &CfgCmpOs7 {
            &self.cfg_cmp_os_7
        }
        #[doc = "0x120 - cfg_cmp_os_8"]
        #[inline(always)]
        pub const fn cfg_cmp_os_8(&self) -> &CfgCmpOs8 {
            &self.cfg_cmp_os_8
        }
        #[doc = "0x124 - cfg_cmp_os_9"]
        #[inline(always)]
        pub const fn cfg_cmp_os_9(&self) -> &CfgCmpOs9 {
            &self.cfg_cmp_os_9
        }
        #[doc = "0x128 - cfg_cmp_os_10"]
        #[inline(always)]
        pub const fn cfg_cmp_os_10(&self) -> &CfgCmpOs10 {
            &self.cfg_cmp_os_10
        }
        #[doc = "0x12c - rpt_cmp_os_0"]
        #[inline(always)]
        pub const fn rpt_cmp_os_0(&self) -> &RptCmpOs0 {
            &self.rpt_cmp_os_0
        }
        #[doc = "0x130 - cfg_cmp_os_11"]
        #[inline(always)]
        pub const fn cfg_cmp_os_11(&self) -> &CfgCmpOs11 {
            &self.cfg_cmp_os_11
        }
        #[doc = "0x134 - cfg_cmp_os_12"]
        #[inline(always)]
        pub const fn cfg_cmp_os_12(&self) -> &CfgCmpOs12 {
            &self.cfg_cmp_os_12
        }
        #[doc = "0x138 - rpt_cmp_os_2"]
        #[inline(always)]
        pub const fn rpt_cmp_os_2(&self) -> &RptCmpOs2 {
            &self.rpt_cmp_os_2
        }
        #[doc = "0x150 - cfg_cdac_fc0_0"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_0(&self) -> &CfgCdacFc0_0 {
            &self.cfg_cdac_fc0_0
        }
        #[doc = "0x154 - cfg_cdac_fc0_1"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_1(&self) -> &CfgCdacFc0_1 {
            &self.cfg_cdac_fc0_1
        }
        #[doc = "0x158 - cfg_cdac_fc0_2"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_2(&self) -> &CfgCdacFc0_2 {
            &self.cfg_cdac_fc0_2
        }
        #[doc = "0x15c - cfg_cdac_fc0_3"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_3(&self) -> &CfgCdacFc0_3 {
            &self.cfg_cdac_fc0_3
        }
        #[doc = "0x160 - cfg_cdac_fc0_4"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_4(&self) -> &CfgCdacFc0_4 {
            &self.cfg_cdac_fc0_4
        }
        #[doc = "0x164 - cfg_cdac_fc0_5"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_5(&self) -> &CfgCdacFc0_5 {
            &self.cfg_cdac_fc0_5
        }
        #[doc = "0x168 - rpt_cdac_fc0_0"]
        #[inline(always)]
        pub const fn rpt_cdac_fc0_0(&self) -> &RptCdacFc0_0 {
            &self.rpt_cdac_fc0_0
        }
        #[doc = "0x16c - cfg_cdac_fc0_6"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_6(&self) -> &CfgCdacFc0_6 {
            &self.cfg_cdac_fc0_6
        }
        #[doc = "0x170 - cfg_cdac_fc0_7"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_7(&self) -> &CfgCdacFc0_7 {
            &self.cfg_cdac_fc0_7
        }
        #[doc = "0x174 - cfg_cdac_fc0_8"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_8(&self) -> &CfgCdacFc0_8 {
            &self.cfg_cdac_fc0_8
        }
        #[doc = "0x178 - cfg_cdac_fc0_9"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_9(&self) -> &CfgCdacFc0_9 {
            &self.cfg_cdac_fc0_9
        }
        #[doc = "0x17c - cfg_cdac_fc0_10"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_10(&self) -> &CfgCdacFc0_10 {
            &self.cfg_cdac_fc0_10
        }
        #[doc = "0x180 - cfg_cdac_fc0_11"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_11(&self) -> &CfgCdacFc0_11 {
            &self.cfg_cdac_fc0_11
        }
        #[doc = "0x184 - cfg_cdac_fc0_12"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_12(&self) -> &CfgCdacFc0_12 {
            &self.cfg_cdac_fc0_12
        }
        #[doc = "0x188 - cfg_cdac_fc0_13"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_13(&self) -> &CfgCdacFc0_13 {
            &self.cfg_cdac_fc0_13
        }
        #[doc = "0x18c - cfg_cdac_fc0_14"]
        #[inline(always)]
        pub const fn cfg_cdac_fc0_14(&self) -> &CfgCdacFc0_14 {
            &self.cfg_cdac_fc0_14
        }
        #[doc = "0x190 - cfg_cdac_fc1_0"]
        #[inline(always)]
        pub const fn cfg_cdac_fc1_0(&self) -> &CfgCdacFc1_0 {
            &self.cfg_cdac_fc1_0
        }
        #[doc = "0x194 - cfg_cdac_fc1_1"]
        #[inline(always)]
        pub const fn cfg_cdac_fc1_1(&self) -> &CfgCdacFc1_1 {
            &self.cfg_cdac_fc1_1
        }
        #[doc = "0x198 - cfg_cdac_fc1_2"]
        #[inline(always)]
        pub const fn cfg_cdac_fc1_2(&self) -> &CfgCdacFc1_2 {
            &self.cfg_cdac_fc1_2
        }
        #[doc = "0x19c - cfg_cdac_fc1_3"]
        #[inline(always)]
        pub const fn cfg_cdac_fc1_3(&self) -> &CfgCdacFc1_3 {
            &self.cfg_cdac_fc1_3
        }
        #[doc = "0x1a0 - rpt_cdac_fc1_0"]
        #[inline(always)]
        pub const fn rpt_cdac_fc1_0(&self) -> &RptCdacFc1_0 {
            &self.rpt_cdac_fc1_0
        }
        #[doc = "0x1a4 - rpt_cdac_fc1_3"]
        #[inline(always)]
        pub const fn rpt_cdac_fc1_3(&self) -> &RptCdacFc1_3 {
            &self.rpt_cdac_fc1_3
        }
        #[doc = "0x1a8 - rpt_cdac_fc3_1"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_1(&self) -> &RptCdacFc3_1 {
            &self.rpt_cdac_fc3_1
        }
        #[doc = "0x1ac - rpt_cdac_fc3_2"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_2(&self) -> &RptCdacFc3_2 {
            &self.rpt_cdac_fc3_2
        }
        #[doc = "0x1b0 - rpt_cdac_fc3_3"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_3(&self) -> &RptCdacFc3_3 {
            &self.rpt_cdac_fc3_3
        }
        #[doc = "0x1b4 - rpt_cdac_fc3_4"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_4(&self) -> &RptCdacFc3_4 {
            &self.rpt_cdac_fc3_4
        }
        #[doc = "0x1b8 - rpt_cdac_fc3_5"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_5(&self) -> &RptCdacFc3_5 {
            &self.rpt_cdac_fc3_5
        }
        #[doc = "0x1bc - rpt_cdac_fc3_6"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_6(&self) -> &RptCdacFc3_6 {
            &self.rpt_cdac_fc3_6
        }
        #[doc = "0x1c0 - rpt_cdac_fc3_7"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_7(&self) -> &RptCdacFc3_7 {
            &self.rpt_cdac_fc3_7
        }
        #[doc = "0x1c4 - rpt_cdac_fc3_8"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_8(&self) -> &RptCdacFc3_8 {
            &self.rpt_cdac_fc3_8
        }
        #[doc = "0x1c8 - rpt_cdac_fc3_9"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_9(&self) -> &RptCdacFc3_9 {
            &self.rpt_cdac_fc3_9
        }
        #[doc = "0x1cc - rpt_cdac_fc3_10"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_10(&self) -> &RptCdacFc3_10 {
            &self.rpt_cdac_fc3_10
        }
        #[doc = "0x1d0 - rpt_cdac_fc3_11"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_11(&self) -> &RptCdacFc3_11 {
            &self.rpt_cdac_fc3_11
        }
        #[doc = "0x1d4 - rpt_cdac_fc3_12"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_12(&self) -> &RptCdacFc3_12 {
            &self.rpt_cdac_fc3_12
        }
        #[doc = "0x1d8 - rpt_cdac_fc3_13"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_13(&self) -> &RptCdacFc3_13 {
            &self.rpt_cdac_fc3_13
        }
        #[doc = "0x1dc - rpt_cdac_fc3_14"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_14(&self) -> &RptCdacFc3_14 {
            &self.rpt_cdac_fc3_14
        }
        #[doc = "0x1e0 - rpt_cdac_fc3_15"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_15(&self) -> &RptCdacFc3_15 {
            &self.rpt_cdac_fc3_15
        }
        #[doc = "0x1e4 - rpt_cdac_fc3_16"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_16(&self) -> &RptCdacFc3_16 {
            &self.rpt_cdac_fc3_16
        }
        #[doc = "0x1e8 - rpt_cdac_fc3_17"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_17(&self) -> &RptCdacFc3_17 {
            &self.rpt_cdac_fc3_17
        }
        #[doc = "0x1ec - rpt_cdac_fc3_18"]
        #[inline(always)]
        pub const fn rpt_cdac_fc3_18(&self) -> &RptCdacFc3_18 {
            &self.rpt_cdac_fc3_18
        }
        #[doc = "0x200 - cfg_dcoc_cal_0"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_0(&self) -> &CfgDcocCal0 {
            &self.cfg_dcoc_cal_0
        }
        #[doc = "0x204 - cfg_dcoc_cal_1"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_1(&self) -> &CfgDcocCal1 {
            &self.cfg_dcoc_cal_1
        }
        #[doc = "0x208 - cfg_dcoc_cal_2"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_2(&self) -> &CfgDcocCal2 {
            &self.cfg_dcoc_cal_2
        }
        #[doc = "0x20c - cfg_dcoc_cal_3"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_3(&self) -> &CfgDcocCal3 {
            &self.cfg_dcoc_cal_3
        }
        #[doc = "0x210 - cfg_dcoc_cal_4"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_4(&self) -> &CfgDcocCal4 {
            &self.cfg_dcoc_cal_4
        }
        #[doc = "0x214 - cfg_dcoc_cal_5"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_5(&self) -> &CfgDcocCal5 {
            &self.cfg_dcoc_cal_5
        }
        #[doc = "0x218 - cfg_dcoc_cal_6"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_6(&self) -> &CfgDcocCal6 {
            &self.cfg_dcoc_cal_6
        }
        #[doc = "0x21c - cfg_dcoc_cal_7"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_7(&self) -> &CfgDcocCal7 {
            &self.cfg_dcoc_cal_7
        }
        #[doc = "0x220 - cfg_dcoc_cal_8"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_8(&self) -> &CfgDcocCal8 {
            &self.cfg_dcoc_cal_8
        }
        #[doc = "0x224 - rpt_dcoc_cal_0"]
        #[inline(always)]
        pub const fn rpt_dcoc_cal_0(&self) -> &RptDcocCal0 {
            &self.rpt_dcoc_cal_0
        }
        #[doc = "0x228 - cfg_dcoc_cal_12"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_12(&self) -> &CfgDcocCal12 {
            &self.cfg_dcoc_cal_12
        }
        #[doc = "0x22c - cfg_dcoc_cal_13"]
        #[inline(always)]
        pub const fn cfg_dcoc_cal_13(&self) -> &CfgDcocCal13 {
            &self.cfg_dcoc_cal_13
        }
        #[doc = "0x230 - rpt_dcoc_cal_1"]
        #[inline(always)]
        pub const fn rpt_dcoc_cal_1(&self) -> &RptDcocCal1 {
            &self.rpt_dcoc_cal_1
        }
        #[doc = "0x240 - cfg_sar_spd_0"]
        #[inline(always)]
        pub const fn cfg_sar_spd_0(&self) -> &CfgSarSpd0 {
            &self.cfg_sar_spd_0
        }
        #[doc = "0x244 - cfg_sar_spd_1"]
        #[inline(always)]
        pub const fn cfg_sar_spd_1(&self) -> &CfgSarSpd1 {
            &self.cfg_sar_spd_1
        }
        #[doc = "0x248 - cfg_sar_spd_2"]
        #[inline(always)]
        pub const fn cfg_sar_spd_2(&self) -> &CfgSarSpd2 {
            &self.cfg_sar_spd_2
        }
        #[doc = "0x24c - cfg_sar_spd_3"]
        #[inline(always)]
        pub const fn cfg_sar_spd_3(&self) -> &CfgSarSpd3 {
            &self.cfg_sar_spd_3
        }
        #[doc = "0x250 - cfg_sar_spd_4"]
        #[inline(always)]
        pub const fn cfg_sar_spd_4(&self) -> &CfgSarSpd4 {
            &self.cfg_sar_spd_4
        }
        #[doc = "0x254 - rpt_sar_spd_0"]
        #[inline(always)]
        pub const fn rpt_sar_spd_0(&self) -> &RptSarSpd0 {
            &self.rpt_sar_spd_0
        }
        #[doc = "0x258 - rpt_sar_spd_1"]
        #[inline(always)]
        pub const fn rpt_sar_spd_1(&self) -> &RptSarSpd1 {
            &self.rpt_sar_spd_1
        }
        #[doc = "0x25c - cfg_sar_spd_6"]
        #[inline(always)]
        pub const fn cfg_sar_spd_6(&self) -> &CfgSarSpd6 {
            &self.cfg_sar_spd_6
        }
        #[doc = "0x260 - rpt_sar_spd_2"]
        #[inline(always)]
        pub const fn rpt_sar_spd_2(&self) -> &RptSarSpd2 {
            &self.rpt_sar_spd_2
        }
        #[doc = "0x280 - cfg_rc_cal_0"]
        #[inline(always)]
        pub const fn cfg_rc_cal_0(&self) -> &CfgRcCal0 {
            &self.cfg_rc_cal_0
        }
        #[doc = "0x284 - cfg_rc_cal_1"]
        #[inline(always)]
        pub const fn cfg_rc_cal_1(&self) -> &CfgRcCal1 {
            &self.cfg_rc_cal_1
        }
        #[doc = "0x288 - cfg_rc_cal_2"]
        #[inline(always)]
        pub const fn cfg_rc_cal_2(&self) -> &CfgRcCal2 {
            &self.cfg_rc_cal_2
        }
        #[doc = "0x28c - cfg_rc_cal_3"]
        #[inline(always)]
        pub const fn cfg_rc_cal_3(&self) -> &CfgRcCal3 {
            &self.cfg_rc_cal_3
        }
        #[doc = "0x290 - cfg_rc_cal_4"]
        #[inline(always)]
        pub const fn cfg_rc_cal_4(&self) -> &CfgRcCal4 {
            &self.cfg_rc_cal_4
        }
        #[doc = "0x294 - rpt_rc_cal_0"]
        #[inline(always)]
        pub const fn rpt_rc_cal_0(&self) -> &RptRcCal0 {
            &self.rpt_rc_cal_0
        }
        #[doc = "0x298 - rpt_rc_cal_1"]
        #[inline(always)]
        pub const fn rpt_rc_cal_1(&self) -> &RptRcCal1 {
            &self.rpt_rc_cal_1
        }
        #[doc = "0x29c - cfg_rc_cal_5"]
        #[inline(always)]
        pub const fn cfg_rc_cal_5(&self) -> &CfgRcCal5 {
            &self.cfg_rc_cal_5
        }
        #[doc = "0x2a0 - cfg_rc_cal_6"]
        #[inline(always)]
        pub const fn cfg_rc_cal_6(&self) -> &CfgRcCal6 {
            &self.cfg_rc_cal_6
        }
        #[doc = "0x2a4 - cfg_rc_cal_7"]
        #[inline(always)]
        pub const fn cfg_rc_cal_7(&self) -> &CfgRcCal7 {
            &self.cfg_rc_cal_7
        }
        #[doc = "0x2a8 - cfg_rc_cal_8"]
        #[inline(always)]
        pub const fn cfg_rc_cal_8(&self) -> &CfgRcCal8 {
            &self.cfg_rc_cal_8
        }
        #[doc = "0x2ac - rpt_rc_cal_2"]
        #[inline(always)]
        pub const fn rpt_rc_cal_2(&self) -> &RptRcCal2 {
            &self.rpt_rc_cal_2
        }
        #[doc = "0x2b0 - rpt_rc_cal_3"]
        #[inline(always)]
        pub const fn rpt_rc_cal_3(&self) -> &RptRcCal3 {
            &self.rpt_rc_cal_3
        }
        #[doc = "0x2c0 - cfg_amux_0"]
        #[inline(always)]
        pub const fn cfg_amux_0(&self) -> &CfgAmux0 {
            &self.cfg_amux_0
        }
        #[doc = "0x2c4 - cfg_amux_1"]
        #[inline(always)]
        pub const fn cfg_amux_1(&self) -> &CfgAmux1 {
            &self.cfg_amux_1
        }
        #[doc = "0x2c8 - cfg_amux_2"]
        #[inline(always)]
        pub const fn cfg_amux_2(&self) -> &CfgAmux2 {
            &self.cfg_amux_2
        }
        #[doc = "0x2cc - cfg_amux_3"]
        #[inline(always)]
        pub const fn cfg_amux_3(&self) -> &CfgAmux3 {
            &self.cfg_amux_3
        }
        #[doc = "0x2d0 - cfg_amux_4"]
        #[inline(always)]
        pub const fn cfg_amux_4(&self) -> &CfgAmux4 {
            &self.cfg_amux_4
        }
        #[doc = "0x2d4 - cfg_amux_5"]
        #[inline(always)]
        pub const fn cfg_amux_5(&self) -> &CfgAmux5 {
            &self.cfg_amux_5
        }
        #[doc = "0x2d8 - rpt_amux_0"]
        #[inline(always)]
        pub const fn rpt_amux_0(&self) -> &RptAmux0 {
            &self.rpt_amux_0
        }
        #[doc = "0x2f0 - cfg_tst_0"]
        #[inline(always)]
        pub const fn cfg_tst_0(&self) -> &CfgTst0 {
            &self.cfg_tst_0
        }
        #[doc = "0x2f4 - cfg_tst_1"]
        #[inline(always)]
        pub const fn cfg_tst_1(&self) -> &CfgTst1 {
            &self.cfg_tst_1
        }
        #[doc = "0x2f8 - cfg_cmp_0"]
        #[inline(always)]
        pub const fn cfg_cmp_0(&self) -> &CfgCmp0 {
            &self.cfg_cmp_0
        }
        #[doc = "0x2fc - cfg_cmp_1"]
        #[inline(always)]
        pub const fn cfg_cmp_1(&self) -> &CfgCmp1 {
            &self.cfg_cmp_1
        }
        #[doc = "0x300 - rpt_cmp_0"]
        #[inline(always)]
        pub const fn rpt_cmp_0(&self) -> &RptCmp0 {
            &self.rpt_cmp_0
        }
        #[doc = "0x304 - rpt_cmp_1"]
        #[inline(always)]
        pub const fn rpt_cmp_1(&self) -> &RptCmp1 {
            &self.rpt_cmp_1
        }
    }
    #[doc = "CFG_RSTN (rw) register accessor: cfg_rstn\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rstn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rstn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rstn`] module"]
    #[doc(alias = "CFG_RSTN")]
    pub type CfgRstn = crate::Reg<cfg_rstn::CfgRstnSpec>;
    #[doc = "cfg_rstn"]
    pub mod cfg_rstn {
        #[doc = "Register `CFG_RSTN` reader"]
        pub type R = crate::R<CfgRstnSpec>;
        #[doc = "Register `CFG_RSTN` writer"]
        pub type W = crate::W<CfgRstnSpec>;
        #[doc = "Field `cfg_rstn_tst` reader - "]
        pub type CfgRstnTstR = crate::BitReader;
        #[doc = "Field `cfg_rstn_tst` writer - "]
        pub type CfgRstnTstW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cfg_gadc_rstn_bc` reader - "]
        pub type CfgGadcRstnBcR = crate::BitReader;
        #[doc = "Field `cfg_gadc_rstn_bc` writer - "]
        pub type CfgGadcRstnBcW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cfg_gadc_rstn_fc` reader - "]
        pub type CfgGadcRstnFcR = crate::BitReader;
        #[doc = "Field `cfg_gadc_rstn_fc` writer - "]
        pub type CfgGadcRstnFcW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cfg_gadc_rstn_data` reader - "]
        pub type CfgGadcRstnDataR = crate::BitReader;
        #[doc = "Field `cfg_gadc_rstn_data` writer - "]
        pub type CfgGadcRstnDataW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cfg_gadc_rstn_ana` reader - "]
        pub type CfgGadcRstnAnaR = crate::BitReader;
        #[doc = "Field `cfg_gadc_rstn_ana` writer - "]
        pub type CfgGadcRstnAnaW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn cfg_rstn_tst(&self) -> CfgRstnTstR {
                CfgRstnTstR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn cfg_gadc_rstn_bc(&self) -> CfgGadcRstnBcR {
                CfgGadcRstnBcR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cfg_gadc_rstn_fc(&self) -> CfgGadcRstnFcR {
                CfgGadcRstnFcR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn cfg_gadc_rstn_data(&self) -> CfgGadcRstnDataR {
                CfgGadcRstnDataR::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn cfg_gadc_rstn_ana(&self) -> CfgGadcRstnAnaR {
                CfgGadcRstnAnaR::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn cfg_rstn_tst(&mut self) -> CfgRstnTstW<'_, CfgRstnSpec> {
                CfgRstnTstW::new(self, 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn cfg_gadc_rstn_bc(&mut self) -> CfgGadcRstnBcW<'_, CfgRstnSpec> {
                CfgGadcRstnBcW::new(self, 4)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cfg_gadc_rstn_fc(&mut self) -> CfgGadcRstnFcW<'_, CfgRstnSpec> {
                CfgGadcRstnFcW::new(self, 8)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn cfg_gadc_rstn_data(&mut self) -> CfgGadcRstnDataW<'_, CfgRstnSpec> {
                CfgGadcRstnDataW::new(self, 12)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn cfg_gadc_rstn_ana(&mut self) -> CfgGadcRstnAnaW<'_, CfgRstnSpec> {
                CfgGadcRstnAnaW::new(self, 16)
            }
        }
        #[doc = "cfg_rstn\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rstn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rstn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRstnSpec;
        impl crate::RegisterSpec for CfgRstnSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rstn::R`](R) reader structure"]
        impl crate::Readable for CfgRstnSpec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rstn::W`](W) writer structure"]
        impl crate::Writable for CfgRstnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RSTN to value 0"]
        impl crate::Resettable for CfgRstnSpec {}
    }
    #[doc = "CFG_CLKEN (rw) register accessor: cfg_clken\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clken::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clken::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_clken`] module"]
    #[doc(alias = "CFG_CLKEN")]
    pub type CfgClken = crate::Reg<cfg_clken::CfgClkenSpec>;
    #[doc = "cfg_clken"]
    pub mod cfg_clken {
        #[doc = "Register `CFG_CLKEN` reader"]
        pub type R = crate::R<CfgClkenSpec>;
        #[doc = "Register `CFG_CLKEN` writer"]
        pub type W = crate::W<CfgClkenSpec>;
        #[doc = "Field `cfg_clken_tst` reader - "]
        pub type CfgClkenTstR = crate::BitReader;
        #[doc = "Field `cfg_clken_tst` writer - "]
        pub type CfgClkenTstW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cfg_gadc_clken_bc` reader - "]
        pub type CfgGadcClkenBcR = crate::BitReader;
        #[doc = "Field `cfg_gadc_clken_bc` writer - "]
        pub type CfgGadcClkenBcW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cfg_gadc_clken_fc` reader - "]
        pub type CfgGadcClkenFcR = crate::BitReader;
        #[doc = "Field `cfg_gadc_clken_fc` writer - "]
        pub type CfgGadcClkenFcW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cfg_gadc_clken_byp` reader - "]
        pub type CfgGadcClkenBypR = crate::BitReader;
        #[doc = "Field `cfg_gadc_clken_byp` writer - "]
        pub type CfgGadcClkenBypW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cfg_gadc_clken_prechg` reader - "]
        pub type CfgGadcClkenPrechgR = crate::BitReader;
        #[doc = "Field `cfg_gadc_clken_prechg` writer - "]
        pub type CfgGadcClkenPrechgW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cfg_gadc_clken_ctrl` reader - "]
        pub type CfgGadcClkenCtrlR = crate::BitReader;
        #[doc = "Field `cfg_gadc_clken_ctrl` writer - "]
        pub type CfgGadcClkenCtrlW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn cfg_clken_tst(&self) -> CfgClkenTstR {
                CfgClkenTstR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn cfg_gadc_clken_bc(&self) -> CfgGadcClkenBcR {
                CfgGadcClkenBcR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cfg_gadc_clken_fc(&self) -> CfgGadcClkenFcR {
                CfgGadcClkenFcR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn cfg_gadc_clken_byp(&self) -> CfgGadcClkenBypR {
                CfgGadcClkenBypR::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn cfg_gadc_clken_prechg(&self) -> CfgGadcClkenPrechgR {
                CfgGadcClkenPrechgR::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn cfg_gadc_clken_ctrl(&self) -> CfgGadcClkenCtrlR {
                CfgGadcClkenCtrlR::new(((self.bits >> 20) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn cfg_clken_tst(&mut self) -> CfgClkenTstW<'_, CfgClkenSpec> {
                CfgClkenTstW::new(self, 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn cfg_gadc_clken_bc(&mut self) -> CfgGadcClkenBcW<'_, CfgClkenSpec> {
                CfgGadcClkenBcW::new(self, 4)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cfg_gadc_clken_fc(&mut self) -> CfgGadcClkenFcW<'_, CfgClkenSpec> {
                CfgGadcClkenFcW::new(self, 8)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn cfg_gadc_clken_byp(&mut self) -> CfgGadcClkenBypW<'_, CfgClkenSpec> {
                CfgGadcClkenBypW::new(self, 12)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn cfg_gadc_clken_prechg(&mut self) -> CfgGadcClkenPrechgW<'_, CfgClkenSpec> {
                CfgGadcClkenPrechgW::new(self, 16)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn cfg_gadc_clken_ctrl(&mut self) -> CfgGadcClkenCtrlW<'_, CfgClkenSpec> {
                CfgGadcClkenCtrlW::new(self, 20)
            }
        }
        #[doc = "cfg_clken\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clken::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clken::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgClkenSpec;
        impl crate::RegisterSpec for CfgClkenSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_clken::R`](R) reader structure"]
        impl crate::Readable for CfgClkenSpec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_clken::W`](W) writer structure"]
        impl crate::Writable for CfgClkenSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CLKEN to value 0"]
        impl crate::Resettable for CfgClkenSpec {}
    }
    #[doc = "CFG_PRECHG_LEAD (rw) register accessor: cfg_prechg_lead\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_prechg_lead::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_prechg_lead::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_prechg_lead`] module"]
    #[doc(alias = "CFG_PRECHG_LEAD")]
    pub type CfgPrechgLead = crate::Reg<cfg_prechg_lead::CfgPrechgLeadSpec>;
    #[doc = "cfg_prechg_lead"]
    pub mod cfg_prechg_lead {
        #[doc = "Register `CFG_PRECHG_LEAD` reader"]
        pub type R = crate::R<CfgPrechgLeadSpec>;
        #[doc = "Register `CFG_PRECHG_LEAD` writer"]
        pub type W = crate::W<CfgPrechgLeadSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_prechg_lead\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_prechg_lead::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_prechg_lead::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgPrechgLeadSpec;
        impl crate::RegisterSpec for CfgPrechgLeadSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_prechg_lead::R`](R) reader structure"]
        impl crate::Readable for CfgPrechgLeadSpec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_prechg_lead::W`](W) writer structure"]
        impl crate::Writable for CfgPrechgLeadSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_PRECHG_LEAD to value 0"]
        impl crate::Resettable for CfgPrechgLeadSpec {}
    }
    #[doc = "CFG_CLK_DIV_0 (rw) register accessor: cfg_clk_div_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clk_div_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clk_div_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_clk_div_0`] module"]
    #[doc(alias = "CFG_CLK_DIV_0")]
    pub type CfgClkDiv0 = crate::Reg<cfg_clk_div_0::CfgClkDiv0Spec>;
    #[doc = "cfg_clk_div_0"]
    pub mod cfg_clk_div_0 {
        #[doc = "Register `CFG_CLK_DIV_0` reader"]
        pub type R = crate::R<CfgClkDiv0Spec>;
        #[doc = "Register `CFG_CLK_DIV_0` writer"]
        pub type W = crate::W<CfgClkDiv0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_clk_div_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clk_div_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clk_div_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgClkDiv0Spec;
        impl crate::RegisterSpec for CfgClkDiv0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_clk_div_0::R`](R) reader structure"]
        impl crate::Readable for CfgClkDiv0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_clk_div_0::W`](W) writer structure"]
        impl crate::Writable for CfgClkDiv0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CLK_DIV_0 to value 0"]
        impl crate::Resettable for CfgClkDiv0Spec {}
    }
    #[doc = "CFG_CLK_DIV_1 (rw) register accessor: cfg_clk_div_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clk_div_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clk_div_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_clk_div_1`] module"]
    #[doc(alias = "CFG_CLK_DIV_1")]
    pub type CfgClkDiv1 = crate::Reg<cfg_clk_div_1::CfgClkDiv1Spec>;
    #[doc = "cfg_clk_div_1"]
    pub mod cfg_clk_div_1 {
        #[doc = "Register `CFG_CLK_DIV_1` reader"]
        pub type R = crate::R<CfgClkDiv1Spec>;
        #[doc = "Register `CFG_CLK_DIV_1` writer"]
        pub type W = crate::W<CfgClkDiv1Spec>;
        #[doc = "Field `ana_div_th` reader - "]
        pub type AnaDivThR = crate::FieldReader<u16>;
        #[doc = "Field `ana_div_th` writer - "]
        pub type AnaDivThW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `prechg_div_th` reader - "]
        pub type PrechgDivThR = crate::FieldReader<u16>;
        #[doc = "Field `prechg_div_th` writer - "]
        pub type PrechgDivThW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        impl R {
            #[doc = "Bits 0:11"]
            #[inline(always)]
            pub fn ana_div_th(&self) -> AnaDivThR {
                AnaDivThR::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bits 12:23"]
            #[inline(always)]
            pub fn prechg_div_th(&self) -> PrechgDivThR {
                PrechgDivThR::new(((self.bits >> 12) & 0x0fff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:11"]
            #[inline(always)]
            pub fn ana_div_th(&mut self) -> AnaDivThW<'_, CfgClkDiv1Spec> {
                AnaDivThW::new(self, 0)
            }
            #[doc = "Bits 12:23"]
            #[inline(always)]
            pub fn prechg_div_th(&mut self) -> PrechgDivThW<'_, CfgClkDiv1Spec> {
                PrechgDivThW::new(self, 12)
            }
        }
        #[doc = "cfg_clk_div_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_clk_div_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_clk_div_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgClkDiv1Spec;
        impl crate::RegisterSpec for CfgClkDiv1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_clk_div_1::R`](R) reader structure"]
        impl crate::Readable for CfgClkDiv1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_clk_div_1::W`](W) writer structure"]
        impl crate::Writable for CfgClkDiv1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CLK_DIV_1 to value 0"]
        impl crate::Resettable for CfgClkDiv1Spec {}
    }
    #[doc = "CFG_MANUAL_CLK_0 (rw) register accessor: cfg_manual_clk_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_manual_clk_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_manual_clk_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_manual_clk_0`] module"]
    #[doc(alias = "CFG_MANUAL_CLK_0")]
    pub type CfgManualClk0 = crate::Reg<cfg_manual_clk_0::CfgManualClk0Spec>;
    #[doc = "cfg_manual_clk_0"]
    pub mod cfg_manual_clk_0 {
        #[doc = "Register `CFG_MANUAL_CLK_0` reader"]
        pub type R = crate::R<CfgManualClk0Spec>;
        #[doc = "Register `CFG_MANUAL_CLK_0` writer"]
        pub type W = crate::W<CfgManualClk0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_manual_clk_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_manual_clk_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_manual_clk_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgManualClk0Spec;
        impl crate::RegisterSpec for CfgManualClk0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_manual_clk_0::R`](R) reader structure"]
        impl crate::Readable for CfgManualClk0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_manual_clk_0::W`](W) writer structure"]
        impl crate::Writable for CfgManualClk0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_MANUAL_CLK_0 to value 0"]
        impl crate::Resettable for CfgManualClk0Spec {}
    }
    #[doc = "CFG_MANUAL_CLK_1 (rw) register accessor: cfg_manual_clk_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_manual_clk_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_manual_clk_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_manual_clk_1`] module"]
    #[doc(alias = "CFG_MANUAL_CLK_1")]
    pub type CfgManualClk1 = crate::Reg<cfg_manual_clk_1::CfgManualClk1Spec>;
    #[doc = "cfg_manual_clk_1"]
    pub mod cfg_manual_clk_1 {
        #[doc = "Register `CFG_MANUAL_CLK_1` reader"]
        pub type R = crate::R<CfgManualClk1Spec>;
        #[doc = "Register `CFG_MANUAL_CLK_1` writer"]
        pub type W = crate::W<CfgManualClk1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_manual_clk_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_manual_clk_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_manual_clk_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgManualClk1Spec;
        impl crate::RegisterSpec for CfgManualClk1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_manual_clk_1::R`](R) reader structure"]
        impl crate::Readable for CfgManualClk1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_manual_clk_1::W`](W) writer structure"]
        impl crate::Writable for CfgManualClk1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_MANUAL_CLK_1 to value 0"]
        impl crate::Resettable for CfgManualClk1Spec {}
    }
    #[doc = "CFG_ISO (rw) register accessor: cfg_iso\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_iso::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_iso::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_iso`] module"]
    #[doc(alias = "CFG_ISO")]
    pub type CfgIso = crate::Reg<cfg_iso::CfgIsoSpec>;
    #[doc = "cfg_iso"]
    pub mod cfg_iso {
        #[doc = "Register `CFG_ISO` reader"]
        pub type R = crate::R<CfgIsoSpec>;
        #[doc = "Register `CFG_ISO` writer"]
        pub type W = crate::W<CfgIsoSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_iso\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_iso::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_iso::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgIsoSpec;
        impl crate::RegisterSpec for CfgIsoSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_iso::R`](R) reader structure"]
        impl crate::Readable for CfgIsoSpec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_iso::W`](W) writer structure"]
        impl crate::Writable for CfgIsoSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_ISO to value 0"]
        impl crate::Resettable for CfgIsoSpec {}
    }
    #[doc = "CFG_GADC_CTRL_0 (rw) register accessor: cfg_gadc_ctrl_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_0`] module"]
    #[doc(alias = "CFG_GADC_CTRL_0")]
    pub type CfgGadcCtrl0 = crate::Reg<cfg_gadc_ctrl_0::CfgGadcCtrl0Spec>;
    #[doc = "cfg_gadc_ctrl_0"]
    pub mod cfg_gadc_ctrl_0 {
        #[doc = "Register `CFG_GADC_CTRL_0` reader"]
        pub type R = crate::R<CfgGadcCtrl0Spec>;
        #[doc = "Register `CFG_GADC_CTRL_0` writer"]
        pub type W = crate::W<CfgGadcCtrl0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_ctrl_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcCtrl0Spec;
        impl crate::RegisterSpec for CfgGadcCtrl0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_ctrl_0::R`](R) reader structure"]
        impl crate::Readable for CfgGadcCtrl0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_0::W`](W) writer structure"]
        impl crate::Writable for CfgGadcCtrl0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_CTRL_0 to value 0"]
        impl crate::Resettable for CfgGadcCtrl0Spec {}
    }
    #[doc = "CFG_GADC_CTRL_1 (rw) register accessor: cfg_gadc_ctrl_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_1`] module"]
    #[doc(alias = "CFG_GADC_CTRL_1")]
    pub type CfgGadcCtrl1 = crate::Reg<cfg_gadc_ctrl_1::CfgGadcCtrl1Spec>;
    #[doc = "cfg_gadc_ctrl_1"]
    pub mod cfg_gadc_ctrl_1 {
        #[doc = "Register `CFG_GADC_CTRL_1` reader"]
        pub type R = crate::R<CfgGadcCtrl1Spec>;
        #[doc = "Register `CFG_GADC_CTRL_1` writer"]
        pub type W = crate::W<CfgGadcCtrl1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_ctrl_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcCtrl1Spec;
        impl crate::RegisterSpec for CfgGadcCtrl1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_ctrl_1::R`](R) reader structure"]
        impl crate::Readable for CfgGadcCtrl1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_1::W`](W) writer structure"]
        impl crate::Writable for CfgGadcCtrl1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_CTRL_1 to value 0"]
        impl crate::Resettable for CfgGadcCtrl1Spec {}
    }
    #[doc = "CFG_GADC_CTRL_2 (rw) register accessor: cfg_gadc_ctrl_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_2`] module"]
    #[doc(alias = "CFG_GADC_CTRL_2")]
    pub type CfgGadcCtrl2 = crate::Reg<cfg_gadc_ctrl_2::CfgGadcCtrl2Spec>;
    #[doc = "cfg_gadc_ctrl_2"]
    pub mod cfg_gadc_ctrl_2 {
        #[doc = "Register `CFG_GADC_CTRL_2` reader"]
        pub type R = crate::R<CfgGadcCtrl2Spec>;
        #[doc = "Register `CFG_GADC_CTRL_2` writer"]
        pub type W = crate::W<CfgGadcCtrl2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_ctrl_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcCtrl2Spec;
        impl crate::RegisterSpec for CfgGadcCtrl2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_ctrl_2::R`](R) reader structure"]
        impl crate::Readable for CfgGadcCtrl2Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_2::W`](W) writer structure"]
        impl crate::Writable for CfgGadcCtrl2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_CTRL_2 to value 0"]
        impl crate::Resettable for CfgGadcCtrl2Spec {}
    }
    #[doc = "CFG_GADC_CTRL_3 (rw) register accessor: cfg_gadc_ctrl_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_3`] module"]
    #[doc(alias = "CFG_GADC_CTRL_3")]
    pub type CfgGadcCtrl3 = crate::Reg<cfg_gadc_ctrl_3::CfgGadcCtrl3Spec>;
    #[doc = "cfg_gadc_ctrl_3"]
    pub mod cfg_gadc_ctrl_3 {
        #[doc = "Register `CFG_GADC_CTRL_3` reader"]
        pub type R = crate::R<CfgGadcCtrl3Spec>;
        #[doc = "Register `CFG_GADC_CTRL_3` writer"]
        pub type W = crate::W<CfgGadcCtrl3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_ctrl_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcCtrl3Spec;
        impl crate::RegisterSpec for CfgGadcCtrl3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_ctrl_3::R`](R) reader structure"]
        impl crate::Readable for CfgGadcCtrl3Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_3::W`](W) writer structure"]
        impl crate::Writable for CfgGadcCtrl3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_CTRL_3 to value 0"]
        impl crate::Resettable for CfgGadcCtrl3Spec {}
    }
    #[doc = "CFG_GADC_CTRL_4 (rw) register accessor: cfg_gadc_ctrl_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_4`] module"]
    #[doc(alias = "CFG_GADC_CTRL_4")]
    pub type CfgGadcCtrl4 = crate::Reg<cfg_gadc_ctrl_4::CfgGadcCtrl4Spec>;
    #[doc = "cfg_gadc_ctrl_4"]
    pub mod cfg_gadc_ctrl_4 {
        #[doc = "Register `CFG_GADC_CTRL_4` reader"]
        pub type R = crate::R<CfgGadcCtrl4Spec>;
        #[doc = "Register `CFG_GADC_CTRL_4` writer"]
        pub type W = crate::W<CfgGadcCtrl4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_ctrl_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcCtrl4Spec;
        impl crate::RegisterSpec for CfgGadcCtrl4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_ctrl_4::R`](R) reader structure"]
        impl crate::Readable for CfgGadcCtrl4Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_4::W`](W) writer structure"]
        impl crate::Writable for CfgGadcCtrl4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_CTRL_4 to value 0"]
        impl crate::Resettable for CfgGadcCtrl4Spec {}
    }
    #[doc = "RPT_GADC_CTRL_0 (rw) register accessor: rpt_gadc_ctrl_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_ctrl_0`] module"]
    #[doc(alias = "RPT_GADC_CTRL_0")]
    pub type RptGadcCtrl0 = crate::Reg<rpt_gadc_ctrl_0::RptGadcCtrl0Spec>;
    #[doc = "rpt_gadc_ctrl_0"]
    pub mod rpt_gadc_ctrl_0 {
        #[doc = "Register `RPT_GADC_CTRL_0` reader"]
        pub type R = crate::R<RptGadcCtrl0Spec>;
        #[doc = "Register `RPT_GADC_CTRL_0` writer"]
        pub type W = crate::W<RptGadcCtrl0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_ctrl_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcCtrl0Spec;
        impl crate::RegisterSpec for RptGadcCtrl0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_ctrl_0::R`](R) reader structure"]
        impl crate::Readable for RptGadcCtrl0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_ctrl_0::W`](W) writer structure"]
        impl crate::Writable for RptGadcCtrl0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_CTRL_0 to value 0"]
        impl crate::Resettable for RptGadcCtrl0Spec {}
    }
    #[doc = "CFG_GADC_CTRL_5 (rw) register accessor: cfg_gadc_ctrl_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_5`] module"]
    #[doc(alias = "CFG_GADC_CTRL_5")]
    pub type CfgGadcCtrl5 = crate::Reg<cfg_gadc_ctrl_5::CfgGadcCtrl5Spec>;
    #[doc = "cfg_gadc_ctrl_5"]
    pub mod cfg_gadc_ctrl_5 {
        #[doc = "Register `CFG_GADC_CTRL_5` reader"]
        pub type R = crate::R<CfgGadcCtrl5Spec>;
        #[doc = "Register `CFG_GADC_CTRL_5` writer"]
        pub type W = crate::W<CfgGadcCtrl5Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_ctrl_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcCtrl5Spec;
        impl crate::RegisterSpec for CfgGadcCtrl5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_ctrl_5::R`](R) reader structure"]
        impl crate::Readable for CfgGadcCtrl5Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_5::W`](W) writer structure"]
        impl crate::Writable for CfgGadcCtrl5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_CTRL_5 to value 0"]
        impl crate::Resettable for CfgGadcCtrl5Spec {}
    }
    #[doc = "CFG_GADC_CTRL_6 (rw) register accessor: cfg_gadc_ctrl_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_6`] module"]
    #[doc(alias = "CFG_GADC_CTRL_6")]
    pub type CfgGadcCtrl6 = crate::Reg<cfg_gadc_ctrl_6::CfgGadcCtrl6Spec>;
    #[doc = "cfg_gadc_ctrl_6"]
    pub mod cfg_gadc_ctrl_6 {
        #[doc = "Register `CFG_GADC_CTRL_6` reader"]
        pub type R = crate::R<CfgGadcCtrl6Spec>;
        #[doc = "Register `CFG_GADC_CTRL_6` writer"]
        pub type W = crate::W<CfgGadcCtrl6Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_ctrl_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcCtrl6Spec;
        impl crate::RegisterSpec for CfgGadcCtrl6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_ctrl_6::R`](R) reader structure"]
        impl crate::Readable for CfgGadcCtrl6Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_6::W`](W) writer structure"]
        impl crate::Writable for CfgGadcCtrl6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_CTRL_6 to value 0"]
        impl crate::Resettable for CfgGadcCtrl6Spec {}
    }
    #[doc = "RPT_GADC_CTRL_1 (rw) register accessor: rpt_gadc_ctrl_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_ctrl_1`] module"]
    #[doc(alias = "RPT_GADC_CTRL_1")]
    pub type RptGadcCtrl1 = crate::Reg<rpt_gadc_ctrl_1::RptGadcCtrl1Spec>;
    #[doc = "rpt_gadc_ctrl_1"]
    pub mod rpt_gadc_ctrl_1 {
        #[doc = "Register `RPT_GADC_CTRL_1` reader"]
        pub type R = crate::R<RptGadcCtrl1Spec>;
        #[doc = "Register `RPT_GADC_CTRL_1` writer"]
        pub type W = crate::W<RptGadcCtrl1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_ctrl_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcCtrl1Spec;
        impl crate::RegisterSpec for RptGadcCtrl1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_ctrl_1::R`](R) reader structure"]
        impl crate::Readable for RptGadcCtrl1Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_ctrl_1::W`](W) writer structure"]
        impl crate::Writable for RptGadcCtrl1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_CTRL_1 to value 0"]
        impl crate::Resettable for RptGadcCtrl1Spec {}
    }
    #[doc = "CFG_GADC_CTRL_7 (rw) register accessor: cfg_gadc_ctrl_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_ctrl_7`] module"]
    #[doc(alias = "CFG_GADC_CTRL_7")]
    pub type CfgGadcCtrl7 = crate::Reg<cfg_gadc_ctrl_7::CfgGadcCtrl7Spec>;
    #[doc = "cfg_gadc_ctrl_7"]
    pub mod cfg_gadc_ctrl_7 {
        #[doc = "Register `CFG_GADC_CTRL_7` reader"]
        pub type R = crate::R<CfgGadcCtrl7Spec>;
        #[doc = "Register `CFG_GADC_CTRL_7` writer"]
        pub type W = crate::W<CfgGadcCtrl7Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_ctrl_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_ctrl_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_ctrl_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcCtrl7Spec;
        impl crate::RegisterSpec for CfgGadcCtrl7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_ctrl_7::R`](R) reader structure"]
        impl crate::Readable for CfgGadcCtrl7Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_ctrl_7::W`](W) writer structure"]
        impl crate::Writable for CfgGadcCtrl7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_CTRL_7 to value 0"]
        impl crate::Resettable for CfgGadcCtrl7Spec {}
    }
    #[doc = "RPT_GADC_CTRL_2 (rw) register accessor: rpt_gadc_ctrl_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_ctrl_2`] module"]
    #[doc(alias = "RPT_GADC_CTRL_2")]
    pub type RptGadcCtrl2 = crate::Reg<rpt_gadc_ctrl_2::RptGadcCtrl2Spec>;
    #[doc = "rpt_gadc_ctrl_2"]
    pub mod rpt_gadc_ctrl_2 {
        #[doc = "Register `RPT_GADC_CTRL_2` reader"]
        pub type R = crate::R<RptGadcCtrl2Spec>;
        #[doc = "Register `RPT_GADC_CTRL_2` writer"]
        pub type W = crate::W<RptGadcCtrl2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_ctrl_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_ctrl_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_ctrl_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcCtrl2Spec;
        impl crate::RegisterSpec for RptGadcCtrl2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_ctrl_2::R`](R) reader structure"]
        impl crate::Readable for RptGadcCtrl2Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_ctrl_2::W`](W) writer structure"]
        impl crate::Writable for RptGadcCtrl2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_CTRL_2 to value 0"]
        impl crate::Resettable for RptGadcCtrl2Spec {}
    }
    #[doc = "CFG_GADC_DATA_0 (rw) register accessor: cfg_gadc_data_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_0`] module"]
    #[doc(alias = "CFG_GADC_DATA_0")]
    pub type CfgGadcData0 = crate::Reg<cfg_gadc_data_0::CfgGadcData0Spec>;
    #[doc = "cfg_gadc_data_0"]
    pub mod cfg_gadc_data_0 {
        #[doc = "Register `CFG_GADC_DATA_0` reader"]
        pub type R = crate::R<CfgGadcData0Spec>;
        #[doc = "Register `CFG_GADC_DATA_0` writer"]
        pub type W = crate::W<CfgGadcData0Spec>;
        #[doc = "Field `data_num` reader - "]
        pub type DataNumR = crate::FieldReader<u16>;
        #[doc = "Field `data_num` writer - "]
        pub type DataNumW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
        #[doc = "Field `wait_num` reader - "]
        pub type WaitNumR = crate::FieldReader;
        #[doc = "Field `wait_num` writer - "]
        pub type WaitNumW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:9"]
            #[inline(always)]
            pub fn data_num(&self) -> DataNumR {
                DataNumR::new((self.bits & 0x03ff) as u16)
            }
            #[doc = "Bits 12:14"]
            #[inline(always)]
            pub fn wait_num(&self) -> WaitNumR {
                WaitNumR::new(((self.bits >> 12) & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:9"]
            #[inline(always)]
            pub fn data_num(&mut self) -> DataNumW<'_, CfgGadcData0Spec> {
                DataNumW::new(self, 0)
            }
            #[doc = "Bits 12:14"]
            #[inline(always)]
            pub fn wait_num(&mut self) -> WaitNumW<'_, CfgGadcData0Spec> {
                WaitNumW::new(self, 12)
            }
        }
        #[doc = "cfg_gadc_data_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData0Spec;
        impl crate::RegisterSpec for CfgGadcData0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_0::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_0::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_0 to value 0"]
        impl crate::Resettable for CfgGadcData0Spec {}
    }
    #[doc = "CFG_GADC_DATA_1 (rw) register accessor: cfg_gadc_data_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_1`] module"]
    #[doc(alias = "CFG_GADC_DATA_1")]
    pub type CfgGadcData1 = crate::Reg<cfg_gadc_data_1::CfgGadcData1Spec>;
    #[doc = "cfg_gadc_data_1"]
    pub mod cfg_gadc_data_1 {
        #[doc = "Register `CFG_GADC_DATA_1` reader"]
        pub type R = crate::R<CfgGadcData1Spec>;
        #[doc = "Register `CFG_GADC_DATA_1` writer"]
        pub type W = crate::W<CfgGadcData1Spec>;
        #[doc = "Field `osr_len` reader - "]
        pub type OsrLenR = crate::FieldReader;
        #[doc = "Field `osr_len` writer - "]
        pub type OsrLenW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `osr_sel` reader - "]
        pub type OsrSelR = crate::FieldReader;
        #[doc = "Field `osr_sel` writer - "]
        pub type OsrSelW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `osr_wait_num` reader - "]
        pub type OsrWaitNumR = crate::FieldReader;
        #[doc = "Field `osr_wait_num` writer - "]
        pub type OsrWaitNumW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn osr_len(&self) -> OsrLenR {
                OsrLenR::new((self.bits & 7) as u8)
            }
            #[doc = "Bits 4:6"]
            #[inline(always)]
            pub fn osr_sel(&self) -> OsrSelR {
                OsrSelR::new(((self.bits >> 4) & 7) as u8)
            }
            #[doc = "Bits 8:13"]
            #[inline(always)]
            pub fn osr_wait_num(&self) -> OsrWaitNumR {
                OsrWaitNumR::new(((self.bits >> 8) & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn osr_len(&mut self) -> OsrLenW<'_, CfgGadcData1Spec> {
                OsrLenW::new(self, 0)
            }
            #[doc = "Bits 4:6"]
            #[inline(always)]
            pub fn osr_sel(&mut self) -> OsrSelW<'_, CfgGadcData1Spec> {
                OsrSelW::new(self, 4)
            }
            #[doc = "Bits 8:13"]
            #[inline(always)]
            pub fn osr_wait_num(&mut self) -> OsrWaitNumW<'_, CfgGadcData1Spec> {
                OsrWaitNumW::new(self, 8)
            }
        }
        #[doc = "cfg_gadc_data_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData1Spec;
        impl crate::RegisterSpec for CfgGadcData1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_1::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_1::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_1 to value 0"]
        impl crate::Resettable for CfgGadcData1Spec {}
    }
    #[doc = "RPT_GADC_DATA_0 (rw) register accessor: rpt_gadc_data_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_0`] module"]
    #[doc(alias = "RPT_GADC_DATA_0")]
    pub type RptGadcData0 = crate::Reg<rpt_gadc_data_0::RptGadcData0Spec>;
    #[doc = "rpt_gadc_data_0"]
    pub mod rpt_gadc_data_0 {
        #[doc = "Register `RPT_GADC_DATA_0` reader"]
        pub type R = crate::R<RptGadcData0Spec>;
        #[doc = "Register `RPT_GADC_DATA_0` writer"]
        pub type W = crate::W<RptGadcData0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData0Spec;
        impl crate::RegisterSpec for RptGadcData0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_0::R`](R) reader structure"]
        impl crate::Readable for RptGadcData0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_0::W`](W) writer structure"]
        impl crate::Writable for RptGadcData0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_0 to value 0"]
        impl crate::Resettable for RptGadcData0Spec {}
    }
    #[doc = "RPT_GADC_DATA_1 (rw) register accessor: rpt_gadc_data_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_1`] module"]
    #[doc(alias = "RPT_GADC_DATA_1")]
    pub type RptGadcData1 = crate::Reg<rpt_gadc_data_1::RptGadcData1Spec>;
    #[doc = "rpt_gadc_data_1"]
    pub mod rpt_gadc_data_1 {
        #[doc = "Register `RPT_GADC_DATA_1` reader"]
        pub type R = crate::R<RptGadcData1Spec>;
        #[doc = "Register `RPT_GADC_DATA_1` writer"]
        pub type W = crate::W<RptGadcData1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData1Spec;
        impl crate::RegisterSpec for RptGadcData1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_1::R`](R) reader structure"]
        impl crate::Readable for RptGadcData1Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_1::W`](W) writer structure"]
        impl crate::Writable for RptGadcData1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_1 to value 0"]
        impl crate::Resettable for RptGadcData1Spec {}
    }
    #[doc = "RPT_GADC_DATA_2 (rw) register accessor: rpt_gadc_data_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_2`] module"]
    #[doc(alias = "RPT_GADC_DATA_2")]
    pub type RptGadcData2 = crate::Reg<rpt_gadc_data_2::RptGadcData2Spec>;
    #[doc = "rpt_gadc_data_2"]
    pub mod rpt_gadc_data_2 {
        #[doc = "Register `RPT_GADC_DATA_2` reader"]
        pub type R = crate::R<RptGadcData2Spec>;
        #[doc = "Register `RPT_GADC_DATA_2` writer"]
        pub type W = crate::W<RptGadcData2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData2Spec;
        impl crate::RegisterSpec for RptGadcData2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_2::R`](R) reader structure"]
        impl crate::Readable for RptGadcData2Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_2::W`](W) writer structure"]
        impl crate::Writable for RptGadcData2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_2 to value 0"]
        impl crate::Resettable for RptGadcData2Spec {}
    }
    #[doc = "RPT_GADC_DATA_3 (rw) register accessor: rpt_gadc_data_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_3`] module"]
    #[doc(alias = "RPT_GADC_DATA_3")]
    pub type RptGadcData3 = crate::Reg<rpt_gadc_data_3::RptGadcData3Spec>;
    #[doc = "rpt_gadc_data_3"]
    pub mod rpt_gadc_data_3 {
        #[doc = "Register `RPT_GADC_DATA_3` reader"]
        pub type R = crate::R<RptGadcData3Spec>;
        #[doc = "Register `RPT_GADC_DATA_3` writer"]
        pub type W = crate::W<RptGadcData3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData3Spec;
        impl crate::RegisterSpec for RptGadcData3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_3::R`](R) reader structure"]
        impl crate::Readable for RptGadcData3Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_3::W`](W) writer structure"]
        impl crate::Writable for RptGadcData3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_3 to value 0"]
        impl crate::Resettable for RptGadcData3Spec {}
    }
    #[doc = "CFG_GADC_DATA_3 (rw) register accessor: cfg_gadc_data_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_3`] module"]
    #[doc(alias = "CFG_GADC_DATA_3")]
    pub type CfgGadcData3 = crate::Reg<cfg_gadc_data_3::CfgGadcData3Spec>;
    #[doc = "cfg_gadc_data_3"]
    pub mod cfg_gadc_data_3 {
        #[doc = "Register `CFG_GADC_DATA_3` reader"]
        pub type R = crate::R<CfgGadcData3Spec>;
        #[doc = "Register `CFG_GADC_DATA_3` writer"]
        pub type W = crate::W<CfgGadcData3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData3Spec;
        impl crate::RegisterSpec for CfgGadcData3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_3::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData3Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_3::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_3 to value 0"]
        impl crate::Resettable for CfgGadcData3Spec {}
    }
    #[doc = "CFG_GADC_DATA_4 (rw) register accessor: cfg_gadc_data_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_4`] module"]
    #[doc(alias = "CFG_GADC_DATA_4")]
    pub type CfgGadcData4 = crate::Reg<cfg_gadc_data_4::CfgGadcData4Spec>;
    #[doc = "cfg_gadc_data_4"]
    pub mod cfg_gadc_data_4 {
        #[doc = "Register `CFG_GADC_DATA_4` reader"]
        pub type R = crate::R<CfgGadcData4Spec>;
        #[doc = "Register `CFG_GADC_DATA_4` writer"]
        pub type W = crate::W<CfgGadcData4Spec>;
        #[doc = "Field `adc_cdac_fc_scale_div` reader - "]
        pub type AdcCdacFcScaleDivR = crate::FieldReader<u16>;
        #[doc = "Field `adc_cdac_fc_scale_div` writer - "]
        pub type AdcCdacFcScaleDivW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `adc_cdac_scale_div_sel` reader - "]
        pub type AdcCdacScaleDivSelR = crate::BitReader;
        #[doc = "Field `adc_cdac_scale_div_sel` writer - "]
        pub type AdcCdacScaleDivSelW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:8"]
            #[inline(always)]
            pub fn adc_cdac_fc_scale_div(&self) -> AdcCdacFcScaleDivR {
                AdcCdacFcScaleDivR::new((self.bits & 0x01ff) as u16)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn adc_cdac_scale_div_sel(&self) -> AdcCdacScaleDivSelR {
                AdcCdacScaleDivSelR::new(((self.bits >> 12) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:8"]
            #[inline(always)]
            pub fn adc_cdac_fc_scale_div(&mut self) -> AdcCdacFcScaleDivW<'_, CfgGadcData4Spec> {
                AdcCdacFcScaleDivW::new(self, 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn adc_cdac_scale_div_sel(&mut self) -> AdcCdacScaleDivSelW<'_, CfgGadcData4Spec> {
                AdcCdacScaleDivSelW::new(self, 12)
            }
        }
        #[doc = "cfg_gadc_data_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData4Spec;
        impl crate::RegisterSpec for CfgGadcData4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_4::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData4Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_4::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_4 to value 0"]
        impl crate::Resettable for CfgGadcData4Spec {}
    }
    #[doc = "RPT_GADC_DATA_4 (rw) register accessor: rpt_gadc_data_4\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_4`] module"]
    #[doc(alias = "RPT_GADC_DATA_4")]
    pub type RptGadcData4 = crate::Reg<rpt_gadc_data_4::RptGadcData4Spec>;
    #[doc = "rpt_gadc_data_4"]
    pub mod rpt_gadc_data_4 {
        #[doc = "Register `RPT_GADC_DATA_4` reader"]
        pub type R = crate::R<RptGadcData4Spec>;
        #[doc = "Register `RPT_GADC_DATA_4` writer"]
        pub type W = crate::W<RptGadcData4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_4\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData4Spec;
        impl crate::RegisterSpec for RptGadcData4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_4::R`](R) reader structure"]
        impl crate::Readable for RptGadcData4Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_4::W`](W) writer structure"]
        impl crate::Writable for RptGadcData4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_4 to value 0"]
        impl crate::Resettable for RptGadcData4Spec {}
    }
    #[doc = "CFG_GADC_DATA_5 (rw) register accessor: cfg_gadc_data_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_5`] module"]
    #[doc(alias = "CFG_GADC_DATA_5")]
    pub type CfgGadcData5 = crate::Reg<cfg_gadc_data_5::CfgGadcData5Spec>;
    #[doc = "cfg_gadc_data_5"]
    pub mod cfg_gadc_data_5 {
        #[doc = "Register `CFG_GADC_DATA_5` reader"]
        pub type R = crate::R<CfgGadcData5Spec>;
        #[doc = "Register `CFG_GADC_DATA_5` writer"]
        pub type W = crate::W<CfgGadcData5Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData5Spec;
        impl crate::RegisterSpec for CfgGadcData5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_5::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData5Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_5::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_5 to value 0"]
        impl crate::Resettable for CfgGadcData5Spec {}
    }
    #[doc = "CFG_GADC_DATA_6 (rw) register accessor: cfg_gadc_data_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_6`] module"]
    #[doc(alias = "CFG_GADC_DATA_6")]
    pub type CfgGadcData6 = crate::Reg<cfg_gadc_data_6::CfgGadcData6Spec>;
    #[doc = "cfg_gadc_data_6"]
    pub mod cfg_gadc_data_6 {
        #[doc = "Register `CFG_GADC_DATA_6` reader"]
        pub type R = crate::R<CfgGadcData6Spec>;
        #[doc = "Register `CFG_GADC_DATA_6` writer"]
        pub type W = crate::W<CfgGadcData6Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData6Spec;
        impl crate::RegisterSpec for CfgGadcData6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_6::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData6Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_6::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_6 to value 0"]
        impl crate::Resettable for CfgGadcData6Spec {}
    }
    #[doc = "CFG_GADC_DATA_7 (rw) register accessor: cfg_gadc_data_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_7`] module"]
    #[doc(alias = "CFG_GADC_DATA_7")]
    pub type CfgGadcData7 = crate::Reg<cfg_gadc_data_7::CfgGadcData7Spec>;
    #[doc = "cfg_gadc_data_7"]
    pub mod cfg_gadc_data_7 {
        #[doc = "Register `CFG_GADC_DATA_7` reader"]
        pub type R = crate::R<CfgGadcData7Spec>;
        #[doc = "Register `CFG_GADC_DATA_7` writer"]
        pub type W = crate::W<CfgGadcData7Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData7Spec;
        impl crate::RegisterSpec for CfgGadcData7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_7::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData7Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_7::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_7 to value 0"]
        impl crate::Resettable for CfgGadcData7Spec {}
    }
    #[doc = "CFG_GADC_DATA_8 (rw) register accessor: cfg_gadc_data_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_8`] module"]
    #[doc(alias = "CFG_GADC_DATA_8")]
    pub type CfgGadcData8 = crate::Reg<cfg_gadc_data_8::CfgGadcData8Spec>;
    #[doc = "cfg_gadc_data_8"]
    pub mod cfg_gadc_data_8 {
        #[doc = "Register `CFG_GADC_DATA_8` reader"]
        pub type R = crate::R<CfgGadcData8Spec>;
        #[doc = "Register `CFG_GADC_DATA_8` writer"]
        pub type W = crate::W<CfgGadcData8Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData8Spec;
        impl crate::RegisterSpec for CfgGadcData8Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_8::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData8Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_8::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData8Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_8 to value 0"]
        impl crate::Resettable for CfgGadcData8Spec {}
    }
    #[doc = "CFG_GADC_DATA_9 (rw) register accessor: cfg_gadc_data_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_9`] module"]
    #[doc(alias = "CFG_GADC_DATA_9")]
    pub type CfgGadcData9 = crate::Reg<cfg_gadc_data_9::CfgGadcData9Spec>;
    #[doc = "cfg_gadc_data_9"]
    pub mod cfg_gadc_data_9 {
        #[doc = "Register `CFG_GADC_DATA_9` reader"]
        pub type R = crate::R<CfgGadcData9Spec>;
        #[doc = "Register `CFG_GADC_DATA_9` writer"]
        pub type W = crate::W<CfgGadcData9Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData9Spec;
        impl crate::RegisterSpec for CfgGadcData9Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_9::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData9Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_9::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData9Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_9 to value 0"]
        impl crate::Resettable for CfgGadcData9Spec {}
    }
    #[doc = "CFG_GADC_DATA_10 (rw) register accessor: cfg_gadc_data_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_10`] module"]
    #[doc(alias = "CFG_GADC_DATA_10")]
    pub type CfgGadcData10 = crate::Reg<cfg_gadc_data_10::CfgGadcData10Spec>;
    #[doc = "cfg_gadc_data_10"]
    pub mod cfg_gadc_data_10 {
        #[doc = "Register `CFG_GADC_DATA_10` reader"]
        pub type R = crate::R<CfgGadcData10Spec>;
        #[doc = "Register `CFG_GADC_DATA_10` writer"]
        pub type W = crate::W<CfgGadcData10Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData10Spec;
        impl crate::RegisterSpec for CfgGadcData10Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_10::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData10Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_10::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData10Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_10 to value 0"]
        impl crate::Resettable for CfgGadcData10Spec {}
    }
    #[doc = "CFG_GADC_DATA_11 (rw) register accessor: cfg_gadc_data_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_11`] module"]
    #[doc(alias = "CFG_GADC_DATA_11")]
    pub type CfgGadcData11 = crate::Reg<cfg_gadc_data_11::CfgGadcData11Spec>;
    #[doc = "cfg_gadc_data_11"]
    pub mod cfg_gadc_data_11 {
        #[doc = "Register `CFG_GADC_DATA_11` reader"]
        pub type R = crate::R<CfgGadcData11Spec>;
        #[doc = "Register `CFG_GADC_DATA_11` writer"]
        pub type W = crate::W<CfgGadcData11Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData11Spec;
        impl crate::RegisterSpec for CfgGadcData11Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_11::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData11Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_11::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData11Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_11 to value 0"]
        impl crate::Resettable for CfgGadcData11Spec {}
    }
    #[doc = "CFG_GADC_DATA_12 (rw) register accessor: cfg_gadc_data_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_12`] module"]
    #[doc(alias = "CFG_GADC_DATA_12")]
    pub type CfgGadcData12 = crate::Reg<cfg_gadc_data_12::CfgGadcData12Spec>;
    #[doc = "cfg_gadc_data_12"]
    pub mod cfg_gadc_data_12 {
        #[doc = "Register `CFG_GADC_DATA_12` reader"]
        pub type R = crate::R<CfgGadcData12Spec>;
        #[doc = "Register `CFG_GADC_DATA_12` writer"]
        pub type W = crate::W<CfgGadcData12Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData12Spec;
        impl crate::RegisterSpec for CfgGadcData12Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_12::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData12Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_12::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData12Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_12 to value 0"]
        impl crate::Resettable for CfgGadcData12Spec {}
    }
    #[doc = "CFG_GADC_DATA_13 (rw) register accessor: cfg_gadc_data_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_13`] module"]
    #[doc(alias = "CFG_GADC_DATA_13")]
    pub type CfgGadcData13 = crate::Reg<cfg_gadc_data_13::CfgGadcData13Spec>;
    #[doc = "cfg_gadc_data_13"]
    pub mod cfg_gadc_data_13 {
        #[doc = "Register `CFG_GADC_DATA_13` reader"]
        pub type R = crate::R<CfgGadcData13Spec>;
        #[doc = "Register `CFG_GADC_DATA_13` writer"]
        pub type W = crate::W<CfgGadcData13Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData13Spec;
        impl crate::RegisterSpec for CfgGadcData13Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_13::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData13Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_13::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData13Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_13 to value 0"]
        impl crate::Resettable for CfgGadcData13Spec {}
    }
    #[doc = "CFG_GADC_DATA_14 (rw) register accessor: cfg_gadc_data_14\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_14`] module"]
    #[doc(alias = "CFG_GADC_DATA_14")]
    pub type CfgGadcData14 = crate::Reg<cfg_gadc_data_14::CfgGadcData14Spec>;
    #[doc = "cfg_gadc_data_14"]
    pub mod cfg_gadc_data_14 {
        #[doc = "Register `CFG_GADC_DATA_14` reader"]
        pub type R = crate::R<CfgGadcData14Spec>;
        #[doc = "Register `CFG_GADC_DATA_14` writer"]
        pub type W = crate::W<CfgGadcData14Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_14\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData14Spec;
        impl crate::RegisterSpec for CfgGadcData14Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_14::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData14Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_14::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData14Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_14 to value 0"]
        impl crate::Resettable for CfgGadcData14Spec {}
    }
    #[doc = "CFG_GADC_DATA_15 (rw) register accessor: cfg_gadc_data_15\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_15`] module"]
    #[doc(alias = "CFG_GADC_DATA_15")]
    pub type CfgGadcData15 = crate::Reg<cfg_gadc_data_15::CfgGadcData15Spec>;
    #[doc = "cfg_gadc_data_15"]
    pub mod cfg_gadc_data_15 {
        #[doc = "Register `CFG_GADC_DATA_15` reader"]
        pub type R = crate::R<CfgGadcData15Spec>;
        #[doc = "Register `CFG_GADC_DATA_15` writer"]
        pub type W = crate::W<CfgGadcData15Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_15\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData15Spec;
        impl crate::RegisterSpec for CfgGadcData15Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_15::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData15Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_15::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData15Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_15 to value 0"]
        impl crate::Resettable for CfgGadcData15Spec {}
    }
    #[doc = "CFG_GADC_DATA_16 (rw) register accessor: cfg_gadc_data_16\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_16`] module"]
    #[doc(alias = "CFG_GADC_DATA_16")]
    pub type CfgGadcData16 = crate::Reg<cfg_gadc_data_16::CfgGadcData16Spec>;
    #[doc = "cfg_gadc_data_16"]
    pub mod cfg_gadc_data_16 {
        #[doc = "Register `CFG_GADC_DATA_16` reader"]
        pub type R = crate::R<CfgGadcData16Spec>;
        #[doc = "Register `CFG_GADC_DATA_16` writer"]
        pub type W = crate::W<CfgGadcData16Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_16\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData16Spec;
        impl crate::RegisterSpec for CfgGadcData16Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_16::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData16Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_16::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData16Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_16 to value 0"]
        impl crate::Resettable for CfgGadcData16Spec {}
    }
    #[doc = "CFG_GADC_DATA_17 (rw) register accessor: cfg_gadc_data_17\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_17`] module"]
    #[doc(alias = "CFG_GADC_DATA_17")]
    pub type CfgGadcData17 = crate::Reg<cfg_gadc_data_17::CfgGadcData17Spec>;
    #[doc = "cfg_gadc_data_17"]
    pub mod cfg_gadc_data_17 {
        #[doc = "Register `CFG_GADC_DATA_17` reader"]
        pub type R = crate::R<CfgGadcData17Spec>;
        #[doc = "Register `CFG_GADC_DATA_17` writer"]
        pub type W = crate::W<CfgGadcData17Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_17\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData17Spec;
        impl crate::RegisterSpec for CfgGadcData17Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_17::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData17Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_17::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData17Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_17 to value 0"]
        impl crate::Resettable for CfgGadcData17Spec {}
    }
    #[doc = "CFG_GADC_DATA_18 (rw) register accessor: cfg_gadc_data_18\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_18`] module"]
    #[doc(alias = "CFG_GADC_DATA_18")]
    pub type CfgGadcData18 = crate::Reg<cfg_gadc_data_18::CfgGadcData18Spec>;
    #[doc = "cfg_gadc_data_18"]
    pub mod cfg_gadc_data_18 {
        #[doc = "Register `CFG_GADC_DATA_18` reader"]
        pub type R = crate::R<CfgGadcData18Spec>;
        #[doc = "Register `CFG_GADC_DATA_18` writer"]
        pub type W = crate::W<CfgGadcData18Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_18\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData18Spec;
        impl crate::RegisterSpec for CfgGadcData18Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_18::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData18Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_18::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData18Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_18 to value 0"]
        impl crate::Resettable for CfgGadcData18Spec {}
    }
    #[doc = "CFG_GADC_DATA_19 (rw) register accessor: cfg_gadc_data_19\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_19`] module"]
    #[doc(alias = "CFG_GADC_DATA_19")]
    pub type CfgGadcData19 = crate::Reg<cfg_gadc_data_19::CfgGadcData19Spec>;
    #[doc = "cfg_gadc_data_19"]
    pub mod cfg_gadc_data_19 {
        #[doc = "Register `CFG_GADC_DATA_19` reader"]
        pub type R = crate::R<CfgGadcData19Spec>;
        #[doc = "Register `CFG_GADC_DATA_19` writer"]
        pub type W = crate::W<CfgGadcData19Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_19\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData19Spec;
        impl crate::RegisterSpec for CfgGadcData19Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_19::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData19Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_19::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData19Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_19 to value 0"]
        impl crate::Resettable for CfgGadcData19Spec {}
    }
    #[doc = "CFG_GADC_DATA_20 (rw) register accessor: cfg_gadc_data_20\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_20`] module"]
    #[doc(alias = "CFG_GADC_DATA_20")]
    pub type CfgGadcData20 = crate::Reg<cfg_gadc_data_20::CfgGadcData20Spec>;
    #[doc = "cfg_gadc_data_20"]
    pub mod cfg_gadc_data_20 {
        #[doc = "Register `CFG_GADC_DATA_20` reader"]
        pub type R = crate::R<CfgGadcData20Spec>;
        #[doc = "Register `CFG_GADC_DATA_20` writer"]
        pub type W = crate::W<CfgGadcData20Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_20\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData20Spec;
        impl crate::RegisterSpec for CfgGadcData20Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_20::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData20Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_20::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData20Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_20 to value 0"]
        impl crate::Resettable for CfgGadcData20Spec {}
    }
    #[doc = "CFG_GADC_DATA_21 (rw) register accessor: cfg_gadc_data_21\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_21`] module"]
    #[doc(alias = "CFG_GADC_DATA_21")]
    pub type CfgGadcData21 = crate::Reg<cfg_gadc_data_21::CfgGadcData21Spec>;
    #[doc = "cfg_gadc_data_21"]
    pub mod cfg_gadc_data_21 {
        #[doc = "Register `CFG_GADC_DATA_21` reader"]
        pub type R = crate::R<CfgGadcData21Spec>;
        #[doc = "Register `CFG_GADC_DATA_21` writer"]
        pub type W = crate::W<CfgGadcData21Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_21\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData21Spec;
        impl crate::RegisterSpec for CfgGadcData21Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_21::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData21Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_21::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData21Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_21 to value 0"]
        impl crate::Resettable for CfgGadcData21Spec {}
    }
    #[doc = "CFG_GADC_DATA_22 (rw) register accessor: cfg_gadc_data_22\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_22`] module"]
    #[doc(alias = "CFG_GADC_DATA_22")]
    pub type CfgGadcData22 = crate::Reg<cfg_gadc_data_22::CfgGadcData22Spec>;
    #[doc = "cfg_gadc_data_22"]
    pub mod cfg_gadc_data_22 {
        #[doc = "Register `CFG_GADC_DATA_22` reader"]
        pub type R = crate::R<CfgGadcData22Spec>;
        #[doc = "Register `CFG_GADC_DATA_22` writer"]
        pub type W = crate::W<CfgGadcData22Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_22\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData22Spec;
        impl crate::RegisterSpec for CfgGadcData22Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_22::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData22Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_22::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData22Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_22 to value 0"]
        impl crate::Resettable for CfgGadcData22Spec {}
    }
    #[doc = "CFG_GADC_DATA_23 (rw) register accessor: cfg_gadc_data_23\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_23`] module"]
    #[doc(alias = "CFG_GADC_DATA_23")]
    pub type CfgGadcData23 = crate::Reg<cfg_gadc_data_23::CfgGadcData23Spec>;
    #[doc = "cfg_gadc_data_23"]
    pub mod cfg_gadc_data_23 {
        #[doc = "Register `CFG_GADC_DATA_23` reader"]
        pub type R = crate::R<CfgGadcData23Spec>;
        #[doc = "Register `CFG_GADC_DATA_23` writer"]
        pub type W = crate::W<CfgGadcData23Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_23\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData23Spec;
        impl crate::RegisterSpec for CfgGadcData23Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_23::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData23Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_23::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData23Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_23 to value 0"]
        impl crate::Resettable for CfgGadcData23Spec {}
    }
    #[doc = "CFG_GADC_DATA_24 (rw) register accessor: cfg_gadc_data_24\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_24`] module"]
    #[doc(alias = "CFG_GADC_DATA_24")]
    pub type CfgGadcData24 = crate::Reg<cfg_gadc_data_24::CfgGadcData24Spec>;
    #[doc = "cfg_gadc_data_24"]
    pub mod cfg_gadc_data_24 {
        #[doc = "Register `CFG_GADC_DATA_24` reader"]
        pub type R = crate::R<CfgGadcData24Spec>;
        #[doc = "Register `CFG_GADC_DATA_24` writer"]
        pub type W = crate::W<CfgGadcData24Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_24\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData24Spec;
        impl crate::RegisterSpec for CfgGadcData24Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_24::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData24Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_24::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData24Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_24 to value 0"]
        impl crate::Resettable for CfgGadcData24Spec {}
    }
    #[doc = "CFG_GADC_DATA_25 (rw) register accessor: cfg_gadc_data_25\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_gadc_data_25`] module"]
    #[doc(alias = "CFG_GADC_DATA_25")]
    pub type CfgGadcData25 = crate::Reg<cfg_gadc_data_25::CfgGadcData25Spec>;
    #[doc = "cfg_gadc_data_25"]
    pub mod cfg_gadc_data_25 {
        #[doc = "Register `CFG_GADC_DATA_25` reader"]
        pub type R = crate::R<CfgGadcData25Spec>;
        #[doc = "Register `CFG_GADC_DATA_25` writer"]
        pub type W = crate::W<CfgGadcData25Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_gadc_data_25\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_gadc_data_25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_gadc_data_25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgGadcData25Spec;
        impl crate::RegisterSpec for CfgGadcData25Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_gadc_data_25::R`](R) reader structure"]
        impl crate::Readable for CfgGadcData25Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_gadc_data_25::W`](W) writer structure"]
        impl crate::Writable for CfgGadcData25Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_GADC_DATA_25 to value 0"]
        impl crate::Resettable for CfgGadcData25Spec {}
    }
    #[doc = "RPT_GADC_DATA_5 (rw) register accessor: rpt_gadc_data_5\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_5`] module"]
    #[doc(alias = "RPT_GADC_DATA_5")]
    pub type RptGadcData5 = crate::Reg<rpt_gadc_data_5::RptGadcData5Spec>;
    #[doc = "rpt_gadc_data_5"]
    pub mod rpt_gadc_data_5 {
        #[doc = "Register `RPT_GADC_DATA_5` reader"]
        pub type R = crate::R<RptGadcData5Spec>;
        #[doc = "Register `RPT_GADC_DATA_5` writer"]
        pub type W = crate::W<RptGadcData5Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_5\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData5Spec;
        impl crate::RegisterSpec for RptGadcData5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_5::R`](R) reader structure"]
        impl crate::Readable for RptGadcData5Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_5::W`](W) writer structure"]
        impl crate::Writable for RptGadcData5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_5 to value 0"]
        impl crate::Resettable for RptGadcData5Spec {}
    }
    #[doc = "RPT_GADC_DATA_6 (rw) register accessor: rpt_gadc_data_6\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_6`] module"]
    #[doc(alias = "RPT_GADC_DATA_6")]
    pub type RptGadcData6 = crate::Reg<rpt_gadc_data_6::RptGadcData6Spec>;
    #[doc = "rpt_gadc_data_6"]
    pub mod rpt_gadc_data_6 {
        #[doc = "Register `RPT_GADC_DATA_6` reader"]
        pub type R = crate::R<RptGadcData6Spec>;
        #[doc = "Register `RPT_GADC_DATA_6` writer"]
        pub type W = crate::W<RptGadcData6Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_6\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData6Spec;
        impl crate::RegisterSpec for RptGadcData6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_6::R`](R) reader structure"]
        impl crate::Readable for RptGadcData6Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_6::W`](W) writer structure"]
        impl crate::Writable for RptGadcData6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_6 to value 0"]
        impl crate::Resettable for RptGadcData6Spec {}
    }
    #[doc = "RPT_GADC_DATA_7 (rw) register accessor: rpt_gadc_data_7\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_7`] module"]
    #[doc(alias = "RPT_GADC_DATA_7")]
    pub type RptGadcData7 = crate::Reg<rpt_gadc_data_7::RptGadcData7Spec>;
    #[doc = "rpt_gadc_data_7"]
    pub mod rpt_gadc_data_7 {
        #[doc = "Register `RPT_GADC_DATA_7` reader"]
        pub type R = crate::R<RptGadcData7Spec>;
        #[doc = "Register `RPT_GADC_DATA_7` writer"]
        pub type W = crate::W<RptGadcData7Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_7\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData7Spec;
        impl crate::RegisterSpec for RptGadcData7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_7::R`](R) reader structure"]
        impl crate::Readable for RptGadcData7Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_7::W`](W) writer structure"]
        impl crate::Writable for RptGadcData7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_7 to value 0"]
        impl crate::Resettable for RptGadcData7Spec {}
    }
    #[doc = "RPT_GADC_DATA_8 (rw) register accessor: rpt_gadc_data_8\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_8`] module"]
    #[doc(alias = "RPT_GADC_DATA_8")]
    pub type RptGadcData8 = crate::Reg<rpt_gadc_data_8::RptGadcData8Spec>;
    #[doc = "rpt_gadc_data_8"]
    pub mod rpt_gadc_data_8 {
        #[doc = "Register `RPT_GADC_DATA_8` reader"]
        pub type R = crate::R<RptGadcData8Spec>;
        #[doc = "Register `RPT_GADC_DATA_8` writer"]
        pub type W = crate::W<RptGadcData8Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_8\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData8Spec;
        impl crate::RegisterSpec for RptGadcData8Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_8::R`](R) reader structure"]
        impl crate::Readable for RptGadcData8Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_8::W`](W) writer structure"]
        impl crate::Writable for RptGadcData8Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_8 to value 0"]
        impl crate::Resettable for RptGadcData8Spec {}
    }
    #[doc = "RPT_GADC_DATA_9 (rw) register accessor: rpt_gadc_data_9\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_9`] module"]
    #[doc(alias = "RPT_GADC_DATA_9")]
    pub type RptGadcData9 = crate::Reg<rpt_gadc_data_9::RptGadcData9Spec>;
    #[doc = "rpt_gadc_data_9"]
    pub mod rpt_gadc_data_9 {
        #[doc = "Register `RPT_GADC_DATA_9` reader"]
        pub type R = crate::R<RptGadcData9Spec>;
        #[doc = "Register `RPT_GADC_DATA_9` writer"]
        pub type W = crate::W<RptGadcData9Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_9\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData9Spec;
        impl crate::RegisterSpec for RptGadcData9Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_9::R`](R) reader structure"]
        impl crate::Readable for RptGadcData9Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_9::W`](W) writer structure"]
        impl crate::Writable for RptGadcData9Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_9 to value 0"]
        impl crate::Resettable for RptGadcData9Spec {}
    }
    #[doc = "RPT_GADC_DATA_10 (rw) register accessor: rpt_gadc_data_10\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_10`] module"]
    #[doc(alias = "RPT_GADC_DATA_10")]
    pub type RptGadcData10 = crate::Reg<rpt_gadc_data_10::RptGadcData10Spec>;
    #[doc = "rpt_gadc_data_10"]
    pub mod rpt_gadc_data_10 {
        #[doc = "Register `RPT_GADC_DATA_10` reader"]
        pub type R = crate::R<RptGadcData10Spec>;
        #[doc = "Register `RPT_GADC_DATA_10` writer"]
        pub type W = crate::W<RptGadcData10Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_10\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData10Spec;
        impl crate::RegisterSpec for RptGadcData10Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_10::R`](R) reader structure"]
        impl crate::Readable for RptGadcData10Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_10::W`](W) writer structure"]
        impl crate::Writable for RptGadcData10Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_10 to value 0"]
        impl crate::Resettable for RptGadcData10Spec {}
    }
    #[doc = "RPT_GADC_DATA_11 (rw) register accessor: rpt_gadc_data_11\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_11`] module"]
    #[doc(alias = "RPT_GADC_DATA_11")]
    pub type RptGadcData11 = crate::Reg<rpt_gadc_data_11::RptGadcData11Spec>;
    #[doc = "rpt_gadc_data_11"]
    pub mod rpt_gadc_data_11 {
        #[doc = "Register `RPT_GADC_DATA_11` reader"]
        pub type R = crate::R<RptGadcData11Spec>;
        #[doc = "Register `RPT_GADC_DATA_11` writer"]
        pub type W = crate::W<RptGadcData11Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_11\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData11Spec;
        impl crate::RegisterSpec for RptGadcData11Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_11::R`](R) reader structure"]
        impl crate::Readable for RptGadcData11Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_11::W`](W) writer structure"]
        impl crate::Writable for RptGadcData11Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_11 to value 0"]
        impl crate::Resettable for RptGadcData11Spec {}
    }
    #[doc = "RPT_GADC_DATA_12 (rw) register accessor: rpt_gadc_data_12\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_12`] module"]
    #[doc(alias = "RPT_GADC_DATA_12")]
    pub type RptGadcData12 = crate::Reg<rpt_gadc_data_12::RptGadcData12Spec>;
    #[doc = "rpt_gadc_data_12"]
    pub mod rpt_gadc_data_12 {
        #[doc = "Register `RPT_GADC_DATA_12` reader"]
        pub type R = crate::R<RptGadcData12Spec>;
        #[doc = "Register `RPT_GADC_DATA_12` writer"]
        pub type W = crate::W<RptGadcData12Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_12\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData12Spec;
        impl crate::RegisterSpec for RptGadcData12Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_12::R`](R) reader structure"]
        impl crate::Readable for RptGadcData12Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_12::W`](W) writer structure"]
        impl crate::Writable for RptGadcData12Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_12 to value 0"]
        impl crate::Resettable for RptGadcData12Spec {}
    }
    #[doc = "RPT_GADC_DATA_13 (rw) register accessor: rpt_gadc_data_13\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_gadc_data_13`] module"]
    #[doc(alias = "RPT_GADC_DATA_13")]
    pub type RptGadcData13 = crate::Reg<rpt_gadc_data_13::RptGadcData13Spec>;
    #[doc = "rpt_gadc_data_13"]
    pub mod rpt_gadc_data_13 {
        #[doc = "Register `RPT_GADC_DATA_13` reader"]
        pub type R = crate::R<RptGadcData13Spec>;
        #[doc = "Register `RPT_GADC_DATA_13` writer"]
        pub type W = crate::W<RptGadcData13Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_gadc_data_13\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_gadc_data_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_gadc_data_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptGadcData13Spec;
        impl crate::RegisterSpec for RptGadcData13Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_gadc_data_13::R`](R) reader structure"]
        impl crate::Readable for RptGadcData13Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_gadc_data_13::W`](W) writer structure"]
        impl crate::Writable for RptGadcData13Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_GADC_DATA_13 to value 0"]
        impl crate::Resettable for RptGadcData13Spec {}
    }
    #[doc = "CFG_CMP_OS_0 (rw) register accessor: cfg_cmp_os_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_0`] module"]
    #[doc(alias = "CFG_CMP_OS_0")]
    pub type CfgCmpOs0 = crate::Reg<cfg_cmp_os_0::CfgCmpOs0Spec>;
    #[doc = "cfg_cmp_os_0"]
    pub mod cfg_cmp_os_0 {
        #[doc = "Register `CFG_CMP_OS_0` reader"]
        pub type R = crate::R<CfgCmpOs0Spec>;
        #[doc = "Register `CFG_CMP_OS_0` writer"]
        pub type W = crate::W<CfgCmpOs0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs0Spec;
        impl crate::RegisterSpec for CfgCmpOs0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_0::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_0::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_0 to value 0"]
        impl crate::Resettable for CfgCmpOs0Spec {}
    }
    #[doc = "CFG_CMP_OS_1 (rw) register accessor: cfg_cmp_os_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_1`] module"]
    #[doc(alias = "CFG_CMP_OS_1")]
    pub type CfgCmpOs1 = crate::Reg<cfg_cmp_os_1::CfgCmpOs1Spec>;
    #[doc = "cfg_cmp_os_1"]
    pub mod cfg_cmp_os_1 {
        #[doc = "Register `CFG_CMP_OS_1` reader"]
        pub type R = crate::R<CfgCmpOs1Spec>;
        #[doc = "Register `CFG_CMP_OS_1` writer"]
        pub type W = crate::W<CfgCmpOs1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs1Spec;
        impl crate::RegisterSpec for CfgCmpOs1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_1::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_1::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_1 to value 0"]
        impl crate::Resettable for CfgCmpOs1Spec {}
    }
    #[doc = "CFG_CMP_OS_2 (rw) register accessor: cfg_cmp_os_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_2`] module"]
    #[doc(alias = "CFG_CMP_OS_2")]
    pub type CfgCmpOs2 = crate::Reg<cfg_cmp_os_2::CfgCmpOs2Spec>;
    #[doc = "cfg_cmp_os_2"]
    pub mod cfg_cmp_os_2 {
        #[doc = "Register `CFG_CMP_OS_2` reader"]
        pub type R = crate::R<CfgCmpOs2Spec>;
        #[doc = "Register `CFG_CMP_OS_2` writer"]
        pub type W = crate::W<CfgCmpOs2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs2Spec;
        impl crate::RegisterSpec for CfgCmpOs2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_2::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs2Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_2::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_2 to value 0"]
        impl crate::Resettable for CfgCmpOs2Spec {}
    }
    #[doc = "CFG_CMP_OS_3 (rw) register accessor: cfg_cmp_os_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_3`] module"]
    #[doc(alias = "CFG_CMP_OS_3")]
    pub type CfgCmpOs3 = crate::Reg<cfg_cmp_os_3::CfgCmpOs3Spec>;
    #[doc = "cfg_cmp_os_3"]
    pub mod cfg_cmp_os_3 {
        #[doc = "Register `CFG_CMP_OS_3` reader"]
        pub type R = crate::R<CfgCmpOs3Spec>;
        #[doc = "Register `CFG_CMP_OS_3` writer"]
        pub type W = crate::W<CfgCmpOs3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs3Spec;
        impl crate::RegisterSpec for CfgCmpOs3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_3::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs3Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_3::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_3 to value 0"]
        impl crate::Resettable for CfgCmpOs3Spec {}
    }
    #[doc = "CFG_CMP_OS_4 (rw) register accessor: cfg_cmp_os_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_4`] module"]
    #[doc(alias = "CFG_CMP_OS_4")]
    pub type CfgCmpOs4 = crate::Reg<cfg_cmp_os_4::CfgCmpOs4Spec>;
    #[doc = "cfg_cmp_os_4"]
    pub mod cfg_cmp_os_4 {
        #[doc = "Register `CFG_CMP_OS_4` reader"]
        pub type R = crate::R<CfgCmpOs4Spec>;
        #[doc = "Register `CFG_CMP_OS_4` writer"]
        pub type W = crate::W<CfgCmpOs4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs4Spec;
        impl crate::RegisterSpec for CfgCmpOs4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_4::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs4Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_4::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_4 to value 0"]
        impl crate::Resettable for CfgCmpOs4Spec {}
    }
    #[doc = "CFG_CMP_OS_5 (rw) register accessor: cfg_cmp_os_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_5`] module"]
    #[doc(alias = "CFG_CMP_OS_5")]
    pub type CfgCmpOs5 = crate::Reg<cfg_cmp_os_5::CfgCmpOs5Spec>;
    #[doc = "cfg_cmp_os_5"]
    pub mod cfg_cmp_os_5 {
        #[doc = "Register `CFG_CMP_OS_5` reader"]
        pub type R = crate::R<CfgCmpOs5Spec>;
        #[doc = "Register `CFG_CMP_OS_5` writer"]
        pub type W = crate::W<CfgCmpOs5Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs5Spec;
        impl crate::RegisterSpec for CfgCmpOs5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_5::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs5Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_5::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_5 to value 0"]
        impl crate::Resettable for CfgCmpOs5Spec {}
    }
    #[doc = "CFG_CMP_OS_6 (rw) register accessor: cfg_cmp_os_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_6`] module"]
    #[doc(alias = "CFG_CMP_OS_6")]
    pub type CfgCmpOs6 = crate::Reg<cfg_cmp_os_6::CfgCmpOs6Spec>;
    #[doc = "cfg_cmp_os_6"]
    pub mod cfg_cmp_os_6 {
        #[doc = "Register `CFG_CMP_OS_6` reader"]
        pub type R = crate::R<CfgCmpOs6Spec>;
        #[doc = "Register `CFG_CMP_OS_6` writer"]
        pub type W = crate::W<CfgCmpOs6Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs6Spec;
        impl crate::RegisterSpec for CfgCmpOs6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_6::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs6Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_6::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_6 to value 0"]
        impl crate::Resettable for CfgCmpOs6Spec {}
    }
    #[doc = "CFG_CMP_OS_7 (rw) register accessor: cfg_cmp_os_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_7`] module"]
    #[doc(alias = "CFG_CMP_OS_7")]
    pub type CfgCmpOs7 = crate::Reg<cfg_cmp_os_7::CfgCmpOs7Spec>;
    #[doc = "cfg_cmp_os_7"]
    pub mod cfg_cmp_os_7 {
        #[doc = "Register `CFG_CMP_OS_7` reader"]
        pub type R = crate::R<CfgCmpOs7Spec>;
        #[doc = "Register `CFG_CMP_OS_7` writer"]
        pub type W = crate::W<CfgCmpOs7Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs7Spec;
        impl crate::RegisterSpec for CfgCmpOs7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_7::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs7Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_7::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_7 to value 0"]
        impl crate::Resettable for CfgCmpOs7Spec {}
    }
    #[doc = "CFG_CMP_OS_8 (rw) register accessor: cfg_cmp_os_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_8`] module"]
    #[doc(alias = "CFG_CMP_OS_8")]
    pub type CfgCmpOs8 = crate::Reg<cfg_cmp_os_8::CfgCmpOs8Spec>;
    #[doc = "cfg_cmp_os_8"]
    pub mod cfg_cmp_os_8 {
        #[doc = "Register `CFG_CMP_OS_8` reader"]
        pub type R = crate::R<CfgCmpOs8Spec>;
        #[doc = "Register `CFG_CMP_OS_8` writer"]
        pub type W = crate::W<CfgCmpOs8Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs8Spec;
        impl crate::RegisterSpec for CfgCmpOs8Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_8::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs8Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_8::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs8Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_8 to value 0"]
        impl crate::Resettable for CfgCmpOs8Spec {}
    }
    #[doc = "CFG_CMP_OS_9 (rw) register accessor: cfg_cmp_os_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_9`] module"]
    #[doc(alias = "CFG_CMP_OS_9")]
    pub type CfgCmpOs9 = crate::Reg<cfg_cmp_os_9::CfgCmpOs9Spec>;
    #[doc = "cfg_cmp_os_9"]
    pub mod cfg_cmp_os_9 {
        #[doc = "Register `CFG_CMP_OS_9` reader"]
        pub type R = crate::R<CfgCmpOs9Spec>;
        #[doc = "Register `CFG_CMP_OS_9` writer"]
        pub type W = crate::W<CfgCmpOs9Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs9Spec;
        impl crate::RegisterSpec for CfgCmpOs9Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_9::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs9Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_9::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs9Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_9 to value 0"]
        impl crate::Resettable for CfgCmpOs9Spec {}
    }
    #[doc = "CFG_CMP_OS_10 (rw) register accessor: cfg_cmp_os_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_10`] module"]
    #[doc(alias = "CFG_CMP_OS_10")]
    pub type CfgCmpOs10 = crate::Reg<cfg_cmp_os_10::CfgCmpOs10Spec>;
    #[doc = "cfg_cmp_os_10"]
    pub mod cfg_cmp_os_10 {
        #[doc = "Register `CFG_CMP_OS_10` reader"]
        pub type R = crate::R<CfgCmpOs10Spec>;
        #[doc = "Register `CFG_CMP_OS_10` writer"]
        pub type W = crate::W<CfgCmpOs10Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs10Spec;
        impl crate::RegisterSpec for CfgCmpOs10Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_10::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs10Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_10::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs10Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_10 to value 0"]
        impl crate::Resettable for CfgCmpOs10Spec {}
    }
    #[doc = "RPT_CMP_OS_0 (rw) register accessor: rpt_cmp_os_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_os_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_os_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cmp_os_0`] module"]
    #[doc(alias = "RPT_CMP_OS_0")]
    pub type RptCmpOs0 = crate::Reg<rpt_cmp_os_0::RptCmpOs0Spec>;
    #[doc = "rpt_cmp_os_0"]
    pub mod rpt_cmp_os_0 {
        #[doc = "Register `RPT_CMP_OS_0` reader"]
        pub type R = crate::R<RptCmpOs0Spec>;
        #[doc = "Register `RPT_CMP_OS_0` writer"]
        pub type W = crate::W<RptCmpOs0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cmp_os_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_os_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_os_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCmpOs0Spec;
        impl crate::RegisterSpec for RptCmpOs0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cmp_os_0::R`](R) reader structure"]
        impl crate::Readable for RptCmpOs0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cmp_os_0::W`](W) writer structure"]
        impl crate::Writable for RptCmpOs0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CMP_OS_0 to value 0"]
        impl crate::Resettable for RptCmpOs0Spec {}
    }
    #[doc = "CFG_CMP_OS_11 (rw) register accessor: cfg_cmp_os_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_11`] module"]
    #[doc(alias = "CFG_CMP_OS_11")]
    pub type CfgCmpOs11 = crate::Reg<cfg_cmp_os_11::CfgCmpOs11Spec>;
    #[doc = "cfg_cmp_os_11"]
    pub mod cfg_cmp_os_11 {
        #[doc = "Register `CFG_CMP_OS_11` reader"]
        pub type R = crate::R<CfgCmpOs11Spec>;
        #[doc = "Register `CFG_CMP_OS_11` writer"]
        pub type W = crate::W<CfgCmpOs11Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_os_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs11Spec;
        impl crate::RegisterSpec for CfgCmpOs11Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_11::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs11Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_11::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs11Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_11 to value 0"]
        impl crate::Resettable for CfgCmpOs11Spec {}
    }
    #[doc = "CFG_CMP_OS_12 (rw) register accessor: cfg_cmp_os_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_os_12`] module"]
    #[doc(alias = "CFG_CMP_OS_12")]
    pub type CfgCmpOs12 = crate::Reg<cfg_cmp_os_12::CfgCmpOs12Spec>;
    #[doc = "cfg_cmp_os_12"]
    pub mod cfg_cmp_os_12 {
        #[doc = "Register `CFG_CMP_OS_12` reader"]
        pub type R = crate::R<CfgCmpOs12Spec>;
        #[doc = "Register `CFG_CMP_OS_12` writer"]
        pub type W = crate::W<CfgCmpOs12Spec>;
        #[doc = "Field `cfg_manual_cmp_os_code` reader - "]
        pub type CfgManualCmpOsCodeR = crate::FieldReader;
        #[doc = "Field `cfg_manual_cmp_os_code` writer - "]
        pub type CfgManualCmpOsCodeW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `cfg_manual_cmp_os_update` reader - "]
        pub type CfgManualCmpOsUpdateR = crate::BitReader;
        #[doc = "Field `cfg_manual_cmp_os_update` writer - "]
        pub type CfgManualCmpOsUpdateW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:6"]
            #[inline(always)]
            pub fn cfg_manual_cmp_os_code(&self) -> CfgManualCmpOsCodeR {
                CfgManualCmpOsCodeR::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cfg_manual_cmp_os_update(&self) -> CfgManualCmpOsUpdateR {
                CfgManualCmpOsUpdateR::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:6"]
            #[inline(always)]
            pub fn cfg_manual_cmp_os_code(&mut self) -> CfgManualCmpOsCodeW<'_, CfgCmpOs12Spec> {
                CfgManualCmpOsCodeW::new(self, 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cfg_manual_cmp_os_update(
                &mut self,
            ) -> CfgManualCmpOsUpdateW<'_, CfgCmpOs12Spec> {
                CfgManualCmpOsUpdateW::new(self, 8)
            }
        }
        #[doc = "cfg_cmp_os_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_os_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_os_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmpOs12Spec;
        impl crate::RegisterSpec for CfgCmpOs12Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_os_12::R`](R) reader structure"]
        impl crate::Readable for CfgCmpOs12Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_os_12::W`](W) writer structure"]
        impl crate::Writable for CfgCmpOs12Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_OS_12 to value 0"]
        impl crate::Resettable for CfgCmpOs12Spec {}
    }
    #[doc = "RPT_CMP_OS_2 (rw) register accessor: rpt_cmp_os_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_os_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_os_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cmp_os_2`] module"]
    #[doc(alias = "RPT_CMP_OS_2")]
    pub type RptCmpOs2 = crate::Reg<rpt_cmp_os_2::RptCmpOs2Spec>;
    #[doc = "rpt_cmp_os_2"]
    pub mod rpt_cmp_os_2 {
        #[doc = "Register `RPT_CMP_OS_2` reader"]
        pub type R = crate::R<RptCmpOs2Spec>;
        #[doc = "Register `RPT_CMP_OS_2` writer"]
        pub type W = crate::W<RptCmpOs2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cmp_os_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_os_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_os_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCmpOs2Spec;
        impl crate::RegisterSpec for RptCmpOs2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cmp_os_2::R`](R) reader structure"]
        impl crate::Readable for RptCmpOs2Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cmp_os_2::W`](W) writer structure"]
        impl crate::Writable for RptCmpOs2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CMP_OS_2 to value 0"]
        impl crate::Resettable for RptCmpOs2Spec {}
    }
    #[doc = "CFG_CDAC_FC0_0 (rw) register accessor: cfg_cdac_fc0_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_0`] module"]
    #[doc(alias = "CFG_CDAC_FC0_0")]
    pub type CfgCdacFc0_0 = crate::Reg<cfg_cdac_fc0_0::CfgCdacFc0_0Spec>;
    #[doc = "cfg_cdac_fc0_0"]
    pub mod cfg_cdac_fc0_0 {
        #[doc = "Register `CFG_CDAC_FC0_0` reader"]
        pub type R = crate::R<CfgCdacFc0_0Spec>;
        #[doc = "Register `CFG_CDAC_FC0_0` writer"]
        pub type W = crate::W<CfgCdacFc0_0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_0Spec;
        impl crate::RegisterSpec for CfgCdacFc0_0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_0::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_0::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_0 to value 0"]
        impl crate::Resettable for CfgCdacFc0_0Spec {}
    }
    #[doc = "CFG_CDAC_FC0_1 (rw) register accessor: cfg_cdac_fc0_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_1`] module"]
    #[doc(alias = "CFG_CDAC_FC0_1")]
    pub type CfgCdacFc0_1 = crate::Reg<cfg_cdac_fc0_1::CfgCdacFc0_1Spec>;
    #[doc = "cfg_cdac_fc0_1"]
    pub mod cfg_cdac_fc0_1 {
        #[doc = "Register `CFG_CDAC_FC0_1` reader"]
        pub type R = crate::R<CfgCdacFc0_1Spec>;
        #[doc = "Register `CFG_CDAC_FC0_1` writer"]
        pub type W = crate::W<CfgCdacFc0_1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_1Spec;
        impl crate::RegisterSpec for CfgCdacFc0_1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_1::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_1::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_1 to value 0"]
        impl crate::Resettable for CfgCdacFc0_1Spec {}
    }
    #[doc = "CFG_CDAC_FC0_2 (rw) register accessor: cfg_cdac_fc0_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_2`] module"]
    #[doc(alias = "CFG_CDAC_FC0_2")]
    pub type CfgCdacFc0_2 = crate::Reg<cfg_cdac_fc0_2::CfgCdacFc0_2Spec>;
    #[doc = "cfg_cdac_fc0_2"]
    pub mod cfg_cdac_fc0_2 {
        #[doc = "Register `CFG_CDAC_FC0_2` reader"]
        pub type R = crate::R<CfgCdacFc0_2Spec>;
        #[doc = "Register `CFG_CDAC_FC0_2` writer"]
        pub type W = crate::W<CfgCdacFc0_2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_2Spec;
        impl crate::RegisterSpec for CfgCdacFc0_2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_2::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_2Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_2::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_2 to value 0"]
        impl crate::Resettable for CfgCdacFc0_2Spec {}
    }
    #[doc = "CFG_CDAC_FC0_3 (rw) register accessor: cfg_cdac_fc0_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_3`] module"]
    #[doc(alias = "CFG_CDAC_FC0_3")]
    pub type CfgCdacFc0_3 = crate::Reg<cfg_cdac_fc0_3::CfgCdacFc0_3Spec>;
    #[doc = "cfg_cdac_fc0_3"]
    pub mod cfg_cdac_fc0_3 {
        #[doc = "Register `CFG_CDAC_FC0_3` reader"]
        pub type R = crate::R<CfgCdacFc0_3Spec>;
        #[doc = "Register `CFG_CDAC_FC0_3` writer"]
        pub type W = crate::W<CfgCdacFc0_3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_3Spec;
        impl crate::RegisterSpec for CfgCdacFc0_3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_3::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_3Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_3::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_3 to value 0"]
        impl crate::Resettable for CfgCdacFc0_3Spec {}
    }
    #[doc = "CFG_CDAC_FC0_4 (rw) register accessor: cfg_cdac_fc0_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_4`] module"]
    #[doc(alias = "CFG_CDAC_FC0_4")]
    pub type CfgCdacFc0_4 = crate::Reg<cfg_cdac_fc0_4::CfgCdacFc0_4Spec>;
    #[doc = "cfg_cdac_fc0_4"]
    pub mod cfg_cdac_fc0_4 {
        #[doc = "Register `CFG_CDAC_FC0_4` reader"]
        pub type R = crate::R<CfgCdacFc0_4Spec>;
        #[doc = "Register `CFG_CDAC_FC0_4` writer"]
        pub type W = crate::W<CfgCdacFc0_4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_4Spec;
        impl crate::RegisterSpec for CfgCdacFc0_4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_4::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_4Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_4::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_4 to value 0"]
        impl crate::Resettable for CfgCdacFc0_4Spec {}
    }
    #[doc = "CFG_CDAC_FC0_5 (rw) register accessor: cfg_cdac_fc0_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_5`] module"]
    #[doc(alias = "CFG_CDAC_FC0_5")]
    pub type CfgCdacFc0_5 = crate::Reg<cfg_cdac_fc0_5::CfgCdacFc0_5Spec>;
    #[doc = "cfg_cdac_fc0_5"]
    pub mod cfg_cdac_fc0_5 {
        #[doc = "Register `CFG_CDAC_FC0_5` reader"]
        pub type R = crate::R<CfgCdacFc0_5Spec>;
        #[doc = "Register `CFG_CDAC_FC0_5` writer"]
        pub type W = crate::W<CfgCdacFc0_5Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_5Spec;
        impl crate::RegisterSpec for CfgCdacFc0_5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_5::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_5Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_5::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_5 to value 0"]
        impl crate::Resettable for CfgCdacFc0_5Spec {}
    }
    #[doc = "RPT_CDAC_FC0_0 (rw) register accessor: rpt_cdac_fc0_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc0_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc0_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc0_0`] module"]
    #[doc(alias = "RPT_CDAC_FC0_0")]
    pub type RptCdacFc0_0 = crate::Reg<rpt_cdac_fc0_0::RptCdacFc0_0Spec>;
    #[doc = "rpt_cdac_fc0_0"]
    pub mod rpt_cdac_fc0_0 {
        #[doc = "Register `RPT_CDAC_FC0_0` reader"]
        pub type R = crate::R<RptCdacFc0_0Spec>;
        #[doc = "Register `RPT_CDAC_FC0_0` writer"]
        pub type W = crate::W<RptCdacFc0_0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc0_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc0_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc0_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc0_0Spec;
        impl crate::RegisterSpec for RptCdacFc0_0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc0_0::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc0_0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc0_0::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc0_0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC0_0 to value 0"]
        impl crate::Resettable for RptCdacFc0_0Spec {}
    }
    #[doc = "CFG_CDAC_FC0_6 (rw) register accessor: cfg_cdac_fc0_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_6`] module"]
    #[doc(alias = "CFG_CDAC_FC0_6")]
    pub type CfgCdacFc0_6 = crate::Reg<cfg_cdac_fc0_6::CfgCdacFc0_6Spec>;
    #[doc = "cfg_cdac_fc0_6"]
    pub mod cfg_cdac_fc0_6 {
        #[doc = "Register `CFG_CDAC_FC0_6` reader"]
        pub type R = crate::R<CfgCdacFc0_6Spec>;
        #[doc = "Register `CFG_CDAC_FC0_6` writer"]
        pub type W = crate::W<CfgCdacFc0_6Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_6Spec;
        impl crate::RegisterSpec for CfgCdacFc0_6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_6::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_6Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_6::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_6 to value 0"]
        impl crate::Resettable for CfgCdacFc0_6Spec {}
    }
    #[doc = "CFG_CDAC_FC0_7 (rw) register accessor: cfg_cdac_fc0_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_7`] module"]
    #[doc(alias = "CFG_CDAC_FC0_7")]
    pub type CfgCdacFc0_7 = crate::Reg<cfg_cdac_fc0_7::CfgCdacFc0_7Spec>;
    #[doc = "cfg_cdac_fc0_7"]
    pub mod cfg_cdac_fc0_7 {
        #[doc = "Register `CFG_CDAC_FC0_7` reader"]
        pub type R = crate::R<CfgCdacFc0_7Spec>;
        #[doc = "Register `CFG_CDAC_FC0_7` writer"]
        pub type W = crate::W<CfgCdacFc0_7Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_7Spec;
        impl crate::RegisterSpec for CfgCdacFc0_7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_7::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_7Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_7::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_7 to value 0"]
        impl crate::Resettable for CfgCdacFc0_7Spec {}
    }
    #[doc = "CFG_CDAC_FC0_8 (rw) register accessor: cfg_cdac_fc0_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_8`] module"]
    #[doc(alias = "CFG_CDAC_FC0_8")]
    pub type CfgCdacFc0_8 = crate::Reg<cfg_cdac_fc0_8::CfgCdacFc0_8Spec>;
    #[doc = "cfg_cdac_fc0_8"]
    pub mod cfg_cdac_fc0_8 {
        #[doc = "Register `CFG_CDAC_FC0_8` reader"]
        pub type R = crate::R<CfgCdacFc0_8Spec>;
        #[doc = "Register `CFG_CDAC_FC0_8` writer"]
        pub type W = crate::W<CfgCdacFc0_8Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_8Spec;
        impl crate::RegisterSpec for CfgCdacFc0_8Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_8::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_8Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_8::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_8Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_8 to value 0"]
        impl crate::Resettable for CfgCdacFc0_8Spec {}
    }
    #[doc = "CFG_CDAC_FC0_9 (rw) register accessor: cfg_cdac_fc0_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_9`] module"]
    #[doc(alias = "CFG_CDAC_FC0_9")]
    pub type CfgCdacFc0_9 = crate::Reg<cfg_cdac_fc0_9::CfgCdacFc0_9Spec>;
    #[doc = "cfg_cdac_fc0_9"]
    pub mod cfg_cdac_fc0_9 {
        #[doc = "Register `CFG_CDAC_FC0_9` reader"]
        pub type R = crate::R<CfgCdacFc0_9Spec>;
        #[doc = "Register `CFG_CDAC_FC0_9` writer"]
        pub type W = crate::W<CfgCdacFc0_9Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_9\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_9Spec;
        impl crate::RegisterSpec for CfgCdacFc0_9Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_9::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_9Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_9::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_9Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_9 to value 0"]
        impl crate::Resettable for CfgCdacFc0_9Spec {}
    }
    #[doc = "CFG_CDAC_FC0_10 (rw) register accessor: cfg_cdac_fc0_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_10`] module"]
    #[doc(alias = "CFG_CDAC_FC0_10")]
    pub type CfgCdacFc0_10 = crate::Reg<cfg_cdac_fc0_10::CfgCdacFc0_10Spec>;
    #[doc = "cfg_cdac_fc0_10"]
    pub mod cfg_cdac_fc0_10 {
        #[doc = "Register `CFG_CDAC_FC0_10` reader"]
        pub type R = crate::R<CfgCdacFc0_10Spec>;
        #[doc = "Register `CFG_CDAC_FC0_10` writer"]
        pub type W = crate::W<CfgCdacFc0_10Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_10\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_10Spec;
        impl crate::RegisterSpec for CfgCdacFc0_10Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_10::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_10Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_10::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_10Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_10 to value 0"]
        impl crate::Resettable for CfgCdacFc0_10Spec {}
    }
    #[doc = "CFG_CDAC_FC0_11 (rw) register accessor: cfg_cdac_fc0_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_11`] module"]
    #[doc(alias = "CFG_CDAC_FC0_11")]
    pub type CfgCdacFc0_11 = crate::Reg<cfg_cdac_fc0_11::CfgCdacFc0_11Spec>;
    #[doc = "cfg_cdac_fc0_11"]
    pub mod cfg_cdac_fc0_11 {
        #[doc = "Register `CFG_CDAC_FC0_11` reader"]
        pub type R = crate::R<CfgCdacFc0_11Spec>;
        #[doc = "Register `CFG_CDAC_FC0_11` writer"]
        pub type W = crate::W<CfgCdacFc0_11Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_11\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_11Spec;
        impl crate::RegisterSpec for CfgCdacFc0_11Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_11::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_11Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_11::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_11Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_11 to value 0"]
        impl crate::Resettable for CfgCdacFc0_11Spec {}
    }
    #[doc = "CFG_CDAC_FC0_12 (rw) register accessor: cfg_cdac_fc0_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_12`] module"]
    #[doc(alias = "CFG_CDAC_FC0_12")]
    pub type CfgCdacFc0_12 = crate::Reg<cfg_cdac_fc0_12::CfgCdacFc0_12Spec>;
    #[doc = "cfg_cdac_fc0_12"]
    pub mod cfg_cdac_fc0_12 {
        #[doc = "Register `CFG_CDAC_FC0_12` reader"]
        pub type R = crate::R<CfgCdacFc0_12Spec>;
        #[doc = "Register `CFG_CDAC_FC0_12` writer"]
        pub type W = crate::W<CfgCdacFc0_12Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_12Spec;
        impl crate::RegisterSpec for CfgCdacFc0_12Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_12::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_12Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_12::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_12Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_12 to value 0"]
        impl crate::Resettable for CfgCdacFc0_12Spec {}
    }
    #[doc = "CFG_CDAC_FC0_13 (rw) register accessor: cfg_cdac_fc0_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_13`] module"]
    #[doc(alias = "CFG_CDAC_FC0_13")]
    pub type CfgCdacFc0_13 = crate::Reg<cfg_cdac_fc0_13::CfgCdacFc0_13Spec>;
    #[doc = "cfg_cdac_fc0_13"]
    pub mod cfg_cdac_fc0_13 {
        #[doc = "Register `CFG_CDAC_FC0_13` reader"]
        pub type R = crate::R<CfgCdacFc0_13Spec>;
        #[doc = "Register `CFG_CDAC_FC0_13` writer"]
        pub type W = crate::W<CfgCdacFc0_13Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_13Spec;
        impl crate::RegisterSpec for CfgCdacFc0_13Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_13::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_13Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_13::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_13Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_13 to value 0"]
        impl crate::Resettable for CfgCdacFc0_13Spec {}
    }
    #[doc = "CFG_CDAC_FC0_14 (rw) register accessor: cfg_cdac_fc0_14\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc0_14`] module"]
    #[doc(alias = "CFG_CDAC_FC0_14")]
    pub type CfgCdacFc0_14 = crate::Reg<cfg_cdac_fc0_14::CfgCdacFc0_14Spec>;
    #[doc = "cfg_cdac_fc0_14"]
    pub mod cfg_cdac_fc0_14 {
        #[doc = "Register `CFG_CDAC_FC0_14` reader"]
        pub type R = crate::R<CfgCdacFc0_14Spec>;
        #[doc = "Register `CFG_CDAC_FC0_14` writer"]
        pub type W = crate::W<CfgCdacFc0_14Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc0_14\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc0_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc0_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc0_14Spec;
        impl crate::RegisterSpec for CfgCdacFc0_14Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc0_14::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc0_14Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc0_14::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc0_14Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC0_14 to value 0"]
        impl crate::Resettable for CfgCdacFc0_14Spec {}
    }
    #[doc = "CFG_CDAC_FC1_0 (rw) register accessor: cfg_cdac_fc1_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc1_0`] module"]
    #[doc(alias = "CFG_CDAC_FC1_0")]
    pub type CfgCdacFc1_0 = crate::Reg<cfg_cdac_fc1_0::CfgCdacFc1_0Spec>;
    #[doc = "cfg_cdac_fc1_0"]
    pub mod cfg_cdac_fc1_0 {
        #[doc = "Register `CFG_CDAC_FC1_0` reader"]
        pub type R = crate::R<CfgCdacFc1_0Spec>;
        #[doc = "Register `CFG_CDAC_FC1_0` writer"]
        pub type W = crate::W<CfgCdacFc1_0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc1_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc1_0Spec;
        impl crate::RegisterSpec for CfgCdacFc1_0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc1_0::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc1_0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc1_0::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc1_0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC1_0 to value 0"]
        impl crate::Resettable for CfgCdacFc1_0Spec {}
    }
    #[doc = "CFG_CDAC_FC1_1 (rw) register accessor: cfg_cdac_fc1_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc1_1`] module"]
    #[doc(alias = "CFG_CDAC_FC1_1")]
    pub type CfgCdacFc1_1 = crate::Reg<cfg_cdac_fc1_1::CfgCdacFc1_1Spec>;
    #[doc = "cfg_cdac_fc1_1"]
    pub mod cfg_cdac_fc1_1 {
        #[doc = "Register `CFG_CDAC_FC1_1` reader"]
        pub type R = crate::R<CfgCdacFc1_1Spec>;
        #[doc = "Register `CFG_CDAC_FC1_1` writer"]
        pub type W = crate::W<CfgCdacFc1_1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc1_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc1_1Spec;
        impl crate::RegisterSpec for CfgCdacFc1_1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc1_1::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc1_1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc1_1::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc1_1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC1_1 to value 0"]
        impl crate::Resettable for CfgCdacFc1_1Spec {}
    }
    #[doc = "CFG_CDAC_FC1_2 (rw) register accessor: cfg_cdac_fc1_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc1_2`] module"]
    #[doc(alias = "CFG_CDAC_FC1_2")]
    pub type CfgCdacFc1_2 = crate::Reg<cfg_cdac_fc1_2::CfgCdacFc1_2Spec>;
    #[doc = "cfg_cdac_fc1_2"]
    pub mod cfg_cdac_fc1_2 {
        #[doc = "Register `CFG_CDAC_FC1_2` reader"]
        pub type R = crate::R<CfgCdacFc1_2Spec>;
        #[doc = "Register `CFG_CDAC_FC1_2` writer"]
        pub type W = crate::W<CfgCdacFc1_2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc1_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc1_2Spec;
        impl crate::RegisterSpec for CfgCdacFc1_2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc1_2::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc1_2Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc1_2::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc1_2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC1_2 to value 0"]
        impl crate::Resettable for CfgCdacFc1_2Spec {}
    }
    #[doc = "CFG_CDAC_FC1_3 (rw) register accessor: cfg_cdac_fc1_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cdac_fc1_3`] module"]
    #[doc(alias = "CFG_CDAC_FC1_3")]
    pub type CfgCdacFc1_3 = crate::Reg<cfg_cdac_fc1_3::CfgCdacFc1_3Spec>;
    #[doc = "cfg_cdac_fc1_3"]
    pub mod cfg_cdac_fc1_3 {
        #[doc = "Register `CFG_CDAC_FC1_3` reader"]
        pub type R = crate::R<CfgCdacFc1_3Spec>;
        #[doc = "Register `CFG_CDAC_FC1_3` writer"]
        pub type W = crate::W<CfgCdacFc1_3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cdac_fc1_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cdac_fc1_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cdac_fc1_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCdacFc1_3Spec;
        impl crate::RegisterSpec for CfgCdacFc1_3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cdac_fc1_3::R`](R) reader structure"]
        impl crate::Readable for CfgCdacFc1_3Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cdac_fc1_3::W`](W) writer structure"]
        impl crate::Writable for CfgCdacFc1_3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CDAC_FC1_3 to value 0"]
        impl crate::Resettable for CfgCdacFc1_3Spec {}
    }
    #[doc = "RPT_CDAC_FC1_0 (rw) register accessor: rpt_cdac_fc1_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc1_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc1_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc1_0`] module"]
    #[doc(alias = "RPT_CDAC_FC1_0")]
    pub type RptCdacFc1_0 = crate::Reg<rpt_cdac_fc1_0::RptCdacFc1_0Spec>;
    #[doc = "rpt_cdac_fc1_0"]
    pub mod rpt_cdac_fc1_0 {
        #[doc = "Register `RPT_CDAC_FC1_0` reader"]
        pub type R = crate::R<RptCdacFc1_0Spec>;
        #[doc = "Register `RPT_CDAC_FC1_0` writer"]
        pub type W = crate::W<RptCdacFc1_0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc1_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc1_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc1_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc1_0Spec;
        impl crate::RegisterSpec for RptCdacFc1_0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc1_0::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc1_0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc1_0::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc1_0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC1_0 to value 0"]
        impl crate::Resettable for RptCdacFc1_0Spec {}
    }
    #[doc = "RPT_CDAC_FC1_3 (rw) register accessor: rpt_cdac_fc1_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc1_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc1_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc1_3`] module"]
    #[doc(alias = "RPT_CDAC_FC1_3")]
    pub type RptCdacFc1_3 = crate::Reg<rpt_cdac_fc1_3::RptCdacFc1_3Spec>;
    #[doc = "rpt_cdac_fc1_3"]
    pub mod rpt_cdac_fc1_3 {
        #[doc = "Register `RPT_CDAC_FC1_3` reader"]
        pub type R = crate::R<RptCdacFc1_3Spec>;
        #[doc = "Register `RPT_CDAC_FC1_3` writer"]
        pub type W = crate::W<RptCdacFc1_3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc1_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc1_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc1_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc1_3Spec;
        impl crate::RegisterSpec for RptCdacFc1_3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc1_3::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc1_3Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc1_3::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc1_3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC1_3 to value 0"]
        impl crate::Resettable for RptCdacFc1_3Spec {}
    }
    #[doc = "RPT_CDAC_FC3_1 (rw) register accessor: rpt_cdac_fc3_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_1`] module"]
    #[doc(alias = "RPT_CDAC_FC3_1")]
    pub type RptCdacFc3_1 = crate::Reg<rpt_cdac_fc3_1::RptCdacFc3_1Spec>;
    #[doc = "rpt_cdac_fc3_1"]
    pub mod rpt_cdac_fc3_1 {
        #[doc = "Register `RPT_CDAC_FC3_1` reader"]
        pub type R = crate::R<RptCdacFc3_1Spec>;
        #[doc = "Register `RPT_CDAC_FC3_1` writer"]
        pub type W = crate::W<RptCdacFc3_1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_1Spec;
        impl crate::RegisterSpec for RptCdacFc3_1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_1::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_1Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_1::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_1 to value 0"]
        impl crate::Resettable for RptCdacFc3_1Spec {}
    }
    #[doc = "RPT_CDAC_FC3_2 (rw) register accessor: rpt_cdac_fc3_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_2`] module"]
    #[doc(alias = "RPT_CDAC_FC3_2")]
    pub type RptCdacFc3_2 = crate::Reg<rpt_cdac_fc3_2::RptCdacFc3_2Spec>;
    #[doc = "rpt_cdac_fc3_2"]
    pub mod rpt_cdac_fc3_2 {
        #[doc = "Register `RPT_CDAC_FC3_2` reader"]
        pub type R = crate::R<RptCdacFc3_2Spec>;
        #[doc = "Register `RPT_CDAC_FC3_2` writer"]
        pub type W = crate::W<RptCdacFc3_2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_2Spec;
        impl crate::RegisterSpec for RptCdacFc3_2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_2::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_2Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_2::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_2 to value 0"]
        impl crate::Resettable for RptCdacFc3_2Spec {}
    }
    #[doc = "RPT_CDAC_FC3_3 (rw) register accessor: rpt_cdac_fc3_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_3`] module"]
    #[doc(alias = "RPT_CDAC_FC3_3")]
    pub type RptCdacFc3_3 = crate::Reg<rpt_cdac_fc3_3::RptCdacFc3_3Spec>;
    #[doc = "rpt_cdac_fc3_3"]
    pub mod rpt_cdac_fc3_3 {
        #[doc = "Register `RPT_CDAC_FC3_3` reader"]
        pub type R = crate::R<RptCdacFc3_3Spec>;
        #[doc = "Register `RPT_CDAC_FC3_3` writer"]
        pub type W = crate::W<RptCdacFc3_3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_3Spec;
        impl crate::RegisterSpec for RptCdacFc3_3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_3::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_3Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_3::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_3 to value 0"]
        impl crate::Resettable for RptCdacFc3_3Spec {}
    }
    #[doc = "RPT_CDAC_FC3_4 (rw) register accessor: rpt_cdac_fc3_4\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_4`] module"]
    #[doc(alias = "RPT_CDAC_FC3_4")]
    pub type RptCdacFc3_4 = crate::Reg<rpt_cdac_fc3_4::RptCdacFc3_4Spec>;
    #[doc = "rpt_cdac_fc3_4"]
    pub mod rpt_cdac_fc3_4 {
        #[doc = "Register `RPT_CDAC_FC3_4` reader"]
        pub type R = crate::R<RptCdacFc3_4Spec>;
        #[doc = "Register `RPT_CDAC_FC3_4` writer"]
        pub type W = crate::W<RptCdacFc3_4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_4\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_4Spec;
        impl crate::RegisterSpec for RptCdacFc3_4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_4::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_4Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_4::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_4 to value 0"]
        impl crate::Resettable for RptCdacFc3_4Spec {}
    }
    #[doc = "RPT_CDAC_FC3_5 (rw) register accessor: rpt_cdac_fc3_5\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_5`] module"]
    #[doc(alias = "RPT_CDAC_FC3_5")]
    pub type RptCdacFc3_5 = crate::Reg<rpt_cdac_fc3_5::RptCdacFc3_5Spec>;
    #[doc = "rpt_cdac_fc3_5"]
    pub mod rpt_cdac_fc3_5 {
        #[doc = "Register `RPT_CDAC_FC3_5` reader"]
        pub type R = crate::R<RptCdacFc3_5Spec>;
        #[doc = "Register `RPT_CDAC_FC3_5` writer"]
        pub type W = crate::W<RptCdacFc3_5Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_5\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_5Spec;
        impl crate::RegisterSpec for RptCdacFc3_5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_5::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_5Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_5::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_5 to value 0"]
        impl crate::Resettable for RptCdacFc3_5Spec {}
    }
    #[doc = "RPT_CDAC_FC3_6 (rw) register accessor: rpt_cdac_fc3_6\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_6`] module"]
    #[doc(alias = "RPT_CDAC_FC3_6")]
    pub type RptCdacFc3_6 = crate::Reg<rpt_cdac_fc3_6::RptCdacFc3_6Spec>;
    #[doc = "rpt_cdac_fc3_6"]
    pub mod rpt_cdac_fc3_6 {
        #[doc = "Register `RPT_CDAC_FC3_6` reader"]
        pub type R = crate::R<RptCdacFc3_6Spec>;
        #[doc = "Register `RPT_CDAC_FC3_6` writer"]
        pub type W = crate::W<RptCdacFc3_6Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_6\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_6Spec;
        impl crate::RegisterSpec for RptCdacFc3_6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_6::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_6Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_6::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_6 to value 0"]
        impl crate::Resettable for RptCdacFc3_6Spec {}
    }
    #[doc = "RPT_CDAC_FC3_7 (rw) register accessor: rpt_cdac_fc3_7\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_7`] module"]
    #[doc(alias = "RPT_CDAC_FC3_7")]
    pub type RptCdacFc3_7 = crate::Reg<rpt_cdac_fc3_7::RptCdacFc3_7Spec>;
    #[doc = "rpt_cdac_fc3_7"]
    pub mod rpt_cdac_fc3_7 {
        #[doc = "Register `RPT_CDAC_FC3_7` reader"]
        pub type R = crate::R<RptCdacFc3_7Spec>;
        #[doc = "Register `RPT_CDAC_FC3_7` writer"]
        pub type W = crate::W<RptCdacFc3_7Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_7\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_7Spec;
        impl crate::RegisterSpec for RptCdacFc3_7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_7::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_7Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_7::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_7 to value 0"]
        impl crate::Resettable for RptCdacFc3_7Spec {}
    }
    #[doc = "RPT_CDAC_FC3_8 (rw) register accessor: rpt_cdac_fc3_8\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_8`] module"]
    #[doc(alias = "RPT_CDAC_FC3_8")]
    pub type RptCdacFc3_8 = crate::Reg<rpt_cdac_fc3_8::RptCdacFc3_8Spec>;
    #[doc = "rpt_cdac_fc3_8"]
    pub mod rpt_cdac_fc3_8 {
        #[doc = "Register `RPT_CDAC_FC3_8` reader"]
        pub type R = crate::R<RptCdacFc3_8Spec>;
        #[doc = "Register `RPT_CDAC_FC3_8` writer"]
        pub type W = crate::W<RptCdacFc3_8Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_8\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_8Spec;
        impl crate::RegisterSpec for RptCdacFc3_8Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_8::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_8Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_8::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_8Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_8 to value 0"]
        impl crate::Resettable for RptCdacFc3_8Spec {}
    }
    #[doc = "RPT_CDAC_FC3_9 (rw) register accessor: rpt_cdac_fc3_9\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_9`] module"]
    #[doc(alias = "RPT_CDAC_FC3_9")]
    pub type RptCdacFc3_9 = crate::Reg<rpt_cdac_fc3_9::RptCdacFc3_9Spec>;
    #[doc = "rpt_cdac_fc3_9"]
    pub mod rpt_cdac_fc3_9 {
        #[doc = "Register `RPT_CDAC_FC3_9` reader"]
        pub type R = crate::R<RptCdacFc3_9Spec>;
        #[doc = "Register `RPT_CDAC_FC3_9` writer"]
        pub type W = crate::W<RptCdacFc3_9Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_9\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_9Spec;
        impl crate::RegisterSpec for RptCdacFc3_9Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_9::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_9Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_9::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_9Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_9 to value 0"]
        impl crate::Resettable for RptCdacFc3_9Spec {}
    }
    #[doc = "RPT_CDAC_FC3_10 (rw) register accessor: rpt_cdac_fc3_10\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_10`] module"]
    #[doc(alias = "RPT_CDAC_FC3_10")]
    pub type RptCdacFc3_10 = crate::Reg<rpt_cdac_fc3_10::RptCdacFc3_10Spec>;
    #[doc = "rpt_cdac_fc3_10"]
    pub mod rpt_cdac_fc3_10 {
        #[doc = "Register `RPT_CDAC_FC3_10` reader"]
        pub type R = crate::R<RptCdacFc3_10Spec>;
        #[doc = "Register `RPT_CDAC_FC3_10` writer"]
        pub type W = crate::W<RptCdacFc3_10Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_10\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_10Spec;
        impl crate::RegisterSpec for RptCdacFc3_10Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_10::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_10Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_10::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_10Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_10 to value 0"]
        impl crate::Resettable for RptCdacFc3_10Spec {}
    }
    #[doc = "RPT_CDAC_FC3_11 (rw) register accessor: rpt_cdac_fc3_11\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_11`] module"]
    #[doc(alias = "RPT_CDAC_FC3_11")]
    pub type RptCdacFc3_11 = crate::Reg<rpt_cdac_fc3_11::RptCdacFc3_11Spec>;
    #[doc = "rpt_cdac_fc3_11"]
    pub mod rpt_cdac_fc3_11 {
        #[doc = "Register `RPT_CDAC_FC3_11` reader"]
        pub type R = crate::R<RptCdacFc3_11Spec>;
        #[doc = "Register `RPT_CDAC_FC3_11` writer"]
        pub type W = crate::W<RptCdacFc3_11Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_11\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_11Spec;
        impl crate::RegisterSpec for RptCdacFc3_11Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_11::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_11Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_11::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_11Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_11 to value 0"]
        impl crate::Resettable for RptCdacFc3_11Spec {}
    }
    #[doc = "RPT_CDAC_FC3_12 (rw) register accessor: rpt_cdac_fc3_12\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_12`] module"]
    #[doc(alias = "RPT_CDAC_FC3_12")]
    pub type RptCdacFc3_12 = crate::Reg<rpt_cdac_fc3_12::RptCdacFc3_12Spec>;
    #[doc = "rpt_cdac_fc3_12"]
    pub mod rpt_cdac_fc3_12 {
        #[doc = "Register `RPT_CDAC_FC3_12` reader"]
        pub type R = crate::R<RptCdacFc3_12Spec>;
        #[doc = "Register `RPT_CDAC_FC3_12` writer"]
        pub type W = crate::W<RptCdacFc3_12Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_12\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_12Spec;
        impl crate::RegisterSpec for RptCdacFc3_12Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_12::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_12Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_12::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_12Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_12 to value 0"]
        impl crate::Resettable for RptCdacFc3_12Spec {}
    }
    #[doc = "RPT_CDAC_FC3_13 (rw) register accessor: rpt_cdac_fc3_13\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_13`] module"]
    #[doc(alias = "RPT_CDAC_FC3_13")]
    pub type RptCdacFc3_13 = crate::Reg<rpt_cdac_fc3_13::RptCdacFc3_13Spec>;
    #[doc = "rpt_cdac_fc3_13"]
    pub mod rpt_cdac_fc3_13 {
        #[doc = "Register `RPT_CDAC_FC3_13` reader"]
        pub type R = crate::R<RptCdacFc3_13Spec>;
        #[doc = "Register `RPT_CDAC_FC3_13` writer"]
        pub type W = crate::W<RptCdacFc3_13Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_13\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_13Spec;
        impl crate::RegisterSpec for RptCdacFc3_13Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_13::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_13Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_13::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_13Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_13 to value 0"]
        impl crate::Resettable for RptCdacFc3_13Spec {}
    }
    #[doc = "RPT_CDAC_FC3_14 (rw) register accessor: rpt_cdac_fc3_14\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_14`] module"]
    #[doc(alias = "RPT_CDAC_FC3_14")]
    pub type RptCdacFc3_14 = crate::Reg<rpt_cdac_fc3_14::RptCdacFc3_14Spec>;
    #[doc = "rpt_cdac_fc3_14"]
    pub mod rpt_cdac_fc3_14 {
        #[doc = "Register `RPT_CDAC_FC3_14` reader"]
        pub type R = crate::R<RptCdacFc3_14Spec>;
        #[doc = "Register `RPT_CDAC_FC3_14` writer"]
        pub type W = crate::W<RptCdacFc3_14Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_14\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_14Spec;
        impl crate::RegisterSpec for RptCdacFc3_14Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_14::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_14Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_14::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_14Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_14 to value 0"]
        impl crate::Resettable for RptCdacFc3_14Spec {}
    }
    #[doc = "RPT_CDAC_FC3_15 (rw) register accessor: rpt_cdac_fc3_15\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_15`] module"]
    #[doc(alias = "RPT_CDAC_FC3_15")]
    pub type RptCdacFc3_15 = crate::Reg<rpt_cdac_fc3_15::RptCdacFc3_15Spec>;
    #[doc = "rpt_cdac_fc3_15"]
    pub mod rpt_cdac_fc3_15 {
        #[doc = "Register `RPT_CDAC_FC3_15` reader"]
        pub type R = crate::R<RptCdacFc3_15Spec>;
        #[doc = "Register `RPT_CDAC_FC3_15` writer"]
        pub type W = crate::W<RptCdacFc3_15Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_15\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_15Spec;
        impl crate::RegisterSpec for RptCdacFc3_15Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_15::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_15Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_15::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_15Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_15 to value 0"]
        impl crate::Resettable for RptCdacFc3_15Spec {}
    }
    #[doc = "RPT_CDAC_FC3_16 (rw) register accessor: rpt_cdac_fc3_16\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_16`] module"]
    #[doc(alias = "RPT_CDAC_FC3_16")]
    pub type RptCdacFc3_16 = crate::Reg<rpt_cdac_fc3_16::RptCdacFc3_16Spec>;
    #[doc = "rpt_cdac_fc3_16"]
    pub mod rpt_cdac_fc3_16 {
        #[doc = "Register `RPT_CDAC_FC3_16` reader"]
        pub type R = crate::R<RptCdacFc3_16Spec>;
        #[doc = "Register `RPT_CDAC_FC3_16` writer"]
        pub type W = crate::W<RptCdacFc3_16Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_16\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_16Spec;
        impl crate::RegisterSpec for RptCdacFc3_16Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_16::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_16Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_16::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_16Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_16 to value 0"]
        impl crate::Resettable for RptCdacFc3_16Spec {}
    }
    #[doc = "RPT_CDAC_FC3_17 (rw) register accessor: rpt_cdac_fc3_17\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_17`] module"]
    #[doc(alias = "RPT_CDAC_FC3_17")]
    pub type RptCdacFc3_17 = crate::Reg<rpt_cdac_fc3_17::RptCdacFc3_17Spec>;
    #[doc = "rpt_cdac_fc3_17"]
    pub mod rpt_cdac_fc3_17 {
        #[doc = "Register `RPT_CDAC_FC3_17` reader"]
        pub type R = crate::R<RptCdacFc3_17Spec>;
        #[doc = "Register `RPT_CDAC_FC3_17` writer"]
        pub type W = crate::W<RptCdacFc3_17Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_17\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_17Spec;
        impl crate::RegisterSpec for RptCdacFc3_17Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_17::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_17Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_17::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_17Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_17 to value 0"]
        impl crate::Resettable for RptCdacFc3_17Spec {}
    }
    #[doc = "RPT_CDAC_FC3_18 (rw) register accessor: rpt_cdac_fc3_18\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cdac_fc3_18`] module"]
    #[doc(alias = "RPT_CDAC_FC3_18")]
    pub type RptCdacFc3_18 = crate::Reg<rpt_cdac_fc3_18::RptCdacFc3_18Spec>;
    #[doc = "rpt_cdac_fc3_18"]
    pub mod rpt_cdac_fc3_18 {
        #[doc = "Register `RPT_CDAC_FC3_18` reader"]
        pub type R = crate::R<RptCdacFc3_18Spec>;
        #[doc = "Register `RPT_CDAC_FC3_18` writer"]
        pub type W = crate::W<RptCdacFc3_18Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cdac_fc3_18\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cdac_fc3_18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cdac_fc3_18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCdacFc3_18Spec;
        impl crate::RegisterSpec for RptCdacFc3_18Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cdac_fc3_18::R`](R) reader structure"]
        impl crate::Readable for RptCdacFc3_18Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cdac_fc3_18::W`](W) writer structure"]
        impl crate::Writable for RptCdacFc3_18Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CDAC_FC3_18 to value 0"]
        impl crate::Resettable for RptCdacFc3_18Spec {}
    }
    #[doc = "CFG_DCOC_CAL_0 (rw) register accessor: cfg_dcoc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_0`] module"]
    #[doc(alias = "CFG_DCOC_CAL_0")]
    pub type CfgDcocCal0 = crate::Reg<cfg_dcoc_cal_0::CfgDcocCal0Spec>;
    #[doc = "cfg_dcoc_cal_0"]
    pub mod cfg_dcoc_cal_0 {
        #[doc = "Register `CFG_DCOC_CAL_0` reader"]
        pub type R = crate::R<CfgDcocCal0Spec>;
        #[doc = "Register `CFG_DCOC_CAL_0` writer"]
        pub type W = crate::W<CfgDcocCal0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal0Spec;
        impl crate::RegisterSpec for CfgDcocCal0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_0::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_0::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_0 to value 0"]
        impl crate::Resettable for CfgDcocCal0Spec {}
    }
    #[doc = "CFG_DCOC_CAL_1 (rw) register accessor: cfg_dcoc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_1`] module"]
    #[doc(alias = "CFG_DCOC_CAL_1")]
    pub type CfgDcocCal1 = crate::Reg<cfg_dcoc_cal_1::CfgDcocCal1Spec>;
    #[doc = "cfg_dcoc_cal_1"]
    pub mod cfg_dcoc_cal_1 {
        #[doc = "Register `CFG_DCOC_CAL_1` reader"]
        pub type R = crate::R<CfgDcocCal1Spec>;
        #[doc = "Register `CFG_DCOC_CAL_1` writer"]
        pub type W = crate::W<CfgDcocCal1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal1Spec;
        impl crate::RegisterSpec for CfgDcocCal1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_1::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_1::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_1 to value 0"]
        impl crate::Resettable for CfgDcocCal1Spec {}
    }
    #[doc = "CFG_DCOC_CAL_2 (rw) register accessor: cfg_dcoc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_2`] module"]
    #[doc(alias = "CFG_DCOC_CAL_2")]
    pub type CfgDcocCal2 = crate::Reg<cfg_dcoc_cal_2::CfgDcocCal2Spec>;
    #[doc = "cfg_dcoc_cal_2"]
    pub mod cfg_dcoc_cal_2 {
        #[doc = "Register `CFG_DCOC_CAL_2` reader"]
        pub type R = crate::R<CfgDcocCal2Spec>;
        #[doc = "Register `CFG_DCOC_CAL_2` writer"]
        pub type W = crate::W<CfgDcocCal2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal2Spec;
        impl crate::RegisterSpec for CfgDcocCal2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_2::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal2Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_2::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_2 to value 0"]
        impl crate::Resettable for CfgDcocCal2Spec {}
    }
    #[doc = "CFG_DCOC_CAL_3 (rw) register accessor: cfg_dcoc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_3`] module"]
    #[doc(alias = "CFG_DCOC_CAL_3")]
    pub type CfgDcocCal3 = crate::Reg<cfg_dcoc_cal_3::CfgDcocCal3Spec>;
    #[doc = "cfg_dcoc_cal_3"]
    pub mod cfg_dcoc_cal_3 {
        #[doc = "Register `CFG_DCOC_CAL_3` reader"]
        pub type R = crate::R<CfgDcocCal3Spec>;
        #[doc = "Register `CFG_DCOC_CAL_3` writer"]
        pub type W = crate::W<CfgDcocCal3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal3Spec;
        impl crate::RegisterSpec for CfgDcocCal3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_3::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal3Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_3::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_3 to value 0"]
        impl crate::Resettable for CfgDcocCal3Spec {}
    }
    #[doc = "CFG_DCOC_CAL_4 (rw) register accessor: cfg_dcoc_cal_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_4`] module"]
    #[doc(alias = "CFG_DCOC_CAL_4")]
    pub type CfgDcocCal4 = crate::Reg<cfg_dcoc_cal_4::CfgDcocCal4Spec>;
    #[doc = "cfg_dcoc_cal_4"]
    pub mod cfg_dcoc_cal_4 {
        #[doc = "Register `CFG_DCOC_CAL_4` reader"]
        pub type R = crate::R<CfgDcocCal4Spec>;
        #[doc = "Register `CFG_DCOC_CAL_4` writer"]
        pub type W = crate::W<CfgDcocCal4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal4Spec;
        impl crate::RegisterSpec for CfgDcocCal4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_4::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal4Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_4::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_4 to value 0"]
        impl crate::Resettable for CfgDcocCal4Spec {}
    }
    #[doc = "CFG_DCOC_CAL_5 (rw) register accessor: cfg_dcoc_cal_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_5`] module"]
    #[doc(alias = "CFG_DCOC_CAL_5")]
    pub type CfgDcocCal5 = crate::Reg<cfg_dcoc_cal_5::CfgDcocCal5Spec>;
    #[doc = "cfg_dcoc_cal_5"]
    pub mod cfg_dcoc_cal_5 {
        #[doc = "Register `CFG_DCOC_CAL_5` reader"]
        pub type R = crate::R<CfgDcocCal5Spec>;
        #[doc = "Register `CFG_DCOC_CAL_5` writer"]
        pub type W = crate::W<CfgDcocCal5Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal5Spec;
        impl crate::RegisterSpec for CfgDcocCal5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_5::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal5Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_5::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_5 to value 0"]
        impl crate::Resettable for CfgDcocCal5Spec {}
    }
    #[doc = "CFG_DCOC_CAL_6 (rw) register accessor: cfg_dcoc_cal_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_6`] module"]
    #[doc(alias = "CFG_DCOC_CAL_6")]
    pub type CfgDcocCal6 = crate::Reg<cfg_dcoc_cal_6::CfgDcocCal6Spec>;
    #[doc = "cfg_dcoc_cal_6"]
    pub mod cfg_dcoc_cal_6 {
        #[doc = "Register `CFG_DCOC_CAL_6` reader"]
        pub type R = crate::R<CfgDcocCal6Spec>;
        #[doc = "Register `CFG_DCOC_CAL_6` writer"]
        pub type W = crate::W<CfgDcocCal6Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal6Spec;
        impl crate::RegisterSpec for CfgDcocCal6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_6::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal6Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_6::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_6 to value 0"]
        impl crate::Resettable for CfgDcocCal6Spec {}
    }
    #[doc = "CFG_DCOC_CAL_7 (rw) register accessor: cfg_dcoc_cal_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_7`] module"]
    #[doc(alias = "CFG_DCOC_CAL_7")]
    pub type CfgDcocCal7 = crate::Reg<cfg_dcoc_cal_7::CfgDcocCal7Spec>;
    #[doc = "cfg_dcoc_cal_7"]
    pub mod cfg_dcoc_cal_7 {
        #[doc = "Register `CFG_DCOC_CAL_7` reader"]
        pub type R = crate::R<CfgDcocCal7Spec>;
        #[doc = "Register `CFG_DCOC_CAL_7` writer"]
        pub type W = crate::W<CfgDcocCal7Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal7Spec;
        impl crate::RegisterSpec for CfgDcocCal7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_7::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal7Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_7::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_7 to value 0"]
        impl crate::Resettable for CfgDcocCal7Spec {}
    }
    #[doc = "CFG_DCOC_CAL_8 (rw) register accessor: cfg_dcoc_cal_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_8`] module"]
    #[doc(alias = "CFG_DCOC_CAL_8")]
    pub type CfgDcocCal8 = crate::Reg<cfg_dcoc_cal_8::CfgDcocCal8Spec>;
    #[doc = "cfg_dcoc_cal_8"]
    pub mod cfg_dcoc_cal_8 {
        #[doc = "Register `CFG_DCOC_CAL_8` reader"]
        pub type R = crate::R<CfgDcocCal8Spec>;
        #[doc = "Register `CFG_DCOC_CAL_8` writer"]
        pub type W = crate::W<CfgDcocCal8Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal8Spec;
        impl crate::RegisterSpec for CfgDcocCal8Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_8::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal8Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_8::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal8Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_8 to value 0"]
        impl crate::Resettable for CfgDcocCal8Spec {}
    }
    #[doc = "RPT_DCOC_CAL_0 (rw) register accessor: rpt_dcoc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_dcoc_cal_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_dcoc_cal_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_dcoc_cal_0`] module"]
    #[doc(alias = "RPT_DCOC_CAL_0")]
    pub type RptDcocCal0 = crate::Reg<rpt_dcoc_cal_0::RptDcocCal0Spec>;
    #[doc = "rpt_dcoc_cal_0"]
    pub mod rpt_dcoc_cal_0 {
        #[doc = "Register `RPT_DCOC_CAL_0` reader"]
        pub type R = crate::R<RptDcocCal0Spec>;
        #[doc = "Register `RPT_DCOC_CAL_0` writer"]
        pub type W = crate::W<RptDcocCal0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_dcoc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_dcoc_cal_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_dcoc_cal_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptDcocCal0Spec;
        impl crate::RegisterSpec for RptDcocCal0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_dcoc_cal_0::R`](R) reader structure"]
        impl crate::Readable for RptDcocCal0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_dcoc_cal_0::W`](W) writer structure"]
        impl crate::Writable for RptDcocCal0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_DCOC_CAL_0 to value 0"]
        impl crate::Resettable for RptDcocCal0Spec {}
    }
    #[doc = "CFG_DCOC_CAL_12 (rw) register accessor: cfg_dcoc_cal_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_12`] module"]
    #[doc(alias = "CFG_DCOC_CAL_12")]
    pub type CfgDcocCal12 = crate::Reg<cfg_dcoc_cal_12::CfgDcocCal12Spec>;
    #[doc = "cfg_dcoc_cal_12"]
    pub mod cfg_dcoc_cal_12 {
        #[doc = "Register `CFG_DCOC_CAL_12` reader"]
        pub type R = crate::R<CfgDcocCal12Spec>;
        #[doc = "Register `CFG_DCOC_CAL_12` writer"]
        pub type W = crate::W<CfgDcocCal12Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_dcoc_cal_12\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal12Spec;
        impl crate::RegisterSpec for CfgDcocCal12Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_12::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal12Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_12::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal12Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_12 to value 0"]
        impl crate::Resettable for CfgDcocCal12Spec {}
    }
    #[doc = "CFG_DCOC_CAL_13 (rw) register accessor: cfg_dcoc_cal_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_dcoc_cal_13`] module"]
    #[doc(alias = "CFG_DCOC_CAL_13")]
    pub type CfgDcocCal13 = crate::Reg<cfg_dcoc_cal_13::CfgDcocCal13Spec>;
    #[doc = "cfg_dcoc_cal_13"]
    pub mod cfg_dcoc_cal_13 {
        #[doc = "Register `CFG_DCOC_CAL_13` reader"]
        pub type R = crate::R<CfgDcocCal13Spec>;
        #[doc = "Register `CFG_DCOC_CAL_13` writer"]
        pub type W = crate::W<CfgDcocCal13Spec>;
        #[doc = "Field `cfg_manual_preamp_os_code` reader - "]
        pub type CfgManualPreampOsCodeR = crate::FieldReader;
        #[doc = "Field `cfg_manual_preamp_os_code` writer - "]
        pub type CfgManualPreampOsCodeW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `cfg_manual_preamp_os_update` reader - "]
        pub type CfgManualPreampOsUpdateR = crate::BitReader;
        #[doc = "Field `cfg_manual_preamp_os_update` writer - "]
        pub type CfgManualPreampOsUpdateW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:5"]
            #[inline(always)]
            pub fn cfg_manual_preamp_os_code(&self) -> CfgManualPreampOsCodeR {
                CfgManualPreampOsCodeR::new((self.bits & 0x3f) as u8)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cfg_manual_preamp_os_update(&self) -> CfgManualPreampOsUpdateR {
                CfgManualPreampOsUpdateR::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:5"]
            #[inline(always)]
            pub fn cfg_manual_preamp_os_code(
                &mut self,
            ) -> CfgManualPreampOsCodeW<'_, CfgDcocCal13Spec> {
                CfgManualPreampOsCodeW::new(self, 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cfg_manual_preamp_os_update(
                &mut self,
            ) -> CfgManualPreampOsUpdateW<'_, CfgDcocCal13Spec> {
                CfgManualPreampOsUpdateW::new(self, 8)
            }
        }
        #[doc = "cfg_dcoc_cal_13\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_dcoc_cal_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_dcoc_cal_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgDcocCal13Spec;
        impl crate::RegisterSpec for CfgDcocCal13Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_dcoc_cal_13::R`](R) reader structure"]
        impl crate::Readable for CfgDcocCal13Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_dcoc_cal_13::W`](W) writer structure"]
        impl crate::Writable for CfgDcocCal13Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_DCOC_CAL_13 to value 0"]
        impl crate::Resettable for CfgDcocCal13Spec {}
    }
    #[doc = "RPT_DCOC_CAL_1 (rw) register accessor: rpt_dcoc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_dcoc_cal_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_dcoc_cal_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_dcoc_cal_1`] module"]
    #[doc(alias = "RPT_DCOC_CAL_1")]
    pub type RptDcocCal1 = crate::Reg<rpt_dcoc_cal_1::RptDcocCal1Spec>;
    #[doc = "rpt_dcoc_cal_1"]
    pub mod rpt_dcoc_cal_1 {
        #[doc = "Register `RPT_DCOC_CAL_1` reader"]
        pub type R = crate::R<RptDcocCal1Spec>;
        #[doc = "Register `RPT_DCOC_CAL_1` writer"]
        pub type W = crate::W<RptDcocCal1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_dcoc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_dcoc_cal_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_dcoc_cal_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptDcocCal1Spec;
        impl crate::RegisterSpec for RptDcocCal1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_dcoc_cal_1::R`](R) reader structure"]
        impl crate::Readable for RptDcocCal1Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_dcoc_cal_1::W`](W) writer structure"]
        impl crate::Writable for RptDcocCal1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_DCOC_CAL_1 to value 0"]
        impl crate::Resettable for RptDcocCal1Spec {}
    }
    #[doc = "CFG_SAR_SPD_0 (rw) register accessor: cfg_sar_spd_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_0`] module"]
    #[doc(alias = "CFG_SAR_SPD_0")]
    pub type CfgSarSpd0 = crate::Reg<cfg_sar_spd_0::CfgSarSpd0Spec>;
    #[doc = "cfg_sar_spd_0"]
    pub mod cfg_sar_spd_0 {
        #[doc = "Register `CFG_SAR_SPD_0` reader"]
        pub type R = crate::R<CfgSarSpd0Spec>;
        #[doc = "Register `CFG_SAR_SPD_0` writer"]
        pub type W = crate::W<CfgSarSpd0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_sar_spd_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgSarSpd0Spec;
        impl crate::RegisterSpec for CfgSarSpd0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_sar_spd_0::R`](R) reader structure"]
        impl crate::Readable for CfgSarSpd0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_0::W`](W) writer structure"]
        impl crate::Writable for CfgSarSpd0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_SAR_SPD_0 to value 0"]
        impl crate::Resettable for CfgSarSpd0Spec {}
    }
    #[doc = "CFG_SAR_SPD_1 (rw) register accessor: cfg_sar_spd_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_1`] module"]
    #[doc(alias = "CFG_SAR_SPD_1")]
    pub type CfgSarSpd1 = crate::Reg<cfg_sar_spd_1::CfgSarSpd1Spec>;
    #[doc = "cfg_sar_spd_1"]
    pub mod cfg_sar_spd_1 {
        #[doc = "Register `CFG_SAR_SPD_1` reader"]
        pub type R = crate::R<CfgSarSpd1Spec>;
        #[doc = "Register `CFG_SAR_SPD_1` writer"]
        pub type W = crate::W<CfgSarSpd1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_sar_spd_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgSarSpd1Spec;
        impl crate::RegisterSpec for CfgSarSpd1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_sar_spd_1::R`](R) reader structure"]
        impl crate::Readable for CfgSarSpd1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_1::W`](W) writer structure"]
        impl crate::Writable for CfgSarSpd1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_SAR_SPD_1 to value 0"]
        impl crate::Resettable for CfgSarSpd1Spec {}
    }
    #[doc = "CFG_SAR_SPD_2 (rw) register accessor: cfg_sar_spd_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_2`] module"]
    #[doc(alias = "CFG_SAR_SPD_2")]
    pub type CfgSarSpd2 = crate::Reg<cfg_sar_spd_2::CfgSarSpd2Spec>;
    #[doc = "cfg_sar_spd_2"]
    pub mod cfg_sar_spd_2 {
        #[doc = "Register `CFG_SAR_SPD_2` reader"]
        pub type R = crate::R<CfgSarSpd2Spec>;
        #[doc = "Register `CFG_SAR_SPD_2` writer"]
        pub type W = crate::W<CfgSarSpd2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_sar_spd_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgSarSpd2Spec;
        impl crate::RegisterSpec for CfgSarSpd2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_sar_spd_2::R`](R) reader structure"]
        impl crate::Readable for CfgSarSpd2Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_2::W`](W) writer structure"]
        impl crate::Writable for CfgSarSpd2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_SAR_SPD_2 to value 0"]
        impl crate::Resettable for CfgSarSpd2Spec {}
    }
    #[doc = "CFG_SAR_SPD_3 (rw) register accessor: cfg_sar_spd_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_3`] module"]
    #[doc(alias = "CFG_SAR_SPD_3")]
    pub type CfgSarSpd3 = crate::Reg<cfg_sar_spd_3::CfgSarSpd3Spec>;
    #[doc = "cfg_sar_spd_3"]
    pub mod cfg_sar_spd_3 {
        #[doc = "Register `CFG_SAR_SPD_3` reader"]
        pub type R = crate::R<CfgSarSpd3Spec>;
        #[doc = "Register `CFG_SAR_SPD_3` writer"]
        pub type W = crate::W<CfgSarSpd3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_sar_spd_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgSarSpd3Spec;
        impl crate::RegisterSpec for CfgSarSpd3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_sar_spd_3::R`](R) reader structure"]
        impl crate::Readable for CfgSarSpd3Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_3::W`](W) writer structure"]
        impl crate::Writable for CfgSarSpd3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_SAR_SPD_3 to value 0"]
        impl crate::Resettable for CfgSarSpd3Spec {}
    }
    #[doc = "CFG_SAR_SPD_4 (rw) register accessor: cfg_sar_spd_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_4`] module"]
    #[doc(alias = "CFG_SAR_SPD_4")]
    pub type CfgSarSpd4 = crate::Reg<cfg_sar_spd_4::CfgSarSpd4Spec>;
    #[doc = "cfg_sar_spd_4"]
    pub mod cfg_sar_spd_4 {
        #[doc = "Register `CFG_SAR_SPD_4` reader"]
        pub type R = crate::R<CfgSarSpd4Spec>;
        #[doc = "Register `CFG_SAR_SPD_4` writer"]
        pub type W = crate::W<CfgSarSpd4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_sar_spd_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgSarSpd4Spec;
        impl crate::RegisterSpec for CfgSarSpd4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_sar_spd_4::R`](R) reader structure"]
        impl crate::Readable for CfgSarSpd4Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_4::W`](W) writer structure"]
        impl crate::Writable for CfgSarSpd4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_SAR_SPD_4 to value 0"]
        impl crate::Resettable for CfgSarSpd4Spec {}
    }
    #[doc = "RPT_SAR_SPD_0 (rw) register accessor: rpt_sar_spd_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_sar_spd_0`] module"]
    #[doc(alias = "RPT_SAR_SPD_0")]
    pub type RptSarSpd0 = crate::Reg<rpt_sar_spd_0::RptSarSpd0Spec>;
    #[doc = "rpt_sar_spd_0"]
    pub mod rpt_sar_spd_0 {
        #[doc = "Register `RPT_SAR_SPD_0` reader"]
        pub type R = crate::R<RptSarSpd0Spec>;
        #[doc = "Register `RPT_SAR_SPD_0` writer"]
        pub type W = crate::W<RptSarSpd0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_sar_spd_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptSarSpd0Spec;
        impl crate::RegisterSpec for RptSarSpd0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_sar_spd_0::R`](R) reader structure"]
        impl crate::Readable for RptSarSpd0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_sar_spd_0::W`](W) writer structure"]
        impl crate::Writable for RptSarSpd0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_SAR_SPD_0 to value 0"]
        impl crate::Resettable for RptSarSpd0Spec {}
    }
    #[doc = "RPT_SAR_SPD_1 (rw) register accessor: rpt_sar_spd_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_sar_spd_1`] module"]
    #[doc(alias = "RPT_SAR_SPD_1")]
    pub type RptSarSpd1 = crate::Reg<rpt_sar_spd_1::RptSarSpd1Spec>;
    #[doc = "rpt_sar_spd_1"]
    pub mod rpt_sar_spd_1 {
        #[doc = "Register `RPT_SAR_SPD_1` reader"]
        pub type R = crate::R<RptSarSpd1Spec>;
        #[doc = "Register `RPT_SAR_SPD_1` writer"]
        pub type W = crate::W<RptSarSpd1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_sar_spd_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptSarSpd1Spec;
        impl crate::RegisterSpec for RptSarSpd1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_sar_spd_1::R`](R) reader structure"]
        impl crate::Readable for RptSarSpd1Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_sar_spd_1::W`](W) writer structure"]
        impl crate::Writable for RptSarSpd1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_SAR_SPD_1 to value 0"]
        impl crate::Resettable for RptSarSpd1Spec {}
    }
    #[doc = "CFG_SAR_SPD_6 (rw) register accessor: cfg_sar_spd_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_sar_spd_6`] module"]
    #[doc(alias = "CFG_SAR_SPD_6")]
    pub type CfgSarSpd6 = crate::Reg<cfg_sar_spd_6::CfgSarSpd6Spec>;
    #[doc = "cfg_sar_spd_6"]
    pub mod cfg_sar_spd_6 {
        #[doc = "Register `CFG_SAR_SPD_6` reader"]
        pub type R = crate::R<CfgSarSpd6Spec>;
        #[doc = "Register `CFG_SAR_SPD_6` writer"]
        pub type W = crate::W<CfgSarSpd6Spec>;
        #[doc = "Field `cfg_manual_sar_spd_dly_code` reader - "]
        pub type CfgManualSarSpdDlyCodeR = crate::FieldReader;
        #[doc = "Field `cfg_manual_sar_spd_dly_code` writer - "]
        pub type CfgManualSarSpdDlyCodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `cfg_manual_sar_spd_update` reader - "]
        pub type CfgManualSarSpdUpdateR = crate::BitReader;
        #[doc = "Field `cfg_manual_sar_spd_update` writer - "]
        pub type CfgManualSarSpdUpdateW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn cfg_manual_sar_spd_dly_code(&self) -> CfgManualSarSpdDlyCodeR {
                CfgManualSarSpdDlyCodeR::new((self.bits & 7) as u8)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn cfg_manual_sar_spd_update(&self) -> CfgManualSarSpdUpdateR {
                CfgManualSarSpdUpdateR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn cfg_manual_sar_spd_dly_code(
                &mut self,
            ) -> CfgManualSarSpdDlyCodeW<'_, CfgSarSpd6Spec> {
                CfgManualSarSpdDlyCodeW::new(self, 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn cfg_manual_sar_spd_update(
                &mut self,
            ) -> CfgManualSarSpdUpdateW<'_, CfgSarSpd6Spec> {
                CfgManualSarSpdUpdateW::new(self, 4)
            }
        }
        #[doc = "cfg_sar_spd_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_sar_spd_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_sar_spd_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgSarSpd6Spec;
        impl crate::RegisterSpec for CfgSarSpd6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_sar_spd_6::R`](R) reader structure"]
        impl crate::Readable for CfgSarSpd6Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_sar_spd_6::W`](W) writer structure"]
        impl crate::Writable for CfgSarSpd6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_SAR_SPD_6 to value 0"]
        impl crate::Resettable for CfgSarSpd6Spec {}
    }
    #[doc = "RPT_SAR_SPD_2 (rw) register accessor: rpt_sar_spd_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_sar_spd_2`] module"]
    #[doc(alias = "RPT_SAR_SPD_2")]
    pub type RptSarSpd2 = crate::Reg<rpt_sar_spd_2::RptSarSpd2Spec>;
    #[doc = "rpt_sar_spd_2"]
    pub mod rpt_sar_spd_2 {
        #[doc = "Register `RPT_SAR_SPD_2` reader"]
        pub type R = crate::R<RptSarSpd2Spec>;
        #[doc = "Register `RPT_SAR_SPD_2` writer"]
        pub type W = crate::W<RptSarSpd2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_sar_spd_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_sar_spd_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_sar_spd_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptSarSpd2Spec;
        impl crate::RegisterSpec for RptSarSpd2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_sar_spd_2::R`](R) reader structure"]
        impl crate::Readable for RptSarSpd2Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_sar_spd_2::W`](W) writer structure"]
        impl crate::Writable for RptSarSpd2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_SAR_SPD_2 to value 0"]
        impl crate::Resettable for RptSarSpd2Spec {}
    }
    #[doc = "CFG_RC_CAL_0 (rw) register accessor: cfg_rc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_0`] module"]
    #[doc(alias = "CFG_RC_CAL_0")]
    pub type CfgRcCal0 = crate::Reg<cfg_rc_cal_0::CfgRcCal0Spec>;
    #[doc = "cfg_rc_cal_0"]
    pub mod cfg_rc_cal_0 {
        #[doc = "Register `CFG_RC_CAL_0` reader"]
        pub type R = crate::R<CfgRcCal0Spec>;
        #[doc = "Register `CFG_RC_CAL_0` writer"]
        pub type W = crate::W<CfgRcCal0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_rc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRcCal0Spec;
        impl crate::RegisterSpec for CfgRcCal0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rc_cal_0::R`](R) reader structure"]
        impl crate::Readable for CfgRcCal0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_0::W`](W) writer structure"]
        impl crate::Writable for CfgRcCal0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RC_CAL_0 to value 0"]
        impl crate::Resettable for CfgRcCal0Spec {}
    }
    #[doc = "CFG_RC_CAL_1 (rw) register accessor: cfg_rc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_1`] module"]
    #[doc(alias = "CFG_RC_CAL_1")]
    pub type CfgRcCal1 = crate::Reg<cfg_rc_cal_1::CfgRcCal1Spec>;
    #[doc = "cfg_rc_cal_1"]
    pub mod cfg_rc_cal_1 {
        #[doc = "Register `CFG_RC_CAL_1` reader"]
        pub type R = crate::R<CfgRcCal1Spec>;
        #[doc = "Register `CFG_RC_CAL_1` writer"]
        pub type W = crate::W<CfgRcCal1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_rc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRcCal1Spec;
        impl crate::RegisterSpec for CfgRcCal1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rc_cal_1::R`](R) reader structure"]
        impl crate::Readable for CfgRcCal1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_1::W`](W) writer structure"]
        impl crate::Writable for CfgRcCal1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RC_CAL_1 to value 0"]
        impl crate::Resettable for CfgRcCal1Spec {}
    }
    #[doc = "CFG_RC_CAL_2 (rw) register accessor: cfg_rc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_2`] module"]
    #[doc(alias = "CFG_RC_CAL_2")]
    pub type CfgRcCal2 = crate::Reg<cfg_rc_cal_2::CfgRcCal2Spec>;
    #[doc = "cfg_rc_cal_2"]
    pub mod cfg_rc_cal_2 {
        #[doc = "Register `CFG_RC_CAL_2` reader"]
        pub type R = crate::R<CfgRcCal2Spec>;
        #[doc = "Register `CFG_RC_CAL_2` writer"]
        pub type W = crate::W<CfgRcCal2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_rc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRcCal2Spec;
        impl crate::RegisterSpec for CfgRcCal2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rc_cal_2::R`](R) reader structure"]
        impl crate::Readable for CfgRcCal2Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_2::W`](W) writer structure"]
        impl crate::Writable for CfgRcCal2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RC_CAL_2 to value 0"]
        impl crate::Resettable for CfgRcCal2Spec {}
    }
    #[doc = "CFG_RC_CAL_3 (rw) register accessor: cfg_rc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_3`] module"]
    #[doc(alias = "CFG_RC_CAL_3")]
    pub type CfgRcCal3 = crate::Reg<cfg_rc_cal_3::CfgRcCal3Spec>;
    #[doc = "cfg_rc_cal_3"]
    pub mod cfg_rc_cal_3 {
        #[doc = "Register `CFG_RC_CAL_3` reader"]
        pub type R = crate::R<CfgRcCal3Spec>;
        #[doc = "Register `CFG_RC_CAL_3` writer"]
        pub type W = crate::W<CfgRcCal3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_rc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRcCal3Spec;
        impl crate::RegisterSpec for CfgRcCal3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rc_cal_3::R`](R) reader structure"]
        impl crate::Readable for CfgRcCal3Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_3::W`](W) writer structure"]
        impl crate::Writable for CfgRcCal3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RC_CAL_3 to value 0"]
        impl crate::Resettable for CfgRcCal3Spec {}
    }
    #[doc = "CFG_RC_CAL_4 (rw) register accessor: cfg_rc_cal_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_4`] module"]
    #[doc(alias = "CFG_RC_CAL_4")]
    pub type CfgRcCal4 = crate::Reg<cfg_rc_cal_4::CfgRcCal4Spec>;
    #[doc = "cfg_rc_cal_4"]
    pub mod cfg_rc_cal_4 {
        #[doc = "Register `CFG_RC_CAL_4` reader"]
        pub type R = crate::R<CfgRcCal4Spec>;
        #[doc = "Register `CFG_RC_CAL_4` writer"]
        pub type W = crate::W<CfgRcCal4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_rc_cal_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRcCal4Spec;
        impl crate::RegisterSpec for CfgRcCal4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rc_cal_4::R`](R) reader structure"]
        impl crate::Readable for CfgRcCal4Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_4::W`](W) writer structure"]
        impl crate::Writable for CfgRcCal4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RC_CAL_4 to value 0"]
        impl crate::Resettable for CfgRcCal4Spec {}
    }
    #[doc = "RPT_RC_CAL_0 (rw) register accessor: rpt_rc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_rc_cal_0`] module"]
    #[doc(alias = "RPT_RC_CAL_0")]
    pub type RptRcCal0 = crate::Reg<rpt_rc_cal_0::RptRcCal0Spec>;
    #[doc = "rpt_rc_cal_0"]
    pub mod rpt_rc_cal_0 {
        #[doc = "Register `RPT_RC_CAL_0` reader"]
        pub type R = crate::R<RptRcCal0Spec>;
        #[doc = "Register `RPT_RC_CAL_0` writer"]
        pub type W = crate::W<RptRcCal0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_rc_cal_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptRcCal0Spec;
        impl crate::RegisterSpec for RptRcCal0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_rc_cal_0::R`](R) reader structure"]
        impl crate::Readable for RptRcCal0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_rc_cal_0::W`](W) writer structure"]
        impl crate::Writable for RptRcCal0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_RC_CAL_0 to value 0"]
        impl crate::Resettable for RptRcCal0Spec {}
    }
    #[doc = "RPT_RC_CAL_1 (rw) register accessor: rpt_rc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_rc_cal_1`] module"]
    #[doc(alias = "RPT_RC_CAL_1")]
    pub type RptRcCal1 = crate::Reg<rpt_rc_cal_1::RptRcCal1Spec>;
    #[doc = "rpt_rc_cal_1"]
    pub mod rpt_rc_cal_1 {
        #[doc = "Register `RPT_RC_CAL_1` reader"]
        pub type R = crate::R<RptRcCal1Spec>;
        #[doc = "Register `RPT_RC_CAL_1` writer"]
        pub type W = crate::W<RptRcCal1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_rc_cal_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptRcCal1Spec;
        impl crate::RegisterSpec for RptRcCal1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_rc_cal_1::R`](R) reader structure"]
        impl crate::Readable for RptRcCal1Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_rc_cal_1::W`](W) writer structure"]
        impl crate::Writable for RptRcCal1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_RC_CAL_1 to value 0"]
        impl crate::Resettable for RptRcCal1Spec {}
    }
    #[doc = "CFG_RC_CAL_5 (rw) register accessor: cfg_rc_cal_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_5`] module"]
    #[doc(alias = "CFG_RC_CAL_5")]
    pub type CfgRcCal5 = crate::Reg<cfg_rc_cal_5::CfgRcCal5Spec>;
    #[doc = "cfg_rc_cal_5"]
    pub mod cfg_rc_cal_5 {
        #[doc = "Register `CFG_RC_CAL_5` reader"]
        pub type R = crate::R<CfgRcCal5Spec>;
        #[doc = "Register `CFG_RC_CAL_5` writer"]
        pub type W = crate::W<CfgRcCal5Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_rc_cal_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRcCal5Spec;
        impl crate::RegisterSpec for CfgRcCal5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rc_cal_5::R`](R) reader structure"]
        impl crate::Readable for CfgRcCal5Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_5::W`](W) writer structure"]
        impl crate::Writable for CfgRcCal5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RC_CAL_5 to value 0"]
        impl crate::Resettable for CfgRcCal5Spec {}
    }
    #[doc = "CFG_RC_CAL_6 (rw) register accessor: cfg_rc_cal_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_6`] module"]
    #[doc(alias = "CFG_RC_CAL_6")]
    pub type CfgRcCal6 = crate::Reg<cfg_rc_cal_6::CfgRcCal6Spec>;
    #[doc = "cfg_rc_cal_6"]
    pub mod cfg_rc_cal_6 {
        #[doc = "Register `CFG_RC_CAL_6` reader"]
        pub type R = crate::R<CfgRcCal6Spec>;
        #[doc = "Register `CFG_RC_CAL_6` writer"]
        pub type W = crate::W<CfgRcCal6Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_rc_cal_6\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRcCal6Spec;
        impl crate::RegisterSpec for CfgRcCal6Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rc_cal_6::R`](R) reader structure"]
        impl crate::Readable for CfgRcCal6Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_6::W`](W) writer structure"]
        impl crate::Writable for CfgRcCal6Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RC_CAL_6 to value 0"]
        impl crate::Resettable for CfgRcCal6Spec {}
    }
    #[doc = "CFG_RC_CAL_7 (rw) register accessor: cfg_rc_cal_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_7`] module"]
    #[doc(alias = "CFG_RC_CAL_7")]
    pub type CfgRcCal7 = crate::Reg<cfg_rc_cal_7::CfgRcCal7Spec>;
    #[doc = "cfg_rc_cal_7"]
    pub mod cfg_rc_cal_7 {
        #[doc = "Register `CFG_RC_CAL_7` reader"]
        pub type R = crate::R<CfgRcCal7Spec>;
        #[doc = "Register `CFG_RC_CAL_7` writer"]
        pub type W = crate::W<CfgRcCal7Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_rc_cal_7\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRcCal7Spec;
        impl crate::RegisterSpec for CfgRcCal7Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rc_cal_7::R`](R) reader structure"]
        impl crate::Readable for CfgRcCal7Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_7::W`](W) writer structure"]
        impl crate::Writable for CfgRcCal7Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RC_CAL_7 to value 0"]
        impl crate::Resettable for CfgRcCal7Spec {}
    }
    #[doc = "CFG_RC_CAL_8 (rw) register accessor: cfg_rc_cal_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_rc_cal_8`] module"]
    #[doc(alias = "CFG_RC_CAL_8")]
    pub type CfgRcCal8 = crate::Reg<cfg_rc_cal_8::CfgRcCal8Spec>;
    #[doc = "cfg_rc_cal_8"]
    pub mod cfg_rc_cal_8 {
        #[doc = "Register `CFG_RC_CAL_8` reader"]
        pub type R = crate::R<CfgRcCal8Spec>;
        #[doc = "Register `CFG_RC_CAL_8` writer"]
        pub type W = crate::W<CfgRcCal8Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_rc_cal_8\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_rc_cal_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_rc_cal_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgRcCal8Spec;
        impl crate::RegisterSpec for CfgRcCal8Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_rc_cal_8::R`](R) reader structure"]
        impl crate::Readable for CfgRcCal8Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_rc_cal_8::W`](W) writer structure"]
        impl crate::Writable for CfgRcCal8Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_RC_CAL_8 to value 0"]
        impl crate::Resettable for CfgRcCal8Spec {}
    }
    #[doc = "RPT_RC_CAL_2 (rw) register accessor: rpt_rc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_rc_cal_2`] module"]
    #[doc(alias = "RPT_RC_CAL_2")]
    pub type RptRcCal2 = crate::Reg<rpt_rc_cal_2::RptRcCal2Spec>;
    #[doc = "rpt_rc_cal_2"]
    pub mod rpt_rc_cal_2 {
        #[doc = "Register `RPT_RC_CAL_2` reader"]
        pub type R = crate::R<RptRcCal2Spec>;
        #[doc = "Register `RPT_RC_CAL_2` writer"]
        pub type W = crate::W<RptRcCal2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_rc_cal_2\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptRcCal2Spec;
        impl crate::RegisterSpec for RptRcCal2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_rc_cal_2::R`](R) reader structure"]
        impl crate::Readable for RptRcCal2Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_rc_cal_2::W`](W) writer structure"]
        impl crate::Writable for RptRcCal2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_RC_CAL_2 to value 0"]
        impl crate::Resettable for RptRcCal2Spec {}
    }
    #[doc = "RPT_RC_CAL_3 (rw) register accessor: rpt_rc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_rc_cal_3`] module"]
    #[doc(alias = "RPT_RC_CAL_3")]
    pub type RptRcCal3 = crate::Reg<rpt_rc_cal_3::RptRcCal3Spec>;
    #[doc = "rpt_rc_cal_3"]
    pub mod rpt_rc_cal_3 {
        #[doc = "Register `RPT_RC_CAL_3` reader"]
        pub type R = crate::R<RptRcCal3Spec>;
        #[doc = "Register `RPT_RC_CAL_3` writer"]
        pub type W = crate::W<RptRcCal3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_rc_cal_3\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_rc_cal_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_rc_cal_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptRcCal3Spec;
        impl crate::RegisterSpec for RptRcCal3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_rc_cal_3::R`](R) reader structure"]
        impl crate::Readable for RptRcCal3Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_rc_cal_3::W`](W) writer structure"]
        impl crate::Writable for RptRcCal3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_RC_CAL_3 to value 0"]
        impl crate::Resettable for RptRcCal3Spec {}
    }
    #[doc = "CFG_AMUX_0 (rw) register accessor: cfg_amux_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_0`] module"]
    #[doc(alias = "CFG_AMUX_0")]
    pub type CfgAmux0 = crate::Reg<cfg_amux_0::CfgAmux0Spec>;
    #[doc = "cfg_amux_0"]
    pub mod cfg_amux_0 {
        #[doc = "Register `CFG_AMUX_0` reader"]
        pub type R = crate::R<CfgAmux0Spec>;
        #[doc = "Register `CFG_AMUX_0` writer"]
        pub type W = crate::W<CfgAmux0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_amux_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgAmux0Spec;
        impl crate::RegisterSpec for CfgAmux0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_amux_0::R`](R) reader structure"]
        impl crate::Readable for CfgAmux0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_amux_0::W`](W) writer structure"]
        impl crate::Writable for CfgAmux0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_AMUX_0 to value 0"]
        impl crate::Resettable for CfgAmux0Spec {}
    }
    #[doc = "CFG_AMUX_1 (rw) register accessor: cfg_amux_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_1`] module"]
    #[doc(alias = "CFG_AMUX_1")]
    pub type CfgAmux1 = crate::Reg<cfg_amux_1::CfgAmux1Spec>;
    #[doc = "cfg_amux_1"]
    pub mod cfg_amux_1 {
        #[doc = "Register `CFG_AMUX_1` reader"]
        pub type R = crate::R<CfgAmux1Spec>;
        #[doc = "Register `CFG_AMUX_1` writer"]
        pub type W = crate::W<CfgAmux1Spec>;
        #[doc = "Field `amuxn_sensor_ch_sel` reader - "]
        pub type AmuxnSensorChSelR = crate::FieldReader<u16>;
        #[doc = "Field `amuxn_sensor_ch_sel` writer - "]
        pub type AmuxnSensorChSelW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
        #[doc = "Field `amuxn_devide_disable` reader - "]
        pub type AmuxnDevideDisableR = crate::BitReader;
        #[doc = "Field `amuxn_devide_disable` writer - "]
        pub type AmuxnDevideDisableW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `amuxp_sensor_ch_sel` reader - "]
        pub type AmuxpSensorChSelR = crate::FieldReader<u16>;
        #[doc = "Field `amuxp_sensor_ch_sel` writer - "]
        pub type AmuxpSensorChSelW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
        #[doc = "Field `amuxp_devide_disable` reader - "]
        pub type AmuxpDevideDisableR = crate::BitReader;
        #[doc = "Field `amuxp_devide_disable` writer - "]
        pub type AmuxpDevideDisableW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:10"]
            #[inline(always)]
            pub fn amuxn_sensor_ch_sel(&self) -> AmuxnSensorChSelR {
                AmuxnSensorChSelR::new((self.bits & 0x07ff) as u16)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn amuxn_devide_disable(&self) -> AmuxnDevideDisableR {
                AmuxnDevideDisableR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bits 12:22"]
            #[inline(always)]
            pub fn amuxp_sensor_ch_sel(&self) -> AmuxpSensorChSelR {
                AmuxpSensorChSelR::new(((self.bits >> 12) & 0x07ff) as u16)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn amuxp_devide_disable(&self) -> AmuxpDevideDisableR {
                AmuxpDevideDisableR::new(((self.bits >> 23) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:10"]
            #[inline(always)]
            pub fn amuxn_sensor_ch_sel(&mut self) -> AmuxnSensorChSelW<'_, CfgAmux1Spec> {
                AmuxnSensorChSelW::new(self, 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn amuxn_devide_disable(&mut self) -> AmuxnDevideDisableW<'_, CfgAmux1Spec> {
                AmuxnDevideDisableW::new(self, 11)
            }
            #[doc = "Bits 12:22"]
            #[inline(always)]
            pub fn amuxp_sensor_ch_sel(&mut self) -> AmuxpSensorChSelW<'_, CfgAmux1Spec> {
                AmuxpSensorChSelW::new(self, 12)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn amuxp_devide_disable(&mut self) -> AmuxpDevideDisableW<'_, CfgAmux1Spec> {
                AmuxpDevideDisableW::new(self, 23)
            }
        }
        #[doc = "cfg_amux_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgAmux1Spec;
        impl crate::RegisterSpec for CfgAmux1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_amux_1::R`](R) reader structure"]
        impl crate::Readable for CfgAmux1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_amux_1::W`](W) writer structure"]
        impl crate::Writable for CfgAmux1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_AMUX_1 to value 0"]
        impl crate::Resettable for CfgAmux1Spec {}
    }
    #[doc = "CFG_AMUX_2 (rw) register accessor: cfg_amux_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_2`] module"]
    #[doc(alias = "CFG_AMUX_2")]
    pub type CfgAmux2 = crate::Reg<cfg_amux_2::CfgAmux2Spec>;
    #[doc = "cfg_amux_2"]
    pub mod cfg_amux_2 {
        #[doc = "Register `CFG_AMUX_2` reader"]
        pub type R = crate::R<CfgAmux2Spec>;
        #[doc = "Register `CFG_AMUX_2` writer"]
        pub type W = crate::W<CfgAmux2Spec>;
        #[doc = "Field `cfg_amuxn_audio_ch_sel` reader - "]
        pub type CfgAmuxnAudioChSelR = crate::FieldReader;
        #[doc = "Field `cfg_amuxn_audio_ch_sel` writer - "]
        pub type CfgAmuxnAudioChSelW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `cfg_amuxp_audio_ch_sel` reader - "]
        pub type CfgAmuxpAudioChSelR = crate::FieldReader;
        #[doc = "Field `cfg_amuxp_audio_ch_sel` writer - "]
        pub type CfgAmuxpAudioChSelW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn cfg_amuxn_audio_ch_sel(&self) -> CfgAmuxnAudioChSelR {
                CfgAmuxnAudioChSelR::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:7"]
            #[inline(always)]
            pub fn cfg_amuxp_audio_ch_sel(&self) -> CfgAmuxpAudioChSelR {
                CfgAmuxpAudioChSelR::new(((self.bits >> 4) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn cfg_amuxn_audio_ch_sel(&mut self) -> CfgAmuxnAudioChSelW<'_, CfgAmux2Spec> {
                CfgAmuxnAudioChSelW::new(self, 0)
            }
            #[doc = "Bits 4:7"]
            #[inline(always)]
            pub fn cfg_amuxp_audio_ch_sel(&mut self) -> CfgAmuxpAudioChSelW<'_, CfgAmux2Spec> {
                CfgAmuxpAudioChSelW::new(self, 4)
            }
        }
        #[doc = "cfg_amux_2\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgAmux2Spec;
        impl crate::RegisterSpec for CfgAmux2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_amux_2::R`](R) reader structure"]
        impl crate::Readable for CfgAmux2Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_amux_2::W`](W) writer structure"]
        impl crate::Writable for CfgAmux2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_AMUX_2 to value 0"]
        impl crate::Resettable for CfgAmux2Spec {}
    }
    #[doc = "CFG_AMUX_3 (rw) register accessor: cfg_amux_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_3`] module"]
    #[doc(alias = "CFG_AMUX_3")]
    pub type CfgAmux3 = crate::Reg<cfg_amux_3::CfgAmux3Spec>;
    #[doc = "cfg_amux_3"]
    pub mod cfg_amux_3 {
        #[doc = "Register `CFG_AMUX_3` reader"]
        pub type R = crate::R<CfgAmux3Spec>;
        #[doc = "Register `CFG_AMUX_3` writer"]
        pub type W = crate::W<CfgAmux3Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_amux_3\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgAmux3Spec;
        impl crate::RegisterSpec for CfgAmux3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_amux_3::R`](R) reader structure"]
        impl crate::Readable for CfgAmux3Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_amux_3::W`](W) writer structure"]
        impl crate::Writable for CfgAmux3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_AMUX_3 to value 0"]
        impl crate::Resettable for CfgAmux3Spec {}
    }
    #[doc = "CFG_AMUX_4 (rw) register accessor: cfg_amux_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_4`] module"]
    #[doc(alias = "CFG_AMUX_4")]
    pub type CfgAmux4 = crate::Reg<cfg_amux_4::CfgAmux4Spec>;
    #[doc = "cfg_amux_4"]
    pub mod cfg_amux_4 {
        #[doc = "Register `CFG_AMUX_4` reader"]
        pub type R = crate::R<CfgAmux4Spec>;
        #[doc = "Register `CFG_AMUX_4` writer"]
        pub type W = crate::W<CfgAmux4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_amux_4\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgAmux4Spec;
        impl crate::RegisterSpec for CfgAmux4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_amux_4::R`](R) reader structure"]
        impl crate::Readable for CfgAmux4Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_amux_4::W`](W) writer structure"]
        impl crate::Writable for CfgAmux4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_AMUX_4 to value 0"]
        impl crate::Resettable for CfgAmux4Spec {}
    }
    #[doc = "CFG_AMUX_5 (rw) register accessor: cfg_amux_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_amux_5`] module"]
    #[doc(alias = "CFG_AMUX_5")]
    pub type CfgAmux5 = crate::Reg<cfg_amux_5::CfgAmux5Spec>;
    #[doc = "cfg_amux_5"]
    pub mod cfg_amux_5 {
        #[doc = "Register `CFG_AMUX_5` reader"]
        pub type R = crate::R<CfgAmux5Spec>;
        #[doc = "Register `CFG_AMUX_5` writer"]
        pub type W = crate::W<CfgAmux5Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_amux_5\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_amux_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_amux_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgAmux5Spec;
        impl crate::RegisterSpec for CfgAmux5Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_amux_5::R`](R) reader structure"]
        impl crate::Readable for CfgAmux5Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_amux_5::W`](W) writer structure"]
        impl crate::Writable for CfgAmux5Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_AMUX_5 to value 0"]
        impl crate::Resettable for CfgAmux5Spec {}
    }
    #[doc = "RPT_AMUX_0 (rw) register accessor: rpt_amux_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_amux_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_amux_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_amux_0`] module"]
    #[doc(alias = "RPT_AMUX_0")]
    pub type RptAmux0 = crate::Reg<rpt_amux_0::RptAmux0Spec>;
    #[doc = "rpt_amux_0"]
    pub mod rpt_amux_0 {
        #[doc = "Register `RPT_AMUX_0` reader"]
        pub type R = crate::R<RptAmux0Spec>;
        #[doc = "Register `RPT_AMUX_0` writer"]
        pub type W = crate::W<RptAmux0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_amux_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_amux_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_amux_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptAmux0Spec;
        impl crate::RegisterSpec for RptAmux0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_amux_0::R`](R) reader structure"]
        impl crate::Readable for RptAmux0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_amux_0::W`](W) writer structure"]
        impl crate::Writable for RptAmux0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_AMUX_0 to value 0"]
        impl crate::Resettable for RptAmux0Spec {}
    }
    #[doc = "CFG_TST_0 (rw) register accessor: cfg_tst_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tst_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tst_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tst_0`] module"]
    #[doc(alias = "CFG_TST_0")]
    pub type CfgTst0 = crate::Reg<cfg_tst_0::CfgTst0Spec>;
    #[doc = "cfg_tst_0"]
    pub mod cfg_tst_0 {
        #[doc = "Register `CFG_TST_0` reader"]
        pub type R = crate::R<CfgTst0Spec>;
        #[doc = "Register `CFG_TST_0` writer"]
        pub type W = crate::W<CfgTst0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_tst_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tst_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tst_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgTst0Spec;
        impl crate::RegisterSpec for CfgTst0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_tst_0::R`](R) reader structure"]
        impl crate::Readable for CfgTst0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_tst_0::W`](W) writer structure"]
        impl crate::Writable for CfgTst0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_TST_0 to value 0"]
        impl crate::Resettable for CfgTst0Spec {}
    }
    #[doc = "CFG_TST_1 (rw) register accessor: cfg_tst_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tst_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tst_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_tst_1`] module"]
    #[doc(alias = "CFG_TST_1")]
    pub type CfgTst1 = crate::Reg<cfg_tst_1::CfgTst1Spec>;
    #[doc = "cfg_tst_1"]
    pub mod cfg_tst_1 {
        #[doc = "Register `CFG_TST_1` reader"]
        pub type R = crate::R<CfgTst1Spec>;
        #[doc = "Register `CFG_TST_1` writer"]
        pub type W = crate::W<CfgTst1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_tst_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_tst_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_tst_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgTst1Spec;
        impl crate::RegisterSpec for CfgTst1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_tst_1::R`](R) reader structure"]
        impl crate::Readable for CfgTst1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_tst_1::W`](W) writer structure"]
        impl crate::Writable for CfgTst1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_TST_1 to value 0"]
        impl crate::Resettable for CfgTst1Spec {}
    }
    #[doc = "CFG_CMP_0 (rw) register accessor: cfg_cmp_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_0`] module"]
    #[doc(alias = "CFG_CMP_0")]
    pub type CfgCmp0 = crate::Reg<cfg_cmp_0::CfgCmp0Spec>;
    #[doc = "cfg_cmp_0"]
    pub mod cfg_cmp_0 {
        #[doc = "Register `CFG_CMP_0` reader"]
        pub type R = crate::R<CfgCmp0Spec>;
        #[doc = "Register `CFG_CMP_0` writer"]
        pub type W = crate::W<CfgCmp0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_0\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmp0Spec;
        impl crate::RegisterSpec for CfgCmp0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_0::R`](R) reader structure"]
        impl crate::Readable for CfgCmp0Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_0::W`](W) writer structure"]
        impl crate::Writable for CfgCmp0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_0 to value 0"]
        impl crate::Resettable for CfgCmp0Spec {}
    }
    #[doc = "CFG_CMP_1 (rw) register accessor: cfg_cmp_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_cmp_1`] module"]
    #[doc(alias = "CFG_CMP_1")]
    pub type CfgCmp1 = crate::Reg<cfg_cmp_1::CfgCmp1Spec>;
    #[doc = "cfg_cmp_1"]
    pub mod cfg_cmp_1 {
        #[doc = "Register `CFG_CMP_1` reader"]
        pub type R = crate::R<CfgCmp1Spec>;
        #[doc = "Register `CFG_CMP_1` writer"]
        pub type W = crate::W<CfgCmp1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "cfg_cmp_1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg_cmp_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg_cmp_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CfgCmp1Spec;
        impl crate::RegisterSpec for CfgCmp1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_cmp_1::R`](R) reader structure"]
        impl crate::Readable for CfgCmp1Spec {}
        #[doc = "`write(|w| ..)` method takes [`cfg_cmp_1::W`](W) writer structure"]
        impl crate::Writable for CfgCmp1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CFG_CMP_1 to value 0"]
        impl crate::Resettable for CfgCmp1Spec {}
    }
    #[doc = "RPT_CMP_0 (rw) register accessor: rpt_cmp_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cmp_0`] module"]
    #[doc(alias = "RPT_CMP_0")]
    pub type RptCmp0 = crate::Reg<rpt_cmp_0::RptCmp0Spec>;
    #[doc = "rpt_cmp_0"]
    pub mod rpt_cmp_0 {
        #[doc = "Register `RPT_CMP_0` reader"]
        pub type R = crate::R<RptCmp0Spec>;
        #[doc = "Register `RPT_CMP_0` writer"]
        pub type W = crate::W<RptCmp0Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cmp_0\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCmp0Spec;
        impl crate::RegisterSpec for RptCmp0Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cmp_0::R`](R) reader structure"]
        impl crate::Readable for RptCmp0Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cmp_0::W`](W) writer structure"]
        impl crate::Writable for RptCmp0Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CMP_0 to value 0"]
        impl crate::Resettable for RptCmp0Spec {}
    }
    #[doc = "RPT_CMP_1 (rw) register accessor: rpt_cmp_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rpt_cmp_1`] module"]
    #[doc(alias = "RPT_CMP_1")]
    pub type RptCmp1 = crate::Reg<rpt_cmp_1::RptCmp1Spec>;
    #[doc = "rpt_cmp_1"]
    pub mod rpt_cmp_1 {
        #[doc = "Register `RPT_CMP_1` reader"]
        pub type R = crate::R<RptCmp1Spec>;
        #[doc = "Register `RPT_CMP_1` writer"]
        pub type W = crate::W<RptCmp1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "rpt_cmp_1\n\nYou can [`read`](crate::Reg::read) this register and get [`rpt_cmp_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpt_cmp_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RptCmp1Spec;
        impl crate::RegisterSpec for RptCmp1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rpt_cmp_1::R`](R) reader structure"]
        impl crate::Readable for RptCmp1Spec {}
        #[doc = "`write(|w| ..)` method takes [`rpt_cmp_1::W`](W) writer structure"]
        impl crate::Writable for RptCmp1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets RPT_CMP_1 to value 0"]
        impl crate::Resettable for RptCmp1Spec {}
    }
}
#[doc = "Key-scan matrix controller (v150)"]
pub type Keyscan = crate::Periph<keyscan::RegisterBlock, 0x5208_d000>;
impl core::fmt::Debug for Keyscan {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Keyscan").finish()
    }
}
#[doc = "Key-scan matrix controller (v150)"]
pub mod keyscan {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x04],
        keyscan_lp_ctl: KeyscanLpCtl,
        keyscan_enable: KeyscanEnable,
        keyscan_clk_ena: KeyscanClkEna,
        keyscan_start: KeyscanStart,
        _reserved4: [u8; 0x0c],
        keyscan_int_en: KeyscanIntEn,
        keyscan_event_clr: KeyscanEventClr,
        keyscan_event_sts: KeyscanEventSts,
        _reserved7: [u8; 0x04],
        keyscan_pin_num: KeyscanPinNum,
        keyscan_mode: KeyscanMode,
        keyscan_pulse: KeyscanPulse,
        _reserved10: [u8; 0x14],
        keyscan_de: KeyscanDe,
        _reserved11: [u8; 0x40],
        key_value_fifo: KeyValueFifo,
    }
    impl RegisterBlock {
        #[doc = "0x04 - keyscan_lp_ctl"]
        #[inline(always)]
        pub const fn keyscan_lp_ctl(&self) -> &KeyscanLpCtl {
            &self.keyscan_lp_ctl
        }
        #[doc = "0x08 - keyscan_enable"]
        #[inline(always)]
        pub const fn keyscan_enable(&self) -> &KeyscanEnable {
            &self.keyscan_enable
        }
        #[doc = "0x0c - keyscan_clk_ena"]
        #[inline(always)]
        pub const fn keyscan_clk_ena(&self) -> &KeyscanClkEna {
            &self.keyscan_clk_ena
        }
        #[doc = "0x10 - keyscan_start"]
        #[inline(always)]
        pub const fn keyscan_start(&self) -> &KeyscanStart {
            &self.keyscan_start
        }
        #[doc = "0x20 - keyscan_int_en"]
        #[inline(always)]
        pub const fn keyscan_int_en(&self) -> &KeyscanIntEn {
            &self.keyscan_int_en
        }
        #[doc = "0x24 - keyscan_event_clr"]
        #[inline(always)]
        pub const fn keyscan_event_clr(&self) -> &KeyscanEventClr {
            &self.keyscan_event_clr
        }
        #[doc = "0x28 - keyscan_event_sts"]
        #[inline(always)]
        pub const fn keyscan_event_sts(&self) -> &KeyscanEventSts {
            &self.keyscan_event_sts
        }
        #[doc = "0x30 - keyscan_pin_num"]
        #[inline(always)]
        pub const fn keyscan_pin_num(&self) -> &KeyscanPinNum {
            &self.keyscan_pin_num
        }
        #[doc = "0x34 - keyscan_mode"]
        #[inline(always)]
        pub const fn keyscan_mode(&self) -> &KeyscanMode {
            &self.keyscan_mode
        }
        #[doc = "0x38 - keyscan_pulse"]
        #[inline(always)]
        pub const fn keyscan_pulse(&self) -> &KeyscanPulse {
            &self.keyscan_pulse
        }
        #[doc = "0x50 - keyscan_de"]
        #[inline(always)]
        pub const fn keyscan_de(&self) -> &KeyscanDe {
            &self.keyscan_de
        }
        #[doc = "0x94 - key_value_fifo"]
        #[inline(always)]
        pub const fn key_value_fifo(&self) -> &KeyValueFifo {
            &self.key_value_fifo
        }
    }
    #[doc = "KEYSCAN_LP_CTL (rw) register accessor: keyscan_lp_ctl\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_lp_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_lp_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_lp_ctl`] module"]
    #[doc(alias = "KEYSCAN_LP_CTL")]
    pub type KeyscanLpCtl = crate::Reg<keyscan_lp_ctl::KeyscanLpCtlSpec>;
    #[doc = "keyscan_lp_ctl"]
    pub mod keyscan_lp_ctl {
        #[doc = "Register `KEYSCAN_LP_CTL` reader"]
        pub type R = crate::R<KeyscanLpCtlSpec>;
        #[doc = "Register `KEYSCAN_LP_CTL` writer"]
        pub type W = crate::W<KeyscanLpCtlSpec>;
        #[doc = "Field `alow_slp` reader - "]
        pub type AlowSlpR = crate::BitReader;
        #[doc = "Field `alow_slp` writer - "]
        pub type AlowSlpW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `slp_req` reader - "]
        pub type SlpReqR = crate::BitReader;
        #[doc = "Field `slp_req` writer - "]
        pub type SlpReqW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `slp_ack` reader - "]
        pub type SlpAckR = crate::BitReader;
        #[doc = "Field `slp_ack` writer - "]
        pub type SlpAckW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn alow_slp(&self) -> AlowSlpR {
                AlowSlpR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn slp_req(&self) -> SlpReqR {
                SlpReqR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn slp_ack(&self) -> SlpAckR {
                SlpAckR::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn alow_slp(&mut self) -> AlowSlpW<'_, KeyscanLpCtlSpec> {
                AlowSlpW::new(self, 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn slp_req(&mut self) -> SlpReqW<'_, KeyscanLpCtlSpec> {
                SlpReqW::new(self, 4)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn slp_ack(&mut self) -> SlpAckW<'_, KeyscanLpCtlSpec> {
                SlpAckW::new(self, 8)
            }
        }
        #[doc = "keyscan_lp_ctl\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_lp_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_lp_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanLpCtlSpec;
        impl crate::RegisterSpec for KeyscanLpCtlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_lp_ctl::R`](R) reader structure"]
        impl crate::Readable for KeyscanLpCtlSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_lp_ctl::W`](W) writer structure"]
        impl crate::Writable for KeyscanLpCtlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_LP_CTL to value 0"]
        impl crate::Resettable for KeyscanLpCtlSpec {}
    }
    #[doc = "KEYSCAN_ENABLE (rw) register accessor: keyscan_enable\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_enable`] module"]
    #[doc(alias = "KEYSCAN_ENABLE")]
    pub type KeyscanEnable = crate::Reg<keyscan_enable::KeyscanEnableSpec>;
    #[doc = "keyscan_enable"]
    pub mod keyscan_enable {
        #[doc = "Register `KEYSCAN_ENABLE` reader"]
        pub type R = crate::R<KeyscanEnableSpec>;
        #[doc = "Register `KEYSCAN_ENABLE` writer"]
        pub type W = crate::W<KeyscanEnableSpec>;
        #[doc = "Field `ena` reader - "]
        pub type EnaR = crate::BitReader;
        #[doc = "Field `ena` writer - "]
        pub type EnaW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn ena(&self) -> EnaR {
                EnaR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn ena(&mut self) -> EnaW<'_, KeyscanEnableSpec> {
                EnaW::new(self, 0)
            }
        }
        #[doc = "keyscan_enable\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanEnableSpec;
        impl crate::RegisterSpec for KeyscanEnableSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_enable::R`](R) reader structure"]
        impl crate::Readable for KeyscanEnableSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_enable::W`](W) writer structure"]
        impl crate::Writable for KeyscanEnableSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_ENABLE to value 0"]
        impl crate::Resettable for KeyscanEnableSpec {}
    }
    #[doc = "KEYSCAN_CLK_ENA (rw) register accessor: keyscan_clk_ena\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_clk_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_clk_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_clk_ena`] module"]
    #[doc(alias = "KEYSCAN_CLK_ENA")]
    pub type KeyscanClkEna = crate::Reg<keyscan_clk_ena::KeyscanClkEnaSpec>;
    #[doc = "keyscan_clk_ena"]
    pub mod keyscan_clk_ena {
        #[doc = "Register `KEYSCAN_CLK_ENA` reader"]
        pub type R = crate::R<KeyscanClkEnaSpec>;
        #[doc = "Register `KEYSCAN_CLK_ENA` writer"]
        pub type W = crate::W<KeyscanClkEnaSpec>;
        #[doc = "Field `fifo_rd_clken` reader - "]
        pub type FifoRdClkenR = crate::BitReader;
        #[doc = "Field `fifo_rd_clken` writer - "]
        pub type FifoRdClkenW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn fifo_rd_clken(&self) -> FifoRdClkenR {
                FifoRdClkenR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn fifo_rd_clken(&mut self) -> FifoRdClkenW<'_, KeyscanClkEnaSpec> {
                FifoRdClkenW::new(self, 0)
            }
        }
        #[doc = "keyscan_clk_ena\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_clk_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_clk_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanClkEnaSpec;
        impl crate::RegisterSpec for KeyscanClkEnaSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_clk_ena::R`](R) reader structure"]
        impl crate::Readable for KeyscanClkEnaSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_clk_ena::W`](W) writer structure"]
        impl crate::Writable for KeyscanClkEnaSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_CLK_ENA to value 0"]
        impl crate::Resettable for KeyscanClkEnaSpec {}
    }
    #[doc = "KEYSCAN_START (rw) register accessor: keyscan_start\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_start`] module"]
    #[doc(alias = "KEYSCAN_START")]
    pub type KeyscanStart = crate::Reg<keyscan_start::KeyscanStartSpec>;
    #[doc = "keyscan_start"]
    pub mod keyscan_start {
        #[doc = "Register `KEYSCAN_START` reader"]
        pub type R = crate::R<KeyscanStartSpec>;
        #[doc = "Register `KEYSCAN_START` writer"]
        pub type W = crate::W<KeyscanStartSpec>;
        #[doc = "Field `task_start` reader - "]
        pub type TaskStartR = crate::BitReader;
        #[doc = "Field `task_start` writer - "]
        pub type TaskStartW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn task_start(&self) -> TaskStartR {
                TaskStartR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn task_start(&mut self) -> TaskStartW<'_, KeyscanStartSpec> {
                TaskStartW::new(self, 0)
            }
        }
        #[doc = "keyscan_start\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanStartSpec;
        impl crate::RegisterSpec for KeyscanStartSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_start::R`](R) reader structure"]
        impl crate::Readable for KeyscanStartSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_start::W`](W) writer structure"]
        impl crate::Writable for KeyscanStartSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_START to value 0"]
        impl crate::Resettable for KeyscanStartSpec {}
    }
    #[doc = "KEYSCAN_INT_EN (rw) register accessor: keyscan_int_en\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_int_en`] module"]
    #[doc(alias = "KEYSCAN_INT_EN")]
    pub type KeyscanIntEn = crate::Reg<keyscan_int_en::KeyscanIntEnSpec>;
    #[doc = "keyscan_int_en"]
    pub mod keyscan_int_en {
        #[doc = "Register `KEYSCAN_INT_EN` reader"]
        pub type R = crate::R<KeyscanIntEnSpec>;
        #[doc = "Register `KEYSCAN_INT_EN` writer"]
        pub type W = crate::W<KeyscanIntEnSpec>;
        #[doc = "Field `event_fifo_full_int_en` reader - "]
        pub type EventFifoFullIntEnR = crate::BitReader;
        #[doc = "Field `event_fifo_full_int_en` writer - "]
        pub type EventFifoFullIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_press_int_en` reader - "]
        pub type EventKeyPressIntEnR = crate::BitReader;
        #[doc = "Field `event_key_press_int_en` writer - "]
        pub type EventKeyPressIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_release_int_en` reader - "]
        pub type EventKeyReleaseIntEnR = crate::BitReader;
        #[doc = "Field `event_key_release_int_en` writer - "]
        pub type EventKeyReleaseIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_value_rdy_int_en` reader - "]
        pub type EventKeyValueRdyIntEnR = crate::BitReader;
        #[doc = "Field `event_key_value_rdy_int_en` writer - "]
        pub type EventKeyValueRdyIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_stopped_int_en` reader - "]
        pub type EventKeyStoppedIntEnR = crate::BitReader;
        #[doc = "Field `event_key_stopped_int_en` writer - "]
        pub type EventKeyStoppedIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_keyscan_one_int_en` reader - "]
        pub type EventKeyscanOneIntEnR = crate::BitReader;
        #[doc = "Field `event_keyscan_one_int_en` writer - "]
        pub type EventKeyscanOneIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_fifo_afull_int_en` reader - "]
        pub type EventFifoAfullIntEnR = crate::BitReader;
        #[doc = "Field `event_fifo_afull_int_en` writer - "]
        pub type EventFifoAfullIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_press_aon_int_en` reader - "]
        pub type EventKeyPressAonIntEnR = crate::BitReader;
        #[doc = "Field `event_key_press_aon_int_en` writer - "]
        pub type EventKeyPressAonIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn event_fifo_full_int_en(&self) -> EventFifoFullIntEnR {
                EventFifoFullIntEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn event_key_press_int_en(&self) -> EventKeyPressIntEnR {
                EventKeyPressIntEnR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn event_key_release_int_en(&self) -> EventKeyReleaseIntEnR {
                EventKeyReleaseIntEnR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn event_key_value_rdy_int_en(&self) -> EventKeyValueRdyIntEnR {
                EventKeyValueRdyIntEnR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn event_key_stopped_int_en(&self) -> EventKeyStoppedIntEnR {
                EventKeyStoppedIntEnR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn event_keyscan_one_int_en(&self) -> EventKeyscanOneIntEnR {
                EventKeyscanOneIntEnR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn event_fifo_afull_int_en(&self) -> EventFifoAfullIntEnR {
                EventFifoAfullIntEnR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn event_key_press_aon_int_en(&self) -> EventKeyPressAonIntEnR {
                EventKeyPressAonIntEnR::new(((self.bits >> 7) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn event_fifo_full_int_en(&mut self) -> EventFifoFullIntEnW<'_, KeyscanIntEnSpec> {
                EventFifoFullIntEnW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn event_key_press_int_en(&mut self) -> EventKeyPressIntEnW<'_, KeyscanIntEnSpec> {
                EventKeyPressIntEnW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn event_key_release_int_en(
                &mut self,
            ) -> EventKeyReleaseIntEnW<'_, KeyscanIntEnSpec> {
                EventKeyReleaseIntEnW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn event_key_value_rdy_int_en(
                &mut self,
            ) -> EventKeyValueRdyIntEnW<'_, KeyscanIntEnSpec> {
                EventKeyValueRdyIntEnW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn event_key_stopped_int_en(
                &mut self,
            ) -> EventKeyStoppedIntEnW<'_, KeyscanIntEnSpec> {
                EventKeyStoppedIntEnW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn event_keyscan_one_int_en(
                &mut self,
            ) -> EventKeyscanOneIntEnW<'_, KeyscanIntEnSpec> {
                EventKeyscanOneIntEnW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn event_fifo_afull_int_en(
                &mut self,
            ) -> EventFifoAfullIntEnW<'_, KeyscanIntEnSpec> {
                EventFifoAfullIntEnW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn event_key_press_aon_int_en(
                &mut self,
            ) -> EventKeyPressAonIntEnW<'_, KeyscanIntEnSpec> {
                EventKeyPressAonIntEnW::new(self, 7)
            }
        }
        #[doc = "keyscan_int_en\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanIntEnSpec;
        impl crate::RegisterSpec for KeyscanIntEnSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_int_en::R`](R) reader structure"]
        impl crate::Readable for KeyscanIntEnSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_int_en::W`](W) writer structure"]
        impl crate::Writable for KeyscanIntEnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_INT_EN to value 0"]
        impl crate::Resettable for KeyscanIntEnSpec {}
    }
    #[doc = "KEYSCAN_EVENT_CLR (rw) register accessor: keyscan_event_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_event_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_event_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_event_clr`] module"]
    #[doc(alias = "KEYSCAN_EVENT_CLR")]
    pub type KeyscanEventClr = crate::Reg<keyscan_event_clr::KeyscanEventClrSpec>;
    #[doc = "keyscan_event_clr"]
    pub mod keyscan_event_clr {
        #[doc = "Register `KEYSCAN_EVENT_CLR` reader"]
        pub type R = crate::R<KeyscanEventClrSpec>;
        #[doc = "Register `KEYSCAN_EVENT_CLR` writer"]
        pub type W = crate::W<KeyscanEventClrSpec>;
        #[doc = "Field `event_fifo_full_clr` reader - "]
        pub type EventFifoFullClrR = crate::BitReader;
        #[doc = "Field `event_fifo_full_clr` writer - "]
        pub type EventFifoFullClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_press_clr` reader - "]
        pub type EventKeyPressClrR = crate::BitReader;
        #[doc = "Field `event_key_press_clr` writer - "]
        pub type EventKeyPressClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_release_clr` reader - "]
        pub type EventKeyReleaseClrR = crate::BitReader;
        #[doc = "Field `event_key_release_clr` writer - "]
        pub type EventKeyReleaseClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_value_rdy_clr` reader - "]
        pub type EventKeyValueRdyClrR = crate::BitReader;
        #[doc = "Field `event_key_value_rdy_clr` writer - "]
        pub type EventKeyValueRdyClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_stopped_clr` reader - "]
        pub type EventKeyStoppedClrR = crate::BitReader;
        #[doc = "Field `event_key_stopped_clr` writer - "]
        pub type EventKeyStoppedClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_keyscan_one_clr` reader - "]
        pub type EventKeyscanOneClrR = crate::BitReader;
        #[doc = "Field `event_keyscan_one_clr` writer - "]
        pub type EventKeyscanOneClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_fifo_afull_clr` reader - "]
        pub type EventFifoAfullClrR = crate::BitReader;
        #[doc = "Field `event_fifo_afull_clr` writer - "]
        pub type EventFifoAfullClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_press_aon_clr` reader - "]
        pub type EventKeyPressAonClrR = crate::BitReader;
        #[doc = "Field `event_key_press_aon_clr` writer - "]
        pub type EventKeyPressAonClrW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn event_fifo_full_clr(&self) -> EventFifoFullClrR {
                EventFifoFullClrR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn event_key_press_clr(&self) -> EventKeyPressClrR {
                EventKeyPressClrR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn event_key_release_clr(&self) -> EventKeyReleaseClrR {
                EventKeyReleaseClrR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn event_key_value_rdy_clr(&self) -> EventKeyValueRdyClrR {
                EventKeyValueRdyClrR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn event_key_stopped_clr(&self) -> EventKeyStoppedClrR {
                EventKeyStoppedClrR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn event_keyscan_one_clr(&self) -> EventKeyscanOneClrR {
                EventKeyscanOneClrR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn event_fifo_afull_clr(&self) -> EventFifoAfullClrR {
                EventFifoAfullClrR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn event_key_press_aon_clr(&self) -> EventKeyPressAonClrR {
                EventKeyPressAonClrR::new(((self.bits >> 7) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn event_fifo_full_clr(&mut self) -> EventFifoFullClrW<'_, KeyscanEventClrSpec> {
                EventFifoFullClrW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn event_key_press_clr(&mut self) -> EventKeyPressClrW<'_, KeyscanEventClrSpec> {
                EventKeyPressClrW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn event_key_release_clr(
                &mut self,
            ) -> EventKeyReleaseClrW<'_, KeyscanEventClrSpec> {
                EventKeyReleaseClrW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn event_key_value_rdy_clr(
                &mut self,
            ) -> EventKeyValueRdyClrW<'_, KeyscanEventClrSpec> {
                EventKeyValueRdyClrW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn event_key_stopped_clr(
                &mut self,
            ) -> EventKeyStoppedClrW<'_, KeyscanEventClrSpec> {
                EventKeyStoppedClrW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn event_keyscan_one_clr(
                &mut self,
            ) -> EventKeyscanOneClrW<'_, KeyscanEventClrSpec> {
                EventKeyscanOneClrW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn event_fifo_afull_clr(&mut self) -> EventFifoAfullClrW<'_, KeyscanEventClrSpec> {
                EventFifoAfullClrW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn event_key_press_aon_clr(
                &mut self,
            ) -> EventKeyPressAonClrW<'_, KeyscanEventClrSpec> {
                EventKeyPressAonClrW::new(self, 7)
            }
        }
        #[doc = "keyscan_event_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_event_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_event_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanEventClrSpec;
        impl crate::RegisterSpec for KeyscanEventClrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_event_clr::R`](R) reader structure"]
        impl crate::Readable for KeyscanEventClrSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_event_clr::W`](W) writer structure"]
        impl crate::Writable for KeyscanEventClrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_EVENT_CLR to value 0"]
        impl crate::Resettable for KeyscanEventClrSpec {}
    }
    #[doc = "KEYSCAN_EVENT_STS (rw) register accessor: keyscan_event_sts\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_event_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_event_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_event_sts`] module"]
    #[doc(alias = "KEYSCAN_EVENT_STS")]
    pub type KeyscanEventSts = crate::Reg<keyscan_event_sts::KeyscanEventStsSpec>;
    #[doc = "keyscan_event_sts"]
    pub mod keyscan_event_sts {
        #[doc = "Register `KEYSCAN_EVENT_STS` reader"]
        pub type R = crate::R<KeyscanEventStsSpec>;
        #[doc = "Register `KEYSCAN_EVENT_STS` writer"]
        pub type W = crate::W<KeyscanEventStsSpec>;
        #[doc = "Field `event_fifo_full` reader - "]
        pub type EventFifoFullR = crate::BitReader;
        #[doc = "Field `event_fifo_full` writer - "]
        pub type EventFifoFullW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_press` reader - "]
        pub type EventKeyPressR = crate::BitReader;
        #[doc = "Field `event_key_press` writer - "]
        pub type EventKeyPressW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_release` reader - "]
        pub type EventKeyReleaseR = crate::BitReader;
        #[doc = "Field `event_key_release` writer - "]
        pub type EventKeyReleaseW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_value_rdy` reader - "]
        pub type EventKeyValueRdyR = crate::BitReader;
        #[doc = "Field `event_key_value_rdy` writer - "]
        pub type EventKeyValueRdyW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_stopped` reader - "]
        pub type EventKeyStoppedR = crate::BitReader;
        #[doc = "Field `event_key_stopped` writer - "]
        pub type EventKeyStoppedW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_keyscan_one` reader - "]
        pub type EventKeyscanOneR = crate::BitReader;
        #[doc = "Field `event_keyscan_one` writer - "]
        pub type EventKeyscanOneW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_fifo_afull` reader - "]
        pub type EventFifoAfullR = crate::BitReader;
        #[doc = "Field `event_fifo_afull` writer - "]
        pub type EventFifoAfullW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `event_key_press_aon` reader - "]
        pub type EventKeyPressAonR = crate::BitReader;
        #[doc = "Field `event_key_press_aon` writer - "]
        pub type EventKeyPressAonW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn event_fifo_full(&self) -> EventFifoFullR {
                EventFifoFullR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn event_key_press(&self) -> EventKeyPressR {
                EventKeyPressR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn event_key_release(&self) -> EventKeyReleaseR {
                EventKeyReleaseR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn event_key_value_rdy(&self) -> EventKeyValueRdyR {
                EventKeyValueRdyR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn event_key_stopped(&self) -> EventKeyStoppedR {
                EventKeyStoppedR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn event_keyscan_one(&self) -> EventKeyscanOneR {
                EventKeyscanOneR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn event_fifo_afull(&self) -> EventFifoAfullR {
                EventFifoAfullR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn event_key_press_aon(&self) -> EventKeyPressAonR {
                EventKeyPressAonR::new(((self.bits >> 7) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn event_fifo_full(&mut self) -> EventFifoFullW<'_, KeyscanEventStsSpec> {
                EventFifoFullW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn event_key_press(&mut self) -> EventKeyPressW<'_, KeyscanEventStsSpec> {
                EventKeyPressW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn event_key_release(&mut self) -> EventKeyReleaseW<'_, KeyscanEventStsSpec> {
                EventKeyReleaseW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn event_key_value_rdy(&mut self) -> EventKeyValueRdyW<'_, KeyscanEventStsSpec> {
                EventKeyValueRdyW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn event_key_stopped(&mut self) -> EventKeyStoppedW<'_, KeyscanEventStsSpec> {
                EventKeyStoppedW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn event_keyscan_one(&mut self) -> EventKeyscanOneW<'_, KeyscanEventStsSpec> {
                EventKeyscanOneW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn event_fifo_afull(&mut self) -> EventFifoAfullW<'_, KeyscanEventStsSpec> {
                EventFifoAfullW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn event_key_press_aon(&mut self) -> EventKeyPressAonW<'_, KeyscanEventStsSpec> {
                EventKeyPressAonW::new(self, 7)
            }
        }
        #[doc = "keyscan_event_sts\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_event_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_event_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanEventStsSpec;
        impl crate::RegisterSpec for KeyscanEventStsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_event_sts::R`](R) reader structure"]
        impl crate::Readable for KeyscanEventStsSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_event_sts::W`](W) writer structure"]
        impl crate::Writable for KeyscanEventStsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_EVENT_STS to value 0"]
        impl crate::Resettable for KeyscanEventStsSpec {}
    }
    #[doc = "KEYSCAN_PIN_NUM (rw) register accessor: keyscan_pin_num\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_pin_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_pin_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_pin_num`] module"]
    #[doc(alias = "KEYSCAN_PIN_NUM")]
    pub type KeyscanPinNum = crate::Reg<keyscan_pin_num::KeyscanPinNumSpec>;
    #[doc = "keyscan_pin_num"]
    pub mod keyscan_pin_num {
        #[doc = "Register `KEYSCAN_PIN_NUM` reader"]
        pub type R = crate::R<KeyscanPinNumSpec>;
        #[doc = "Register `KEYSCAN_PIN_NUM` writer"]
        pub type W = crate::W<KeyscanPinNumSpec>;
        #[doc = "Field `clo_pin_en` reader - "]
        pub type CloPinEnR = crate::FieldReader;
        #[doc = "Field `clo_pin_en` writer - "]
        pub type CloPinEnW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `row_pin_en` reader - "]
        pub type RowPinEnR = crate::FieldReader;
        #[doc = "Field `row_pin_en` writer - "]
        pub type RowPinEnW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn clo_pin_en(&self) -> CloPinEnR {
                CloPinEnR::new((self.bits & 7) as u8)
            }
            #[doc = "Bits 4:8"]
            #[inline(always)]
            pub fn row_pin_en(&self) -> RowPinEnR {
                RowPinEnR::new(((self.bits >> 4) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn clo_pin_en(&mut self) -> CloPinEnW<'_, KeyscanPinNumSpec> {
                CloPinEnW::new(self, 0)
            }
            #[doc = "Bits 4:8"]
            #[inline(always)]
            pub fn row_pin_en(&mut self) -> RowPinEnW<'_, KeyscanPinNumSpec> {
                RowPinEnW::new(self, 4)
            }
        }
        #[doc = "keyscan_pin_num\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_pin_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_pin_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanPinNumSpec;
        impl crate::RegisterSpec for KeyscanPinNumSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_pin_num::R`](R) reader structure"]
        impl crate::Readable for KeyscanPinNumSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_pin_num::W`](W) writer structure"]
        impl crate::Writable for KeyscanPinNumSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_PIN_NUM to value 0"]
        impl crate::Resettable for KeyscanPinNumSpec {}
    }
    #[doc = "KEYSCAN_MODE (rw) register accessor: keyscan_mode\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_mode`] module"]
    #[doc(alias = "KEYSCAN_MODE")]
    pub type KeyscanMode = crate::Reg<keyscan_mode::KeyscanModeSpec>;
    #[doc = "keyscan_mode"]
    pub mod keyscan_mode {
        #[doc = "Register `KEYSCAN_MODE` reader"]
        pub type R = crate::R<KeyscanModeSpec>;
        #[doc = "Register `KEYSCAN_MODE` writer"]
        pub type W = crate::W<KeyscanModeSpec>;
        #[doc = "Field `scan_dir` reader - "]
        pub type ScanDirR = crate::BitReader;
        #[doc = "Field `scan_dir` writer - "]
        pub type ScanDirW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `scan_mode` reader - "]
        pub type ScanModeR = crate::FieldReader;
        #[doc = "Field `scan_mode` writer - "]
        pub type ScanModeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn scan_dir(&self) -> ScanDirR {
                ScanDirR::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 4:5"]
            #[inline(always)]
            pub fn scan_mode(&self) -> ScanModeR {
                ScanModeR::new(((self.bits >> 4) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn scan_dir(&mut self) -> ScanDirW<'_, KeyscanModeSpec> {
                ScanDirW::new(self, 0)
            }
            #[doc = "Bits 4:5"]
            #[inline(always)]
            pub fn scan_mode(&mut self) -> ScanModeW<'_, KeyscanModeSpec> {
                ScanModeW::new(self, 4)
            }
        }
        #[doc = "keyscan_mode\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanModeSpec;
        impl crate::RegisterSpec for KeyscanModeSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_mode::R`](R) reader structure"]
        impl crate::Readable for KeyscanModeSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_mode::W`](W) writer structure"]
        impl crate::Writable for KeyscanModeSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_MODE to value 0"]
        impl crate::Resettable for KeyscanModeSpec {}
    }
    #[doc = "KEYSCAN_PULSE (rw) register accessor: keyscan_pulse\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_pulse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_pulse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_pulse`] module"]
    #[doc(alias = "KEYSCAN_PULSE")]
    pub type KeyscanPulse = crate::Reg<keyscan_pulse::KeyscanPulseSpec>;
    #[doc = "keyscan_pulse"]
    pub mod keyscan_pulse {
        #[doc = "Register `KEYSCAN_PULSE` reader"]
        pub type R = crate::R<KeyscanPulseSpec>;
        #[doc = "Register `KEYSCAN_PULSE` writer"]
        pub type W = crate::W<KeyscanPulseSpec>;
        #[doc = "Field `tpulse` reader - "]
        pub type TpulseR = crate::FieldReader;
        #[doc = "Field `tpulse` writer - "]
        pub type TpulseW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `ttern` reader - "]
        pub type TternR = crate::FieldReader;
        #[doc = "Field `ttern` writer - "]
        pub type TternW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `tidle` reader - "]
        pub type TidleR = crate::FieldReader;
        #[doc = "Field `tidle` writer - "]
        pub type TidleW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn tpulse(&self) -> TpulseR {
                TpulseR::new((self.bits & 3) as u8)
            }
            #[doc = "Bits 4:5"]
            #[inline(always)]
            pub fn ttern(&self) -> TternR {
                TternR::new(((self.bits >> 4) & 3) as u8)
            }
            #[doc = "Bits 8:10"]
            #[inline(always)]
            pub fn tidle(&self) -> TidleR {
                TidleR::new(((self.bits >> 8) & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn tpulse(&mut self) -> TpulseW<'_, KeyscanPulseSpec> {
                TpulseW::new(self, 0)
            }
            #[doc = "Bits 4:5"]
            #[inline(always)]
            pub fn ttern(&mut self) -> TternW<'_, KeyscanPulseSpec> {
                TternW::new(self, 4)
            }
            #[doc = "Bits 8:10"]
            #[inline(always)]
            pub fn tidle(&mut self) -> TidleW<'_, KeyscanPulseSpec> {
                TidleW::new(self, 8)
            }
        }
        #[doc = "keyscan_pulse\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_pulse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_pulse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanPulseSpec;
        impl crate::RegisterSpec for KeyscanPulseSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_pulse::R`](R) reader structure"]
        impl crate::Readable for KeyscanPulseSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_pulse::W`](W) writer structure"]
        impl crate::Writable for KeyscanPulseSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_PULSE to value 0"]
        impl crate::Resettable for KeyscanPulseSpec {}
    }
    #[doc = "KEYSCAN_DE (rw) register accessor: keyscan_de\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_de::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_de::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyscan_de`] module"]
    #[doc(alias = "KEYSCAN_DE")]
    pub type KeyscanDe = crate::Reg<keyscan_de::KeyscanDeSpec>;
    #[doc = "keyscan_de"]
    pub mod keyscan_de {
        #[doc = "Register `KEYSCAN_DE` reader"]
        pub type R = crate::R<KeyscanDeSpec>;
        #[doc = "Register `KEYSCAN_DE` writer"]
        pub type W = crate::W<KeyscanDeSpec>;
        #[doc = "Field `scan_num` reader - "]
        pub type ScanNumR = crate::FieldReader;
        #[doc = "Field `scan_num` writer - "]
        pub type ScanNumW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `ghost` reader - "]
        pub type GhostR = crate::BitReader;
        #[doc = "Field `ghost` writer - "]
        pub type GhostW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `io_de` reader - "]
        pub type IoDeR = crate::BitReader;
        #[doc = "Field `io_de` writer - "]
        pub type IoDeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `key_num_sel` reader - "]
        pub type KeyNumSelR = crate::FieldReader;
        #[doc = "Field `key_num_sel` writer - "]
        pub type KeyNumSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `rep_all_key` reader - "]
        pub type RepAllKeyR = crate::BitReader;
        #[doc = "Field `rep_all_key` writer - "]
        pub type RepAllKeyW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn scan_num(&self) -> ScanNumR {
                ScanNumR::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn ghost(&self) -> GhostR {
                GhostR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn io_de(&self) -> IoDeR {
                IoDeR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bits 12:13"]
            #[inline(always)]
            pub fn key_num_sel(&self) -> KeyNumSelR {
                KeyNumSelR::new(((self.bits >> 12) & 3) as u8)
            }
            #[doc = "Bit 14"]
            #[inline(always)]
            pub fn rep_all_key(&self) -> RepAllKeyR {
                RepAllKeyR::new(((self.bits >> 14) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn scan_num(&mut self) -> ScanNumW<'_, KeyscanDeSpec> {
                ScanNumW::new(self, 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn ghost(&mut self) -> GhostW<'_, KeyscanDeSpec> {
                GhostW::new(self, 4)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn io_de(&mut self) -> IoDeW<'_, KeyscanDeSpec> {
                IoDeW::new(self, 8)
            }
            #[doc = "Bits 12:13"]
            #[inline(always)]
            pub fn key_num_sel(&mut self) -> KeyNumSelW<'_, KeyscanDeSpec> {
                KeyNumSelW::new(self, 12)
            }
            #[doc = "Bit 14"]
            #[inline(always)]
            pub fn rep_all_key(&mut self) -> RepAllKeyW<'_, KeyscanDeSpec> {
                RepAllKeyW::new(self, 14)
            }
        }
        #[doc = "keyscan_de\n\nYou can [`read`](crate::Reg::read) this register and get [`keyscan_de::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`keyscan_de::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyscanDeSpec;
        impl crate::RegisterSpec for KeyscanDeSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyscan_de::R`](R) reader structure"]
        impl crate::Readable for KeyscanDeSpec {}
        #[doc = "`write(|w| ..)` method takes [`keyscan_de::W`](W) writer structure"]
        impl crate::Writable for KeyscanDeSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEYSCAN_DE to value 0"]
        impl crate::Resettable for KeyscanDeSpec {}
    }
    #[doc = "KEY_VALUE_FIFO (rw) register accessor: key_value_fifo\n\nYou can [`read`](crate::Reg::read) this register and get [`key_value_fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key_value_fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_value_fifo`] module"]
    #[doc(alias = "KEY_VALUE_FIFO")]
    pub type KeyValueFifo = crate::Reg<key_value_fifo::KeyValueFifoSpec>;
    #[doc = "key_value_fifo"]
    pub mod key_value_fifo {
        #[doc = "Register `KEY_VALUE_FIFO` reader"]
        pub type R = crate::R<KeyValueFifoSpec>;
        #[doc = "Register `KEY_VALUE_FIFO` writer"]
        pub type W = crate::W<KeyValueFifoSpec>;
        #[doc = "Field `key_value` reader - "]
        pub type KeyValueR = crate::FieldReader<u16>;
        #[doc = "Field `key_value` writer - "]
        pub type KeyValueW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        impl R {
            #[doc = "Bits 0:8"]
            #[inline(always)]
            pub fn key_value(&self) -> KeyValueR {
                KeyValueR::new((self.bits & 0x01ff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:8"]
            #[inline(always)]
            pub fn key_value(&mut self) -> KeyValueW<'_, KeyValueFifoSpec> {
                KeyValueW::new(self, 0)
            }
        }
        #[doc = "key_value_fifo\n\nYou can [`read`](crate::Reg::read) this register and get [`key_value_fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key_value_fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KeyValueFifoSpec;
        impl crate::RegisterSpec for KeyValueFifoSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`key_value_fifo::R`](R) reader structure"]
        impl crate::Readable for KeyValueFifoSpec {}
        #[doc = "`write(|w| ..)` method takes [`key_value_fifo::W`](W) writer structure"]
        impl crate::Writable for KeyValueFifoSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets KEY_VALUE_FIFO to value 0"]
        impl crate::Resettable for KeyValueFifoSpec {}
    }
}
#[doc = "PDM microphone interface (v150)"]
pub type Pdm = crate::Periph<pdm::RegisterBlock, 0x5208_e000>;
impl core::fmt::Debug for Pdm {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Pdm").finish()
    }
}
#[doc = "PDM microphone interface (v150)"]
pub mod pdm {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        version: Version,
        clk_rst_en: ClkRstEn,
        ch_ctrl: ChCtrl,
        mic_ctrl: MicCtrl,
        cic_ctrl: CicCtrl,
        compd_ctrl: CompdCtrl,
        _reserved6: [u8; 0x08],
        srcdn_ctrl: SrcdnCtrl,
        up_fifo_ctrl: UpFifoCtrl,
        up_fifo_st_ctrl: UpFifoStCtrl,
        up_fifo_st_clr: UpFifoStClr,
    }
    impl RegisterBlock {
        #[doc = "0x00 - version"]
        #[inline(always)]
        pub const fn version(&self) -> &Version {
            &self.version
        }
        #[doc = "0x04 - clk_rst_en"]
        #[inline(always)]
        pub const fn clk_rst_en(&self) -> &ClkRstEn {
            &self.clk_rst_en
        }
        #[doc = "0x08 - ch_ctrl"]
        #[inline(always)]
        pub const fn ch_ctrl(&self) -> &ChCtrl {
            &self.ch_ctrl
        }
        #[doc = "0x0c - mic_ctrl"]
        #[inline(always)]
        pub const fn mic_ctrl(&self) -> &MicCtrl {
            &self.mic_ctrl
        }
        #[doc = "0x10 - cic_ctrl"]
        #[inline(always)]
        pub const fn cic_ctrl(&self) -> &CicCtrl {
            &self.cic_ctrl
        }
        #[doc = "0x14 - compd_ctrl"]
        #[inline(always)]
        pub const fn compd_ctrl(&self) -> &CompdCtrl {
            &self.compd_ctrl
        }
        #[doc = "0x20 - srcdn_ctrl"]
        #[inline(always)]
        pub const fn srcdn_ctrl(&self) -> &SrcdnCtrl {
            &self.srcdn_ctrl
        }
        #[doc = "0x24 - up_fifo_ctrl"]
        #[inline(always)]
        pub const fn up_fifo_ctrl(&self) -> &UpFifoCtrl {
            &self.up_fifo_ctrl
        }
        #[doc = "0x28 - up_fifo_st_ctrl"]
        #[inline(always)]
        pub const fn up_fifo_st_ctrl(&self) -> &UpFifoStCtrl {
            &self.up_fifo_st_ctrl
        }
        #[doc = "0x2c - up_fifo_st_clr"]
        #[inline(always)]
        pub const fn up_fifo_st_clr(&self) -> &UpFifoStClr {
            &self.up_fifo_st_clr
        }
    }
    #[doc = "VERSION (rw) register accessor: version\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"]
    #[doc(alias = "VERSION")]
    pub type Version = crate::Reg<version::VersionSpec>;
    #[doc = "version"]
    pub mod version {
        #[doc = "Register `VERSION` reader"]
        pub type R = crate::R<VersionSpec>;
        #[doc = "Register `VERSION` writer"]
        pub type W = crate::W<VersionSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "version\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct VersionSpec;
        impl crate::RegisterSpec for VersionSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`version::R`](R) reader structure"]
        impl crate::Readable for VersionSpec {}
        #[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"]
        impl crate::Writable for VersionSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets VERSION to value 0"]
        impl crate::Resettable for VersionSpec {}
    }
    #[doc = "CLK_RST_EN (rw) register accessor: clk_rst_en\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_rst_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_rst_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_rst_en`] module"]
    #[doc(alias = "CLK_RST_EN")]
    pub type ClkRstEn = crate::Reg<clk_rst_en::ClkRstEnSpec>;
    #[doc = "clk_rst_en"]
    pub mod clk_rst_en {
        #[doc = "Register `CLK_RST_EN` reader"]
        pub type R = crate::R<ClkRstEnSpec>;
        #[doc = "Register `CLK_RST_EN` writer"]
        pub type W = crate::W<ClkRstEnSpec>;
        #[doc = "Field `pdm_dp_rst_n` reader - "]
        pub type PdmDpRstNR = crate::BitReader;
        #[doc = "Field `pdm_dp_rst_n` writer - "]
        pub type PdmDpRstNW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `clk_freq_sel` reader - "]
        pub type ClkFreqSelR = crate::BitReader;
        #[doc = "Field `clk_freq_sel` writer - "]
        pub type ClkFreqSelW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `func_up_en` reader - "]
        pub type FuncUpEnR = crate::BitReader;
        #[doc = "Field `func_up_en` writer - "]
        pub type FuncUpEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmic_clken` reader - "]
        pub type DmicClkenR = crate::BitReader;
        #[doc = "Field `dmic_clken` writer - "]
        pub type DmicClkenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `saradc_clken` reader - "]
        pub type SaradcClkenR = crate::BitReader;
        #[doc = "Field `saradc_clken` writer - "]
        pub type SaradcClkenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ckdiv_6144k_clken` reader - "]
        pub type Ckdiv6144kClkenR = crate::BitReader;
        #[doc = "Field `ckdiv_6144k_clken` writer - "]
        pub type Ckdiv6144kClkenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fifo_clken` reader - "]
        pub type UpFifoClkenR = crate::BitReader;
        #[doc = "Field `up_fifo_clken` writer - "]
        pub type UpFifoClkenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `func_up_ch_en_0` reader - "]
        pub type FuncUpChEn0R = crate::BitReader;
        #[doc = "Field `func_up_ch_en_0` writer - "]
        pub type FuncUpChEn0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cic_clken_0` reader - "]
        pub type CicClken0R = crate::BitReader;
        #[doc = "Field `cic_clken_0` writer - "]
        pub type CicClken0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `compd_clken_0` reader - "]
        pub type CompdClken0R = crate::BitReader;
        #[doc = "Field `compd_clken_0` writer - "]
        pub type CompdClken0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `hpf_clken_0` reader - "]
        pub type HpfClken0R = crate::BitReader;
        #[doc = "Field `hpf_clken_0` writer - "]
        pub type HpfClken0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `srcdn_clken_0` reader - "]
        pub type SrcdnClken0R = crate::BitReader;
        #[doc = "Field `srcdn_clken_0` writer - "]
        pub type SrcdnClken0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `func_up_ch_en_1` reader - "]
        pub type FuncUpChEn1R = crate::BitReader;
        #[doc = "Field `func_up_ch_en_1` writer - "]
        pub type FuncUpChEn1W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cic_clken_1` reader - "]
        pub type CicClken1R = crate::BitReader;
        #[doc = "Field `cic_clken_1` writer - "]
        pub type CicClken1W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `compd_clken_1` reader - "]
        pub type CompdClken1R = crate::BitReader;
        #[doc = "Field `compd_clken_1` writer - "]
        pub type CompdClken1W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `hpf_clken_1` reader - "]
        pub type HpfClken1R = crate::BitReader;
        #[doc = "Field `hpf_clken_1` writer - "]
        pub type HpfClken1W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `srcdn_clken_1` reader - "]
        pub type SrcdnClken1R = crate::BitReader;
        #[doc = "Field `srcdn_clken_1` writer - "]
        pub type SrcdnClken1W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn pdm_dp_rst_n(&self) -> PdmDpRstNR {
                PdmDpRstNR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn clk_freq_sel(&self) -> ClkFreqSelR {
                ClkFreqSelR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn func_up_en(&self) -> FuncUpEnR {
                FuncUpEnR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn dmic_clken(&self) -> DmicClkenR {
                DmicClkenR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn saradc_clken(&self) -> SaradcClkenR {
                SaradcClkenR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn ckdiv_6144k_clken(&self) -> Ckdiv6144kClkenR {
                Ckdiv6144kClkenR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn up_fifo_clken(&self) -> UpFifoClkenR {
                UpFifoClkenR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn func_up_ch_en_0(&self) -> FuncUpChEn0R {
                FuncUpChEn0R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn cic_clken_0(&self) -> CicClken0R {
                CicClken0R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn compd_clken_0(&self) -> CompdClken0R {
                CompdClken0R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn hpf_clken_0(&self) -> HpfClken0R {
                HpfClken0R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn srcdn_clken_0(&self) -> SrcdnClken0R {
                SrcdnClken0R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn func_up_ch_en_1(&self) -> FuncUpChEn1R {
                FuncUpChEn1R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn cic_clken_1(&self) -> CicClken1R {
                CicClken1R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn compd_clken_1(&self) -> CompdClken1R {
                CompdClken1R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn hpf_clken_1(&self) -> HpfClken1R {
                HpfClken1R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn srcdn_clken_1(&self) -> SrcdnClken1R {
                SrcdnClken1R::new(((self.bits >> 20) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn pdm_dp_rst_n(&mut self) -> PdmDpRstNW<'_, ClkRstEnSpec> {
                PdmDpRstNW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn clk_freq_sel(&mut self) -> ClkFreqSelW<'_, ClkRstEnSpec> {
                ClkFreqSelW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn func_up_en(&mut self) -> FuncUpEnW<'_, ClkRstEnSpec> {
                FuncUpEnW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn dmic_clken(&mut self) -> DmicClkenW<'_, ClkRstEnSpec> {
                DmicClkenW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn saradc_clken(&mut self) -> SaradcClkenW<'_, ClkRstEnSpec> {
                SaradcClkenW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn ckdiv_6144k_clken(&mut self) -> Ckdiv6144kClkenW<'_, ClkRstEnSpec> {
                Ckdiv6144kClkenW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn up_fifo_clken(&mut self) -> UpFifoClkenW<'_, ClkRstEnSpec> {
                UpFifoClkenW::new(self, 6)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn func_up_ch_en_0(&mut self) -> FuncUpChEn0W<'_, ClkRstEnSpec> {
                FuncUpChEn0W::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn cic_clken_0(&mut self) -> CicClken0W<'_, ClkRstEnSpec> {
                CicClken0W::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn compd_clken_0(&mut self) -> CompdClken0W<'_, ClkRstEnSpec> {
                CompdClken0W::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn hpf_clken_0(&mut self) -> HpfClken0W<'_, ClkRstEnSpec> {
                HpfClken0W::new(self, 11)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn srcdn_clken_0(&mut self) -> SrcdnClken0W<'_, ClkRstEnSpec> {
                SrcdnClken0W::new(self, 12)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn func_up_ch_en_1(&mut self) -> FuncUpChEn1W<'_, ClkRstEnSpec> {
                FuncUpChEn1W::new(self, 16)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn cic_clken_1(&mut self) -> CicClken1W<'_, ClkRstEnSpec> {
                CicClken1W::new(self, 17)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn compd_clken_1(&mut self) -> CompdClken1W<'_, ClkRstEnSpec> {
                CompdClken1W::new(self, 18)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn hpf_clken_1(&mut self) -> HpfClken1W<'_, ClkRstEnSpec> {
                HpfClken1W::new(self, 19)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn srcdn_clken_1(&mut self) -> SrcdnClken1W<'_, ClkRstEnSpec> {
                SrcdnClken1W::new(self, 20)
            }
        }
        #[doc = "clk_rst_en\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_rst_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_rst_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ClkRstEnSpec;
        impl crate::RegisterSpec for ClkRstEnSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`clk_rst_en::R`](R) reader structure"]
        impl crate::Readable for ClkRstEnSpec {}
        #[doc = "`write(|w| ..)` method takes [`clk_rst_en::W`](W) writer structure"]
        impl crate::Writable for ClkRstEnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CLK_RST_EN to value 0"]
        impl crate::Resettable for ClkRstEnSpec {}
    }
    #[doc = "CH_CTRL (rw) register accessor: ch_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ctrl`] module"]
    #[doc(alias = "CH_CTRL")]
    pub type ChCtrl = crate::Reg<ch_ctrl::ChCtrlSpec>;
    #[doc = "ch_ctrl"]
    pub mod ch_ctrl {
        #[doc = "Register `CH_CTRL` reader"]
        pub type R = crate::R<ChCtrlSpec>;
        #[doc = "Register `CH_CTRL` writer"]
        pub type W = crate::W<ChCtrlSpec>;
        #[doc = "Field `mic_sel` reader - "]
        pub type MicSelR = crate::BitReader;
        #[doc = "Field `mic_sel` writer - "]
        pub type MicSelW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fs_sel_0` reader - "]
        pub type UpFsSel0R = crate::BitReader;
        #[doc = "Field `up_fs_sel_0` writer - "]
        pub type UpFsSel0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fs_sel_1` reader - "]
        pub type UpFsSel1R = crate::BitReader;
        #[doc = "Field `up_fs_sel_1` writer - "]
        pub type UpFsSel1W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn mic_sel(&self) -> MicSelR {
                MicSelR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn up_fs_sel_0(&self) -> UpFsSel0R {
                UpFsSel0R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn up_fs_sel_1(&self) -> UpFsSel1R {
                UpFsSel1R::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn mic_sel(&mut self) -> MicSelW<'_, ChCtrlSpec> {
                MicSelW::new(self, 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn up_fs_sel_0(&mut self) -> UpFsSel0W<'_, ChCtrlSpec> {
                UpFsSel0W::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn up_fs_sel_1(&mut self) -> UpFsSel1W<'_, ChCtrlSpec> {
                UpFsSel1W::new(self, 5)
            }
        }
        #[doc = "ch_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ChCtrlSpec;
        impl crate::RegisterSpec for ChCtrlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ch_ctrl::R`](R) reader structure"]
        impl crate::Readable for ChCtrlSpec {}
        #[doc = "`write(|w| ..)` method takes [`ch_ctrl::W`](W) writer structure"]
        impl crate::Writable for ChCtrlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CH_CTRL to value 0"]
        impl crate::Resettable for ChCtrlSpec {}
    }
    #[doc = "MIC_CTRL (rw) register accessor: mic_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`mic_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mic_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mic_ctrl`] module"]
    #[doc(alias = "MIC_CTRL")]
    pub type MicCtrl = crate::Reg<mic_ctrl::MicCtrlSpec>;
    #[doc = "mic_ctrl"]
    pub mod mic_ctrl {
        #[doc = "Register `MIC_CTRL` reader"]
        pub type R = crate::R<MicCtrlSpec>;
        #[doc = "Register `MIC_CTRL` writer"]
        pub type W = crate::W<MicCtrlSpec>;
        #[doc = "Field `dmic_clk_sel` reader - "]
        pub type DmicClkSelR = crate::FieldReader;
        #[doc = "Field `dmic_clk_sel` writer - "]
        pub type DmicClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `dmic_mode` reader - "]
        pub type DmicModeR = crate::BitReader;
        #[doc = "Field `dmic_mode` writer - "]
        pub type DmicModeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dmic_reverse` reader - "]
        pub type DmicReverseR = crate::BitReader;
        #[doc = "Field `dmic_reverse` writer - "]
        pub type DmicReverseW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `saradc_gain` reader - "]
        pub type SaradcGainR = crate::FieldReader;
        #[doc = "Field `saradc_gain` writer - "]
        pub type SaradcGainW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn dmic_clk_sel(&self) -> DmicClkSelR {
                DmicClkSelR::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn dmic_mode(&self) -> DmicModeR {
                DmicModeR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn dmic_reverse(&self) -> DmicReverseR {
                DmicReverseR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 8:15"]
            #[inline(always)]
            pub fn saradc_gain(&self) -> SaradcGainR {
                SaradcGainR::new(((self.bits >> 8) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn dmic_clk_sel(&mut self) -> DmicClkSelW<'_, MicCtrlSpec> {
                DmicClkSelW::new(self, 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn dmic_mode(&mut self) -> DmicModeW<'_, MicCtrlSpec> {
                DmicModeW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn dmic_reverse(&mut self) -> DmicReverseW<'_, MicCtrlSpec> {
                DmicReverseW::new(self, 3)
            }
            #[doc = "Bits 8:15"]
            #[inline(always)]
            pub fn saradc_gain(&mut self) -> SaradcGainW<'_, MicCtrlSpec> {
                SaradcGainW::new(self, 8)
            }
        }
        #[doc = "mic_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`mic_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mic_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MicCtrlSpec;
        impl crate::RegisterSpec for MicCtrlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`mic_ctrl::R`](R) reader structure"]
        impl crate::Readable for MicCtrlSpec {}
        #[doc = "`write(|w| ..)` method takes [`mic_ctrl::W`](W) writer structure"]
        impl crate::Writable for MicCtrlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets MIC_CTRL to value 0"]
        impl crate::Resettable for MicCtrlSpec {}
    }
    #[doc = "CIC_CTRL (rw) register accessor: cic_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`cic_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cic_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cic_ctrl`] module"]
    #[doc(alias = "CIC_CTRL")]
    pub type CicCtrl = crate::Reg<cic_ctrl::CicCtrlSpec>;
    #[doc = "cic_ctrl"]
    pub mod cic_ctrl {
        #[doc = "Register `CIC_CTRL` reader"]
        pub type R = crate::R<CicCtrlSpec>;
        #[doc = "Register `CIC_CTRL` writer"]
        pub type W = crate::W<CicCtrlSpec>;
        #[doc = "Field `cic_en_0` reader - "]
        pub type CicEn0R = crate::BitReader;
        #[doc = "Field `cic_en_0` writer - "]
        pub type CicEn0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cic_en_1` reader - "]
        pub type CicEn1R = crate::BitReader;
        #[doc = "Field `cic_en_1` writer - "]
        pub type CicEn1W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `cic_gain_0` reader - "]
        pub type CicGain0R = crate::FieldReader;
        #[doc = "Field `cic_gain_0` writer - "]
        pub type CicGain0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `cic_gain_1` reader - "]
        pub type CicGain1R = crate::FieldReader;
        #[doc = "Field `cic_gain_1` writer - "]
        pub type CicGain1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn cic_en_0(&self) -> CicEn0R {
                CicEn0R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn cic_en_1(&self) -> CicEn1R {
                CicEn1R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bits 8:15"]
            #[inline(always)]
            pub fn cic_gain_0(&self) -> CicGain0R {
                CicGain0R::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:23"]
            #[inline(always)]
            pub fn cic_gain_1(&self) -> CicGain1R {
                CicGain1R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn cic_en_0(&mut self) -> CicEn0W<'_, CicCtrlSpec> {
                CicEn0W::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn cic_en_1(&mut self) -> CicEn1W<'_, CicCtrlSpec> {
                CicEn1W::new(self, 1)
            }
            #[doc = "Bits 8:15"]
            #[inline(always)]
            pub fn cic_gain_0(&mut self) -> CicGain0W<'_, CicCtrlSpec> {
                CicGain0W::new(self, 8)
            }
            #[doc = "Bits 16:23"]
            #[inline(always)]
            pub fn cic_gain_1(&mut self) -> CicGain1W<'_, CicCtrlSpec> {
                CicGain1W::new(self, 16)
            }
        }
        #[doc = "cic_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`cic_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cic_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CicCtrlSpec;
        impl crate::RegisterSpec for CicCtrlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cic_ctrl::R`](R) reader structure"]
        impl crate::Readable for CicCtrlSpec {}
        #[doc = "`write(|w| ..)` method takes [`cic_ctrl::W`](W) writer structure"]
        impl crate::Writable for CicCtrlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets CIC_CTRL to value 0"]
        impl crate::Resettable for CicCtrlSpec {}
    }
    #[doc = "COMPD_CTRL (rw) register accessor: compd_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`compd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`compd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@compd_ctrl`] module"]
    #[doc(alias = "COMPD_CTRL")]
    pub type CompdCtrl = crate::Reg<compd_ctrl::CompdCtrlSpec>;
    #[doc = "compd_ctrl"]
    pub mod compd_ctrl {
        #[doc = "Register `COMPD_CTRL` reader"]
        pub type R = crate::R<CompdCtrlSpec>;
        #[doc = "Register `COMPD_CTRL` writer"]
        pub type W = crate::W<CompdCtrlSpec>;
        #[doc = "Field `compd_bypass_en_0` reader - "]
        pub type CompdBypassEn0R = crate::BitReader;
        #[doc = "Field `compd_bypass_en_0` writer - "]
        pub type CompdBypassEn0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `compd_bypass_en_1` reader - "]
        pub type CompdBypassEn1R = crate::BitReader;
        #[doc = "Field `compd_bypass_en_1` writer - "]
        pub type CompdBypassEn1W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn compd_bypass_en_0(&self) -> CompdBypassEn0R {
                CompdBypassEn0R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn compd_bypass_en_1(&self) -> CompdBypassEn1R {
                CompdBypassEn1R::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn compd_bypass_en_0(&mut self) -> CompdBypassEn0W<'_, CompdCtrlSpec> {
                CompdBypassEn0W::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn compd_bypass_en_1(&mut self) -> CompdBypassEn1W<'_, CompdCtrlSpec> {
                CompdBypassEn1W::new(self, 1)
            }
        }
        #[doc = "compd_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`compd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`compd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CompdCtrlSpec;
        impl crate::RegisterSpec for CompdCtrlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`compd_ctrl::R`](R) reader structure"]
        impl crate::Readable for CompdCtrlSpec {}
        #[doc = "`write(|w| ..)` method takes [`compd_ctrl::W`](W) writer structure"]
        impl crate::Writable for CompdCtrlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets COMPD_CTRL to value 0"]
        impl crate::Resettable for CompdCtrlSpec {}
    }
    #[doc = "SRCDN_CTRL (rw) register accessor: srcdn_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`srcdn_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srcdn_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srcdn_ctrl`] module"]
    #[doc(alias = "SRCDN_CTRL")]
    pub type SrcdnCtrl = crate::Reg<srcdn_ctrl::SrcdnCtrlSpec>;
    #[doc = "srcdn_ctrl"]
    pub mod srcdn_ctrl {
        #[doc = "Register `SRCDN_CTRL` reader"]
        pub type R = crate::R<SrcdnCtrlSpec>;
        #[doc = "Register `SRCDN_CTRL` writer"]
        pub type W = crate::W<SrcdnCtrlSpec>;
        #[doc = "Field `srcdn_bypass_en_0` reader - "]
        pub type SrcdnBypassEn0R = crate::BitReader;
        #[doc = "Field `srcdn_bypass_en_0` writer - "]
        pub type SrcdnBypassEn0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `srcdn_bypass_en_1` reader - "]
        pub type SrcdnBypassEn1R = crate::BitReader;
        #[doc = "Field `srcdn_bypass_en_1` writer - "]
        pub type SrcdnBypassEn1W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `srcdn_mode_0` reader - "]
        pub type SrcdnMode0R = crate::FieldReader;
        #[doc = "Field `srcdn_mode_0` writer - "]
        pub type SrcdnMode0W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `srcdn_mode_1` reader - "]
        pub type SrcdnMode1R = crate::FieldReader;
        #[doc = "Field `srcdn_mode_1` writer - "]
        pub type SrcdnMode1W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `srcdn_fifo_clr_0` reader - "]
        pub type SrcdnFifoClr0R = crate::BitReader;
        #[doc = "Field `srcdn_fifo_clr_0` writer - "]
        pub type SrcdnFifoClr0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `srcdn_fifo_clr_1` reader - "]
        pub type SrcdnFifoClr1R = crate::BitReader;
        #[doc = "Field `srcdn_fifo_clr_1` writer - "]
        pub type SrcdnFifoClr1W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn srcdn_bypass_en_0(&self) -> SrcdnBypassEn0R {
                SrcdnBypassEn0R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn srcdn_bypass_en_1(&self) -> SrcdnBypassEn1R {
                SrcdnBypassEn1R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bits 4:5"]
            #[inline(always)]
            pub fn srcdn_mode_0(&self) -> SrcdnMode0R {
                SrcdnMode0R::new(((self.bits >> 4) & 3) as u8)
            }
            #[doc = "Bits 6:7"]
            #[inline(always)]
            pub fn srcdn_mode_1(&self) -> SrcdnMode1R {
                SrcdnMode1R::new(((self.bits >> 6) & 3) as u8)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn srcdn_fifo_clr_0(&self) -> SrcdnFifoClr0R {
                SrcdnFifoClr0R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn srcdn_fifo_clr_1(&self) -> SrcdnFifoClr1R {
                SrcdnFifoClr1R::new(((self.bits >> 9) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn srcdn_bypass_en_0(&mut self) -> SrcdnBypassEn0W<'_, SrcdnCtrlSpec> {
                SrcdnBypassEn0W::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn srcdn_bypass_en_1(&mut self) -> SrcdnBypassEn1W<'_, SrcdnCtrlSpec> {
                SrcdnBypassEn1W::new(self, 1)
            }
            #[doc = "Bits 4:5"]
            #[inline(always)]
            pub fn srcdn_mode_0(&mut self) -> SrcdnMode0W<'_, SrcdnCtrlSpec> {
                SrcdnMode0W::new(self, 4)
            }
            #[doc = "Bits 6:7"]
            #[inline(always)]
            pub fn srcdn_mode_1(&mut self) -> SrcdnMode1W<'_, SrcdnCtrlSpec> {
                SrcdnMode1W::new(self, 6)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn srcdn_fifo_clr_0(&mut self) -> SrcdnFifoClr0W<'_, SrcdnCtrlSpec> {
                SrcdnFifoClr0W::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn srcdn_fifo_clr_1(&mut self) -> SrcdnFifoClr1W<'_, SrcdnCtrlSpec> {
                SrcdnFifoClr1W::new(self, 9)
            }
        }
        #[doc = "srcdn_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`srcdn_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srcdn_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SrcdnCtrlSpec;
        impl crate::RegisterSpec for SrcdnCtrlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`srcdn_ctrl::R`](R) reader structure"]
        impl crate::Readable for SrcdnCtrlSpec {}
        #[doc = "`write(|w| ..)` method takes [`srcdn_ctrl::W`](W) writer structure"]
        impl crate::Writable for SrcdnCtrlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets SRCDN_CTRL to value 0"]
        impl crate::Resettable for SrcdnCtrlSpec {}
    }
    #[doc = "UP_FIFO_CTRL (rw) register accessor: up_fifo_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@up_fifo_ctrl`] module"]
    #[doc(alias = "UP_FIFO_CTRL")]
    pub type UpFifoCtrl = crate::Reg<up_fifo_ctrl::UpFifoCtrlSpec>;
    #[doc = "up_fifo_ctrl"]
    pub mod up_fifo_ctrl {
        #[doc = "Register `UP_FIFO_CTRL` reader"]
        pub type R = crate::R<UpFifoCtrlSpec>;
        #[doc = "Register `UP_FIFO_CTRL` writer"]
        pub type W = crate::W<UpFifoCtrlSpec>;
        #[doc = "Field `up_fifo_aempty_th` reader - "]
        pub type UpFifoAemptyThR = crate::FieldReader;
        #[doc = "Field `up_fifo_aempty_th` writer - "]
        pub type UpFifoAemptyThW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `up_fifo_afull_th` reader - "]
        pub type UpFifoAfullThR = crate::FieldReader;
        #[doc = "Field `up_fifo_afull_th` writer - "]
        pub type UpFifoAfullThW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 0:4"]
            #[inline(always)]
            pub fn up_fifo_aempty_th(&self) -> UpFifoAemptyThR {
                UpFifoAemptyThR::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bits 8:12"]
            #[inline(always)]
            pub fn up_fifo_afull_th(&self) -> UpFifoAfullThR {
                UpFifoAfullThR::new(((self.bits >> 8) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:4"]
            #[inline(always)]
            pub fn up_fifo_aempty_th(&mut self) -> UpFifoAemptyThW<'_, UpFifoCtrlSpec> {
                UpFifoAemptyThW::new(self, 0)
            }
            #[doc = "Bits 8:12"]
            #[inline(always)]
            pub fn up_fifo_afull_th(&mut self) -> UpFifoAfullThW<'_, UpFifoCtrlSpec> {
                UpFifoAfullThW::new(self, 8)
            }
        }
        #[doc = "up_fifo_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UpFifoCtrlSpec;
        impl crate::RegisterSpec for UpFifoCtrlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`up_fifo_ctrl::R`](R) reader structure"]
        impl crate::Readable for UpFifoCtrlSpec {}
        #[doc = "`write(|w| ..)` method takes [`up_fifo_ctrl::W`](W) writer structure"]
        impl crate::Writable for UpFifoCtrlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets UP_FIFO_CTRL to value 0"]
        impl crate::Resettable for UpFifoCtrlSpec {}
    }
    #[doc = "UP_FIFO_ST_CTRL (rw) register accessor: up_fifo_st_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_st_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_st_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@up_fifo_st_ctrl`] module"]
    #[doc(alias = "UP_FIFO_ST_CTRL")]
    pub type UpFifoStCtrl = crate::Reg<up_fifo_st_ctrl::UpFifoStCtrlSpec>;
    #[doc = "up_fifo_st_ctrl"]
    pub mod up_fifo_st_ctrl {
        #[doc = "Register `UP_FIFO_ST_CTRL` reader"]
        pub type R = crate::R<UpFifoStCtrlSpec>;
        #[doc = "Register `UP_FIFO_ST_CTRL` writer"]
        pub type W = crate::W<UpFifoStCtrlSpec>;
        #[doc = "Field `up_fifo_full_int_en` reader - "]
        pub type UpFifoFullIntEnR = crate::BitReader;
        #[doc = "Field `up_fifo_full_int_en` writer - "]
        pub type UpFifoFullIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fifo_afull_int_en` reader - "]
        pub type UpFifoAfullIntEnR = crate::BitReader;
        #[doc = "Field `up_fifo_afull_int_en` writer - "]
        pub type UpFifoAfullIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fifo_empty_int_en` reader - "]
        pub type UpFifoEmptyIntEnR = crate::BitReader;
        #[doc = "Field `up_fifo_empty_int_en` writer - "]
        pub type UpFifoEmptyIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fifo_aempty_int_en` reader - "]
        pub type UpFifoAemptyIntEnR = crate::BitReader;
        #[doc = "Field `up_fifo_aempty_int_en` writer - "]
        pub type UpFifoAemptyIntEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn up_fifo_full_int_en(&self) -> UpFifoFullIntEnR {
                UpFifoFullIntEnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn up_fifo_afull_int_en(&self) -> UpFifoAfullIntEnR {
                UpFifoAfullIntEnR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn up_fifo_empty_int_en(&self) -> UpFifoEmptyIntEnR {
                UpFifoEmptyIntEnR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn up_fifo_aempty_int_en(&self) -> UpFifoAemptyIntEnR {
                UpFifoAemptyIntEnR::new(((self.bits >> 3) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn up_fifo_full_int_en(&mut self) -> UpFifoFullIntEnW<'_, UpFifoStCtrlSpec> {
                UpFifoFullIntEnW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn up_fifo_afull_int_en(&mut self) -> UpFifoAfullIntEnW<'_, UpFifoStCtrlSpec> {
                UpFifoAfullIntEnW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn up_fifo_empty_int_en(&mut self) -> UpFifoEmptyIntEnW<'_, UpFifoStCtrlSpec> {
                UpFifoEmptyIntEnW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn up_fifo_aempty_int_en(&mut self) -> UpFifoAemptyIntEnW<'_, UpFifoStCtrlSpec> {
                UpFifoAemptyIntEnW::new(self, 3)
            }
        }
        #[doc = "up_fifo_st_ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_st_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_st_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UpFifoStCtrlSpec;
        impl crate::RegisterSpec for UpFifoStCtrlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`up_fifo_st_ctrl::R`](R) reader structure"]
        impl crate::Readable for UpFifoStCtrlSpec {}
        #[doc = "`write(|w| ..)` method takes [`up_fifo_st_ctrl::W`](W) writer structure"]
        impl crate::Writable for UpFifoStCtrlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets UP_FIFO_ST_CTRL to value 0"]
        impl crate::Resettable for UpFifoStCtrlSpec {}
    }
    #[doc = "UP_FIFO_ST_CLR (rw) register accessor: up_fifo_st_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_st_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_st_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@up_fifo_st_clr`] module"]
    #[doc(alias = "UP_FIFO_ST_CLR")]
    pub type UpFifoStClr = crate::Reg<up_fifo_st_clr::UpFifoStClrSpec>;
    #[doc = "up_fifo_st_clr"]
    pub mod up_fifo_st_clr {
        #[doc = "Register `UP_FIFO_ST_CLR` reader"]
        pub type R = crate::R<UpFifoStClrSpec>;
        #[doc = "Register `UP_FIFO_ST_CLR` writer"]
        pub type W = crate::W<UpFifoStClrSpec>;
        #[doc = "Field `up_fifo_full_int_clr` reader - "]
        pub type UpFifoFullIntClrR = crate::BitReader;
        #[doc = "Field `up_fifo_full_int_clr` writer - "]
        pub type UpFifoFullIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fifo_afull_int_clr` reader - "]
        pub type UpFifoAfullIntClrR = crate::BitReader;
        #[doc = "Field `up_fifo_afull_int_clr` writer - "]
        pub type UpFifoAfullIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fifo_empty_int_clr` reader - "]
        pub type UpFifoEmptyIntClrR = crate::BitReader;
        #[doc = "Field `up_fifo_empty_int_clr` writer - "]
        pub type UpFifoEmptyIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fifo_aempty_int_clr` reader - "]
        pub type UpFifoAemptyIntClrR = crate::BitReader;
        #[doc = "Field `up_fifo_aempty_int_clr` writer - "]
        pub type UpFifoAemptyIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `up_fifo_clr` reader - "]
        pub type UpFifoClrR = crate::BitReader;
        #[doc = "Field `up_fifo_clr` writer - "]
        pub type UpFifoClrW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn up_fifo_full_int_clr(&self) -> UpFifoFullIntClrR {
                UpFifoFullIntClrR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn up_fifo_afull_int_clr(&self) -> UpFifoAfullIntClrR {
                UpFifoAfullIntClrR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn up_fifo_empty_int_clr(&self) -> UpFifoEmptyIntClrR {
                UpFifoEmptyIntClrR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn up_fifo_aempty_int_clr(&self) -> UpFifoAemptyIntClrR {
                UpFifoAemptyIntClrR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn up_fifo_clr(&self) -> UpFifoClrR {
                UpFifoClrR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn up_fifo_full_int_clr(&mut self) -> UpFifoFullIntClrW<'_, UpFifoStClrSpec> {
                UpFifoFullIntClrW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn up_fifo_afull_int_clr(&mut self) -> UpFifoAfullIntClrW<'_, UpFifoStClrSpec> {
                UpFifoAfullIntClrW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn up_fifo_empty_int_clr(&mut self) -> UpFifoEmptyIntClrW<'_, UpFifoStClrSpec> {
                UpFifoEmptyIntClrW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn up_fifo_aempty_int_clr(&mut self) -> UpFifoAemptyIntClrW<'_, UpFifoStClrSpec> {
                UpFifoAemptyIntClrW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn up_fifo_clr(&mut self) -> UpFifoClrW<'_, UpFifoStClrSpec> {
                UpFifoClrW::new(self, 4)
            }
        }
        #[doc = "up_fifo_st_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`up_fifo_st_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`up_fifo_st_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UpFifoStClrSpec;
        impl crate::RegisterSpec for UpFifoStClrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`up_fifo_st_clr::R`](R) reader structure"]
        impl crate::Readable for UpFifoStClrSpec {}
        #[doc = "`write(|w| ..)` method takes [`up_fifo_st_clr::W`](W) writer structure"]
        impl crate::Writable for UpFifoStClrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets UP_FIFO_ST_CLR to value 0"]
        impl crate::Resettable for UpFifoStClrSpec {}
    }
}
#[doc = "Quadrature decoder (v150)"]
pub type Qdec = crate::Periph<qdec::RegisterBlock, 0x5200_0200>;
impl core::fmt::Debug for Qdec {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Qdec").finish()
    }
}
#[doc = "Quadrature decoder (v150)"]
pub mod qdec {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x04],
        qdec_task_start: QdecTaskStart,
        qdec_task_stop: QdecTaskStop,
        qdec_task_readclr_acc: QdecTaskReadclrAcc,
        qdec_task_rd_clr_acc: QdecTaskRdClrAcc,
        qdec_task_rd_clr_dbl: QdecTaskRdClrDbl,
        qdec_enable: QdecEnable,
        _reserved6: [u8; 0x04],
        qdec_event_int_sts: QdecEventIntSts,
        _reserved7: [u8; 0x10],
        qdec_int_en: QdecIntEn,
        qdec_int_clr: QdecIntClr,
        qdec_ledpol_data: QdecLedpolData,
        qdec_sampleper_data: QdecSampleperData,
        qdec_reporter_data: QdecReporterData,
        qdec_defen_data: QdecDefenData,
        qdec_ledpre_data: QdecLedpreData,
        qdec_sample_data: QdecSampleData,
        qdec_acc_data: QdecAccData,
        qdec_accdbl_data: QdecAccdblData,
        qdec_acc_read: QdecAccRead,
        qdec_accdbl_read: QdecAccdblRead,
        qdec_acc_event: QdecAccEvent,
        qdec_fpga_io_sel: QdecFpgaIoSel,
        _reserved21: [u8; 0x04],
        qdec_clk_ctl: QdecClkCtl,
        qdec_soft_rst: QdecSoftRst,
    }
    impl RegisterBlock {
        #[doc = "0x04 - qdec_task_start"]
        #[inline(always)]
        pub const fn qdec_task_start(&self) -> &QdecTaskStart {
            &self.qdec_task_start
        }
        #[doc = "0x08 - qdec_task_stop"]
        #[inline(always)]
        pub const fn qdec_task_stop(&self) -> &QdecTaskStop {
            &self.qdec_task_stop
        }
        #[doc = "0x0c - qdec_task_readclr_acc"]
        #[inline(always)]
        pub const fn qdec_task_readclr_acc(&self) -> &QdecTaskReadclrAcc {
            &self.qdec_task_readclr_acc
        }
        #[doc = "0x10 - qdec_task_rd_clr_acc"]
        #[inline(always)]
        pub const fn qdec_task_rd_clr_acc(&self) -> &QdecTaskRdClrAcc {
            &self.qdec_task_rd_clr_acc
        }
        #[doc = "0x14 - qdec_task_rd_clr_dbl"]
        #[inline(always)]
        pub const fn qdec_task_rd_clr_dbl(&self) -> &QdecTaskRdClrDbl {
            &self.qdec_task_rd_clr_dbl
        }
        #[doc = "0x18 - qdec_enable"]
        #[inline(always)]
        pub const fn qdec_enable(&self) -> &QdecEnable {
            &self.qdec_enable
        }
        #[doc = "0x20 - qdec_event_int_sts"]
        #[inline(always)]
        pub const fn qdec_event_int_sts(&self) -> &QdecEventIntSts {
            &self.qdec_event_int_sts
        }
        #[doc = "0x34 - qdec_int_en"]
        #[inline(always)]
        pub const fn qdec_int_en(&self) -> &QdecIntEn {
            &self.qdec_int_en
        }
        #[doc = "0x38 - qdec_int_clr"]
        #[inline(always)]
        pub const fn qdec_int_clr(&self) -> &QdecIntClr {
            &self.qdec_int_clr
        }
        #[doc = "0x3c - qdec_ledpol_data"]
        #[inline(always)]
        pub const fn qdec_ledpol_data(&self) -> &QdecLedpolData {
            &self.qdec_ledpol_data
        }
        #[doc = "0x40 - qdec_sampleper_data"]
        #[inline(always)]
        pub const fn qdec_sampleper_data(&self) -> &QdecSampleperData {
            &self.qdec_sampleper_data
        }
        #[doc = "0x44 - qdec_reporter_data"]
        #[inline(always)]
        pub const fn qdec_reporter_data(&self) -> &QdecReporterData {
            &self.qdec_reporter_data
        }
        #[doc = "0x48 - qdec_defen_data"]
        #[inline(always)]
        pub const fn qdec_defen_data(&self) -> &QdecDefenData {
            &self.qdec_defen_data
        }
        #[doc = "0x4c - qdec_ledpre_data"]
        #[inline(always)]
        pub const fn qdec_ledpre_data(&self) -> &QdecLedpreData {
            &self.qdec_ledpre_data
        }
        #[doc = "0x50 - qdec_sample_data"]
        #[inline(always)]
        pub const fn qdec_sample_data(&self) -> &QdecSampleData {
            &self.qdec_sample_data
        }
        #[doc = "0x54 - qdec_acc_data"]
        #[inline(always)]
        pub const fn qdec_acc_data(&self) -> &QdecAccData {
            &self.qdec_acc_data
        }
        #[doc = "0x58 - qdec_accdbl_data"]
        #[inline(always)]
        pub const fn qdec_accdbl_data(&self) -> &QdecAccdblData {
            &self.qdec_accdbl_data
        }
        #[doc = "0x5c - qdec_acc_read"]
        #[inline(always)]
        pub const fn qdec_acc_read(&self) -> &QdecAccRead {
            &self.qdec_acc_read
        }
        #[doc = "0x60 - qdec_accdbl_read"]
        #[inline(always)]
        pub const fn qdec_accdbl_read(&self) -> &QdecAccdblRead {
            &self.qdec_accdbl_read
        }
        #[doc = "0x64 - qdec_acc_event"]
        #[inline(always)]
        pub const fn qdec_acc_event(&self) -> &QdecAccEvent {
            &self.qdec_acc_event
        }
        #[doc = "0x68 - qdec_fpga_io_sel"]
        #[inline(always)]
        pub const fn qdec_fpga_io_sel(&self) -> &QdecFpgaIoSel {
            &self.qdec_fpga_io_sel
        }
        #[doc = "0x70 - qdec_clk_ctl"]
        #[inline(always)]
        pub const fn qdec_clk_ctl(&self) -> &QdecClkCtl {
            &self.qdec_clk_ctl
        }
        #[doc = "0x74 - qdec_soft_rst"]
        #[inline(always)]
        pub const fn qdec_soft_rst(&self) -> &QdecSoftRst {
            &self.qdec_soft_rst
        }
    }
    #[doc = "QDEC_TASK_START (rw) register accessor: qdec_task_start\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_start`] module"]
    #[doc(alias = "QDEC_TASK_START")]
    pub type QdecTaskStart = crate::Reg<qdec_task_start::QdecTaskStartSpec>;
    #[doc = "qdec_task_start"]
    pub mod qdec_task_start {
        #[doc = "Register `QDEC_TASK_START` reader"]
        pub type R = crate::R<QdecTaskStartSpec>;
        #[doc = "Register `QDEC_TASK_START` writer"]
        pub type W = crate::W<QdecTaskStartSpec>;
        #[doc = "Field `start` reader - "]
        pub type StartR = crate::BitReader;
        #[doc = "Field `start` writer - "]
        pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn start(&self) -> StartR {
                StartR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn start(&mut self) -> StartW<'_, QdecTaskStartSpec> {
                StartW::new(self, 0)
            }
        }
        #[doc = "qdec_task_start\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecTaskStartSpec;
        impl crate::RegisterSpec for QdecTaskStartSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_task_start::R`](R) reader structure"]
        impl crate::Readable for QdecTaskStartSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_task_start::W`](W) writer structure"]
        impl crate::Writable for QdecTaskStartSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_TASK_START to value 0"]
        impl crate::Resettable for QdecTaskStartSpec {}
    }
    #[doc = "QDEC_TASK_STOP (rw) register accessor: qdec_task_stop\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_stop::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_stop::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_stop`] module"]
    #[doc(alias = "QDEC_TASK_STOP")]
    pub type QdecTaskStop = crate::Reg<qdec_task_stop::QdecTaskStopSpec>;
    #[doc = "qdec_task_stop"]
    pub mod qdec_task_stop {
        #[doc = "Register `QDEC_TASK_STOP` reader"]
        pub type R = crate::R<QdecTaskStopSpec>;
        #[doc = "Register `QDEC_TASK_STOP` writer"]
        pub type W = crate::W<QdecTaskStopSpec>;
        #[doc = "Field `stop` reader - "]
        pub type StopR = crate::BitReader;
        #[doc = "Field `stop` writer - "]
        pub type StopW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn stop(&self) -> StopR {
                StopR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn stop(&mut self) -> StopW<'_, QdecTaskStopSpec> {
                StopW::new(self, 0)
            }
        }
        #[doc = "qdec_task_stop\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_stop::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_stop::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecTaskStopSpec;
        impl crate::RegisterSpec for QdecTaskStopSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_task_stop::R`](R) reader structure"]
        impl crate::Readable for QdecTaskStopSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_task_stop::W`](W) writer structure"]
        impl crate::Writable for QdecTaskStopSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_TASK_STOP to value 0"]
        impl crate::Resettable for QdecTaskStopSpec {}
    }
    #[doc = "QDEC_TASK_READCLR_ACC (rw) register accessor: qdec_task_readclr_acc\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_readclr_acc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_readclr_acc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_readclr_acc`] module"]
    #[doc(alias = "QDEC_TASK_READCLR_ACC")]
    pub type QdecTaskReadclrAcc = crate::Reg<qdec_task_readclr_acc::QdecTaskReadclrAccSpec>;
    #[doc = "qdec_task_readclr_acc"]
    pub mod qdec_task_readclr_acc {
        #[doc = "Register `QDEC_TASK_READCLR_ACC` reader"]
        pub type R = crate::R<QdecTaskReadclrAccSpec>;
        #[doc = "Register `QDEC_TASK_READCLR_ACC` writer"]
        pub type W = crate::W<QdecTaskReadclrAccSpec>;
        #[doc = "Field `readclr_acc` reader - "]
        pub type ReadclrAccR = crate::BitReader;
        #[doc = "Field `readclr_acc` writer - "]
        pub type ReadclrAccW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn readclr_acc(&self) -> ReadclrAccR {
                ReadclrAccR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn readclr_acc(&mut self) -> ReadclrAccW<'_, QdecTaskReadclrAccSpec> {
                ReadclrAccW::new(self, 0)
            }
        }
        #[doc = "qdec_task_readclr_acc\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_readclr_acc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_readclr_acc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecTaskReadclrAccSpec;
        impl crate::RegisterSpec for QdecTaskReadclrAccSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_task_readclr_acc::R`](R) reader structure"]
        impl crate::Readable for QdecTaskReadclrAccSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_task_readclr_acc::W`](W) writer structure"]
        impl crate::Writable for QdecTaskReadclrAccSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_TASK_READCLR_ACC to value 0"]
        impl crate::Resettable for QdecTaskReadclrAccSpec {}
    }
    #[doc = "QDEC_TASK_RD_CLR_ACC (rw) register accessor: qdec_task_rd_clr_acc\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_rd_clr_acc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_rd_clr_acc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_rd_clr_acc`] module"]
    #[doc(alias = "QDEC_TASK_RD_CLR_ACC")]
    pub type QdecTaskRdClrAcc = crate::Reg<qdec_task_rd_clr_acc::QdecTaskRdClrAccSpec>;
    #[doc = "qdec_task_rd_clr_acc"]
    pub mod qdec_task_rd_clr_acc {
        #[doc = "Register `QDEC_TASK_RD_CLR_ACC` reader"]
        pub type R = crate::R<QdecTaskRdClrAccSpec>;
        #[doc = "Register `QDEC_TASK_RD_CLR_ACC` writer"]
        pub type W = crate::W<QdecTaskRdClrAccSpec>;
        #[doc = "Field `rd_clr_acc` reader - "]
        pub type RdClrAccR = crate::BitReader;
        #[doc = "Field `rd_clr_acc` writer - "]
        pub type RdClrAccW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rd_clr_acc(&self) -> RdClrAccR {
                RdClrAccR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rd_clr_acc(&mut self) -> RdClrAccW<'_, QdecTaskRdClrAccSpec> {
                RdClrAccW::new(self, 0)
            }
        }
        #[doc = "qdec_task_rd_clr_acc\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_rd_clr_acc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_rd_clr_acc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecTaskRdClrAccSpec;
        impl crate::RegisterSpec for QdecTaskRdClrAccSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_task_rd_clr_acc::R`](R) reader structure"]
        impl crate::Readable for QdecTaskRdClrAccSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_task_rd_clr_acc::W`](W) writer structure"]
        impl crate::Writable for QdecTaskRdClrAccSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_TASK_RD_CLR_ACC to value 0"]
        impl crate::Resettable for QdecTaskRdClrAccSpec {}
    }
    #[doc = "QDEC_TASK_RD_CLR_DBL (rw) register accessor: qdec_task_rd_clr_dbl\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_rd_clr_dbl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_rd_clr_dbl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_task_rd_clr_dbl`] module"]
    #[doc(alias = "QDEC_TASK_RD_CLR_DBL")]
    pub type QdecTaskRdClrDbl = crate::Reg<qdec_task_rd_clr_dbl::QdecTaskRdClrDblSpec>;
    #[doc = "qdec_task_rd_clr_dbl"]
    pub mod qdec_task_rd_clr_dbl {
        #[doc = "Register `QDEC_TASK_RD_CLR_DBL` reader"]
        pub type R = crate::R<QdecTaskRdClrDblSpec>;
        #[doc = "Register `QDEC_TASK_RD_CLR_DBL` writer"]
        pub type W = crate::W<QdecTaskRdClrDblSpec>;
        #[doc = "Field `rd_clr_dbl` reader - "]
        pub type RdClrDblR = crate::BitReader;
        #[doc = "Field `rd_clr_dbl` writer - "]
        pub type RdClrDblW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rd_clr_dbl(&self) -> RdClrDblR {
                RdClrDblR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rd_clr_dbl(&mut self) -> RdClrDblW<'_, QdecTaskRdClrDblSpec> {
                RdClrDblW::new(self, 0)
            }
        }
        #[doc = "qdec_task_rd_clr_dbl\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_task_rd_clr_dbl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_task_rd_clr_dbl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecTaskRdClrDblSpec;
        impl crate::RegisterSpec for QdecTaskRdClrDblSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_task_rd_clr_dbl::R`](R) reader structure"]
        impl crate::Readable for QdecTaskRdClrDblSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_task_rd_clr_dbl::W`](W) writer structure"]
        impl crate::Writable for QdecTaskRdClrDblSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_TASK_RD_CLR_DBL to value 0"]
        impl crate::Resettable for QdecTaskRdClrDblSpec {}
    }
    #[doc = "QDEC_ENABLE (rw) register accessor: qdec_enable\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_enable`] module"]
    #[doc(alias = "QDEC_ENABLE")]
    pub type QdecEnable = crate::Reg<qdec_enable::QdecEnableSpec>;
    #[doc = "qdec_enable"]
    pub mod qdec_enable {
        #[doc = "Register `QDEC_ENABLE` reader"]
        pub type R = crate::R<QdecEnableSpec>;
        #[doc = "Register `QDEC_ENABLE` writer"]
        pub type W = crate::W<QdecEnableSpec>;
        #[doc = "Field `en` reader - "]
        pub type EnR = crate::BitReader;
        #[doc = "Field `en` writer - "]
        pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn en(&self) -> EnR {
                EnR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn en(&mut self) -> EnW<'_, QdecEnableSpec> {
                EnW::new(self, 0)
            }
        }
        #[doc = "qdec_enable\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecEnableSpec;
        impl crate::RegisterSpec for QdecEnableSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_enable::R`](R) reader structure"]
        impl crate::Readable for QdecEnableSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_enable::W`](W) writer structure"]
        impl crate::Writable for QdecEnableSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_ENABLE to value 0"]
        impl crate::Resettable for QdecEnableSpec {}
    }
    #[doc = "QDEC_EVENT_INT_STS (rw) register accessor: qdec_event_int_sts\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_event_int_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_event_int_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_event_int_sts`] module"]
    #[doc(alias = "QDEC_EVENT_INT_STS")]
    pub type QdecEventIntSts = crate::Reg<qdec_event_int_sts::QdecEventIntStsSpec>;
    #[doc = "qdec_event_int_sts"]
    pub mod qdec_event_int_sts {
        #[doc = "Register `QDEC_EVENT_INT_STS` reader"]
        pub type R = crate::R<QdecEventIntStsSpec>;
        #[doc = "Register `QDEC_EVENT_INT_STS` writer"]
        pub type W = crate::W<QdecEventIntStsSpec>;
        #[doc = "Field `events_stopped` reader - "]
        pub type EventsStoppedR = crate::BitReader;
        #[doc = "Field `events_stopped` writer - "]
        pub type EventsStoppedW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `acc_rdy` reader - "]
        pub type AccRdyR = crate::BitReader;
        #[doc = "Field `acc_rdy` writer - "]
        pub type AccRdyW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dbl_rdy` reader - "]
        pub type DblRdyR = crate::BitReader;
        #[doc = "Field `dbl_rdy` writer - "]
        pub type DblRdyW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `report_rdy` reader - "]
        pub type ReportRdyR = crate::BitReader;
        #[doc = "Field `report_rdy` writer - "]
        pub type ReportRdyW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `sample_rdy` reader - "]
        pub type SampleRdyR = crate::BitReader;
        #[doc = "Field `sample_rdy` writer - "]
        pub type SampleRdyW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn events_stopped(&self) -> EventsStoppedR {
                EventsStoppedR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn acc_rdy(&self) -> AccRdyR {
                AccRdyR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn dbl_rdy(&self) -> DblRdyR {
                DblRdyR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn report_rdy(&self) -> ReportRdyR {
                ReportRdyR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn sample_rdy(&self) -> SampleRdyR {
                SampleRdyR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn events_stopped(&mut self) -> EventsStoppedW<'_, QdecEventIntStsSpec> {
                EventsStoppedW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn acc_rdy(&mut self) -> AccRdyW<'_, QdecEventIntStsSpec> {
                AccRdyW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn dbl_rdy(&mut self) -> DblRdyW<'_, QdecEventIntStsSpec> {
                DblRdyW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn report_rdy(&mut self) -> ReportRdyW<'_, QdecEventIntStsSpec> {
                ReportRdyW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn sample_rdy(&mut self) -> SampleRdyW<'_, QdecEventIntStsSpec> {
                SampleRdyW::new(self, 4)
            }
        }
        #[doc = "qdec_event_int_sts\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_event_int_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_event_int_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecEventIntStsSpec;
        impl crate::RegisterSpec for QdecEventIntStsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_event_int_sts::R`](R) reader structure"]
        impl crate::Readable for QdecEventIntStsSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_event_int_sts::W`](W) writer structure"]
        impl crate::Writable for QdecEventIntStsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_EVENT_INT_STS to value 0"]
        impl crate::Resettable for QdecEventIntStsSpec {}
    }
    #[doc = "QDEC_INT_EN (rw) register accessor: qdec_int_en\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_int_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_int_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_int_en`] module"]
    #[doc(alias = "QDEC_INT_EN")]
    pub type QdecIntEn = crate::Reg<qdec_int_en::QdecIntEnSpec>;
    #[doc = "qdec_int_en"]
    pub mod qdec_int_en {
        #[doc = "Register `QDEC_INT_EN` reader"]
        pub type R = crate::R<QdecIntEnSpec>;
        #[doc = "Register `QDEC_INT_EN` writer"]
        pub type W = crate::W<QdecIntEnSpec>;
        #[doc = "Field `stopped` reader - "]
        pub type StoppedR = crate::BitReader;
        #[doc = "Field `stopped` writer - "]
        pub type StoppedW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `acc_en` reader - "]
        pub type AccEnR = crate::BitReader;
        #[doc = "Field `acc_en` writer - "]
        pub type AccEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dbl_en` reader - "]
        pub type DblEnR = crate::BitReader;
        #[doc = "Field `dbl_en` writer - "]
        pub type DblEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `report_en` reader - "]
        pub type ReportEnR = crate::BitReader;
        #[doc = "Field `report_en` writer - "]
        pub type ReportEnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `sample_en` reader - "]
        pub type SampleEnR = crate::BitReader;
        #[doc = "Field `sample_en` writer - "]
        pub type SampleEnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn stopped(&self) -> StoppedR {
                StoppedR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn acc_en(&self) -> AccEnR {
                AccEnR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn dbl_en(&self) -> DblEnR {
                DblEnR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn report_en(&self) -> ReportEnR {
                ReportEnR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn sample_en(&self) -> SampleEnR {
                SampleEnR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn stopped(&mut self) -> StoppedW<'_, QdecIntEnSpec> {
                StoppedW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn acc_en(&mut self) -> AccEnW<'_, QdecIntEnSpec> {
                AccEnW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn dbl_en(&mut self) -> DblEnW<'_, QdecIntEnSpec> {
                DblEnW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn report_en(&mut self) -> ReportEnW<'_, QdecIntEnSpec> {
                ReportEnW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn sample_en(&mut self) -> SampleEnW<'_, QdecIntEnSpec> {
                SampleEnW::new(self, 4)
            }
        }
        #[doc = "qdec_int_en\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_int_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_int_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecIntEnSpec;
        impl crate::RegisterSpec for QdecIntEnSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_int_en::R`](R) reader structure"]
        impl crate::Readable for QdecIntEnSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_int_en::W`](W) writer structure"]
        impl crate::Writable for QdecIntEnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_INT_EN to value 0"]
        impl crate::Resettable for QdecIntEnSpec {}
    }
    #[doc = "QDEC_INT_CLR (rw) register accessor: qdec_int_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_int_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_int_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_int_clr`] module"]
    #[doc(alias = "QDEC_INT_CLR")]
    pub type QdecIntClr = crate::Reg<qdec_int_clr::QdecIntClrSpec>;
    #[doc = "qdec_int_clr"]
    pub mod qdec_int_clr {
        #[doc = "Register `QDEC_INT_CLR` reader"]
        pub type R = crate::R<QdecIntClrSpec>;
        #[doc = "Register `QDEC_INT_CLR` writer"]
        pub type W = crate::W<QdecIntClrSpec>;
        #[doc = "Field `stop_int_clr` reader - "]
        pub type StopIntClrR = crate::BitReader;
        #[doc = "Field `stop_int_clr` writer - "]
        pub type StopIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `acc_clr` reader - "]
        pub type AccClrR = crate::BitReader;
        #[doc = "Field `acc_clr` writer - "]
        pub type AccClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `dbl_clr` reader - "]
        pub type DblClrR = crate::BitReader;
        #[doc = "Field `dbl_clr` writer - "]
        pub type DblClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `report_clr` reader - "]
        pub type ReportClrR = crate::BitReader;
        #[doc = "Field `report_clr` writer - "]
        pub type ReportClrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `sample_clr` reader - "]
        pub type SampleClrR = crate::BitReader;
        #[doc = "Field `sample_clr` writer - "]
        pub type SampleClrW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn stop_int_clr(&self) -> StopIntClrR {
                StopIntClrR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn acc_clr(&self) -> AccClrR {
                AccClrR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn dbl_clr(&self) -> DblClrR {
                DblClrR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn report_clr(&self) -> ReportClrR {
                ReportClrR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn sample_clr(&self) -> SampleClrR {
                SampleClrR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn stop_int_clr(&mut self) -> StopIntClrW<'_, QdecIntClrSpec> {
                StopIntClrW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn acc_clr(&mut self) -> AccClrW<'_, QdecIntClrSpec> {
                AccClrW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn dbl_clr(&mut self) -> DblClrW<'_, QdecIntClrSpec> {
                DblClrW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn report_clr(&mut self) -> ReportClrW<'_, QdecIntClrSpec> {
                ReportClrW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn sample_clr(&mut self) -> SampleClrW<'_, QdecIntClrSpec> {
                SampleClrW::new(self, 4)
            }
        }
        #[doc = "qdec_int_clr\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecIntClrSpec;
        impl crate::RegisterSpec for QdecIntClrSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_int_clr::R`](R) reader structure"]
        impl crate::Readable for QdecIntClrSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_int_clr::W`](W) writer structure"]
        impl crate::Writable for QdecIntClrSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_INT_CLR to value 0"]
        impl crate::Resettable for QdecIntClrSpec {}
    }
    #[doc = "QDEC_LEDPOL_DATA (rw) register accessor: qdec_ledpol_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_ledpol_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_ledpol_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_ledpol_data`] module"]
    #[doc(alias = "QDEC_LEDPOL_DATA")]
    pub type QdecLedpolData = crate::Reg<qdec_ledpol_data::QdecLedpolDataSpec>;
    #[doc = "qdec_ledpol_data"]
    pub mod qdec_ledpol_data {
        #[doc = "Register `QDEC_LEDPOL_DATA` reader"]
        pub type R = crate::R<QdecLedpolDataSpec>;
        #[doc = "Register `QDEC_LEDPOL_DATA` writer"]
        pub type W = crate::W<QdecLedpolDataSpec>;
        #[doc = "Field `pol` reader - "]
        pub type PolR = crate::BitReader;
        #[doc = "Field `pol` writer - "]
        pub type PolW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `en` reader - "]
        pub type EnR = crate::BitReader;
        #[doc = "Field `en` writer - "]
        pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn pol(&self) -> PolR {
                PolR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn en(&self) -> EnR {
                EnR::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn pol(&mut self) -> PolW<'_, QdecLedpolDataSpec> {
                PolW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn en(&mut self) -> EnW<'_, QdecLedpolDataSpec> {
                EnW::new(self, 1)
            }
        }
        #[doc = "qdec_ledpol_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_ledpol_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_ledpol_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecLedpolDataSpec;
        impl crate::RegisterSpec for QdecLedpolDataSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_ledpol_data::R`](R) reader structure"]
        impl crate::Readable for QdecLedpolDataSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_ledpol_data::W`](W) writer structure"]
        impl crate::Writable for QdecLedpolDataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_LEDPOL_DATA to value 0"]
        impl crate::Resettable for QdecLedpolDataSpec {}
    }
    #[doc = "QDEC_SAMPLEPER_DATA (rw) register accessor: qdec_sampleper_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_sampleper_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_sampleper_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_sampleper_data`] module"]
    #[doc(alias = "QDEC_SAMPLEPER_DATA")]
    pub type QdecSampleperData = crate::Reg<qdec_sampleper_data::QdecSampleperDataSpec>;
    #[doc = "qdec_sampleper_data"]
    pub mod qdec_sampleper_data {
        #[doc = "Register `QDEC_SAMPLEPER_DATA` reader"]
        pub type R = crate::R<QdecSampleperDataSpec>;
        #[doc = "Register `QDEC_SAMPLEPER_DATA` writer"]
        pub type W = crate::W<QdecSampleperDataSpec>;
        #[doc = "Field `period` reader - "]
        pub type PeriodR = crate::FieldReader;
        #[doc = "Field `period` writer - "]
        pub type PeriodW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `clk_freq` reader - "]
        pub type ClkFreqR = crate::BitReader;
        #[doc = "Field `clk_freq` writer - "]
        pub type ClkFreqW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn period(&self) -> PeriodR {
                PeriodR::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn clk_freq(&self) -> ClkFreqR {
                ClkFreqR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn period(&mut self) -> PeriodW<'_, QdecSampleperDataSpec> {
                PeriodW::new(self, 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn clk_freq(&mut self) -> ClkFreqW<'_, QdecSampleperDataSpec> {
                ClkFreqW::new(self, 4)
            }
        }
        #[doc = "qdec_sampleper_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_sampleper_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_sampleper_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecSampleperDataSpec;
        impl crate::RegisterSpec for QdecSampleperDataSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_sampleper_data::R`](R) reader structure"]
        impl crate::Readable for QdecSampleperDataSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_sampleper_data::W`](W) writer structure"]
        impl crate::Writable for QdecSampleperDataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_SAMPLEPER_DATA to value 0"]
        impl crate::Resettable for QdecSampleperDataSpec {}
    }
    #[doc = "QDEC_REPORTER_DATA (rw) register accessor: qdec_reporter_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_reporter_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_reporter_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_reporter_data`] module"]
    #[doc(alias = "QDEC_REPORTER_DATA")]
    pub type QdecReporterData = crate::Reg<qdec_reporter_data::QdecReporterDataSpec>;
    #[doc = "qdec_reporter_data"]
    pub mod qdec_reporter_data {
        #[doc = "Register `QDEC_REPORTER_DATA` reader"]
        pub type R = crate::R<QdecReporterDataSpec>;
        #[doc = "Register `QDEC_REPORTER_DATA` writer"]
        pub type W = crate::W<QdecReporterDataSpec>;
        #[doc = "Field `samlple_repo_val` reader - "]
        pub type SamlpleRepoValR = crate::FieldReader;
        #[doc = "Field `samlple_repo_val` writer - "]
        pub type SamlpleRepoValW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn samlple_repo_val(&self) -> SamlpleRepoValR {
                SamlpleRepoValR::new((self.bits & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn samlple_repo_val(&mut self) -> SamlpleRepoValW<'_, QdecReporterDataSpec> {
                SamlpleRepoValW::new(self, 0)
            }
        }
        #[doc = "qdec_reporter_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_reporter_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_reporter_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecReporterDataSpec;
        impl crate::RegisterSpec for QdecReporterDataSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_reporter_data::R`](R) reader structure"]
        impl crate::Readable for QdecReporterDataSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_reporter_data::W`](W) writer structure"]
        impl crate::Writable for QdecReporterDataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_REPORTER_DATA to value 0"]
        impl crate::Resettable for QdecReporterDataSpec {}
    }
    #[doc = "QDEC_DEFEN_DATA (rw) register accessor: qdec_defen_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_defen_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_defen_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_defen_data`] module"]
    #[doc(alias = "QDEC_DEFEN_DATA")]
    pub type QdecDefenData = crate::Reg<qdec_defen_data::QdecDefenDataSpec>;
    #[doc = "qdec_defen_data"]
    pub mod qdec_defen_data {
        #[doc = "Register `QDEC_DEFEN_DATA` reader"]
        pub type R = crate::R<QdecDefenDataSpec>;
        #[doc = "Register `QDEC_DEFEN_DATA` writer"]
        pub type W = crate::W<QdecDefenDataSpec>;
        #[doc = "Field `en` reader - "]
        pub type EnR = crate::BitReader;
        #[doc = "Field `en` writer - "]
        pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `defen_num` reader - "]
        pub type DefenNumR = crate::FieldReader;
        #[doc = "Field `defen_num` writer - "]
        pub type DefenNumW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn en(&self) -> EnR {
                EnR::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 4:6"]
            #[inline(always)]
            pub fn defen_num(&self) -> DefenNumR {
                DefenNumR::new(((self.bits >> 4) & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn en(&mut self) -> EnW<'_, QdecDefenDataSpec> {
                EnW::new(self, 0)
            }
            #[doc = "Bits 4:6"]
            #[inline(always)]
            pub fn defen_num(&mut self) -> DefenNumW<'_, QdecDefenDataSpec> {
                DefenNumW::new(self, 4)
            }
        }
        #[doc = "qdec_defen_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_defen_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_defen_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecDefenDataSpec;
        impl crate::RegisterSpec for QdecDefenDataSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_defen_data::R`](R) reader structure"]
        impl crate::Readable for QdecDefenDataSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_defen_data::W`](W) writer structure"]
        impl crate::Writable for QdecDefenDataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_DEFEN_DATA to value 0"]
        impl crate::Resettable for QdecDefenDataSpec {}
    }
    #[doc = "QDEC_LEDPRE_DATA (rw) register accessor: qdec_ledpre_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_ledpre_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_ledpre_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_ledpre_data`] module"]
    #[doc(alias = "QDEC_LEDPRE_DATA")]
    pub type QdecLedpreData = crate::Reg<qdec_ledpre_data::QdecLedpreDataSpec>;
    #[doc = "qdec_ledpre_data"]
    pub mod qdec_ledpre_data {
        #[doc = "Register `QDEC_LEDPRE_DATA` reader"]
        pub type R = crate::R<QdecLedpreDataSpec>;
        #[doc = "Register `QDEC_LEDPRE_DATA` writer"]
        pub type W = crate::W<QdecLedpreDataSpec>;
        #[doc = "Field `led_pre` reader - "]
        pub type LedPreR = crate::FieldReader<u16>;
        #[doc = "Field `led_pre` writer - "]
        pub type LedPreW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
        impl R {
            #[doc = "Bits 0:9"]
            #[inline(always)]
            pub fn led_pre(&self) -> LedPreR {
                LedPreR::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:9"]
            #[inline(always)]
            pub fn led_pre(&mut self) -> LedPreW<'_, QdecLedpreDataSpec> {
                LedPreW::new(self, 0)
            }
        }
        #[doc = "qdec_ledpre_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_ledpre_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_ledpre_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecLedpreDataSpec;
        impl crate::RegisterSpec for QdecLedpreDataSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_ledpre_data::R`](R) reader structure"]
        impl crate::Readable for QdecLedpreDataSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_ledpre_data::W`](W) writer structure"]
        impl crate::Writable for QdecLedpreDataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_LEDPRE_DATA to value 0"]
        impl crate::Resettable for QdecLedpreDataSpec {}
    }
    #[doc = "QDEC_SAMPLE_DATA (rw) register accessor: qdec_sample_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_sample_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_sample_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_sample_data`] module"]
    #[doc(alias = "QDEC_SAMPLE_DATA")]
    pub type QdecSampleData = crate::Reg<qdec_sample_data::QdecSampleDataSpec>;
    #[doc = "qdec_sample_data"]
    pub mod qdec_sample_data {
        #[doc = "Register `QDEC_SAMPLE_DATA` reader"]
        pub type R = crate::R<QdecSampleDataSpec>;
        #[doc = "Register `QDEC_SAMPLE_DATA` writer"]
        pub type W = crate::W<QdecSampleDataSpec>;
        #[doc = "Field `sample_val` reader - "]
        pub type SampleValR = crate::FieldReader;
        #[doc = "Field `sample_val` writer - "]
        pub type SampleValW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn sample_val(&self) -> SampleValR {
                SampleValR::new((self.bits & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn sample_val(&mut self) -> SampleValW<'_, QdecSampleDataSpec> {
                SampleValW::new(self, 0)
            }
        }
        #[doc = "qdec_sample_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_sample_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_sample_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecSampleDataSpec;
        impl crate::RegisterSpec for QdecSampleDataSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_sample_data::R`](R) reader structure"]
        impl crate::Readable for QdecSampleDataSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_sample_data::W`](W) writer structure"]
        impl crate::Writable for QdecSampleDataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_SAMPLE_DATA to value 0"]
        impl crate::Resettable for QdecSampleDataSpec {}
    }
    #[doc = "QDEC_ACC_DATA (rw) register accessor: qdec_acc_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_acc_data`] module"]
    #[doc(alias = "QDEC_ACC_DATA")]
    pub type QdecAccData = crate::Reg<qdec_acc_data::QdecAccDataSpec>;
    #[doc = "qdec_acc_data"]
    pub mod qdec_acc_data {
        #[doc = "Register `QDEC_ACC_DATA` reader"]
        pub type R = crate::R<QdecAccDataSpec>;
        #[doc = "Register `QDEC_ACC_DATA` writer"]
        pub type W = crate::W<QdecAccDataSpec>;
        #[doc = "Field `acc_rd_val` reader - "]
        pub type AccRdValR = crate::FieldReader<u16>;
        #[doc = "Field `acc_rd_val` writer - "]
        pub type AccRdValW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn acc_rd_val(&self) -> AccRdValR {
                AccRdValR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn acc_rd_val(&mut self) -> AccRdValW<'_, QdecAccDataSpec> {
                AccRdValW::new(self, 0)
            }
        }
        #[doc = "qdec_acc_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecAccDataSpec;
        impl crate::RegisterSpec for QdecAccDataSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_acc_data::R`](R) reader structure"]
        impl crate::Readable for QdecAccDataSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_acc_data::W`](W) writer structure"]
        impl crate::Writable for QdecAccDataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_ACC_DATA to value 0"]
        impl crate::Resettable for QdecAccDataSpec {}
    }
    #[doc = "QDEC_ACCDBL_DATA (rw) register accessor: qdec_accdbl_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_accdbl_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_accdbl_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_accdbl_data`] module"]
    #[doc(alias = "QDEC_ACCDBL_DATA")]
    pub type QdecAccdblData = crate::Reg<qdec_accdbl_data::QdecAccdblDataSpec>;
    #[doc = "qdec_accdbl_data"]
    pub mod qdec_accdbl_data {
        #[doc = "Register `QDEC_ACCDBL_DATA` reader"]
        pub type R = crate::R<QdecAccdblDataSpec>;
        #[doc = "Register `QDEC_ACCDBL_DATA` writer"]
        pub type W = crate::W<QdecAccdblDataSpec>;
        #[doc = "Field `dbl_rd_val` reader - "]
        pub type DblRdValR = crate::FieldReader;
        #[doc = "Field `dbl_rd_val` writer - "]
        pub type DblRdValW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn dbl_rd_val(&self) -> DblRdValR {
                DblRdValR::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn dbl_rd_val(&mut self) -> DblRdValW<'_, QdecAccdblDataSpec> {
                DblRdValW::new(self, 0)
            }
        }
        #[doc = "qdec_accdbl_data\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_accdbl_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_accdbl_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecAccdblDataSpec;
        impl crate::RegisterSpec for QdecAccdblDataSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_accdbl_data::R`](R) reader structure"]
        impl crate::Readable for QdecAccdblDataSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_accdbl_data::W`](W) writer structure"]
        impl crate::Writable for QdecAccdblDataSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_ACCDBL_DATA to value 0"]
        impl crate::Resettable for QdecAccdblDataSpec {}
    }
    #[doc = "QDEC_ACC_READ (rw) register accessor: qdec_acc_read\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_read::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_read::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_acc_read`] module"]
    #[doc(alias = "QDEC_ACC_READ")]
    pub type QdecAccRead = crate::Reg<qdec_acc_read::QdecAccReadSpec>;
    #[doc = "qdec_acc_read"]
    pub mod qdec_acc_read {
        #[doc = "Register `QDEC_ACC_READ` reader"]
        pub type R = crate::R<QdecAccReadSpec>;
        #[doc = "Register `QDEC_ACC_READ` writer"]
        pub type W = crate::W<QdecAccReadSpec>;
        #[doc = "Field `acc_rd_val_shadow` reader - "]
        pub type AccRdValShadowR = crate::FieldReader<u16>;
        #[doc = "Field `acc_rd_val_shadow` writer - "]
        pub type AccRdValShadowW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn acc_rd_val_shadow(&self) -> AccRdValShadowR {
                AccRdValShadowR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn acc_rd_val_shadow(&mut self) -> AccRdValShadowW<'_, QdecAccReadSpec> {
                AccRdValShadowW::new(self, 0)
            }
        }
        #[doc = "qdec_acc_read\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_read::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_read::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecAccReadSpec;
        impl crate::RegisterSpec for QdecAccReadSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_acc_read::R`](R) reader structure"]
        impl crate::Readable for QdecAccReadSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_acc_read::W`](W) writer structure"]
        impl crate::Writable for QdecAccReadSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_ACC_READ to value 0"]
        impl crate::Resettable for QdecAccReadSpec {}
    }
    #[doc = "QDEC_ACCDBL_READ (rw) register accessor: qdec_accdbl_read\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_accdbl_read::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_accdbl_read::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_accdbl_read`] module"]
    #[doc(alias = "QDEC_ACCDBL_READ")]
    pub type QdecAccdblRead = crate::Reg<qdec_accdbl_read::QdecAccdblReadSpec>;
    #[doc = "qdec_accdbl_read"]
    pub mod qdec_accdbl_read {
        #[doc = "Register `QDEC_ACCDBL_READ` reader"]
        pub type R = crate::R<QdecAccdblReadSpec>;
        #[doc = "Register `QDEC_ACCDBL_READ` writer"]
        pub type W = crate::W<QdecAccdblReadSpec>;
        #[doc = "Field `dbl_rd_val_shadow` reader - "]
        pub type DblRdValShadowR = crate::FieldReader;
        #[doc = "Field `dbl_rd_val_shadow` writer - "]
        pub type DblRdValShadowW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn dbl_rd_val_shadow(&self) -> DblRdValShadowR {
                DblRdValShadowR::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn dbl_rd_val_shadow(&mut self) -> DblRdValShadowW<'_, QdecAccdblReadSpec> {
                DblRdValShadowW::new(self, 0)
            }
        }
        #[doc = "qdec_accdbl_read\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_accdbl_read::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_accdbl_read::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecAccdblReadSpec;
        impl crate::RegisterSpec for QdecAccdblReadSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_accdbl_read::R`](R) reader structure"]
        impl crate::Readable for QdecAccdblReadSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_accdbl_read::W`](W) writer structure"]
        impl crate::Writable for QdecAccdblReadSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_ACCDBL_READ to value 0"]
        impl crate::Resettable for QdecAccdblReadSpec {}
    }
    #[doc = "QDEC_ACC_EVENT (rw) register accessor: qdec_acc_event\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_event::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_event::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_acc_event`] module"]
    #[doc(alias = "QDEC_ACC_EVENT")]
    pub type QdecAccEvent = crate::Reg<qdec_acc_event::QdecAccEventSpec>;
    #[doc = "qdec_acc_event"]
    pub mod qdec_acc_event {
        #[doc = "Register `QDEC_ACC_EVENT` reader"]
        pub type R = crate::R<QdecAccEventSpec>;
        #[doc = "Register `QDEC_ACC_EVENT` writer"]
        pub type W = crate::W<QdecAccEventSpec>;
        #[doc = "Field `acc_event_cnt` reader - "]
        pub type AccEventCntR = crate::FieldReader<u16>;
        #[doc = "Field `acc_event_cnt` writer - "]
        pub type AccEventCntW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        impl R {
            #[doc = "Bits 0:8"]
            #[inline(always)]
            pub fn acc_event_cnt(&self) -> AccEventCntR {
                AccEventCntR::new((self.bits & 0x01ff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:8"]
            #[inline(always)]
            pub fn acc_event_cnt(&mut self) -> AccEventCntW<'_, QdecAccEventSpec> {
                AccEventCntW::new(self, 0)
            }
        }
        #[doc = "qdec_acc_event\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_acc_event::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_acc_event::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecAccEventSpec;
        impl crate::RegisterSpec for QdecAccEventSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_acc_event::R`](R) reader structure"]
        impl crate::Readable for QdecAccEventSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_acc_event::W`](W) writer structure"]
        impl crate::Writable for QdecAccEventSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_ACC_EVENT to value 0"]
        impl crate::Resettable for QdecAccEventSpec {}
    }
    #[doc = "QDEC_FPGA_IO_SEL (rw) register accessor: qdec_fpga_io_sel\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_fpga_io_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_fpga_io_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_fpga_io_sel`] module"]
    #[doc(alias = "QDEC_FPGA_IO_SEL")]
    pub type QdecFpgaIoSel = crate::Reg<qdec_fpga_io_sel::QdecFpgaIoSelSpec>;
    #[doc = "qdec_fpga_io_sel"]
    pub mod qdec_fpga_io_sel {
        #[doc = "Register `QDEC_FPGA_IO_SEL` reader"]
        pub type R = crate::R<QdecFpgaIoSelSpec>;
        #[doc = "Register `QDEC_FPGA_IO_SEL` writer"]
        pub type W = crate::W<QdecFpgaIoSelSpec>;
        #[doc = "Field `fpga_io_src` reader - "]
        pub type FpgaIoSrcR = crate::BitReader;
        #[doc = "Field `fpga_io_src` writer - "]
        pub type FpgaIoSrcW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn fpga_io_src(&self) -> FpgaIoSrcR {
                FpgaIoSrcR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn fpga_io_src(&mut self) -> FpgaIoSrcW<'_, QdecFpgaIoSelSpec> {
                FpgaIoSrcW::new(self, 0)
            }
        }
        #[doc = "qdec_fpga_io_sel\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_fpga_io_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_fpga_io_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecFpgaIoSelSpec;
        impl crate::RegisterSpec for QdecFpgaIoSelSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_fpga_io_sel::R`](R) reader structure"]
        impl crate::Readable for QdecFpgaIoSelSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_fpga_io_sel::W`](W) writer structure"]
        impl crate::Writable for QdecFpgaIoSelSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_FPGA_IO_SEL to value 0"]
        impl crate::Resettable for QdecFpgaIoSelSpec {}
    }
    #[doc = "QDEC_CLK_CTL (rw) register accessor: qdec_clk_ctl\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_clk_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_clk_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_clk_ctl`] module"]
    #[doc(alias = "QDEC_CLK_CTL")]
    pub type QdecClkCtl = crate::Reg<qdec_clk_ctl::QdecClkCtlSpec>;
    #[doc = "qdec_clk_ctl"]
    pub mod qdec_clk_ctl {
        #[doc = "Register `QDEC_CLK_CTL` reader"]
        pub type R = crate::R<QdecClkCtlSpec>;
        #[doc = "Register `QDEC_CLK_CTL` writer"]
        pub type W = crate::W<QdecClkCtlSpec>;
        #[doc = "Field `sel` reader - "]
        pub type SelR = crate::BitReader;
        #[doc = "Field `sel` writer - "]
        pub type SelW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `en` reader - "]
        pub type EnR = crate::BitReader;
        #[doc = "Field `en` writer - "]
        pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn sel(&self) -> SelR {
                SelR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn en(&self) -> EnR {
                EnR::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn sel(&mut self) -> SelW<'_, QdecClkCtlSpec> {
                SelW::new(self, 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn en(&mut self) -> EnW<'_, QdecClkCtlSpec> {
                EnW::new(self, 4)
            }
        }
        #[doc = "qdec_clk_ctl\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_clk_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_clk_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecClkCtlSpec;
        impl crate::RegisterSpec for QdecClkCtlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_clk_ctl::R`](R) reader structure"]
        impl crate::Readable for QdecClkCtlSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_clk_ctl::W`](W) writer structure"]
        impl crate::Writable for QdecClkCtlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_CLK_CTL to value 0"]
        impl crate::Resettable for QdecClkCtlSpec {}
    }
    #[doc = "QDEC_SOFT_RST (rw) register accessor: qdec_soft_rst\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_soft_rst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_soft_rst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdec_soft_rst`] module"]
    #[doc(alias = "QDEC_SOFT_RST")]
    pub type QdecSoftRst = crate::Reg<qdec_soft_rst::QdecSoftRstSpec>;
    #[doc = "qdec_soft_rst"]
    pub mod qdec_soft_rst {
        #[doc = "Register `QDEC_SOFT_RST` reader"]
        pub type R = crate::R<QdecSoftRstSpec>;
        #[doc = "Register `QDEC_SOFT_RST` writer"]
        pub type W = crate::W<QdecSoftRstSpec>;
        #[doc = "Field `soft_rst` reader - "]
        pub type SoftRstR = crate::BitReader;
        #[doc = "Field `soft_rst` writer - "]
        pub type SoftRstW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn soft_rst(&self) -> SoftRstR {
                SoftRstR::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn soft_rst(&mut self) -> SoftRstW<'_, QdecSoftRstSpec> {
                SoftRstW::new(self, 0)
            }
        }
        #[doc = "qdec_soft_rst\n\nYou can [`read`](crate::Reg::read) this register and get [`qdec_soft_rst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdec_soft_rst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QdecSoftRstSpec;
        impl crate::RegisterSpec for QdecSoftRstSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qdec_soft_rst::R`](R) reader structure"]
        impl crate::Readable for QdecSoftRstSpec {}
        #[doc = "`write(|w| ..)` method takes [`qdec_soft_rst::W`](W) writer structure"]
        impl crate::Writable for QdecSoftRstSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets QDEC_SOFT_RST to value 0"]
        impl crate::Resettable for QdecSoftRstSpec {}
    }
}
#[doc = "USB 2.0 OTG controller (Synopsys DWC OTG, device-controller base)"]
pub type Usb = crate::Periph<usb::RegisterBlock, 0x5800_0000>;
impl core::fmt::Debug for Usb {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Usb").finish()
    }
}
#[doc = "USB 2.0 OTG controller (Synopsys DWC OTG, device-controller base)"]
pub mod usb {
    #[repr(C)]
    #[doc = "Register block"]
    pub struct RegisterBlock {
        gotgctl: Gotgctl,
        gotgint: Gotgint,
        gahbcfg: Gahbcfg,
        gusbcfg: Gusbcfg,
        grstctl: Grstctl,
        gintsts: Gintsts,
        gintmsk: Gintmsk,
        grxstsrd: Grxstsrd,
        grxstspd: Grxstspd,
        grxfsiz: Grxfsiz,
        gnptxfsiz: Gnptxfsiz,
        gnptxsts: Gnptxsts,
        gi2cctl: Gi2cctl,
        gpvndctl: Gpvndctl,
        ggpio: Ggpio,
        guid: Guid,
        gsnpsid: Gsnpsid,
        ghwcfg1: Ghwcfg1,
        ghwcfg2: Ghwcfg2,
        ghwcfg3: Ghwcfg3,
        ghwcfg4: Ghwcfg4,
        glpmcfg: Glpmcfg,
        gpwrdn: Gpwrdn,
        gdfifocfg: Gdfifocfg,
        gadpctl: Gadpctl,
        _reserved25: [u8; 0x9c],
        hptxfsiz: Hptxfsiz,
        _reserved26: [u8; 0x02fc],
        hcfg: Hcfg,
        hfir: Hfir,
        hfnum: Hfnum,
        _reserved29: [u8; 0x04],
        hptxsts: Hptxsts,
        haint: Haint,
        haintmsk: Haintmsk,
        _reserved32: [u8; 0x24],
        hprt: Hprt,
        _reserved33: [u8; 0x03bc],
        dcfg: Dcfg,
        dctl: Dctl,
        dsts: Dsts,
        _reserved36: [u8; 0x04],
        diepmsk: Diepmsk,
        doepmsk: Doepmsk,
        daint: Daint,
        daintmsk: Daintmsk,
        dtknqr1: Dtknqr1,
        dtknqr2: Dtknqr2,
        dvbusdis: Dvbusdis,
        dvbuspulse: Dvbuspulse,
        dthrctl: Dthrctl,
        dtknqr4: Dtknqr4,
        deachint: Deachint,
        deachintmsk: Deachintmsk,
        _reserved48: [u8; 0x05c0],
        pcgcctl: Pcgcctl,
    }
    impl RegisterBlock {
        #[doc = "0x00 - DOTG_GOTGCTL"]
        #[inline(always)]
        pub const fn gotgctl(&self) -> &Gotgctl {
            &self.gotgctl
        }
        #[doc = "0x04 - DOTG_GOTGINT"]
        #[inline(always)]
        pub const fn gotgint(&self) -> &Gotgint {
            &self.gotgint
        }
        #[doc = "0x08 - DOTG_GAHBCFG"]
        #[inline(always)]
        pub const fn gahbcfg(&self) -> &Gahbcfg {
            &self.gahbcfg
        }
        #[doc = "0x0c - DOTG_GUSBCFG"]
        #[inline(always)]
        pub const fn gusbcfg(&self) -> &Gusbcfg {
            &self.gusbcfg
        }
        #[doc = "0x10 - DOTG_GRSTCTL"]
        #[inline(always)]
        pub const fn grstctl(&self) -> &Grstctl {
            &self.grstctl
        }
        #[doc = "0x14 - DOTG_GINTSTS"]
        #[inline(always)]
        pub const fn gintsts(&self) -> &Gintsts {
            &self.gintsts
        }
        #[doc = "0x18 - DOTG_GINTMSK"]
        #[inline(always)]
        pub const fn gintmsk(&self) -> &Gintmsk {
            &self.gintmsk
        }
        #[doc = "0x1c - DOTG_GRXSTSRD"]
        #[inline(always)]
        pub const fn grxstsrd(&self) -> &Grxstsrd {
            &self.grxstsrd
        }
        #[doc = "0x20 - DOTG_GRXSTSPD"]
        #[inline(always)]
        pub const fn grxstspd(&self) -> &Grxstspd {
            &self.grxstspd
        }
        #[doc = "0x24 - DOTG_GRXFSIZ"]
        #[inline(always)]
        pub const fn grxfsiz(&self) -> &Grxfsiz {
            &self.grxfsiz
        }
        #[doc = "0x28 - DOTG_GNPTXFSIZ"]
        #[inline(always)]
        pub const fn gnptxfsiz(&self) -> &Gnptxfsiz {
            &self.gnptxfsiz
        }
        #[doc = "0x2c - DOTG_GNPTXSTS"]
        #[inline(always)]
        pub const fn gnptxsts(&self) -> &Gnptxsts {
            &self.gnptxsts
        }
        #[doc = "0x30 - DOTG_GI2CCTL"]
        #[inline(always)]
        pub const fn gi2cctl(&self) -> &Gi2cctl {
            &self.gi2cctl
        }
        #[doc = "0x34 - DOTG_GPVNDCTL"]
        #[inline(always)]
        pub const fn gpvndctl(&self) -> &Gpvndctl {
            &self.gpvndctl
        }
        #[doc = "0x38 - DOTG_GGPIO"]
        #[inline(always)]
        pub const fn ggpio(&self) -> &Ggpio {
            &self.ggpio
        }
        #[doc = "0x3c - DOTG_GUID"]
        #[inline(always)]
        pub const fn guid(&self) -> &Guid {
            &self.guid
        }
        #[doc = "0x40 - DOTG_GSNPSID"]
        #[inline(always)]
        pub const fn gsnpsid(&self) -> &Gsnpsid {
            &self.gsnpsid
        }
        #[doc = "0x44 - DOTG_GHWCFG1"]
        #[inline(always)]
        pub const fn ghwcfg1(&self) -> &Ghwcfg1 {
            &self.ghwcfg1
        }
        #[doc = "0x48 - DOTG_GHWCFG2"]
        #[inline(always)]
        pub const fn ghwcfg2(&self) -> &Ghwcfg2 {
            &self.ghwcfg2
        }
        #[doc = "0x4c - DOTG_GHWCFG3"]
        #[inline(always)]
        pub const fn ghwcfg3(&self) -> &Ghwcfg3 {
            &self.ghwcfg3
        }
        #[doc = "0x50 - DOTG_GHWCFG4"]
        #[inline(always)]
        pub const fn ghwcfg4(&self) -> &Ghwcfg4 {
            &self.ghwcfg4
        }
        #[doc = "0x54 - DOTG_GLPMCFG"]
        #[inline(always)]
        pub const fn glpmcfg(&self) -> &Glpmcfg {
            &self.glpmcfg
        }
        #[doc = "0x58 - DOTG_GPWRDN"]
        #[inline(always)]
        pub const fn gpwrdn(&self) -> &Gpwrdn {
            &self.gpwrdn
        }
        #[doc = "0x5c - DOTG_GDFIFOCFG"]
        #[inline(always)]
        pub const fn gdfifocfg(&self) -> &Gdfifocfg {
            &self.gdfifocfg
        }
        #[doc = "0x60 - DOTG_GADPCTL"]
        #[inline(always)]
        pub const fn gadpctl(&self) -> &Gadpctl {
            &self.gadpctl
        }
        #[doc = "0x100 - DOTG_HPTXFSIZ"]
        #[inline(always)]
        pub const fn hptxfsiz(&self) -> &Hptxfsiz {
            &self.hptxfsiz
        }
        #[doc = "0x400 - DOTG_HCFG"]
        #[inline(always)]
        pub const fn hcfg(&self) -> &Hcfg {
            &self.hcfg
        }
        #[doc = "0x404 - DOTG_HFIR"]
        #[inline(always)]
        pub const fn hfir(&self) -> &Hfir {
            &self.hfir
        }
        #[doc = "0x408 - DOTG_HFNUM"]
        #[inline(always)]
        pub const fn hfnum(&self) -> &Hfnum {
            &self.hfnum
        }
        #[doc = "0x410 - DOTG_HPTXSTS"]
        #[inline(always)]
        pub const fn hptxsts(&self) -> &Hptxsts {
            &self.hptxsts
        }
        #[doc = "0x414 - DOTG_HAINT"]
        #[inline(always)]
        pub const fn haint(&self) -> &Haint {
            &self.haint
        }
        #[doc = "0x418 - DOTG_HAINTMSK"]
        #[inline(always)]
        pub const fn haintmsk(&self) -> &Haintmsk {
            &self.haintmsk
        }
        #[doc = "0x440 - DOTG_HPRT"]
        #[inline(always)]
        pub const fn hprt(&self) -> &Hprt {
            &self.hprt
        }
        #[doc = "0x800 - DOTG_DCFG"]
        #[inline(always)]
        pub const fn dcfg(&self) -> &Dcfg {
            &self.dcfg
        }
        #[doc = "0x804 - DOTG_DCTL"]
        #[inline(always)]
        pub const fn dctl(&self) -> &Dctl {
            &self.dctl
        }
        #[doc = "0x808 - DOTG_DSTS"]
        #[inline(always)]
        pub const fn dsts(&self) -> &Dsts {
            &self.dsts
        }
        #[doc = "0x810 - DOTG_DIEPMSK"]
        #[inline(always)]
        pub const fn diepmsk(&self) -> &Diepmsk {
            &self.diepmsk
        }
        #[doc = "0x814 - DOTG_DOEPMSK"]
        #[inline(always)]
        pub const fn doepmsk(&self) -> &Doepmsk {
            &self.doepmsk
        }
        #[doc = "0x818 - DOTG_DAINT"]
        #[inline(always)]
        pub const fn daint(&self) -> &Daint {
            &self.daint
        }
        #[doc = "0x81c - DOTG_DAINTMSK"]
        #[inline(always)]
        pub const fn daintmsk(&self) -> &Daintmsk {
            &self.daintmsk
        }
        #[doc = "0x820 - DOTG_DTKNQR1"]
        #[inline(always)]
        pub const fn dtknqr1(&self) -> &Dtknqr1 {
            &self.dtknqr1
        }
        #[doc = "0x824 - DOTG_DTKNQR2"]
        #[inline(always)]
        pub const fn dtknqr2(&self) -> &Dtknqr2 {
            &self.dtknqr2
        }
        #[doc = "0x828 - DOTG_DVBUSDIS"]
        #[inline(always)]
        pub const fn dvbusdis(&self) -> &Dvbusdis {
            &self.dvbusdis
        }
        #[doc = "0x82c - DOTG_DVBUSPULSE"]
        #[inline(always)]
        pub const fn dvbuspulse(&self) -> &Dvbuspulse {
            &self.dvbuspulse
        }
        #[doc = "0x830 - DOTG_DTHRCTL"]
        #[inline(always)]
        pub const fn dthrctl(&self) -> &Dthrctl {
            &self.dthrctl
        }
        #[doc = "0x834 - DOTG_DTKNQR4"]
        #[inline(always)]
        pub const fn dtknqr4(&self) -> &Dtknqr4 {
            &self.dtknqr4
        }
        #[doc = "0x838 - DOTG_DEACHINT"]
        #[inline(always)]
        pub const fn deachint(&self) -> &Deachint {
            &self.deachint
        }
        #[doc = "0x83c - DOTG_DEACHINTMSK"]
        #[inline(always)]
        pub const fn deachintmsk(&self) -> &Deachintmsk {
            &self.deachintmsk
        }
        #[doc = "0xe00 - DOTG_PCGCCTL"]
        #[inline(always)]
        pub const fn pcgcctl(&self) -> &Pcgcctl {
            &self.pcgcctl
        }
    }
    #[doc = "GOTGCTL (rw) register accessor: DOTG_GOTGCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gotgctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgctl`] module"]
    #[doc(alias = "GOTGCTL")]
    pub type Gotgctl = crate::Reg<gotgctl::GotgctlSpec>;
    #[doc = "DOTG_GOTGCTL"]
    pub mod gotgctl {
        #[doc = "Register `GOTGCTL` reader"]
        pub type R = crate::R<GotgctlSpec>;
        #[doc = "Register `GOTGCTL` writer"]
        pub type W = crate::W<GotgctlSpec>;
        #[doc = "Field `SESREQSCS` reader - "]
        pub type SesreqscsR = crate::BitReader;
        #[doc = "Field `SESREQSCS` writer - "]
        pub type SesreqscsW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SESREQ` reader - "]
        pub type SesreqR = crate::BitReader;
        #[doc = "Field `SESREQ` writer - "]
        pub type SesreqW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SESENDDET` reader - "]
        pub type SesenddetR = crate::BitReader;
        #[doc = "Field `SESENDDET` writer - "]
        pub type SesenddetW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HSTNEGSCS` reader - "]
        pub type HstnegscsR = crate::BitReader;
        #[doc = "Field `HSTNEGSCS` writer - "]
        pub type HstnegscsW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HNPREQ` reader - "]
        pub type HnpreqR = crate::BitReader;
        #[doc = "Field `HNPREQ` writer - "]
        pub type HnpreqW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HSTSETHNPEN` reader - "]
        pub type HstsethnpenR = crate::BitReader;
        #[doc = "Field `HSTSETHNPEN` writer - "]
        pub type HstsethnpenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DEVHNPEN` reader - "]
        pub type DevhnpenR = crate::BitReader;
        #[doc = "Field `DEVHNPEN` writer - "]
        pub type DevhnpenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CONIDSTS` reader - "]
        pub type ConidstsR = crate::BitReader;
        #[doc = "Field `CONIDSTS` writer - "]
        pub type ConidstsW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DBNCTIME` reader - "]
        pub type DbnctimeR = crate::BitReader;
        #[doc = "Field `DBNCTIME` writer - "]
        pub type DbnctimeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ASESVLD` reader - "]
        pub type AsesvldR = crate::BitReader;
        #[doc = "Field `ASESVLD` writer - "]
        pub type AsesvldW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BSESVLD` reader - "]
        pub type BsesvldR = crate::BitReader;
        #[doc = "Field `BSESVLD` writer - "]
        pub type BsesvldW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CHIRP_ON` reader - "]
        pub type ChirpOnR = crate::BitReader;
        #[doc = "Field `CHIRP_ON` writer - "]
        pub type ChirpOnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn sesreqscs(&self) -> SesreqscsR {
                SesreqscsR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn sesreq(&self) -> SesreqR {
                SesreqR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn sesenddet(&self) -> SesenddetR {
                SesenddetR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn hstnegscs(&self) -> HstnegscsR {
                HstnegscsR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn hnpreq(&self) -> HnpreqR {
                HnpreqR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn hstsethnpen(&self) -> HstsethnpenR {
                HstsethnpenR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn devhnpen(&self) -> DevhnpenR {
                DevhnpenR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn conidsts(&self) -> ConidstsR {
                ConidstsR::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn dbnctime(&self) -> DbnctimeR {
                DbnctimeR::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn asesvld(&self) -> AsesvldR {
                AsesvldR::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn bsesvld(&self) -> BsesvldR {
                BsesvldR::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn chirp_on(&self) -> ChirpOnR {
                ChirpOnR::new(((self.bits >> 27) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn sesreqscs(&mut self) -> SesreqscsW<'_, GotgctlSpec> {
                SesreqscsW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn sesreq(&mut self) -> SesreqW<'_, GotgctlSpec> {
                SesreqW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn sesenddet(&mut self) -> SesenddetW<'_, GotgctlSpec> {
                SesenddetW::new(self, 2)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn hstnegscs(&mut self) -> HstnegscsW<'_, GotgctlSpec> {
                HstnegscsW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn hnpreq(&mut self) -> HnpreqW<'_, GotgctlSpec> {
                HnpreqW::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn hstsethnpen(&mut self) -> HstsethnpenW<'_, GotgctlSpec> {
                HstsethnpenW::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn devhnpen(&mut self) -> DevhnpenW<'_, GotgctlSpec> {
                DevhnpenW::new(self, 11)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn conidsts(&mut self) -> ConidstsW<'_, GotgctlSpec> {
                ConidstsW::new(self, 16)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn dbnctime(&mut self) -> DbnctimeW<'_, GotgctlSpec> {
                DbnctimeW::new(self, 17)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn asesvld(&mut self) -> AsesvldW<'_, GotgctlSpec> {
                AsesvldW::new(self, 18)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn bsesvld(&mut self) -> BsesvldW<'_, GotgctlSpec> {
                BsesvldW::new(self, 19)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn chirp_on(&mut self) -> ChirpOnW<'_, GotgctlSpec> {
                ChirpOnW::new(self, 27)
            }
        }
        #[doc = "DOTG_GOTGCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gotgctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GotgctlSpec;
        impl crate::RegisterSpec for GotgctlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gotgctl::R`](R) reader structure"]
        impl crate::Readable for GotgctlSpec {}
        #[doc = "`write(|w| ..)` method takes [`gotgctl::W`](W) writer structure"]
        impl crate::Writable for GotgctlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GOTGCTL to value 0"]
        impl crate::Resettable for GotgctlSpec {}
    }
    #[doc = "GOTGINT (rw) register accessor: DOTG_GOTGINT\n\nYou can [`read`](crate::Reg::read) this register and get [`gotgint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgint`] module"]
    #[doc(alias = "GOTGINT")]
    pub type Gotgint = crate::Reg<gotgint::GotgintSpec>;
    #[doc = "DOTG_GOTGINT"]
    pub mod gotgint {
        #[doc = "Register `GOTGINT` reader"]
        pub type R = crate::R<GotgintSpec>;
        #[doc = "Register `GOTGINT` writer"]
        pub type W = crate::W<GotgintSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_GOTGINT\n\nYou can [`read`](crate::Reg::read) this register and get [`gotgint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gotgint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GotgintSpec;
        impl crate::RegisterSpec for GotgintSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gotgint::R`](R) reader structure"]
        impl crate::Readable for GotgintSpec {}
        #[doc = "`write(|w| ..)` method takes [`gotgint::W`](W) writer structure"]
        impl crate::Writable for GotgintSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GOTGINT to value 0"]
        impl crate::Resettable for GotgintSpec {}
    }
    #[doc = "GAHBCFG (rw) register accessor: DOTG_GAHBCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gahbcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gahbcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gahbcfg`] module"]
    #[doc(alias = "GAHBCFG")]
    pub type Gahbcfg = crate::Reg<gahbcfg::GahbcfgSpec>;
    #[doc = "DOTG_GAHBCFG"]
    pub mod gahbcfg {
        #[doc = "Register `GAHBCFG` reader"]
        pub type R = crate::R<GahbcfgSpec>;
        #[doc = "Register `GAHBCFG` writer"]
        pub type W = crate::W<GahbcfgSpec>;
        #[doc = "Field `GLBLINTRMSK` reader - "]
        pub type GlblintrmskR = crate::BitReader;
        #[doc = "Field `GLBLINTRMSK` writer - "]
        pub type GlblintrmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HBSTLEN` reader - "]
        pub type HbstlenR = crate::FieldReader;
        #[doc = "Field `HBSTLEN` writer - "]
        pub type HbstlenW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `DMAEN` reader - "]
        pub type DmaenR = crate::BitReader;
        #[doc = "Field `DMAEN` writer - "]
        pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NPTXFEMPLVL` reader - "]
        pub type NptxfemplvlR = crate::BitReader;
        #[doc = "Field `NPTXFEMPLVL` writer - "]
        pub type NptxfemplvlW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PTXFEMPLVL` reader - "]
        pub type PtxfemplvlR = crate::BitReader;
        #[doc = "Field `PTXFEMPLVL` writer - "]
        pub type PtxfemplvlW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn glblintrmsk(&self) -> GlblintrmskR {
                GlblintrmskR::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 1:4"]
            #[inline(always)]
            pub fn hbstlen(&self) -> HbstlenR {
                HbstlenR::new(((self.bits >> 1) & 0x0f) as u8)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn dmaen(&self) -> DmaenR {
                DmaenR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn nptxfemplvl(&self) -> NptxfemplvlR {
                NptxfemplvlR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn ptxfemplvl(&self) -> PtxfemplvlR {
                PtxfemplvlR::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn glblintrmsk(&mut self) -> GlblintrmskW<'_, GahbcfgSpec> {
                GlblintrmskW::new(self, 0)
            }
            #[doc = "Bits 1:4"]
            #[inline(always)]
            pub fn hbstlen(&mut self) -> HbstlenW<'_, GahbcfgSpec> {
                HbstlenW::new(self, 1)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn dmaen(&mut self) -> DmaenW<'_, GahbcfgSpec> {
                DmaenW::new(self, 5)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn nptxfemplvl(&mut self) -> NptxfemplvlW<'_, GahbcfgSpec> {
                NptxfemplvlW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn ptxfemplvl(&mut self) -> PtxfemplvlW<'_, GahbcfgSpec> {
                PtxfemplvlW::new(self, 8)
            }
        }
        #[doc = "DOTG_GAHBCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gahbcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gahbcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GahbcfgSpec;
        impl crate::RegisterSpec for GahbcfgSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gahbcfg::R`](R) reader structure"]
        impl crate::Readable for GahbcfgSpec {}
        #[doc = "`write(|w| ..)` method takes [`gahbcfg::W`](W) writer structure"]
        impl crate::Writable for GahbcfgSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GAHBCFG to value 0"]
        impl crate::Resettable for GahbcfgSpec {}
    }
    #[doc = "GUSBCFG (rw) register accessor: DOTG_GUSBCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gusbcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gusbcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gusbcfg`] module"]
    #[doc(alias = "GUSBCFG")]
    pub type Gusbcfg = crate::Reg<gusbcfg::GusbcfgSpec>;
    #[doc = "DOTG_GUSBCFG"]
    pub mod gusbcfg {
        #[doc = "Register `GUSBCFG` reader"]
        pub type R = crate::R<GusbcfgSpec>;
        #[doc = "Register `GUSBCFG` writer"]
        pub type W = crate::W<GusbcfgSpec>;
        #[doc = "Field `TOUTCAL` reader - "]
        pub type ToutcalR = crate::FieldReader;
        #[doc = "Field `TOUTCAL` writer - "]
        pub type ToutcalW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `PHYIF` reader - "]
        pub type PhyifR = crate::BitReader;
        #[doc = "Field `PHYIF` writer - "]
        pub type PhyifW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ULPI_UTMI_SEL` reader - "]
        pub type UlpiUtmiSelR = crate::BitReader;
        #[doc = "Field `ULPI_UTMI_SEL` writer - "]
        pub type UlpiUtmiSelW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FSINTF` reader - "]
        pub type FsintfR = crate::BitReader;
        #[doc = "Field `FSINTF` writer - "]
        pub type FsintfW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHYSEL` reader - "]
        pub type PhyselR = crate::BitReader;
        #[doc = "Field `PHYSEL` writer - "]
        pub type PhyselW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DDRSEL` reader - "]
        pub type DdrselR = crate::BitReader;
        #[doc = "Field `DDRSEL` writer - "]
        pub type DdrselW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SRPCAP` reader - "]
        pub type SrpcapR = crate::BitReader;
        #[doc = "Field `SRPCAP` writer - "]
        pub type SrpcapW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HNPCAP` reader - "]
        pub type HnpcapR = crate::BitReader;
        #[doc = "Field `HNPCAP` writer - "]
        pub type HnpcapW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `USBTRDTIM` reader - "]
        pub type UsbtrdtimR = crate::FieldReader;
        #[doc = "Field `USBTRDTIM` writer - "]
        pub type UsbtrdtimW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `PHYLPWRCLKSEL` reader - "]
        pub type PhylpwrclkselR = crate::BitReader;
        #[doc = "Field `PHYLPWRCLKSEL` writer - "]
        pub type PhylpwrclkselW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTGI2CSEL` reader - "]
        pub type Otgi2cselR = crate::BitReader;
        #[doc = "Field `OTGI2CSEL` writer - "]
        pub type Otgi2cselW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ULPIFSLS` reader - "]
        pub type UlpifslsR = crate::BitReader;
        #[doc = "Field `ULPIFSLS` writer - "]
        pub type UlpifslsW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ULPIAUTORES` reader - "]
        pub type UlpiautoresR = crate::BitReader;
        #[doc = "Field `ULPIAUTORES` writer - "]
        pub type UlpiautoresW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ULPICLKSUSM` reader - "]
        pub type UlpiclksusmR = crate::BitReader;
        #[doc = "Field `ULPICLKSUSM` writer - "]
        pub type UlpiclksusmW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ULPIEXTVBUSDRV` reader - "]
        pub type UlpiextvbusdrvR = crate::BitReader;
        #[doc = "Field `ULPIEXTVBUSDRV` writer - "]
        pub type UlpiextvbusdrvW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ULPIEXTVBUSINDICATOR` reader - "]
        pub type UlpiextvbusindicatorR = crate::BitReader;
        #[doc = "Field `ULPIEXTVBUSINDICATOR` writer - "]
        pub type UlpiextvbusindicatorW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TERMSELDLPULSE` reader - "]
        pub type TermseldlpulseR = crate::BitReader;
        #[doc = "Field `TERMSELDLPULSE` writer - "]
        pub type TermseldlpulseW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IC_USB_CAP` reader - "]
        pub type IcUsbCapR = crate::BitReader;
        #[doc = "Field `IC_USB_CAP` writer - "]
        pub type IcUsbCapW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NO_PULLUP` reader - "]
        pub type NoPullupR = crate::BitReader;
        #[doc = "Field `NO_PULLUP` writer - "]
        pub type NoPullupW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FORCEHOSTMODE` reader - "]
        pub type ForcehostmodeR = crate::BitReader;
        #[doc = "Field `FORCEHOSTMODE` writer - "]
        pub type ForcehostmodeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FORCEDEVMODE` reader - "]
        pub type ForcedevmodeR = crate::BitReader;
        #[doc = "Field `FORCEDEVMODE` writer - "]
        pub type ForcedevmodeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CORRUPTTXPACKET` reader - "]
        pub type CorrupttxpacketR = crate::BitReader;
        #[doc = "Field `CORRUPTTXPACKET` writer - "]
        pub type CorrupttxpacketW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn toutcal(&self) -> ToutcalR {
                ToutcalR::new((self.bits & 7) as u8)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn phyif(&self) -> PhyifR {
                PhyifR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn ulpi_utmi_sel(&self) -> UlpiUtmiSelR {
                UlpiUtmiSelR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn fsintf(&self) -> FsintfR {
                FsintfR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn physel(&self) -> PhyselR {
                PhyselR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn ddrsel(&self) -> DdrselR {
                DdrselR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn srpcap(&self) -> SrpcapR {
                SrpcapR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn hnpcap(&self) -> HnpcapR {
                HnpcapR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bits 10:13"]
            #[inline(always)]
            pub fn usbtrdtim(&self) -> UsbtrdtimR {
                UsbtrdtimR::new(((self.bits >> 10) & 0x0f) as u8)
            }
            #[doc = "Bit 15"]
            #[inline(always)]
            pub fn phylpwrclksel(&self) -> PhylpwrclkselR {
                PhylpwrclkselR::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn otgi2csel(&self) -> Otgi2cselR {
                Otgi2cselR::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn ulpifsls(&self) -> UlpifslsR {
                UlpifslsR::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn ulpiautores(&self) -> UlpiautoresR {
                UlpiautoresR::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn ulpiclksusm(&self) -> UlpiclksusmR {
                UlpiclksusmR::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn ulpiextvbusdrv(&self) -> UlpiextvbusdrvR {
                UlpiextvbusdrvR::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn ulpiextvbusindicator(&self) -> UlpiextvbusindicatorR {
                UlpiextvbusindicatorR::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn termseldlpulse(&self) -> TermseldlpulseR {
                TermseldlpulseR::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn ic_usb_cap(&self) -> IcUsbCapR {
                IcUsbCapR::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn no_pullup(&self) -> NoPullupR {
                NoPullupR::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 29"]
            #[inline(always)]
            pub fn forcehostmode(&self) -> ForcehostmodeR {
                ForcehostmodeR::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn forcedevmode(&self) -> ForcedevmodeR {
                ForcedevmodeR::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn corrupttxpacket(&self) -> CorrupttxpacketR {
                CorrupttxpacketR::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn toutcal(&mut self) -> ToutcalW<'_, GusbcfgSpec> {
                ToutcalW::new(self, 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn phyif(&mut self) -> PhyifW<'_, GusbcfgSpec> {
                PhyifW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn ulpi_utmi_sel(&mut self) -> UlpiUtmiSelW<'_, GusbcfgSpec> {
                UlpiUtmiSelW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn fsintf(&mut self) -> FsintfW<'_, GusbcfgSpec> {
                FsintfW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn physel(&mut self) -> PhyselW<'_, GusbcfgSpec> {
                PhyselW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn ddrsel(&mut self) -> DdrselW<'_, GusbcfgSpec> {
                DdrselW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn srpcap(&mut self) -> SrpcapW<'_, GusbcfgSpec> {
                SrpcapW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn hnpcap(&mut self) -> HnpcapW<'_, GusbcfgSpec> {
                HnpcapW::new(self, 9)
            }
            #[doc = "Bits 10:13"]
            #[inline(always)]
            pub fn usbtrdtim(&mut self) -> UsbtrdtimW<'_, GusbcfgSpec> {
                UsbtrdtimW::new(self, 10)
            }
            #[doc = "Bit 15"]
            #[inline(always)]
            pub fn phylpwrclksel(&mut self) -> PhylpwrclkselW<'_, GusbcfgSpec> {
                PhylpwrclkselW::new(self, 15)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn otgi2csel(&mut self) -> Otgi2cselW<'_, GusbcfgSpec> {
                Otgi2cselW::new(self, 16)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn ulpifsls(&mut self) -> UlpifslsW<'_, GusbcfgSpec> {
                UlpifslsW::new(self, 17)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn ulpiautores(&mut self) -> UlpiautoresW<'_, GusbcfgSpec> {
                UlpiautoresW::new(self, 18)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn ulpiclksusm(&mut self) -> UlpiclksusmW<'_, GusbcfgSpec> {
                UlpiclksusmW::new(self, 19)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn ulpiextvbusdrv(&mut self) -> UlpiextvbusdrvW<'_, GusbcfgSpec> {
                UlpiextvbusdrvW::new(self, 20)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn ulpiextvbusindicator(&mut self) -> UlpiextvbusindicatorW<'_, GusbcfgSpec> {
                UlpiextvbusindicatorW::new(self, 21)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn termseldlpulse(&mut self) -> TermseldlpulseW<'_, GusbcfgSpec> {
                TermseldlpulseW::new(self, 22)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn ic_usb_cap(&mut self) -> IcUsbCapW<'_, GusbcfgSpec> {
                IcUsbCapW::new(self, 26)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn no_pullup(&mut self) -> NoPullupW<'_, GusbcfgSpec> {
                NoPullupW::new(self, 27)
            }
            #[doc = "Bit 29"]
            #[inline(always)]
            pub fn forcehostmode(&mut self) -> ForcehostmodeW<'_, GusbcfgSpec> {
                ForcehostmodeW::new(self, 29)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn forcedevmode(&mut self) -> ForcedevmodeW<'_, GusbcfgSpec> {
                ForcedevmodeW::new(self, 30)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn corrupttxpacket(&mut self) -> CorrupttxpacketW<'_, GusbcfgSpec> {
                CorrupttxpacketW::new(self, 31)
            }
        }
        #[doc = "DOTG_GUSBCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gusbcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gusbcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GusbcfgSpec;
        impl crate::RegisterSpec for GusbcfgSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gusbcfg::R`](R) reader structure"]
        impl crate::Readable for GusbcfgSpec {}
        #[doc = "`write(|w| ..)` method takes [`gusbcfg::W`](W) writer structure"]
        impl crate::Writable for GusbcfgSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GUSBCFG to value 0"]
        impl crate::Resettable for GusbcfgSpec {}
    }
    #[doc = "GRSTCTL (rw) register accessor: DOTG_GRSTCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`grstctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grstctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grstctl`] module"]
    #[doc(alias = "GRSTCTL")]
    pub type Grstctl = crate::Reg<grstctl::GrstctlSpec>;
    #[doc = "DOTG_GRSTCTL"]
    pub mod grstctl {
        #[doc = "Register `GRSTCTL` reader"]
        pub type R = crate::R<GrstctlSpec>;
        #[doc = "Register `GRSTCTL` writer"]
        pub type W = crate::W<GrstctlSpec>;
        #[doc = "Field `CSFTRST` reader - "]
        pub type CsftrstR = crate::BitReader;
        #[doc = "Field `CSFTRST` writer - "]
        pub type CsftrstW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HSFTRST` reader - "]
        pub type HsftrstR = crate::BitReader;
        #[doc = "Field `HSFTRST` writer - "]
        pub type HsftrstW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FRMCNTRRST` reader - "]
        pub type FrmcntrrstR = crate::BitReader;
        #[doc = "Field `FRMCNTRRST` writer - "]
        pub type FrmcntrrstW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INTKNQFLSH` reader - "]
        pub type IntknqflshR = crate::BitReader;
        #[doc = "Field `INTKNQFLSH` writer - "]
        pub type IntknqflshW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXFFLSH` reader - "]
        pub type RxfflshR = crate::BitReader;
        #[doc = "Field `RXFFLSH` writer - "]
        pub type RxfflshW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXFFLSH` reader - "]
        pub type TxfflshR = crate::BitReader;
        #[doc = "Field `TXFFLSH` writer - "]
        pub type TxfflshW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXFNUM` reader - "]
        pub type TxfnumR = crate::FieldReader;
        #[doc = "Field `TXFNUM` writer - "]
        pub type TxfnumW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `DMAREQ` reader - "]
        pub type DmareqR = crate::BitReader;
        #[doc = "Field `DMAREQ` writer - "]
        pub type DmareqW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AHBIDLE` reader - "]
        pub type AhbidleR = crate::BitReader;
        #[doc = "Field `AHBIDLE` writer - "]
        pub type AhbidleW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn csftrst(&self) -> CsftrstR {
                CsftrstR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn hsftrst(&self) -> HsftrstR {
                HsftrstR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn frmcntrrst(&self) -> FrmcntrrstR {
                FrmcntrrstR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn intknqflsh(&self) -> IntknqflshR {
                IntknqflshR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn rxfflsh(&self) -> RxfflshR {
                RxfflshR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn txfflsh(&self) -> TxfflshR {
                TxfflshR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bits 6:10"]
            #[inline(always)]
            pub fn txfnum(&self) -> TxfnumR {
                TxfnumR::new(((self.bits >> 6) & 0x1f) as u8)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn dmareq(&self) -> DmareqR {
                DmareqR::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn ahbidle(&self) -> AhbidleR {
                AhbidleR::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn csftrst(&mut self) -> CsftrstW<'_, GrstctlSpec> {
                CsftrstW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn hsftrst(&mut self) -> HsftrstW<'_, GrstctlSpec> {
                HsftrstW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn frmcntrrst(&mut self) -> FrmcntrrstW<'_, GrstctlSpec> {
                FrmcntrrstW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn intknqflsh(&mut self) -> IntknqflshW<'_, GrstctlSpec> {
                IntknqflshW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn rxfflsh(&mut self) -> RxfflshW<'_, GrstctlSpec> {
                RxfflshW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn txfflsh(&mut self) -> TxfflshW<'_, GrstctlSpec> {
                TxfflshW::new(self, 5)
            }
            #[doc = "Bits 6:10"]
            #[inline(always)]
            pub fn txfnum(&mut self) -> TxfnumW<'_, GrstctlSpec> {
                TxfnumW::new(self, 6)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn dmareq(&mut self) -> DmareqW<'_, GrstctlSpec> {
                DmareqW::new(self, 30)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn ahbidle(&mut self) -> AhbidleW<'_, GrstctlSpec> {
                AhbidleW::new(self, 31)
            }
        }
        #[doc = "DOTG_GRSTCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`grstctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grstctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GrstctlSpec;
        impl crate::RegisterSpec for GrstctlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`grstctl::R`](R) reader structure"]
        impl crate::Readable for GrstctlSpec {}
        #[doc = "`write(|w| ..)` method takes [`grstctl::W`](W) writer structure"]
        impl crate::Writable for GrstctlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GRSTCTL to value 0"]
        impl crate::Resettable for GrstctlSpec {}
    }
    #[doc = "GINTSTS (rw) register accessor: DOTG_GINTSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`gintsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintsts`] module"]
    #[doc(alias = "GINTSTS")]
    pub type Gintsts = crate::Reg<gintsts::GintstsSpec>;
    #[doc = "DOTG_GINTSTS"]
    pub mod gintsts {
        #[doc = "Register `GINTSTS` reader"]
        pub type R = crate::R<GintstsSpec>;
        #[doc = "Register `GINTSTS` writer"]
        pub type W = crate::W<GintstsSpec>;
        #[doc = "Field `CURMOD` reader - "]
        pub type CurmodR = crate::BitReader;
        #[doc = "Field `CURMOD` writer - "]
        pub type CurmodW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MODEMIS` reader - "]
        pub type ModemisR = crate::BitReader;
        #[doc = "Field `MODEMIS` writer - "]
        pub type ModemisW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTGINT` reader - "]
        pub type OtgintR = crate::BitReader;
        #[doc = "Field `OTGINT` writer - "]
        pub type OtgintW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SOF` reader - "]
        pub type SofR = crate::BitReader;
        #[doc = "Field `SOF` writer - "]
        pub type SofW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXFLVL` reader - "]
        pub type RxflvlR = crate::BitReader;
        #[doc = "Field `RXFLVL` writer - "]
        pub type RxflvlW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NPTXFEMP` reader - "]
        pub type NptxfempR = crate::BitReader;
        #[doc = "Field `NPTXFEMP` writer - "]
        pub type NptxfempW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GINNAKEFF` reader - "]
        pub type GinnakeffR = crate::BitReader;
        #[doc = "Field `GINNAKEFF` writer - "]
        pub type GinnakeffW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GOUTNAKEFF` reader - "]
        pub type GoutnakeffR = crate::BitReader;
        #[doc = "Field `GOUTNAKEFF` writer - "]
        pub type GoutnakeffW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ULPICKINT` reader - "]
        pub type UlpickintR = crate::BitReader;
        #[doc = "Field `ULPICKINT` writer - "]
        pub type UlpickintW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `I2CINT` reader - "]
        pub type I2cintR = crate::BitReader;
        #[doc = "Field `I2CINT` writer - "]
        pub type I2cintW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERLYSUSP` reader - "]
        pub type ErlysuspR = crate::BitReader;
        #[doc = "Field `ERLYSUSP` writer - "]
        pub type ErlysuspW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `USBSUSP` reader - "]
        pub type UsbsuspR = crate::BitReader;
        #[doc = "Field `USBSUSP` writer - "]
        pub type UsbsuspW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `USBRST` reader - "]
        pub type UsbrstR = crate::BitReader;
        #[doc = "Field `USBRST` writer - "]
        pub type UsbrstW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ENUMDONE` reader - "]
        pub type EnumdoneR = crate::BitReader;
        #[doc = "Field `ENUMDONE` writer - "]
        pub type EnumdoneW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ISOOUTDROP` reader - "]
        pub type IsooutdropR = crate::BitReader;
        #[doc = "Field `ISOOUTDROP` writer - "]
        pub type IsooutdropW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EOPF` reader - "]
        pub type EopfR = crate::BitReader;
        #[doc = "Field `EOPF` writer - "]
        pub type EopfW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESTORE_DONE` reader - "]
        pub type RestoreDoneR = crate::BitReader;
        #[doc = "Field `RESTORE_DONE` writer - "]
        pub type RestoreDoneW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EPMIS` reader - "]
        pub type EpmisR = crate::BitReader;
        #[doc = "Field `EPMIS` writer - "]
        pub type EpmisW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IEPINT` reader - "]
        pub type IepintR = crate::BitReader;
        #[doc = "Field `IEPINT` writer - "]
        pub type IepintW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OEPINT` reader - "]
        pub type OepintR = crate::BitReader;
        #[doc = "Field `OEPINT` writer - "]
        pub type OepintW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INCOMPISOIN` reader - "]
        pub type IncompisoinR = crate::BitReader;
        #[doc = "Field `INCOMPISOIN` writer - "]
        pub type IncompisoinW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INCOMPLP` reader - "]
        pub type IncomplpR = crate::BitReader;
        #[doc = "Field `INCOMPLP` writer - "]
        pub type IncomplpW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FETSUSP` reader - "]
        pub type FetsuspR = crate::BitReader;
        #[doc = "Field `FETSUSP` writer - "]
        pub type FetsuspW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESETDET` reader - "]
        pub type ResetdetR = crate::BitReader;
        #[doc = "Field `RESETDET` writer - "]
        pub type ResetdetW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTINT` reader - "]
        pub type PrtintR = crate::BitReader;
        #[doc = "Field `PRTINT` writer - "]
        pub type PrtintW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HCHINT` reader - "]
        pub type HchintR = crate::BitReader;
        #[doc = "Field `HCHINT` writer - "]
        pub type HchintW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PTXFEMP` reader - "]
        pub type PtxfempR = crate::BitReader;
        #[doc = "Field `PTXFEMP` writer - "]
        pub type PtxfempW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LPM` reader - "]
        pub type LpmR = crate::BitReader;
        #[doc = "Field `LPM` writer - "]
        pub type LpmW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CONIDSTSCHNG` reader - "]
        pub type ConidstschngR = crate::BitReader;
        #[doc = "Field `CONIDSTSCHNG` writer - "]
        pub type ConidstschngW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DISCONNINT` reader - "]
        pub type DisconnintR = crate::BitReader;
        #[doc = "Field `DISCONNINT` writer - "]
        pub type DisconnintW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SESSREQINT` reader - "]
        pub type SessreqintR = crate::BitReader;
        #[doc = "Field `SESSREQINT` writer - "]
        pub type SessreqintW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WKUPINT` reader - "]
        pub type WkupintR = crate::BitReader;
        #[doc = "Field `WKUPINT` writer - "]
        pub type WkupintW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn curmod(&self) -> CurmodR {
                CurmodR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn modemis(&self) -> ModemisR {
                ModemisR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn otgint(&self) -> OtgintR {
                OtgintR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn sof(&self) -> SofR {
                SofR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn rxflvl(&self) -> RxflvlR {
                RxflvlR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn nptxfemp(&self) -> NptxfempR {
                NptxfempR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn ginnakeff(&self) -> GinnakeffR {
                GinnakeffR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn goutnakeff(&self) -> GoutnakeffR {
                GoutnakeffR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn ulpickint(&self) -> UlpickintR {
                UlpickintR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn i2cint(&self) -> I2cintR {
                I2cintR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn erlysusp(&self) -> ErlysuspR {
                ErlysuspR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn usbsusp(&self) -> UsbsuspR {
                UsbsuspR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn usbrst(&self) -> UsbrstR {
                UsbrstR::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13"]
            #[inline(always)]
            pub fn enumdone(&self) -> EnumdoneR {
                EnumdoneR::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14"]
            #[inline(always)]
            pub fn isooutdrop(&self) -> IsooutdropR {
                IsooutdropR::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15"]
            #[inline(always)]
            pub fn eopf(&self) -> EopfR {
                EopfR::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn restore_done(&self) -> RestoreDoneR {
                RestoreDoneR::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn epmis(&self) -> EpmisR {
                EpmisR::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn iepint(&self) -> IepintR {
                IepintR::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn oepint(&self) -> OepintR {
                OepintR::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn incompisoin(&self) -> IncompisoinR {
                IncompisoinR::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn incomplp(&self) -> IncomplpR {
                IncomplpR::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn fetsusp(&self) -> FetsuspR {
                FetsuspR::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn resetdet(&self) -> ResetdetR {
                ResetdetR::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn prtint(&self) -> PrtintR {
                PrtintR::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25"]
            #[inline(always)]
            pub fn hchint(&self) -> HchintR {
                HchintR::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn ptxfemp(&self) -> PtxfempR {
                PtxfempR::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn lpm(&self) -> LpmR {
                LpmR::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28"]
            #[inline(always)]
            pub fn conidstschng(&self) -> ConidstschngR {
                ConidstschngR::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29"]
            #[inline(always)]
            pub fn disconnint(&self) -> DisconnintR {
                DisconnintR::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn sessreqint(&self) -> SessreqintR {
                SessreqintR::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn wkupint(&self) -> WkupintR {
                WkupintR::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn curmod(&mut self) -> CurmodW<'_, GintstsSpec> {
                CurmodW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn modemis(&mut self) -> ModemisW<'_, GintstsSpec> {
                ModemisW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn otgint(&mut self) -> OtgintW<'_, GintstsSpec> {
                OtgintW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn sof(&mut self) -> SofW<'_, GintstsSpec> {
                SofW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn rxflvl(&mut self) -> RxflvlW<'_, GintstsSpec> {
                RxflvlW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn nptxfemp(&mut self) -> NptxfempW<'_, GintstsSpec> {
                NptxfempW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn ginnakeff(&mut self) -> GinnakeffW<'_, GintstsSpec> {
                GinnakeffW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn goutnakeff(&mut self) -> GoutnakeffW<'_, GintstsSpec> {
                GoutnakeffW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn ulpickint(&mut self) -> UlpickintW<'_, GintstsSpec> {
                UlpickintW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn i2cint(&mut self) -> I2cintW<'_, GintstsSpec> {
                I2cintW::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn erlysusp(&mut self) -> ErlysuspW<'_, GintstsSpec> {
                ErlysuspW::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn usbsusp(&mut self) -> UsbsuspW<'_, GintstsSpec> {
                UsbsuspW::new(self, 11)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn usbrst(&mut self) -> UsbrstW<'_, GintstsSpec> {
                UsbrstW::new(self, 12)
            }
            #[doc = "Bit 13"]
            #[inline(always)]
            pub fn enumdone(&mut self) -> EnumdoneW<'_, GintstsSpec> {
                EnumdoneW::new(self, 13)
            }
            #[doc = "Bit 14"]
            #[inline(always)]
            pub fn isooutdrop(&mut self) -> IsooutdropW<'_, GintstsSpec> {
                IsooutdropW::new(self, 14)
            }
            #[doc = "Bit 15"]
            #[inline(always)]
            pub fn eopf(&mut self) -> EopfW<'_, GintstsSpec> {
                EopfW::new(self, 15)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn restore_done(&mut self) -> RestoreDoneW<'_, GintstsSpec> {
                RestoreDoneW::new(self, 16)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn epmis(&mut self) -> EpmisW<'_, GintstsSpec> {
                EpmisW::new(self, 17)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn iepint(&mut self) -> IepintW<'_, GintstsSpec> {
                IepintW::new(self, 18)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn oepint(&mut self) -> OepintW<'_, GintstsSpec> {
                OepintW::new(self, 19)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn incompisoin(&mut self) -> IncompisoinW<'_, GintstsSpec> {
                IncompisoinW::new(self, 20)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn incomplp(&mut self) -> IncomplpW<'_, GintstsSpec> {
                IncomplpW::new(self, 21)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn fetsusp(&mut self) -> FetsuspW<'_, GintstsSpec> {
                FetsuspW::new(self, 22)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn resetdet(&mut self) -> ResetdetW<'_, GintstsSpec> {
                ResetdetW::new(self, 23)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn prtint(&mut self) -> PrtintW<'_, GintstsSpec> {
                PrtintW::new(self, 24)
            }
            #[doc = "Bit 25"]
            #[inline(always)]
            pub fn hchint(&mut self) -> HchintW<'_, GintstsSpec> {
                HchintW::new(self, 25)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn ptxfemp(&mut self) -> PtxfempW<'_, GintstsSpec> {
                PtxfempW::new(self, 26)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn lpm(&mut self) -> LpmW<'_, GintstsSpec> {
                LpmW::new(self, 27)
            }
            #[doc = "Bit 28"]
            #[inline(always)]
            pub fn conidstschng(&mut self) -> ConidstschngW<'_, GintstsSpec> {
                ConidstschngW::new(self, 28)
            }
            #[doc = "Bit 29"]
            #[inline(always)]
            pub fn disconnint(&mut self) -> DisconnintW<'_, GintstsSpec> {
                DisconnintW::new(self, 29)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn sessreqint(&mut self) -> SessreqintW<'_, GintstsSpec> {
                SessreqintW::new(self, 30)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn wkupint(&mut self) -> WkupintW<'_, GintstsSpec> {
                WkupintW::new(self, 31)
            }
        }
        #[doc = "DOTG_GINTSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`gintsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GintstsSpec;
        impl crate::RegisterSpec for GintstsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gintsts::R`](R) reader structure"]
        impl crate::Readable for GintstsSpec {}
        #[doc = "`write(|w| ..)` method takes [`gintsts::W`](W) writer structure"]
        impl crate::Writable for GintstsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GINTSTS to value 0"]
        impl crate::Resettable for GintstsSpec {}
    }
    #[doc = "GINTMSK (rw) register accessor: DOTG_GINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`gintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintmsk`] module"]
    #[doc(alias = "GINTMSK")]
    pub type Gintmsk = crate::Reg<gintmsk::GintmskSpec>;
    #[doc = "DOTG_GINTMSK"]
    pub mod gintmsk {
        #[doc = "Register `GINTMSK` reader"]
        pub type R = crate::R<GintmskSpec>;
        #[doc = "Register `GINTMSK` writer"]
        pub type W = crate::W<GintmskSpec>;
        #[doc = "Field `CURMODMSK` reader - "]
        pub type CurmodmskR = crate::BitReader;
        #[doc = "Field `CURMODMSK` writer - "]
        pub type CurmodmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MODEMISMSK` reader - "]
        pub type ModemismskR = crate::BitReader;
        #[doc = "Field `MODEMISMSK` writer - "]
        pub type ModemismskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTGINTMSK` reader - "]
        pub type OtgintmskR = crate::BitReader;
        #[doc = "Field `OTGINTMSK` writer - "]
        pub type OtgintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SOFMSK` reader - "]
        pub type SofmskR = crate::BitReader;
        #[doc = "Field `SOFMSK` writer - "]
        pub type SofmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXFLVLMSK` reader - "]
        pub type RxflvlmskR = crate::BitReader;
        #[doc = "Field `RXFLVLMSK` writer - "]
        pub type RxflvlmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NPTXFEMPMSK` reader - "]
        pub type NptxfempmskR = crate::BitReader;
        #[doc = "Field `NPTXFEMPMSK` writer - "]
        pub type NptxfempmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GINNAKEFFMSK` reader - "]
        pub type GinnakeffmskR = crate::BitReader;
        #[doc = "Field `GINNAKEFFMSK` writer - "]
        pub type GinnakeffmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GOUTNAKEFFMSK` reader - "]
        pub type GoutnakeffmskR = crate::BitReader;
        #[doc = "Field `GOUTNAKEFFMSK` writer - "]
        pub type GoutnakeffmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ULPICKINTMSK` reader - "]
        pub type UlpickintmskR = crate::BitReader;
        #[doc = "Field `ULPICKINTMSK` writer - "]
        pub type UlpickintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `I2CINTMSK` reader - "]
        pub type I2cintmskR = crate::BitReader;
        #[doc = "Field `I2CINTMSK` writer - "]
        pub type I2cintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERLYSUSPMSK` reader - "]
        pub type ErlysuspmskR = crate::BitReader;
        #[doc = "Field `ERLYSUSPMSK` writer - "]
        pub type ErlysuspmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `USBSUSPMSK` reader - "]
        pub type UsbsuspmskR = crate::BitReader;
        #[doc = "Field `USBSUSPMSK` writer - "]
        pub type UsbsuspmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `USBRSTMSK` reader - "]
        pub type UsbrstmskR = crate::BitReader;
        #[doc = "Field `USBRSTMSK` writer - "]
        pub type UsbrstmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ENUMDONEMSK` reader - "]
        pub type EnumdonemskR = crate::BitReader;
        #[doc = "Field `ENUMDONEMSK` writer - "]
        pub type EnumdonemskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ISOOUTDROPMSK` reader - "]
        pub type IsooutdropmskR = crate::BitReader;
        #[doc = "Field `ISOOUTDROPMSK` writer - "]
        pub type IsooutdropmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EOPFMSK` reader - "]
        pub type EopfmskR = crate::BitReader;
        #[doc = "Field `EOPFMSK` writer - "]
        pub type EopfmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EPMISMSK` reader - "]
        pub type EpmismskR = crate::BitReader;
        #[doc = "Field `EPMISMSK` writer - "]
        pub type EpmismskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IEPINTMSK` reader - "]
        pub type IepintmskR = crate::BitReader;
        #[doc = "Field `IEPINTMSK` writer - "]
        pub type IepintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OEPINTMSK` reader - "]
        pub type OepintmskR = crate::BitReader;
        #[doc = "Field `OEPINTMSK` writer - "]
        pub type OepintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INCOMPISOINMSK` reader - "]
        pub type IncompisoinmskR = crate::BitReader;
        #[doc = "Field `INCOMPISOINMSK` writer - "]
        pub type IncompisoinmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INCOMPLPMSK` reader - "]
        pub type IncomplpmskR = crate::BitReader;
        #[doc = "Field `INCOMPLPMSK` writer - "]
        pub type IncomplpmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FETSUSPMSK` reader - "]
        pub type FetsuspmskR = crate::BitReader;
        #[doc = "Field `FETSUSPMSK` writer - "]
        pub type FetsuspmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTINTMSK` reader - "]
        pub type PrtintmskR = crate::BitReader;
        #[doc = "Field `PRTINTMSK` writer - "]
        pub type PrtintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HCHINTMSK` reader - "]
        pub type HchintmskR = crate::BitReader;
        #[doc = "Field `HCHINTMSK` writer - "]
        pub type HchintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PTXFEMPMSK` reader - "]
        pub type PtxfempmskR = crate::BitReader;
        #[doc = "Field `PTXFEMPMSK` writer - "]
        pub type PtxfempmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CONIDSTSCHNGMSK` reader - "]
        pub type ConidstschngmskR = crate::BitReader;
        #[doc = "Field `CONIDSTSCHNGMSK` writer - "]
        pub type ConidstschngmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DISCONNINTMSK` reader - "]
        pub type DisconnintmskR = crate::BitReader;
        #[doc = "Field `DISCONNINTMSK` writer - "]
        pub type DisconnintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SESSREQINTMSK` reader - "]
        pub type SessreqintmskR = crate::BitReader;
        #[doc = "Field `SESSREQINTMSK` writer - "]
        pub type SessreqintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WKUPINTMSK` reader - "]
        pub type WkupintmskR = crate::BitReader;
        #[doc = "Field `WKUPINTMSK` writer - "]
        pub type WkupintmskW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn curmodmsk(&self) -> CurmodmskR {
                CurmodmskR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn modemismsk(&self) -> ModemismskR {
                ModemismskR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn otgintmsk(&self) -> OtgintmskR {
                OtgintmskR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn sofmsk(&self) -> SofmskR {
                SofmskR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn rxflvlmsk(&self) -> RxflvlmskR {
                RxflvlmskR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn nptxfempmsk(&self) -> NptxfempmskR {
                NptxfempmskR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn ginnakeffmsk(&self) -> GinnakeffmskR {
                GinnakeffmskR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn goutnakeffmsk(&self) -> GoutnakeffmskR {
                GoutnakeffmskR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn ulpickintmsk(&self) -> UlpickintmskR {
                UlpickintmskR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn i2cintmsk(&self) -> I2cintmskR {
                I2cintmskR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn erlysuspmsk(&self) -> ErlysuspmskR {
                ErlysuspmskR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn usbsuspmsk(&self) -> UsbsuspmskR {
                UsbsuspmskR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn usbrstmsk(&self) -> UsbrstmskR {
                UsbrstmskR::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13"]
            #[inline(always)]
            pub fn enumdonemsk(&self) -> EnumdonemskR {
                EnumdonemskR::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14"]
            #[inline(always)]
            pub fn isooutdropmsk(&self) -> IsooutdropmskR {
                IsooutdropmskR::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15"]
            #[inline(always)]
            pub fn eopfmsk(&self) -> EopfmskR {
                EopfmskR::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn epmismsk(&self) -> EpmismskR {
                EpmismskR::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn iepintmsk(&self) -> IepintmskR {
                IepintmskR::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn oepintmsk(&self) -> OepintmskR {
                OepintmskR::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn incompisoinmsk(&self) -> IncompisoinmskR {
                IncompisoinmskR::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn incomplpmsk(&self) -> IncomplpmskR {
                IncomplpmskR::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn fetsuspmsk(&self) -> FetsuspmskR {
                FetsuspmskR::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn prtintmsk(&self) -> PrtintmskR {
                PrtintmskR::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25"]
            #[inline(always)]
            pub fn hchintmsk(&self) -> HchintmskR {
                HchintmskR::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn ptxfempmsk(&self) -> PtxfempmskR {
                PtxfempmskR::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 28"]
            #[inline(always)]
            pub fn conidstschngmsk(&self) -> ConidstschngmskR {
                ConidstschngmskR::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29"]
            #[inline(always)]
            pub fn disconnintmsk(&self) -> DisconnintmskR {
                DisconnintmskR::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn sessreqintmsk(&self) -> SessreqintmskR {
                SessreqintmskR::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn wkupintmsk(&self) -> WkupintmskR {
                WkupintmskR::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn curmodmsk(&mut self) -> CurmodmskW<'_, GintmskSpec> {
                CurmodmskW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn modemismsk(&mut self) -> ModemismskW<'_, GintmskSpec> {
                ModemismskW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn otgintmsk(&mut self) -> OtgintmskW<'_, GintmskSpec> {
                OtgintmskW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn sofmsk(&mut self) -> SofmskW<'_, GintmskSpec> {
                SofmskW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn rxflvlmsk(&mut self) -> RxflvlmskW<'_, GintmskSpec> {
                RxflvlmskW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn nptxfempmsk(&mut self) -> NptxfempmskW<'_, GintmskSpec> {
                NptxfempmskW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn ginnakeffmsk(&mut self) -> GinnakeffmskW<'_, GintmskSpec> {
                GinnakeffmskW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn goutnakeffmsk(&mut self) -> GoutnakeffmskW<'_, GintmskSpec> {
                GoutnakeffmskW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn ulpickintmsk(&mut self) -> UlpickintmskW<'_, GintmskSpec> {
                UlpickintmskW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn i2cintmsk(&mut self) -> I2cintmskW<'_, GintmskSpec> {
                I2cintmskW::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn erlysuspmsk(&mut self) -> ErlysuspmskW<'_, GintmskSpec> {
                ErlysuspmskW::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn usbsuspmsk(&mut self) -> UsbsuspmskW<'_, GintmskSpec> {
                UsbsuspmskW::new(self, 11)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn usbrstmsk(&mut self) -> UsbrstmskW<'_, GintmskSpec> {
                UsbrstmskW::new(self, 12)
            }
            #[doc = "Bit 13"]
            #[inline(always)]
            pub fn enumdonemsk(&mut self) -> EnumdonemskW<'_, GintmskSpec> {
                EnumdonemskW::new(self, 13)
            }
            #[doc = "Bit 14"]
            #[inline(always)]
            pub fn isooutdropmsk(&mut self) -> IsooutdropmskW<'_, GintmskSpec> {
                IsooutdropmskW::new(self, 14)
            }
            #[doc = "Bit 15"]
            #[inline(always)]
            pub fn eopfmsk(&mut self) -> EopfmskW<'_, GintmskSpec> {
                EopfmskW::new(self, 15)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn epmismsk(&mut self) -> EpmismskW<'_, GintmskSpec> {
                EpmismskW::new(self, 17)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn iepintmsk(&mut self) -> IepintmskW<'_, GintmskSpec> {
                IepintmskW::new(self, 18)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn oepintmsk(&mut self) -> OepintmskW<'_, GintmskSpec> {
                OepintmskW::new(self, 19)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn incompisoinmsk(&mut self) -> IncompisoinmskW<'_, GintmskSpec> {
                IncompisoinmskW::new(self, 20)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn incomplpmsk(&mut self) -> IncomplpmskW<'_, GintmskSpec> {
                IncomplpmskW::new(self, 21)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn fetsuspmsk(&mut self) -> FetsuspmskW<'_, GintmskSpec> {
                FetsuspmskW::new(self, 22)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn prtintmsk(&mut self) -> PrtintmskW<'_, GintmskSpec> {
                PrtintmskW::new(self, 24)
            }
            #[doc = "Bit 25"]
            #[inline(always)]
            pub fn hchintmsk(&mut self) -> HchintmskW<'_, GintmskSpec> {
                HchintmskW::new(self, 25)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn ptxfempmsk(&mut self) -> PtxfempmskW<'_, GintmskSpec> {
                PtxfempmskW::new(self, 26)
            }
            #[doc = "Bit 28"]
            #[inline(always)]
            pub fn conidstschngmsk(&mut self) -> ConidstschngmskW<'_, GintmskSpec> {
                ConidstschngmskW::new(self, 28)
            }
            #[doc = "Bit 29"]
            #[inline(always)]
            pub fn disconnintmsk(&mut self) -> DisconnintmskW<'_, GintmskSpec> {
                DisconnintmskW::new(self, 29)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn sessreqintmsk(&mut self) -> SessreqintmskW<'_, GintmskSpec> {
                SessreqintmskW::new(self, 30)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn wkupintmsk(&mut self) -> WkupintmskW<'_, GintmskSpec> {
                WkupintmskW::new(self, 31)
            }
        }
        #[doc = "DOTG_GINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`gintmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gintmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GintmskSpec;
        impl crate::RegisterSpec for GintmskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gintmsk::R`](R) reader structure"]
        impl crate::Readable for GintmskSpec {}
        #[doc = "`write(|w| ..)` method takes [`gintmsk::W`](W) writer structure"]
        impl crate::Writable for GintmskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GINTMSK to value 0"]
        impl crate::Resettable for GintmskSpec {}
    }
    #[doc = "GRXSTSRD (rw) register accessor: DOTG_GRXSTSRD\n\nYou can [`read`](crate::Reg::read) this register and get [`grxstsrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxstsrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsrd`] module"]
    #[doc(alias = "GRXSTSRD")]
    pub type Grxstsrd = crate::Reg<grxstsrd::GrxstsrdSpec>;
    #[doc = "DOTG_GRXSTSRD"]
    pub mod grxstsrd {
        #[doc = "Register `GRXSTSRD` reader"]
        pub type R = crate::R<GrxstsrdSpec>;
        #[doc = "Register `GRXSTSRD` writer"]
        pub type W = crate::W<GrxstsrdSpec>;
        #[doc = "Field `CHNUM` reader - "]
        pub type ChnumR = crate::FieldReader;
        #[doc = "Field `CHNUM` writer - "]
        pub type ChnumW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `BCNT` reader - "]
        pub type BcntR = crate::FieldReader<u16>;
        #[doc = "Field `BCNT` writer - "]
        pub type BcntW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
        #[doc = "Field `DPID_DATA2` reader - "]
        pub type DpidData2R = crate::BitReader;
        #[doc = "Field `DPID_DATA2` writer - "]
        pub type DpidData2W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GLOB_OUT_NAK` reader - "]
        pub type GlobOutNakR = crate::BitReader;
        #[doc = "Field `GLOB_OUT_NAK` writer - "]
        pub type GlobOutNakW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FN` reader - "]
        pub type FnR = crate::FieldReader;
        #[doc = "Field `FN` writer - "]
        pub type FnW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn chnum(&self) -> ChnumR {
                ChnumR::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:14"]
            #[inline(always)]
            pub fn bcnt(&self) -> BcntR {
                BcntR::new(((self.bits >> 4) & 0x07ff) as u16)
            }
            #[doc = "Bit 15"]
            #[inline(always)]
            pub fn dpid_data2(&self) -> DpidData2R {
                DpidData2R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn glob_out_nak(&self) -> GlobOutNakR {
                GlobOutNakR::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bits 21:24"]
            #[inline(always)]
            pub fn fn_(&self) -> FnR {
                FnR::new(((self.bits >> 21) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn chnum(&mut self) -> ChnumW<'_, GrxstsrdSpec> {
                ChnumW::new(self, 0)
            }
            #[doc = "Bits 4:14"]
            #[inline(always)]
            pub fn bcnt(&mut self) -> BcntW<'_, GrxstsrdSpec> {
                BcntW::new(self, 4)
            }
            #[doc = "Bit 15"]
            #[inline(always)]
            pub fn dpid_data2(&mut self) -> DpidData2W<'_, GrxstsrdSpec> {
                DpidData2W::new(self, 15)
            }
            #[doc = "Bit 17"]
            #[inline(always)]
            pub fn glob_out_nak(&mut self) -> GlobOutNakW<'_, GrxstsrdSpec> {
                GlobOutNakW::new(self, 17)
            }
            #[doc = "Bits 21:24"]
            #[inline(always)]
            pub fn fn_(&mut self) -> FnW<'_, GrxstsrdSpec> {
                FnW::new(self, 21)
            }
        }
        #[doc = "DOTG_GRXSTSRD\n\nYou can [`read`](crate::Reg::read) this register and get [`grxstsrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxstsrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GrxstsrdSpec;
        impl crate::RegisterSpec for GrxstsrdSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`grxstsrd::R`](R) reader structure"]
        impl crate::Readable for GrxstsrdSpec {}
        #[doc = "`write(|w| ..)` method takes [`grxstsrd::W`](W) writer structure"]
        impl crate::Writable for GrxstsrdSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GRXSTSRD to value 0"]
        impl crate::Resettable for GrxstsrdSpec {}
    }
    #[doc = "GRXSTSPD (rw) register accessor: DOTG_GRXSTSPD\n\nYou can [`read`](crate::Reg::read) this register and get [`grxstspd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxstspd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstspd`] module"]
    #[doc(alias = "GRXSTSPD")]
    pub type Grxstspd = crate::Reg<grxstspd::GrxstspdSpec>;
    #[doc = "DOTG_GRXSTSPD"]
    pub mod grxstspd {
        #[doc = "Register `GRXSTSPD` reader"]
        pub type R = crate::R<GrxstspdSpec>;
        #[doc = "Register `GRXSTSPD` writer"]
        pub type W = crate::W<GrxstspdSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_GRXSTSPD\n\nYou can [`read`](crate::Reg::read) this register and get [`grxstspd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxstspd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GrxstspdSpec;
        impl crate::RegisterSpec for GrxstspdSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`grxstspd::R`](R) reader structure"]
        impl crate::Readable for GrxstspdSpec {}
        #[doc = "`write(|w| ..)` method takes [`grxstspd::W`](W) writer structure"]
        impl crate::Writable for GrxstspdSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GRXSTSPD to value 0"]
        impl crate::Resettable for GrxstspdSpec {}
    }
    #[doc = "GRXFSIZ (rw) register accessor: DOTG_GRXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`grxfsiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxfsiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxfsiz`] module"]
    #[doc(alias = "GRXFSIZ")]
    pub type Grxfsiz = crate::Reg<grxfsiz::GrxfsizSpec>;
    #[doc = "DOTG_GRXFSIZ"]
    pub mod grxfsiz {
        #[doc = "Register `GRXFSIZ` reader"]
        pub type R = crate::R<GrxfsizSpec>;
        #[doc = "Register `GRXFSIZ` writer"]
        pub type W = crate::W<GrxfsizSpec>;
        #[doc = "Field `RXFDEP` reader - "]
        pub type RxfdepR = crate::FieldReader<u16>;
        #[doc = "Field `RXFDEP` writer - "]
        pub type RxfdepW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn rxfdep(&self) -> RxfdepR {
                RxfdepR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn rxfdep(&mut self) -> RxfdepW<'_, GrxfsizSpec> {
                RxfdepW::new(self, 0)
            }
        }
        #[doc = "DOTG_GRXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`grxfsiz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grxfsiz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GrxfsizSpec;
        impl crate::RegisterSpec for GrxfsizSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`grxfsiz::R`](R) reader structure"]
        impl crate::Readable for GrxfsizSpec {}
        #[doc = "`write(|w| ..)` method takes [`grxfsiz::W`](W) writer structure"]
        impl crate::Writable for GrxfsizSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GRXFSIZ to value 0"]
        impl crate::Resettable for GrxfsizSpec {}
    }
    #[doc = "GNPTXFSIZ (rw) register accessor: DOTG_GNPTXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`gnptxfsiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gnptxfsiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxfsiz`] module"]
    #[doc(alias = "GNPTXFSIZ")]
    pub type Gnptxfsiz = crate::Reg<gnptxfsiz::GnptxfsizSpec>;
    #[doc = "DOTG_GNPTXFSIZ"]
    pub mod gnptxfsiz {
        #[doc = "Register `GNPTXFSIZ` reader"]
        pub type R = crate::R<GnptxfsizSpec>;
        #[doc = "Register `GNPTXFSIZ` writer"]
        pub type W = crate::W<GnptxfsizSpec>;
        #[doc = "Field `NPTXFDEP` reader - "]
        pub type NptxfdepR = crate::FieldReader<u16>;
        #[doc = "Field `NPTXFDEP` writer - "]
        pub type NptxfdepW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn nptxfdep(&self) -> NptxfdepR {
                NptxfdepR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn nptxfdep(&mut self) -> NptxfdepW<'_, GnptxfsizSpec> {
                NptxfdepW::new(self, 0)
            }
        }
        #[doc = "DOTG_GNPTXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`gnptxfsiz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gnptxfsiz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GnptxfsizSpec;
        impl crate::RegisterSpec for GnptxfsizSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gnptxfsiz::R`](R) reader structure"]
        impl crate::Readable for GnptxfsizSpec {}
        #[doc = "`write(|w| ..)` method takes [`gnptxfsiz::W`](W) writer structure"]
        impl crate::Writable for GnptxfsizSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GNPTXFSIZ to value 0"]
        impl crate::Resettable for GnptxfsizSpec {}
    }
    #[doc = "GNPTXSTS (rw) register accessor: DOTG_GNPTXSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`gnptxsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gnptxsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxsts`] module"]
    #[doc(alias = "GNPTXSTS")]
    pub type Gnptxsts = crate::Reg<gnptxsts::GnptxstsSpec>;
    #[doc = "DOTG_GNPTXSTS"]
    pub mod gnptxsts {
        #[doc = "Register `GNPTXSTS` reader"]
        pub type R = crate::R<GnptxstsSpec>;
        #[doc = "Register `GNPTXSTS` writer"]
        pub type W = crate::W<GnptxstsSpec>;
        #[doc = "Field `NPTXFSPCAVAIL` reader - "]
        pub type NptxfspcavailR = crate::FieldReader<u16>;
        #[doc = "Field `NPTXFSPCAVAIL` writer - "]
        pub type NptxfspcavailW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `NPTXQSPCAVAIL` reader - "]
        pub type NptxqspcavailR = crate::FieldReader;
        #[doc = "Field `NPTXQSPCAVAIL` writer - "]
        pub type NptxqspcavailW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `NPTXQTOP` reader - "]
        pub type NptxqtopR = crate::FieldReader;
        #[doc = "Field `NPTXQTOP` writer - "]
        pub type NptxqtopW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn nptxfspcavail(&self) -> NptxfspcavailR {
                NptxfspcavailR::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:23"]
            #[inline(always)]
            pub fn nptxqspcavail(&self) -> NptxqspcavailR {
                NptxqspcavailR::new(((self.bits >> 16) & 0xff) as u8)
            }
            #[doc = "Bits 24:30"]
            #[inline(always)]
            pub fn nptxqtop(&self) -> NptxqtopR {
                NptxqtopR::new(((self.bits >> 24) & 0x7f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn nptxfspcavail(&mut self) -> NptxfspcavailW<'_, GnptxstsSpec> {
                NptxfspcavailW::new(self, 0)
            }
            #[doc = "Bits 16:23"]
            #[inline(always)]
            pub fn nptxqspcavail(&mut self) -> NptxqspcavailW<'_, GnptxstsSpec> {
                NptxqspcavailW::new(self, 16)
            }
            #[doc = "Bits 24:30"]
            #[inline(always)]
            pub fn nptxqtop(&mut self) -> NptxqtopW<'_, GnptxstsSpec> {
                NptxqtopW::new(self, 24)
            }
        }
        #[doc = "DOTG_GNPTXSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`gnptxsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gnptxsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GnptxstsSpec;
        impl crate::RegisterSpec for GnptxstsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gnptxsts::R`](R) reader structure"]
        impl crate::Readable for GnptxstsSpec {}
        #[doc = "`write(|w| ..)` method takes [`gnptxsts::W`](W) writer structure"]
        impl crate::Writable for GnptxstsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GNPTXSTS to value 0"]
        impl crate::Resettable for GnptxstsSpec {}
    }
    #[doc = "GI2CCTL (rw) register accessor: DOTG_GI2CCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gi2cctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gi2cctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gi2cctl`] module"]
    #[doc(alias = "GI2CCTL")]
    pub type Gi2cctl = crate::Reg<gi2cctl::Gi2cctlSpec>;
    #[doc = "DOTG_GI2CCTL"]
    pub mod gi2cctl {
        #[doc = "Register `GI2CCTL` reader"]
        pub type R = crate::R<Gi2cctlSpec>;
        #[doc = "Register `GI2CCTL` writer"]
        pub type W = crate::W<Gi2cctlSpec>;
        #[doc = "Field `RWDATA` reader - "]
        pub type RwdataR = crate::FieldReader;
        #[doc = "Field `RWDATA` writer - "]
        pub type RwdataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `REGADDR` reader - "]
        pub type RegaddrR = crate::FieldReader;
        #[doc = "Field `REGADDR` writer - "]
        pub type RegaddrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `ADDR` reader - "]
        pub type AddrR = crate::FieldReader;
        #[doc = "Field `ADDR` writer - "]
        pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `I2CEN` reader - "]
        pub type I2cenR = crate::BitReader;
        #[doc = "Field `I2CEN` writer - "]
        pub type I2cenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACK` reader - "]
        pub type AckR = crate::BitReader;
        #[doc = "Field `ACK` writer - "]
        pub type AckW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `I2CSUSPCTL` reader - "]
        pub type I2csuspctlR = crate::BitReader;
        #[doc = "Field `I2CSUSPCTL` writer - "]
        pub type I2csuspctlW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `I2CDEVADR` reader - "]
        pub type I2cdevadrR = crate::FieldReader;
        #[doc = "Field `I2CDEVADR` writer - "]
        pub type I2cdevadrW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `I2CDATSE0` reader - "]
        pub type I2cdatse0R = crate::BitReader;
        #[doc = "Field `I2CDATSE0` writer - "]
        pub type I2cdatse0W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RW` reader - "]
        pub type RwR = crate::BitReader;
        #[doc = "Field `RW` writer - "]
        pub type RwW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BSYDNE_SC` reader - "]
        pub type BsydneScR = crate::BitReader;
        #[doc = "Field `BSYDNE_SC` writer - "]
        pub type BsydneScW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn rwdata(&self) -> RwdataR {
                RwdataR::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15"]
            #[inline(always)]
            pub fn regaddr(&self) -> RegaddrR {
                RegaddrR::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:22"]
            #[inline(always)]
            pub fn addr(&self) -> AddrR {
                AddrR::new(((self.bits >> 16) & 0x7f) as u8)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn i2cen(&self) -> I2cenR {
                I2cenR::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn ack(&self) -> AckR {
                AckR::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25"]
            #[inline(always)]
            pub fn i2csuspctl(&self) -> I2csuspctlR {
                I2csuspctlR::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bits 26:27"]
            #[inline(always)]
            pub fn i2cdevadr(&self) -> I2cdevadrR {
                I2cdevadrR::new(((self.bits >> 26) & 3) as u8)
            }
            #[doc = "Bit 28"]
            #[inline(always)]
            pub fn i2cdatse0(&self) -> I2cdatse0R {
                I2cdatse0R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn rw(&self) -> RwR {
                RwR::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn bsydne_sc(&self) -> BsydneScR {
                BsydneScR::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn rwdata(&mut self) -> RwdataW<'_, Gi2cctlSpec> {
                RwdataW::new(self, 0)
            }
            #[doc = "Bits 8:15"]
            #[inline(always)]
            pub fn regaddr(&mut self) -> RegaddrW<'_, Gi2cctlSpec> {
                RegaddrW::new(self, 8)
            }
            #[doc = "Bits 16:22"]
            #[inline(always)]
            pub fn addr(&mut self) -> AddrW<'_, Gi2cctlSpec> {
                AddrW::new(self, 16)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn i2cen(&mut self) -> I2cenW<'_, Gi2cctlSpec> {
                I2cenW::new(self, 23)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn ack(&mut self) -> AckW<'_, Gi2cctlSpec> {
                AckW::new(self, 24)
            }
            #[doc = "Bit 25"]
            #[inline(always)]
            pub fn i2csuspctl(&mut self) -> I2csuspctlW<'_, Gi2cctlSpec> {
                I2csuspctlW::new(self, 25)
            }
            #[doc = "Bits 26:27"]
            #[inline(always)]
            pub fn i2cdevadr(&mut self) -> I2cdevadrW<'_, Gi2cctlSpec> {
                I2cdevadrW::new(self, 26)
            }
            #[doc = "Bit 28"]
            #[inline(always)]
            pub fn i2cdatse0(&mut self) -> I2cdatse0W<'_, Gi2cctlSpec> {
                I2cdatse0W::new(self, 28)
            }
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn rw(&mut self) -> RwW<'_, Gi2cctlSpec> {
                RwW::new(self, 30)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn bsydne_sc(&mut self) -> BsydneScW<'_, Gi2cctlSpec> {
                BsydneScW::new(self, 31)
            }
        }
        #[doc = "DOTG_GI2CCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gi2cctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gi2cctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct Gi2cctlSpec;
        impl crate::RegisterSpec for Gi2cctlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gi2cctl::R`](R) reader structure"]
        impl crate::Readable for Gi2cctlSpec {}
        #[doc = "`write(|w| ..)` method takes [`gi2cctl::W`](W) writer structure"]
        impl crate::Writable for Gi2cctlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GI2CCTL to value 0"]
        impl crate::Resettable for Gi2cctlSpec {}
    }
    #[doc = "GPVNDCTL (rw) register accessor: DOTG_GPVNDCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gpvndctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpvndctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpvndctl`] module"]
    #[doc(alias = "GPVNDCTL")]
    pub type Gpvndctl = crate::Reg<gpvndctl::GpvndctlSpec>;
    #[doc = "DOTG_GPVNDCTL"]
    pub mod gpvndctl {
        #[doc = "Register `GPVNDCTL` reader"]
        pub type R = crate::R<GpvndctlSpec>;
        #[doc = "Register `GPVNDCTL` writer"]
        pub type W = crate::W<GpvndctlSpec>;
        #[doc = "Field `REGDATA` reader - "]
        pub type RegdataR = crate::FieldReader;
        #[doc = "Field `REGDATA` writer - "]
        pub type RegdataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `VCTRL` reader - "]
        pub type VctrlR = crate::FieldReader;
        #[doc = "Field `VCTRL` writer - "]
        pub type VctrlW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `REGADDR` reader - "]
        pub type RegaddrR = crate::FieldReader;
        #[doc = "Field `REGADDR` writer - "]
        pub type RegaddrW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `REGWR` reader - "]
        pub type RegwrR = crate::BitReader;
        #[doc = "Field `REGWR` writer - "]
        pub type RegwrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NEWREGREQ` reader - "]
        pub type NewregreqR = crate::BitReader;
        #[doc = "Field `NEWREGREQ` writer - "]
        pub type NewregreqW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `VSTSBSY` reader - "]
        pub type VstsbsyR = crate::BitReader;
        #[doc = "Field `VSTSBSY` writer - "]
        pub type VstsbsyW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `VSTSDONE` reader - "]
        pub type VstsdoneR = crate::BitReader;
        #[doc = "Field `VSTSDONE` writer - "]
        pub type VstsdoneW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DISULPIDRVR` reader - "]
        pub type DisulpidrvrR = crate::BitReader;
        #[doc = "Field `DISULPIDRVR` writer - "]
        pub type DisulpidrvrW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn regdata(&self) -> RegdataR {
                RegdataR::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15"]
            #[inline(always)]
            pub fn vctrl(&self) -> VctrlR {
                VctrlR::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:21"]
            #[inline(always)]
            pub fn regaddr(&self) -> RegaddrR {
                RegaddrR::new(((self.bits >> 16) & 0x3f) as u8)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn regwr(&self) -> RegwrR {
                RegwrR::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 25"]
            #[inline(always)]
            pub fn newregreq(&self) -> NewregreqR {
                NewregreqR::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn vstsbsy(&self) -> VstsbsyR {
                VstsbsyR::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn vstsdone(&self) -> VstsdoneR {
                VstsdoneR::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn disulpidrvr(&self) -> DisulpidrvrR {
                DisulpidrvrR::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:7"]
            #[inline(always)]
            pub fn regdata(&mut self) -> RegdataW<'_, GpvndctlSpec> {
                RegdataW::new(self, 0)
            }
            #[doc = "Bits 8:15"]
            #[inline(always)]
            pub fn vctrl(&mut self) -> VctrlW<'_, GpvndctlSpec> {
                VctrlW::new(self, 8)
            }
            #[doc = "Bits 16:21"]
            #[inline(always)]
            pub fn regaddr(&mut self) -> RegaddrW<'_, GpvndctlSpec> {
                RegaddrW::new(self, 16)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn regwr(&mut self) -> RegwrW<'_, GpvndctlSpec> {
                RegwrW::new(self, 22)
            }
            #[doc = "Bit 25"]
            #[inline(always)]
            pub fn newregreq(&mut self) -> NewregreqW<'_, GpvndctlSpec> {
                NewregreqW::new(self, 25)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn vstsbsy(&mut self) -> VstsbsyW<'_, GpvndctlSpec> {
                VstsbsyW::new(self, 26)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn vstsdone(&mut self) -> VstsdoneW<'_, GpvndctlSpec> {
                VstsdoneW::new(self, 27)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn disulpidrvr(&mut self) -> DisulpidrvrW<'_, GpvndctlSpec> {
                DisulpidrvrW::new(self, 31)
            }
        }
        #[doc = "DOTG_GPVNDCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gpvndctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpvndctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpvndctlSpec;
        impl crate::RegisterSpec for GpvndctlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpvndctl::R`](R) reader structure"]
        impl crate::Readable for GpvndctlSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpvndctl::W`](W) writer structure"]
        impl crate::Writable for GpvndctlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPVNDCTL to value 0"]
        impl crate::Resettable for GpvndctlSpec {}
    }
    #[doc = "GGPIO (rw) register accessor: DOTG_GGPIO\n\nYou can [`read`](crate::Reg::read) this register and get [`ggpio::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ggpio::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ggpio`] module"]
    #[doc(alias = "GGPIO")]
    pub type Ggpio = crate::Reg<ggpio::GgpioSpec>;
    #[doc = "DOTG_GGPIO"]
    pub mod ggpio {
        #[doc = "Register `GGPIO` reader"]
        pub type R = crate::R<GgpioSpec>;
        #[doc = "Register `GGPIO` writer"]
        pub type W = crate::W<GgpioSpec>;
        #[doc = "Field `GPI` reader - "]
        pub type GpiR = crate::FieldReader<u16>;
        #[doc = "Field `GPI` writer - "]
        pub type GpiW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `GPO` reader - "]
        pub type GpoR = crate::FieldReader<u16>;
        #[doc = "Field `GPO` writer - "]
        pub type GpoW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn gpi(&self) -> GpiR {
                GpiR::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31"]
            #[inline(always)]
            pub fn gpo(&self) -> GpoR {
                GpoR::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn gpi(&mut self) -> GpiW<'_, GgpioSpec> {
                GpiW::new(self, 0)
            }
            #[doc = "Bits 16:31"]
            #[inline(always)]
            pub fn gpo(&mut self) -> GpoW<'_, GgpioSpec> {
                GpoW::new(self, 16)
            }
        }
        #[doc = "DOTG_GGPIO\n\nYou can [`read`](crate::Reg::read) this register and get [`ggpio::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ggpio::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GgpioSpec;
        impl crate::RegisterSpec for GgpioSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ggpio::R`](R) reader structure"]
        impl crate::Readable for GgpioSpec {}
        #[doc = "`write(|w| ..)` method takes [`ggpio::W`](W) writer structure"]
        impl crate::Writable for GgpioSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GGPIO to value 0"]
        impl crate::Resettable for GgpioSpec {}
    }
    #[doc = "GUID (rw) register accessor: DOTG_GUID\n\nYou can [`read`](crate::Reg::read) this register and get [`guid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`guid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@guid`] module"]
    #[doc(alias = "GUID")]
    pub type Guid = crate::Reg<guid::GuidSpec>;
    #[doc = "DOTG_GUID"]
    pub mod guid {
        #[doc = "Register `GUID` reader"]
        pub type R = crate::R<GuidSpec>;
        #[doc = "Register `GUID` writer"]
        pub type W = crate::W<GuidSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_GUID\n\nYou can [`read`](crate::Reg::read) this register and get [`guid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`guid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GuidSpec;
        impl crate::RegisterSpec for GuidSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`guid::R`](R) reader structure"]
        impl crate::Readable for GuidSpec {}
        #[doc = "`write(|w| ..)` method takes [`guid::W`](W) writer structure"]
        impl crate::Writable for GuidSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GUID to value 0"]
        impl crate::Resettable for GuidSpec {}
    }
    #[doc = "GSNPSID (rw) register accessor: DOTG_GSNPSID\n\nYou can [`read`](crate::Reg::read) this register and get [`gsnpsid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gsnpsid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gsnpsid`] module"]
    #[doc(alias = "GSNPSID")]
    pub type Gsnpsid = crate::Reg<gsnpsid::GsnpsidSpec>;
    #[doc = "DOTG_GSNPSID"]
    pub mod gsnpsid {
        #[doc = "Register `GSNPSID` reader"]
        pub type R = crate::R<GsnpsidSpec>;
        #[doc = "Register `GSNPSID` writer"]
        pub type W = crate::W<GsnpsidSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_GSNPSID\n\nYou can [`read`](crate::Reg::read) this register and get [`gsnpsid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gsnpsid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GsnpsidSpec;
        impl crate::RegisterSpec for GsnpsidSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gsnpsid::R`](R) reader structure"]
        impl crate::Readable for GsnpsidSpec {}
        #[doc = "`write(|w| ..)` method takes [`gsnpsid::W`](W) writer structure"]
        impl crate::Writable for GsnpsidSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GSNPSID to value 0"]
        impl crate::Resettable for GsnpsidSpec {}
    }
    #[doc = "GHWCFG1 (rw) register accessor: DOTG_GHWCFG1\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ghwcfg1`] module"]
    #[doc(alias = "GHWCFG1")]
    pub type Ghwcfg1 = crate::Reg<ghwcfg1::Ghwcfg1Spec>;
    #[doc = "DOTG_GHWCFG1"]
    pub mod ghwcfg1 {
        #[doc = "Register `GHWCFG1` reader"]
        pub type R = crate::R<Ghwcfg1Spec>;
        #[doc = "Register `GHWCFG1` writer"]
        pub type W = crate::W<Ghwcfg1Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_GHWCFG1\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct Ghwcfg1Spec;
        impl crate::RegisterSpec for Ghwcfg1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ghwcfg1::R`](R) reader structure"]
        impl crate::Readable for Ghwcfg1Spec {}
        #[doc = "`write(|w| ..)` method takes [`ghwcfg1::W`](W) writer structure"]
        impl crate::Writable for Ghwcfg1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GHWCFG1 to value 0"]
        impl crate::Resettable for Ghwcfg1Spec {}
    }
    #[doc = "GHWCFG2 (rw) register accessor: DOTG_GHWCFG2\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ghwcfg2`] module"]
    #[doc(alias = "GHWCFG2")]
    pub type Ghwcfg2 = crate::Reg<ghwcfg2::Ghwcfg2Spec>;
    #[doc = "DOTG_GHWCFG2"]
    pub mod ghwcfg2 {
        #[doc = "Register `GHWCFG2` reader"]
        pub type R = crate::R<Ghwcfg2Spec>;
        #[doc = "Register `GHWCFG2` writer"]
        pub type W = crate::W<Ghwcfg2Spec>;
        #[doc = "Field `OTGMODE` reader - "]
        pub type OtgmodeR = crate::FieldReader;
        #[doc = "Field `OTGMODE` writer - "]
        pub type OtgmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `OTGARCH` reader - "]
        pub type OtgarchR = crate::FieldReader;
        #[doc = "Field `OTGARCH` writer - "]
        pub type OtgarchW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `SINGPNT` reader - "]
        pub type SingpntR = crate::BitReader;
        #[doc = "Field `SINGPNT` writer - "]
        pub type SingpntW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HSPHYTYPE` reader - "]
        pub type HsphytypeR = crate::FieldReader;
        #[doc = "Field `HSPHYTYPE` writer - "]
        pub type HsphytypeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `FSPHYTYPE` reader - "]
        pub type FsphytypeR = crate::FieldReader;
        #[doc = "Field `FSPHYTYPE` writer - "]
        pub type FsphytypeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `NUMDEVEPS` reader - "]
        pub type NumdevepsR = crate::FieldReader;
        #[doc = "Field `NUMDEVEPS` writer - "]
        pub type NumdevepsW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `NUMHSTCHNL` reader - "]
        pub type NumhstchnlR = crate::FieldReader;
        #[doc = "Field `NUMHSTCHNL` writer - "]
        pub type NumhstchnlW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `PERIOSUPPORT` reader - "]
        pub type PeriosupportR = crate::BitReader;
        #[doc = "Field `PERIOSUPPORT` writer - "]
        pub type PeriosupportW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DYNFIFOSIZING` reader - "]
        pub type DynfifosizingR = crate::BitReader;
        #[doc = "Field `DYNFIFOSIZING` writer - "]
        pub type DynfifosizingW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MPI` reader - "]
        pub type MpiR = crate::BitReader;
        #[doc = "Field `MPI` writer - "]
        pub type MpiW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NPTXQDEPTH` reader - "]
        pub type NptxqdepthR = crate::FieldReader;
        #[doc = "Field `NPTXQDEPTH` writer - "]
        pub type NptxqdepthW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PTXQDEPTH` reader - "]
        pub type PtxqdepthR = crate::FieldReader;
        #[doc = "Field `PTXQDEPTH` writer - "]
        pub type PtxqdepthW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `TKNQDEPTH` reader - "]
        pub type TknqdepthR = crate::FieldReader;
        #[doc = "Field `TKNQDEPTH` writer - "]
        pub type TknqdepthW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn otgmode(&self) -> OtgmodeR {
                OtgmodeR::new((self.bits & 7) as u8)
            }
            #[doc = "Bits 3:4"]
            #[inline(always)]
            pub fn otgarch(&self) -> OtgarchR {
                OtgarchR::new(((self.bits >> 3) & 3) as u8)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn singpnt(&self) -> SingpntR {
                SingpntR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bits 6:7"]
            #[inline(always)]
            pub fn hsphytype(&self) -> HsphytypeR {
                HsphytypeR::new(((self.bits >> 6) & 3) as u8)
            }
            #[doc = "Bits 8:9"]
            #[inline(always)]
            pub fn fsphytype(&self) -> FsphytypeR {
                FsphytypeR::new(((self.bits >> 8) & 3) as u8)
            }
            #[doc = "Bits 10:13"]
            #[inline(always)]
            pub fn numdeveps(&self) -> NumdevepsR {
                NumdevepsR::new(((self.bits >> 10) & 0x0f) as u8)
            }
            #[doc = "Bits 14:17"]
            #[inline(always)]
            pub fn numhstchnl(&self) -> NumhstchnlR {
                NumhstchnlR::new(((self.bits >> 14) & 0x0f) as u8)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn periosupport(&self) -> PeriosupportR {
                PeriosupportR::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn dynfifosizing(&self) -> DynfifosizingR {
                DynfifosizingR::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn mpi(&self) -> MpiR {
                MpiR::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bits 22:23"]
            #[inline(always)]
            pub fn nptxqdepth(&self) -> NptxqdepthR {
                NptxqdepthR::new(((self.bits >> 22) & 3) as u8)
            }
            #[doc = "Bits 24:25"]
            #[inline(always)]
            pub fn ptxqdepth(&self) -> PtxqdepthR {
                PtxqdepthR::new(((self.bits >> 24) & 3) as u8)
            }
            #[doc = "Bits 26:30"]
            #[inline(always)]
            pub fn tknqdepth(&self) -> TknqdepthR {
                TknqdepthR::new(((self.bits >> 26) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2"]
            #[inline(always)]
            pub fn otgmode(&mut self) -> OtgmodeW<'_, Ghwcfg2Spec> {
                OtgmodeW::new(self, 0)
            }
            #[doc = "Bits 3:4"]
            #[inline(always)]
            pub fn otgarch(&mut self) -> OtgarchW<'_, Ghwcfg2Spec> {
                OtgarchW::new(self, 3)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn singpnt(&mut self) -> SingpntW<'_, Ghwcfg2Spec> {
                SingpntW::new(self, 5)
            }
            #[doc = "Bits 6:7"]
            #[inline(always)]
            pub fn hsphytype(&mut self) -> HsphytypeW<'_, Ghwcfg2Spec> {
                HsphytypeW::new(self, 6)
            }
            #[doc = "Bits 8:9"]
            #[inline(always)]
            pub fn fsphytype(&mut self) -> FsphytypeW<'_, Ghwcfg2Spec> {
                FsphytypeW::new(self, 8)
            }
            #[doc = "Bits 10:13"]
            #[inline(always)]
            pub fn numdeveps(&mut self) -> NumdevepsW<'_, Ghwcfg2Spec> {
                NumdevepsW::new(self, 10)
            }
            #[doc = "Bits 14:17"]
            #[inline(always)]
            pub fn numhstchnl(&mut self) -> NumhstchnlW<'_, Ghwcfg2Spec> {
                NumhstchnlW::new(self, 14)
            }
            #[doc = "Bit 18"]
            #[inline(always)]
            pub fn periosupport(&mut self) -> PeriosupportW<'_, Ghwcfg2Spec> {
                PeriosupportW::new(self, 18)
            }
            #[doc = "Bit 19"]
            #[inline(always)]
            pub fn dynfifosizing(&mut self) -> DynfifosizingW<'_, Ghwcfg2Spec> {
                DynfifosizingW::new(self, 19)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn mpi(&mut self) -> MpiW<'_, Ghwcfg2Spec> {
                MpiW::new(self, 20)
            }
            #[doc = "Bits 22:23"]
            #[inline(always)]
            pub fn nptxqdepth(&mut self) -> NptxqdepthW<'_, Ghwcfg2Spec> {
                NptxqdepthW::new(self, 22)
            }
            #[doc = "Bits 24:25"]
            #[inline(always)]
            pub fn ptxqdepth(&mut self) -> PtxqdepthW<'_, Ghwcfg2Spec> {
                PtxqdepthW::new(self, 24)
            }
            #[doc = "Bits 26:30"]
            #[inline(always)]
            pub fn tknqdepth(&mut self) -> TknqdepthW<'_, Ghwcfg2Spec> {
                TknqdepthW::new(self, 26)
            }
        }
        #[doc = "DOTG_GHWCFG2\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct Ghwcfg2Spec;
        impl crate::RegisterSpec for Ghwcfg2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ghwcfg2::R`](R) reader structure"]
        impl crate::Readable for Ghwcfg2Spec {}
        #[doc = "`write(|w| ..)` method takes [`ghwcfg2::W`](W) writer structure"]
        impl crate::Writable for Ghwcfg2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GHWCFG2 to value 0"]
        impl crate::Resettable for Ghwcfg2Spec {}
    }
    #[doc = "GHWCFG3 (rw) register accessor: DOTG_GHWCFG3\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ghwcfg3`] module"]
    #[doc(alias = "GHWCFG3")]
    pub type Ghwcfg3 = crate::Reg<ghwcfg3::Ghwcfg3Spec>;
    #[doc = "DOTG_GHWCFG3"]
    pub mod ghwcfg3 {
        #[doc = "Register `GHWCFG3` reader"]
        pub type R = crate::R<Ghwcfg3Spec>;
        #[doc = "Register `GHWCFG3` writer"]
        pub type W = crate::W<Ghwcfg3Spec>;
        #[doc = "Field `XFERSIZEWIDTH` reader - "]
        pub type XfersizewidthR = crate::FieldReader;
        #[doc = "Field `XFERSIZEWIDTH` writer - "]
        pub type XfersizewidthW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `PKTSIZEWIDTH` reader - "]
        pub type PktsizewidthR = crate::FieldReader;
        #[doc = "Field `PKTSIZEWIDTH` writer - "]
        pub type PktsizewidthW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `OTGEN` reader - "]
        pub type OtgenR = crate::BitReader;
        #[doc = "Field `OTGEN` writer - "]
        pub type OtgenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `I2CINTSEL` reader - "]
        pub type I2cintselR = crate::BitReader;
        #[doc = "Field `I2CINTSEL` writer - "]
        pub type I2cintselW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `VNDCTLSUPT` reader - "]
        pub type VndctlsuptR = crate::BitReader;
        #[doc = "Field `VNDCTLSUPT` writer - "]
        pub type VndctlsuptW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OPTFEATURE` reader - "]
        pub type OptfeatureR = crate::BitReader;
        #[doc = "Field `OPTFEATURE` writer - "]
        pub type OptfeatureW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RSTTYPE` reader - "]
        pub type RsttypeR = crate::BitReader;
        #[doc = "Field `RSTTYPE` writer - "]
        pub type RsttypeW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DFIFODEPTH` reader - "]
        pub type DfifodepthR = crate::FieldReader<u16>;
        #[doc = "Field `DFIFODEPTH` writer - "]
        pub type DfifodepthW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn xfersizewidth(&self) -> XfersizewidthR {
                XfersizewidthR::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:6"]
            #[inline(always)]
            pub fn pktsizewidth(&self) -> PktsizewidthR {
                PktsizewidthR::new(((self.bits >> 4) & 7) as u8)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn otgen(&self) -> OtgenR {
                OtgenR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn i2cintsel(&self) -> I2cintselR {
                I2cintselR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn vndctlsupt(&self) -> VndctlsuptR {
                VndctlsuptR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn optfeature(&self) -> OptfeatureR {
                OptfeatureR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn rsttype(&self) -> RsttypeR {
                RsttypeR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bits 16:31"]
            #[inline(always)]
            pub fn dfifodepth(&self) -> DfifodepthR {
                DfifodepthR::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn xfersizewidth(&mut self) -> XfersizewidthW<'_, Ghwcfg3Spec> {
                XfersizewidthW::new(self, 0)
            }
            #[doc = "Bits 4:6"]
            #[inline(always)]
            pub fn pktsizewidth(&mut self) -> PktsizewidthW<'_, Ghwcfg3Spec> {
                PktsizewidthW::new(self, 4)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn otgen(&mut self) -> OtgenW<'_, Ghwcfg3Spec> {
                OtgenW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn i2cintsel(&mut self) -> I2cintselW<'_, Ghwcfg3Spec> {
                I2cintselW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn vndctlsupt(&mut self) -> VndctlsuptW<'_, Ghwcfg3Spec> {
                VndctlsuptW::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn optfeature(&mut self) -> OptfeatureW<'_, Ghwcfg3Spec> {
                OptfeatureW::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn rsttype(&mut self) -> RsttypeW<'_, Ghwcfg3Spec> {
                RsttypeW::new(self, 11)
            }
            #[doc = "Bits 16:31"]
            #[inline(always)]
            pub fn dfifodepth(&mut self) -> DfifodepthW<'_, Ghwcfg3Spec> {
                DfifodepthW::new(self, 16)
            }
        }
        #[doc = "DOTG_GHWCFG3\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct Ghwcfg3Spec;
        impl crate::RegisterSpec for Ghwcfg3Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ghwcfg3::R`](R) reader structure"]
        impl crate::Readable for Ghwcfg3Spec {}
        #[doc = "`write(|w| ..)` method takes [`ghwcfg3::W`](W) writer structure"]
        impl crate::Writable for Ghwcfg3Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GHWCFG3 to value 0"]
        impl crate::Resettable for Ghwcfg3Spec {}
    }
    #[doc = "GHWCFG4 (rw) register accessor: DOTG_GHWCFG4\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ghwcfg4`] module"]
    #[doc(alias = "GHWCFG4")]
    pub type Ghwcfg4 = crate::Reg<ghwcfg4::Ghwcfg4Spec>;
    #[doc = "DOTG_GHWCFG4"]
    pub mod ghwcfg4 {
        #[doc = "Register `GHWCFG4` reader"]
        pub type R = crate::R<Ghwcfg4Spec>;
        #[doc = "Register `GHWCFG4` writer"]
        pub type W = crate::W<Ghwcfg4Spec>;
        #[doc = "Field `NUMDEVPERIOEPS` reader - "]
        pub type NumdevperioepsR = crate::FieldReader;
        #[doc = "Field `NUMDEVPERIOEPS` writer - "]
        pub type NumdevperioepsW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `ENABLEPWROPT` reader - "]
        pub type EnablepwroptR = crate::BitReader;
        #[doc = "Field `ENABLEPWROPT` writer - "]
        pub type EnablepwroptW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AHBFREQ` reader - "]
        pub type AhbfreqR = crate::BitReader;
        #[doc = "Field `AHBFREQ` writer - "]
        pub type AhbfreqW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHYDATAWIDTH` reader - "]
        pub type PhydatawidthR = crate::FieldReader;
        #[doc = "Field `PHYDATAWIDTH` writer - "]
        pub type PhydatawidthW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `NUMCTLEPS` reader - "]
        pub type NumctlepsR = crate::FieldReader;
        #[doc = "Field `NUMCTLEPS` writer - "]
        pub type NumctlepsW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `IDDGFLTR` reader - "]
        pub type IddgfltrR = crate::BitReader;
        #[doc = "Field `IDDGFLTR` writer - "]
        pub type IddgfltrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `VBUSVALIDFLTR` reader - "]
        pub type VbusvalidfltrR = crate::BitReader;
        #[doc = "Field `VBUSVALIDFLTR` writer - "]
        pub type VbusvalidfltrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AVALIDFLTR` reader - "]
        pub type AvalidfltrR = crate::BitReader;
        #[doc = "Field `AVALIDFLTR` writer - "]
        pub type AvalidfltrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BVALIDFLTR` reader - "]
        pub type BvalidfltrR = crate::BitReader;
        #[doc = "Field `BVALIDFLTR` writer - "]
        pub type BvalidfltrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SESSENDFLTR` reader - "]
        pub type SessendfltrR = crate::BitReader;
        #[doc = "Field `SESSENDFLTR` writer - "]
        pub type SessendfltrW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn numdevperioeps(&self) -> NumdevperioepsR {
                NumdevperioepsR::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn enablepwropt(&self) -> EnablepwroptR {
                EnablepwroptR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn ahbfreq(&self) -> AhbfreqR {
                AhbfreqR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bits 14:15"]
            #[inline(always)]
            pub fn phydatawidth(&self) -> PhydatawidthR {
                PhydatawidthR::new(((self.bits >> 14) & 3) as u8)
            }
            #[doc = "Bits 16:19"]
            #[inline(always)]
            pub fn numctleps(&self) -> NumctlepsR {
                NumctlepsR::new(((self.bits >> 16) & 0x0f) as u8)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn iddgfltr(&self) -> IddgfltrR {
                IddgfltrR::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn vbusvalidfltr(&self) -> VbusvalidfltrR {
                VbusvalidfltrR::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn avalidfltr(&self) -> AvalidfltrR {
                AvalidfltrR::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn bvalidfltr(&self) -> BvalidfltrR {
                BvalidfltrR::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn sessendfltr(&self) -> SessendfltrR {
                SessendfltrR::new(((self.bits >> 24) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:3"]
            #[inline(always)]
            pub fn numdevperioeps(&mut self) -> NumdevperioepsW<'_, Ghwcfg4Spec> {
                NumdevperioepsW::new(self, 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn enablepwropt(&mut self) -> EnablepwroptW<'_, Ghwcfg4Spec> {
                EnablepwroptW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn ahbfreq(&mut self) -> AhbfreqW<'_, Ghwcfg4Spec> {
                AhbfreqW::new(self, 5)
            }
            #[doc = "Bits 14:15"]
            #[inline(always)]
            pub fn phydatawidth(&mut self) -> PhydatawidthW<'_, Ghwcfg4Spec> {
                PhydatawidthW::new(self, 14)
            }
            #[doc = "Bits 16:19"]
            #[inline(always)]
            pub fn numctleps(&mut self) -> NumctlepsW<'_, Ghwcfg4Spec> {
                NumctlepsW::new(self, 16)
            }
            #[doc = "Bit 20"]
            #[inline(always)]
            pub fn iddgfltr(&mut self) -> IddgfltrW<'_, Ghwcfg4Spec> {
                IddgfltrW::new(self, 20)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn vbusvalidfltr(&mut self) -> VbusvalidfltrW<'_, Ghwcfg4Spec> {
                VbusvalidfltrW::new(self, 21)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn avalidfltr(&mut self) -> AvalidfltrW<'_, Ghwcfg4Spec> {
                AvalidfltrW::new(self, 22)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn bvalidfltr(&mut self) -> BvalidfltrW<'_, Ghwcfg4Spec> {
                BvalidfltrW::new(self, 23)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn sessendfltr(&mut self) -> SessendfltrW<'_, Ghwcfg4Spec> {
                SessendfltrW::new(self, 24)
            }
        }
        #[doc = "DOTG_GHWCFG4\n\nYou can [`read`](crate::Reg::read) this register and get [`ghwcfg4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghwcfg4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct Ghwcfg4Spec;
        impl crate::RegisterSpec for Ghwcfg4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ghwcfg4::R`](R) reader structure"]
        impl crate::Readable for Ghwcfg4Spec {}
        #[doc = "`write(|w| ..)` method takes [`ghwcfg4::W`](W) writer structure"]
        impl crate::Writable for Ghwcfg4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GHWCFG4 to value 0"]
        impl crate::Resettable for Ghwcfg4Spec {}
    }
    #[doc = "GLPMCFG (rw) register accessor: DOTG_GLPMCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`glpmcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`glpmcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@glpmcfg`] module"]
    #[doc(alias = "GLPMCFG")]
    pub type Glpmcfg = crate::Reg<glpmcfg::GlpmcfgSpec>;
    #[doc = "DOTG_GLPMCFG"]
    pub mod glpmcfg {
        #[doc = "Register `GLPMCFG` reader"]
        pub type R = crate::R<GlpmcfgSpec>;
        #[doc = "Register `GLPMCFG` writer"]
        pub type W = crate::W<GlpmcfgSpec>;
        #[doc = "Field `HSIC_CONN` reader - "]
        pub type HsicConnR = crate::BitReader;
        #[doc = "Field `HSIC_CONN` writer - "]
        pub type HsicConnW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn hsic_conn(&self) -> HsicConnR {
                HsicConnR::new(((self.bits >> 30) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 30"]
            #[inline(always)]
            pub fn hsic_conn(&mut self) -> HsicConnW<'_, GlpmcfgSpec> {
                HsicConnW::new(self, 30)
            }
        }
        #[doc = "DOTG_GLPMCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`glpmcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`glpmcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GlpmcfgSpec;
        impl crate::RegisterSpec for GlpmcfgSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`glpmcfg::R`](R) reader structure"]
        impl crate::Readable for GlpmcfgSpec {}
        #[doc = "`write(|w| ..)` method takes [`glpmcfg::W`](W) writer structure"]
        impl crate::Writable for GlpmcfgSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GLPMCFG to value 0"]
        impl crate::Resettable for GlpmcfgSpec {}
    }
    #[doc = "GPWRDN (rw) register accessor: DOTG_GPWRDN\n\nYou can [`read`](crate::Reg::read) this register and get [`gpwrdn::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpwrdn::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpwrdn`] module"]
    #[doc(alias = "GPWRDN")]
    pub type Gpwrdn = crate::Reg<gpwrdn::GpwrdnSpec>;
    #[doc = "DOTG_GPWRDN"]
    pub mod gpwrdn {
        #[doc = "Register `GPWRDN` reader"]
        pub type R = crate::R<GpwrdnSpec>;
        #[doc = "Register `GPWRDN` writer"]
        pub type W = crate::W<GpwrdnSpec>;
        #[doc = "Field `PMU_IRQ_SEL` reader - "]
        pub type PmuIrqSelR = crate::BitReader;
        #[doc = "Field `PMU_IRQ_SEL` writer - "]
        pub type PmuIrqSelW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PMU_ACTIVE` reader - "]
        pub type PmuActiveR = crate::BitReader;
        #[doc = "Field `PMU_ACTIVE` writer - "]
        pub type PmuActiveW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESTORE` reader - "]
        pub type RestoreR = crate::BitReader;
        #[doc = "Field `RESTORE` writer - "]
        pub type RestoreW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POWER_DOWN_CLAMP` reader - "]
        pub type PowerDownClampR = crate::BitReader;
        #[doc = "Field `POWER_DOWN_CLAMP` writer - "]
        pub type PowerDownClampW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POWER_DOWN_RST` reader - "]
        pub type PowerDownRstR = crate::BitReader;
        #[doc = "Field `POWER_DOWN_RST` writer - "]
        pub type PowerDownRstW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POWER_DOWN` reader - "]
        pub type PowerDownR = crate::BitReader;
        #[doc = "Field `POWER_DOWN` writer - "]
        pub type PowerDownW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DISABLE_VBUS` reader - "]
        pub type DisableVbusR = crate::BitReader;
        #[doc = "Field `DISABLE_VBUS` writer - "]
        pub type DisableVbusW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LINESTATE` reader - "]
        pub type LinestateR = crate::BitReader;
        #[doc = "Field `LINESTATE` writer - "]
        pub type LinestateW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LINESTATE_INT` reader - "]
        pub type LinestateIntR = crate::BitReader;
        #[doc = "Field `LINESTATE_INT` writer - "]
        pub type LinestateIntW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESETDET` reader - "]
        pub type ResetdetR = crate::BitReader;
        #[doc = "Field `RESETDET` writer - "]
        pub type ResetdetW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESETDET_INT` reader - "]
        pub type ResetdetIntR = crate::BitReader;
        #[doc = "Field `RESETDET_INT` writer - "]
        pub type ResetdetIntW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DISCONN` reader - "]
        pub type DisconnR = crate::BitReader;
        #[doc = "Field `DISCONN` writer - "]
        pub type DisconnW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DISCONN_INT` reader - "]
        pub type DisconnIntR = crate::BitReader;
        #[doc = "Field `DISCONN_INT` writer - "]
        pub type DisconnIntW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CONNDET` reader - "]
        pub type ConndetR = crate::BitReader;
        #[doc = "Field `CONNDET` writer - "]
        pub type ConndetW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CONNDET_INT` reader - "]
        pub type ConndetIntR = crate::BitReader;
        #[doc = "Field `CONNDET_INT` writer - "]
        pub type ConndetIntW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IDDIG` reader - "]
        pub type IddigR = crate::BitReader;
        #[doc = "Field `IDDIG` writer - "]
        pub type IddigW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BVALID` reader - "]
        pub type BvalidR = crate::BitReader;
        #[doc = "Field `BVALID` writer - "]
        pub type BvalidW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn pmu_irq_sel(&self) -> PmuIrqSelR {
                PmuIrqSelR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn pmu_active(&self) -> PmuActiveR {
                PmuActiveR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn restore(&self) -> RestoreR {
                RestoreR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn power_down_clamp(&self) -> PowerDownClampR {
                PowerDownClampR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn power_down_rst(&self) -> PowerDownRstR {
                PowerDownRstR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn power_down(&self) -> PowerDownR {
                PowerDownR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn disable_vbus(&self) -> DisableVbusR {
                DisableVbusR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn linestate(&self) -> LinestateR {
                LinestateR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn linestate_int(&self) -> LinestateIntR {
                LinestateIntR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn resetdet(&self) -> ResetdetR {
                ResetdetR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn resetdet_int(&self) -> ResetdetIntR {
                ResetdetIntR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn disconn(&self) -> DisconnR {
                DisconnR::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn disconn_int(&self) -> DisconnIntR {
                DisconnIntR::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13"]
            #[inline(always)]
            pub fn conndet(&self) -> ConndetR {
                ConndetR::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14"]
            #[inline(always)]
            pub fn conndet_int(&self) -> ConndetIntR {
                ConndetIntR::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn iddig(&self) -> IddigR {
                IddigR::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn bvalid(&self) -> BvalidR {
                BvalidR::new(((self.bits >> 22) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn pmu_irq_sel(&mut self) -> PmuIrqSelW<'_, GpwrdnSpec> {
                PmuIrqSelW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn pmu_active(&mut self) -> PmuActiveW<'_, GpwrdnSpec> {
                PmuActiveW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn restore(&mut self) -> RestoreW<'_, GpwrdnSpec> {
                RestoreW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn power_down_clamp(&mut self) -> PowerDownClampW<'_, GpwrdnSpec> {
                PowerDownClampW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn power_down_rst(&mut self) -> PowerDownRstW<'_, GpwrdnSpec> {
                PowerDownRstW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn power_down(&mut self) -> PowerDownW<'_, GpwrdnSpec> {
                PowerDownW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn disable_vbus(&mut self) -> DisableVbusW<'_, GpwrdnSpec> {
                DisableVbusW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn linestate(&mut self) -> LinestateW<'_, GpwrdnSpec> {
                LinestateW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn linestate_int(&mut self) -> LinestateIntW<'_, GpwrdnSpec> {
                LinestateIntW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn resetdet(&mut self) -> ResetdetW<'_, GpwrdnSpec> {
                ResetdetW::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn resetdet_int(&mut self) -> ResetdetIntW<'_, GpwrdnSpec> {
                ResetdetIntW::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn disconn(&mut self) -> DisconnW<'_, GpwrdnSpec> {
                DisconnW::new(self, 11)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn disconn_int(&mut self) -> DisconnIntW<'_, GpwrdnSpec> {
                DisconnIntW::new(self, 12)
            }
            #[doc = "Bit 13"]
            #[inline(always)]
            pub fn conndet(&mut self) -> ConndetW<'_, GpwrdnSpec> {
                ConndetW::new(self, 13)
            }
            #[doc = "Bit 14"]
            #[inline(always)]
            pub fn conndet_int(&mut self) -> ConndetIntW<'_, GpwrdnSpec> {
                ConndetIntW::new(self, 14)
            }
            #[doc = "Bit 21"]
            #[inline(always)]
            pub fn iddig(&mut self) -> IddigW<'_, GpwrdnSpec> {
                IddigW::new(self, 21)
            }
            #[doc = "Bit 22"]
            #[inline(always)]
            pub fn bvalid(&mut self) -> BvalidW<'_, GpwrdnSpec> {
                BvalidW::new(self, 22)
            }
        }
        #[doc = "DOTG_GPWRDN\n\nYou can [`read`](crate::Reg::read) this register and get [`gpwrdn::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpwrdn::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GpwrdnSpec;
        impl crate::RegisterSpec for GpwrdnSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpwrdn::R`](R) reader structure"]
        impl crate::Readable for GpwrdnSpec {}
        #[doc = "`write(|w| ..)` method takes [`gpwrdn::W`](W) writer structure"]
        impl crate::Writable for GpwrdnSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GPWRDN to value 0"]
        impl crate::Resettable for GpwrdnSpec {}
    }
    #[doc = "GDFIFOCFG (rw) register accessor: DOTG_GDFIFOCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gdfifocfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gdfifocfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gdfifocfg`] module"]
    #[doc(alias = "GDFIFOCFG")]
    pub type Gdfifocfg = crate::Reg<gdfifocfg::GdfifocfgSpec>;
    #[doc = "DOTG_GDFIFOCFG"]
    pub mod gdfifocfg {
        #[doc = "Register `GDFIFOCFG` reader"]
        pub type R = crate::R<GdfifocfgSpec>;
        #[doc = "Register `GDFIFOCFG` writer"]
        pub type W = crate::W<GdfifocfgSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_GDFIFOCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`gdfifocfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gdfifocfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GdfifocfgSpec;
        impl crate::RegisterSpec for GdfifocfgSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gdfifocfg::R`](R) reader structure"]
        impl crate::Readable for GdfifocfgSpec {}
        #[doc = "`write(|w| ..)` method takes [`gdfifocfg::W`](W) writer structure"]
        impl crate::Writable for GdfifocfgSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GDFIFOCFG to value 0"]
        impl crate::Resettable for GdfifocfgSpec {}
    }
    #[doc = "GADPCTL (rw) register accessor: DOTG_GADPCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gadpctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gadpctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gadpctl`] module"]
    #[doc(alias = "GADPCTL")]
    pub type Gadpctl = crate::Reg<gadpctl::GadpctlSpec>;
    #[doc = "DOTG_GADPCTL"]
    pub mod gadpctl {
        #[doc = "Register `GADPCTL` reader"]
        pub type R = crate::R<GadpctlSpec>;
        #[doc = "Register `GADPCTL` writer"]
        pub type W = crate::W<GadpctlSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_GADPCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`gadpctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gadpctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GadpctlSpec;
        impl crate::RegisterSpec for GadpctlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gadpctl::R`](R) reader structure"]
        impl crate::Readable for GadpctlSpec {}
        #[doc = "`write(|w| ..)` method takes [`gadpctl::W`](W) writer structure"]
        impl crate::Writable for GadpctlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets GADPCTL to value 0"]
        impl crate::Resettable for GadpctlSpec {}
    }
    #[doc = "HPTXFSIZ (rw) register accessor: DOTG_HPTXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`hptxfsiz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hptxfsiz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxfsiz`] module"]
    #[doc(alias = "HPTXFSIZ")]
    pub type Hptxfsiz = crate::Reg<hptxfsiz::HptxfsizSpec>;
    #[doc = "DOTG_HPTXFSIZ"]
    pub mod hptxfsiz {
        #[doc = "Register `HPTXFSIZ` reader"]
        pub type R = crate::R<HptxfsizSpec>;
        #[doc = "Register `HPTXFSIZ` writer"]
        pub type W = crate::W<HptxfsizSpec>;
        #[doc = "Field `PTXFSTADDR` reader - "]
        pub type PtxfstaddrR = crate::FieldReader<u16>;
        #[doc = "Field `PTXFSTADDR` writer - "]
        pub type PtxfstaddrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `PTXFSIZE` reader - "]
        pub type PtxfsizeR = crate::FieldReader<u16>;
        #[doc = "Field `PTXFSIZE` writer - "]
        pub type PtxfsizeW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn ptxfstaddr(&self) -> PtxfstaddrR {
                PtxfstaddrR::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31"]
            #[inline(always)]
            pub fn ptxfsize(&self) -> PtxfsizeR {
                PtxfsizeR::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn ptxfstaddr(&mut self) -> PtxfstaddrW<'_, HptxfsizSpec> {
                PtxfstaddrW::new(self, 0)
            }
            #[doc = "Bits 16:31"]
            #[inline(always)]
            pub fn ptxfsize(&mut self) -> PtxfsizeW<'_, HptxfsizSpec> {
                PtxfsizeW::new(self, 16)
            }
        }
        #[doc = "DOTG_HPTXFSIZ\n\nYou can [`read`](crate::Reg::read) this register and get [`hptxfsiz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hptxfsiz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HptxfsizSpec;
        impl crate::RegisterSpec for HptxfsizSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`hptxfsiz::R`](R) reader structure"]
        impl crate::Readable for HptxfsizSpec {}
        #[doc = "`write(|w| ..)` method takes [`hptxfsiz::W`](W) writer structure"]
        impl crate::Writable for HptxfsizSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets HPTXFSIZ to value 0"]
        impl crate::Resettable for HptxfsizSpec {}
    }
    #[doc = "HCFG (rw) register accessor: DOTG_HCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`hcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcfg`] module"]
    #[doc(alias = "HCFG")]
    pub type Hcfg = crate::Reg<hcfg::HcfgSpec>;
    #[doc = "DOTG_HCFG"]
    pub mod hcfg {
        #[doc = "Register `HCFG` reader"]
        pub type R = crate::R<HcfgSpec>;
        #[doc = "Register `HCFG` writer"]
        pub type W = crate::W<HcfgSpec>;
        #[doc = "Field `FSLSPCLKSEL` reader - "]
        pub type FslspclkselR = crate::FieldReader;
        #[doc = "Field `FSLSPCLKSEL` writer - "]
        pub type FslspclkselW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `FSLSSUPP` reader - "]
        pub type FslssuppR = crate::BitReader;
        #[doc = "Field `FSLSSUPP` writer - "]
        pub type FslssuppW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `32KHZSUSPEND` reader - "]
        pub type _32khzsuspendR = crate::BitReader;
        #[doc = "Field `32KHZSUSPEND` writer - "]
        pub type _32khzsuspendW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MULTISEGDMA` reader - "]
        pub type MultisegdmaR = crate::BitReader;
        #[doc = "Field `MULTISEGDMA` writer - "]
        pub type MultisegdmaW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FLENTRIES` reader - "]
        pub type FlentriesR = crate::FieldReader;
        #[doc = "Field `FLENTRIES` writer - "]
        pub type FlentriesW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PERSCHEDENABLE` reader - "]
        pub type PerschedenableR = crate::BitReader;
        #[doc = "Field `PERSCHEDENABLE` writer - "]
        pub type PerschedenableW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MODECHANGERDY` reader - "]
        pub type ModechangerdyR = crate::BitReader;
        #[doc = "Field `MODECHANGERDY` writer - "]
        pub type ModechangerdyW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn fslspclksel(&self) -> FslspclkselR {
                FslspclkselR::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn fslssupp(&self) -> FslssuppR {
                FslssuppR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn _32khzsuspend(&self) -> _32khzsuspendR {
                _32khzsuspendR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn multisegdma(&self) -> MultisegdmaR {
                MultisegdmaR::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bits 24:25"]
            #[inline(always)]
            pub fn flentries(&self) -> FlentriesR {
                FlentriesR::new(((self.bits >> 24) & 3) as u8)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn perschedenable(&self) -> PerschedenableR {
                PerschedenableR::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn modechangerdy(&self) -> ModechangerdyR {
                ModechangerdyR::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn fslspclksel(&mut self) -> FslspclkselW<'_, HcfgSpec> {
                FslspclkselW::new(self, 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn fslssupp(&mut self) -> FslssuppW<'_, HcfgSpec> {
                FslssuppW::new(self, 2)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn _32khzsuspend(&mut self) -> _32khzsuspendW<'_, HcfgSpec> {
                _32khzsuspendW::new(self, 7)
            }
            #[doc = "Bit 23"]
            #[inline(always)]
            pub fn multisegdma(&mut self) -> MultisegdmaW<'_, HcfgSpec> {
                MultisegdmaW::new(self, 23)
            }
            #[doc = "Bits 24:25"]
            #[inline(always)]
            pub fn flentries(&mut self) -> FlentriesW<'_, HcfgSpec> {
                FlentriesW::new(self, 24)
            }
            #[doc = "Bit 26"]
            #[inline(always)]
            pub fn perschedenable(&mut self) -> PerschedenableW<'_, HcfgSpec> {
                PerschedenableW::new(self, 26)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn modechangerdy(&mut self) -> ModechangerdyW<'_, HcfgSpec> {
                ModechangerdyW::new(self, 31)
            }
        }
        #[doc = "DOTG_HCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`hcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HcfgSpec;
        impl crate::RegisterSpec for HcfgSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`hcfg::R`](R) reader structure"]
        impl crate::Readable for HcfgSpec {}
        #[doc = "`write(|w| ..)` method takes [`hcfg::W`](W) writer structure"]
        impl crate::Writable for HcfgSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets HCFG to value 0"]
        impl crate::Resettable for HcfgSpec {}
    }
    #[doc = "HFIR (rw) register accessor: DOTG_HFIR\n\nYou can [`read`](crate::Reg::read) this register and get [`hfir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfir`] module"]
    #[doc(alias = "HFIR")]
    pub type Hfir = crate::Reg<hfir::HfirSpec>;
    #[doc = "DOTG_HFIR"]
    pub mod hfir {
        #[doc = "Register `HFIR` reader"]
        pub type R = crate::R<HfirSpec>;
        #[doc = "Register `HFIR` writer"]
        pub type W = crate::W<HfirSpec>;
        #[doc = "Field `FRINT` reader - "]
        pub type FrintR = crate::FieldReader<u16>;
        #[doc = "Field `FRINT` writer - "]
        pub type FrintW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `RELOADCTRL` reader - "]
        pub type ReloadctrlR = crate::BitReader;
        #[doc = "Field `RELOADCTRL` writer - "]
        pub type ReloadctrlW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn frint(&self) -> FrintR {
                FrintR::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn reloadctrl(&self) -> ReloadctrlR {
                ReloadctrlR::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn frint(&mut self) -> FrintW<'_, HfirSpec> {
                FrintW::new(self, 0)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn reloadctrl(&mut self) -> ReloadctrlW<'_, HfirSpec> {
                ReloadctrlW::new(self, 16)
            }
        }
        #[doc = "DOTG_HFIR\n\nYou can [`read`](crate::Reg::read) this register and get [`hfir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HfirSpec;
        impl crate::RegisterSpec for HfirSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`hfir::R`](R) reader structure"]
        impl crate::Readable for HfirSpec {}
        #[doc = "`write(|w| ..)` method takes [`hfir::W`](W) writer structure"]
        impl crate::Writable for HfirSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets HFIR to value 0"]
        impl crate::Resettable for HfirSpec {}
    }
    #[doc = "HFNUM (rw) register accessor: DOTG_HFNUM\n\nYou can [`read`](crate::Reg::read) this register and get [`hfnum::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfnum::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfnum`] module"]
    #[doc(alias = "HFNUM")]
    pub type Hfnum = crate::Reg<hfnum::HfnumSpec>;
    #[doc = "DOTG_HFNUM"]
    pub mod hfnum {
        #[doc = "Register `HFNUM` reader"]
        pub type R = crate::R<HfnumSpec>;
        #[doc = "Register `HFNUM` writer"]
        pub type W = crate::W<HfnumSpec>;
        #[doc = "Field `FRNUM` reader - "]
        pub type FrnumR = crate::FieldReader<u16>;
        #[doc = "Field `FRNUM` writer - "]
        pub type FrnumW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `FRREM` reader - "]
        pub type FrremR = crate::FieldReader<u16>;
        #[doc = "Field `FRREM` writer - "]
        pub type FrremW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn frnum(&self) -> FrnumR {
                FrnumR::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31"]
            #[inline(always)]
            pub fn frrem(&self) -> FrremR {
                FrremR::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn frnum(&mut self) -> FrnumW<'_, HfnumSpec> {
                FrnumW::new(self, 0)
            }
            #[doc = "Bits 16:31"]
            #[inline(always)]
            pub fn frrem(&mut self) -> FrremW<'_, HfnumSpec> {
                FrremW::new(self, 16)
            }
        }
        #[doc = "DOTG_HFNUM\n\nYou can [`read`](crate::Reg::read) this register and get [`hfnum::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfnum::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HfnumSpec;
        impl crate::RegisterSpec for HfnumSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`hfnum::R`](R) reader structure"]
        impl crate::Readable for HfnumSpec {}
        #[doc = "`write(|w| ..)` method takes [`hfnum::W`](W) writer structure"]
        impl crate::Writable for HfnumSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets HFNUM to value 0"]
        impl crate::Resettable for HfnumSpec {}
    }
    #[doc = "HPTXSTS (rw) register accessor: DOTG_HPTXSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`hptxsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hptxsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxsts`] module"]
    #[doc(alias = "HPTXSTS")]
    pub type Hptxsts = crate::Reg<hptxsts::HptxstsSpec>;
    #[doc = "DOTG_HPTXSTS"]
    pub mod hptxsts {
        #[doc = "Register `HPTXSTS` reader"]
        pub type R = crate::R<HptxstsSpec>;
        #[doc = "Register `HPTXSTS` writer"]
        pub type W = crate::W<HptxstsSpec>;
        #[doc = "Field `PTXFSPCAVAIL` reader - "]
        pub type PtxfspcavailR = crate::FieldReader<u16>;
        #[doc = "Field `PTXFSPCAVAIL` writer - "]
        pub type PtxfspcavailW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `PTXQSPCAVAIL` reader - "]
        pub type PtxqspcavailR = crate::FieldReader;
        #[doc = "Field `PTXQSPCAVAIL` writer - "]
        pub type PtxqspcavailW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `TERMINATE` reader - "]
        pub type TerminateR = crate::BitReader;
        #[doc = "Field `TERMINATE` writer - "]
        pub type TerminateW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TOKEN` reader - "]
        pub type TokenR = crate::FieldReader;
        #[doc = "Field `TOKEN` writer - "]
        pub type TokenW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `CHAN` reader - "]
        pub type ChanR = crate::FieldReader;
        #[doc = "Field `CHAN` writer - "]
        pub type ChanW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `ODD` reader - "]
        pub type OddR = crate::BitReader;
        #[doc = "Field `ODD` writer - "]
        pub type OddW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn ptxfspcavail(&self) -> PtxfspcavailR {
                PtxfspcavailR::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:23"]
            #[inline(always)]
            pub fn ptxqspcavail(&self) -> PtxqspcavailR {
                PtxqspcavailR::new(((self.bits >> 16) & 0xff) as u8)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn terminate(&self) -> TerminateR {
                TerminateR::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bits 25:26"]
            #[inline(always)]
            pub fn token(&self) -> TokenR {
                TokenR::new(((self.bits >> 25) & 3) as u8)
            }
            #[doc = "Bits 27:30"]
            #[inline(always)]
            pub fn chan(&self) -> ChanR {
                ChanR::new(((self.bits >> 27) & 0x0f) as u8)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn odd(&self) -> OddR {
                OddR::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn ptxfspcavail(&mut self) -> PtxfspcavailW<'_, HptxstsSpec> {
                PtxfspcavailW::new(self, 0)
            }
            #[doc = "Bits 16:23"]
            #[inline(always)]
            pub fn ptxqspcavail(&mut self) -> PtxqspcavailW<'_, HptxstsSpec> {
                PtxqspcavailW::new(self, 16)
            }
            #[doc = "Bit 24"]
            #[inline(always)]
            pub fn terminate(&mut self) -> TerminateW<'_, HptxstsSpec> {
                TerminateW::new(self, 24)
            }
            #[doc = "Bits 25:26"]
            #[inline(always)]
            pub fn token(&mut self) -> TokenW<'_, HptxstsSpec> {
                TokenW::new(self, 25)
            }
            #[doc = "Bits 27:30"]
            #[inline(always)]
            pub fn chan(&mut self) -> ChanW<'_, HptxstsSpec> {
                ChanW::new(self, 27)
            }
            #[doc = "Bit 31"]
            #[inline(always)]
            pub fn odd(&mut self) -> OddW<'_, HptxstsSpec> {
                OddW::new(self, 31)
            }
        }
        #[doc = "DOTG_HPTXSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`hptxsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hptxsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HptxstsSpec;
        impl crate::RegisterSpec for HptxstsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`hptxsts::R`](R) reader structure"]
        impl crate::Readable for HptxstsSpec {}
        #[doc = "`write(|w| ..)` method takes [`hptxsts::W`](W) writer structure"]
        impl crate::Writable for HptxstsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets HPTXSTS to value 0"]
        impl crate::Resettable for HptxstsSpec {}
    }
    #[doc = "HAINT (rw) register accessor: DOTG_HAINT\n\nYou can [`read`](crate::Reg::read) this register and get [`haint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`haint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haint`] module"]
    #[doc(alias = "HAINT")]
    pub type Haint = crate::Reg<haint::HaintSpec>;
    #[doc = "DOTG_HAINT"]
    pub mod haint {
        #[doc = "Register `HAINT` reader"]
        pub type R = crate::R<HaintSpec>;
        #[doc = "Register `HAINT` writer"]
        pub type W = crate::W<HaintSpec>;
        #[doc = "Field `HAINT` reader - "]
        pub type HaintR = crate::FieldReader<u16>;
        #[doc = "Field `HAINT` writer - "]
        pub type HaintW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn haint(&self) -> HaintR {
                HaintR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn haint(&mut self) -> HaintW<'_, HaintSpec> {
                HaintW::new(self, 0)
            }
        }
        #[doc = "DOTG_HAINT\n\nYou can [`read`](crate::Reg::read) this register and get [`haint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`haint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HaintSpec;
        impl crate::RegisterSpec for HaintSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`haint::R`](R) reader structure"]
        impl crate::Readable for HaintSpec {}
        #[doc = "`write(|w| ..)` method takes [`haint::W`](W) writer structure"]
        impl crate::Writable for HaintSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets HAINT to value 0"]
        impl crate::Resettable for HaintSpec {}
    }
    #[doc = "HAINTMSK (rw) register accessor: DOTG_HAINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`haintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`haintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haintmsk`] module"]
    #[doc(alias = "HAINTMSK")]
    pub type Haintmsk = crate::Reg<haintmsk::HaintmskSpec>;
    #[doc = "DOTG_HAINTMSK"]
    pub mod haintmsk {
        #[doc = "Register `HAINTMSK` reader"]
        pub type R = crate::R<HaintmskSpec>;
        #[doc = "Register `HAINTMSK` writer"]
        pub type W = crate::W<HaintmskSpec>;
        #[doc = "Field `HAINTMSK` reader - "]
        pub type HaintmskR = crate::FieldReader<u16>;
        #[doc = "Field `HAINTMSK` writer - "]
        pub type HaintmskW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn haintmsk(&self) -> HaintmskR {
                HaintmskR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn haintmsk(&mut self) -> HaintmskW<'_, HaintmskSpec> {
                HaintmskW::new(self, 0)
            }
        }
        #[doc = "DOTG_HAINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`haintmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`haintmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HaintmskSpec;
        impl crate::RegisterSpec for HaintmskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`haintmsk::R`](R) reader structure"]
        impl crate::Readable for HaintmskSpec {}
        #[doc = "`write(|w| ..)` method takes [`haintmsk::W`](W) writer structure"]
        impl crate::Writable for HaintmskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets HAINTMSK to value 0"]
        impl crate::Resettable for HaintmskSpec {}
    }
    #[doc = "HPRT (rw) register accessor: DOTG_HPRT\n\nYou can [`read`](crate::Reg::read) this register and get [`hprt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hprt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hprt`] module"]
    #[doc(alias = "HPRT")]
    pub type Hprt = crate::Reg<hprt::HprtSpec>;
    #[doc = "DOTG_HPRT"]
    pub mod hprt {
        #[doc = "Register `HPRT` reader"]
        pub type R = crate::R<HprtSpec>;
        #[doc = "Register `HPRT` writer"]
        pub type W = crate::W<HprtSpec>;
        #[doc = "Field `PRTCONNSTS` reader - "]
        pub type PrtconnstsR = crate::BitReader;
        #[doc = "Field `PRTCONNSTS` writer - "]
        pub type PrtconnstsW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTCONNDET` reader - "]
        pub type PrtconndetR = crate::BitReader;
        #[doc = "Field `PRTCONNDET` writer - "]
        pub type PrtconndetW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTENA` reader - "]
        pub type PrtenaR = crate::BitReader;
        #[doc = "Field `PRTENA` writer - "]
        pub type PrtenaW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTENCHNG` reader - "]
        pub type PrtenchngR = crate::BitReader;
        #[doc = "Field `PRTENCHNG` writer - "]
        pub type PrtenchngW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTOVRCURRACT` reader - "]
        pub type PrtovrcurractR = crate::BitReader;
        #[doc = "Field `PRTOVRCURRACT` writer - "]
        pub type PrtovrcurractW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTOVRCURRCHNG` reader - "]
        pub type PrtovrcurrchngR = crate::BitReader;
        #[doc = "Field `PRTOVRCURRCHNG` writer - "]
        pub type PrtovrcurrchngW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTRES` reader - "]
        pub type PrtresR = crate::BitReader;
        #[doc = "Field `PRTRES` writer - "]
        pub type PrtresW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTSUSP` reader - "]
        pub type PrtsuspR = crate::BitReader;
        #[doc = "Field `PRTSUSP` writer - "]
        pub type PrtsuspW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTRST` reader - "]
        pub type PrtrstR = crate::BitReader;
        #[doc = "Field `PRTRST` writer - "]
        pub type PrtrstW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTLNSTS` reader - "]
        pub type PrtlnstsR = crate::FieldReader;
        #[doc = "Field `PRTLNSTS` writer - "]
        pub type PrtlnstsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PRTPWR` reader - "]
        pub type PrtpwrR = crate::BitReader;
        #[doc = "Field `PRTPWR` writer - "]
        pub type PrtpwrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRTTSTCTL` reader - "]
        pub type PrttstctlR = crate::FieldReader;
        #[doc = "Field `PRTTSTCTL` writer - "]
        pub type PrttstctlW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `PRTSPD` reader - "]
        pub type PrtspdR = crate::FieldReader;
        #[doc = "Field `PRTSPD` writer - "]
        pub type PrtspdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn prtconnsts(&self) -> PrtconnstsR {
                PrtconnstsR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn prtconndet(&self) -> PrtconndetR {
                PrtconndetR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn prtena(&self) -> PrtenaR {
                PrtenaR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn prtenchng(&self) -> PrtenchngR {
                PrtenchngR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn prtovrcurract(&self) -> PrtovrcurractR {
                PrtovrcurractR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn prtovrcurrchng(&self) -> PrtovrcurrchngR {
                PrtovrcurrchngR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn prtres(&self) -> PrtresR {
                PrtresR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn prtsusp(&self) -> PrtsuspR {
                PrtsuspR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn prtrst(&self) -> PrtrstR {
                PrtrstR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bits 10:11"]
            #[inline(always)]
            pub fn prtlnsts(&self) -> PrtlnstsR {
                PrtlnstsR::new(((self.bits >> 10) & 3) as u8)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn prtpwr(&self) -> PrtpwrR {
                PrtpwrR::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bits 13:16"]
            #[inline(always)]
            pub fn prttstctl(&self) -> PrttstctlR {
                PrttstctlR::new(((self.bits >> 13) & 0x0f) as u8)
            }
            #[doc = "Bits 17:18"]
            #[inline(always)]
            pub fn prtspd(&self) -> PrtspdR {
                PrtspdR::new(((self.bits >> 17) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn prtconnsts(&mut self) -> PrtconnstsW<'_, HprtSpec> {
                PrtconnstsW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn prtconndet(&mut self) -> PrtconndetW<'_, HprtSpec> {
                PrtconndetW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn prtena(&mut self) -> PrtenaW<'_, HprtSpec> {
                PrtenaW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn prtenchng(&mut self) -> PrtenchngW<'_, HprtSpec> {
                PrtenchngW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn prtovrcurract(&mut self) -> PrtovrcurractW<'_, HprtSpec> {
                PrtovrcurractW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn prtovrcurrchng(&mut self) -> PrtovrcurrchngW<'_, HprtSpec> {
                PrtovrcurrchngW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn prtres(&mut self) -> PrtresW<'_, HprtSpec> {
                PrtresW::new(self, 6)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn prtsusp(&mut self) -> PrtsuspW<'_, HprtSpec> {
                PrtsuspW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn prtrst(&mut self) -> PrtrstW<'_, HprtSpec> {
                PrtrstW::new(self, 8)
            }
            #[doc = "Bits 10:11"]
            #[inline(always)]
            pub fn prtlnsts(&mut self) -> PrtlnstsW<'_, HprtSpec> {
                PrtlnstsW::new(self, 10)
            }
            #[doc = "Bit 12"]
            #[inline(always)]
            pub fn prtpwr(&mut self) -> PrtpwrW<'_, HprtSpec> {
                PrtpwrW::new(self, 12)
            }
            #[doc = "Bits 13:16"]
            #[inline(always)]
            pub fn prttstctl(&mut self) -> PrttstctlW<'_, HprtSpec> {
                PrttstctlW::new(self, 13)
            }
            #[doc = "Bits 17:18"]
            #[inline(always)]
            pub fn prtspd(&mut self) -> PrtspdW<'_, HprtSpec> {
                PrtspdW::new(self, 17)
            }
        }
        #[doc = "DOTG_HPRT\n\nYou can [`read`](crate::Reg::read) this register and get [`hprt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hprt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HprtSpec;
        impl crate::RegisterSpec for HprtSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`hprt::R`](R) reader structure"]
        impl crate::Readable for HprtSpec {}
        #[doc = "`write(|w| ..)` method takes [`hprt::W`](W) writer structure"]
        impl crate::Writable for HprtSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets HPRT to value 0"]
        impl crate::Resettable for HprtSpec {}
    }
    #[doc = "DCFG (rw) register accessor: DOTG_DCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`dcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcfg`] module"]
    #[doc(alias = "DCFG")]
    pub type Dcfg = crate::Reg<dcfg::DcfgSpec>;
    #[doc = "DOTG_DCFG"]
    pub mod dcfg {
        #[doc = "Register `DCFG` reader"]
        pub type R = crate::R<DcfgSpec>;
        #[doc = "Register `DCFG` writer"]
        pub type W = crate::W<DcfgSpec>;
        #[doc = "Field `DEVSPD` reader - "]
        pub type DevspdR = crate::FieldReader;
        #[doc = "Field `DEVSPD` writer - "]
        pub type DevspdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `NZSTSOUTHSHK` reader - "]
        pub type NzstsouthshkR = crate::BitReader;
        #[doc = "Field `NZSTSOUTHSHK` writer - "]
        pub type NzstsouthshkW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DEVADDR` reader - "]
        pub type DevaddrR = crate::FieldReader;
        #[doc = "Field `DEVADDR` writer - "]
        pub type DevaddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `PERFRINT` reader - "]
        pub type PerfrintR = crate::FieldReader;
        #[doc = "Field `PERFRINT` writer - "]
        pub type PerfrintW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `EPMISCNT` reader - "]
        pub type EpmiscntR = crate::FieldReader;
        #[doc = "Field `EPMISCNT` writer - "]
        pub type EpmiscntW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn devspd(&self) -> DevspdR {
                DevspdR::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn nzstsouthshk(&self) -> NzstsouthshkR {
                NzstsouthshkR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bits 4:10"]
            #[inline(always)]
            pub fn devaddr(&self) -> DevaddrR {
                DevaddrR::new(((self.bits >> 4) & 0x7f) as u8)
            }
            #[doc = "Bits 11:12"]
            #[inline(always)]
            pub fn perfrint(&self) -> PerfrintR {
                PerfrintR::new(((self.bits >> 11) & 3) as u8)
            }
            #[doc = "Bits 18:22"]
            #[inline(always)]
            pub fn epmiscnt(&self) -> EpmiscntR {
                EpmiscntR::new(((self.bits >> 18) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:1"]
            #[inline(always)]
            pub fn devspd(&mut self) -> DevspdW<'_, DcfgSpec> {
                DevspdW::new(self, 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn nzstsouthshk(&mut self) -> NzstsouthshkW<'_, DcfgSpec> {
                NzstsouthshkW::new(self, 2)
            }
            #[doc = "Bits 4:10"]
            #[inline(always)]
            pub fn devaddr(&mut self) -> DevaddrW<'_, DcfgSpec> {
                DevaddrW::new(self, 4)
            }
            #[doc = "Bits 11:12"]
            #[inline(always)]
            pub fn perfrint(&mut self) -> PerfrintW<'_, DcfgSpec> {
                PerfrintW::new(self, 11)
            }
            #[doc = "Bits 18:22"]
            #[inline(always)]
            pub fn epmiscnt(&mut self) -> EpmiscntW<'_, DcfgSpec> {
                EpmiscntW::new(self, 18)
            }
        }
        #[doc = "DOTG_DCFG\n\nYou can [`read`](crate::Reg::read) this register and get [`dcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DcfgSpec;
        impl crate::RegisterSpec for DcfgSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcfg::R`](R) reader structure"]
        impl crate::Readable for DcfgSpec {}
        #[doc = "`write(|w| ..)` method takes [`dcfg::W`](W) writer structure"]
        impl crate::Writable for DcfgSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DCFG to value 0"]
        impl crate::Resettable for DcfgSpec {}
    }
    #[doc = "DCTL (rw) register accessor: DOTG_DCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`dctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dctl`] module"]
    #[doc(alias = "DCTL")]
    pub type Dctl = crate::Reg<dctl::DctlSpec>;
    #[doc = "DOTG_DCTL"]
    pub mod dctl {
        #[doc = "Register `DCTL` reader"]
        pub type R = crate::R<DctlSpec>;
        #[doc = "Register `DCTL` writer"]
        pub type W = crate::W<DctlSpec>;
        #[doc = "Field `RMTWKUPSIG` reader - "]
        pub type RmtwkupsigR = crate::BitReader;
        #[doc = "Field `RMTWKUPSIG` writer - "]
        pub type RmtwkupsigW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SFTDISCON` reader - "]
        pub type SftdisconR = crate::BitReader;
        #[doc = "Field `SFTDISCON` writer - "]
        pub type SftdisconW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GNPINNAKSTS` reader - "]
        pub type GnpinnakstsR = crate::BitReader;
        #[doc = "Field `GNPINNAKSTS` writer - "]
        pub type GnpinnakstsW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GOUTNAKSTS` reader - "]
        pub type GoutnakstsR = crate::BitReader;
        #[doc = "Field `GOUTNAKSTS` writer - "]
        pub type GoutnakstsW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TSTCTL` reader - "]
        pub type TstctlR = crate::FieldReader;
        #[doc = "Field `TSTCTL` writer - "]
        pub type TstctlW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `SGNPINNAK` reader - "]
        pub type SgnpinnakR = crate::BitReader;
        #[doc = "Field `SGNPINNAK` writer - "]
        pub type SgnpinnakW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CGNPINNAK` reader - "]
        pub type CgnpinnakR = crate::BitReader;
        #[doc = "Field `CGNPINNAK` writer - "]
        pub type CgnpinnakW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SGOUTNAK` reader - "]
        pub type SgoutnakR = crate::BitReader;
        #[doc = "Field `SGOUTNAK` writer - "]
        pub type SgoutnakW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CGOUTNAK` reader - "]
        pub type CgoutnakR = crate::BitReader;
        #[doc = "Field `CGOUTNAK` writer - "]
        pub type CgoutnakW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PWRONPRGDONE` reader - "]
        pub type PwronprgdoneR = crate::BitReader;
        #[doc = "Field `PWRONPRGDONE` writer - "]
        pub type PwronprgdoneW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rmtwkupsig(&self) -> RmtwkupsigR {
                RmtwkupsigR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn sftdiscon(&self) -> SftdisconR {
                SftdisconR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn gnpinnaksts(&self) -> GnpinnakstsR {
                GnpinnakstsR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn goutnaksts(&self) -> GoutnakstsR {
                GoutnakstsR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 4:6"]
            #[inline(always)]
            pub fn tstctl(&self) -> TstctlR {
                TstctlR::new(((self.bits >> 4) & 7) as u8)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn sgnpinnak(&self) -> SgnpinnakR {
                SgnpinnakR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cgnpinnak(&self) -> CgnpinnakR {
                CgnpinnakR::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn sgoutnak(&self) -> SgoutnakR {
                SgoutnakR::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn cgoutnak(&self) -> CgoutnakR {
                CgoutnakR::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn pwronprgdone(&self) -> PwronprgdoneR {
                PwronprgdoneR::new(((self.bits >> 11) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn rmtwkupsig(&mut self) -> RmtwkupsigW<'_, DctlSpec> {
                RmtwkupsigW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn sftdiscon(&mut self) -> SftdisconW<'_, DctlSpec> {
                SftdisconW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn gnpinnaksts(&mut self) -> GnpinnakstsW<'_, DctlSpec> {
                GnpinnakstsW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn goutnaksts(&mut self) -> GoutnakstsW<'_, DctlSpec> {
                GoutnakstsW::new(self, 3)
            }
            #[doc = "Bits 4:6"]
            #[inline(always)]
            pub fn tstctl(&mut self) -> TstctlW<'_, DctlSpec> {
                TstctlW::new(self, 4)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn sgnpinnak(&mut self) -> SgnpinnakW<'_, DctlSpec> {
                SgnpinnakW::new(self, 7)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn cgnpinnak(&mut self) -> CgnpinnakW<'_, DctlSpec> {
                CgnpinnakW::new(self, 8)
            }
            #[doc = "Bit 9"]
            #[inline(always)]
            pub fn sgoutnak(&mut self) -> SgoutnakW<'_, DctlSpec> {
                SgoutnakW::new(self, 9)
            }
            #[doc = "Bit 10"]
            #[inline(always)]
            pub fn cgoutnak(&mut self) -> CgoutnakW<'_, DctlSpec> {
                CgoutnakW::new(self, 10)
            }
            #[doc = "Bit 11"]
            #[inline(always)]
            pub fn pwronprgdone(&mut self) -> PwronprgdoneW<'_, DctlSpec> {
                PwronprgdoneW::new(self, 11)
            }
        }
        #[doc = "DOTG_DCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`dctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DctlSpec;
        impl crate::RegisterSpec for DctlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dctl::R`](R) reader structure"]
        impl crate::Readable for DctlSpec {}
        #[doc = "`write(|w| ..)` method takes [`dctl::W`](W) writer structure"]
        impl crate::Writable for DctlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DCTL to value 0"]
        impl crate::Resettable for DctlSpec {}
    }
    #[doc = "DSTS (rw) register accessor: DOTG_DSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`dsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsts`] module"]
    #[doc(alias = "DSTS")]
    pub type Dsts = crate::Reg<dsts::DstsSpec>;
    #[doc = "DOTG_DSTS"]
    pub mod dsts {
        #[doc = "Register `DSTS` reader"]
        pub type R = crate::R<DstsSpec>;
        #[doc = "Register `DSTS` writer"]
        pub type W = crate::W<DstsSpec>;
        #[doc = "Field `SUSPSTS` reader - "]
        pub type SuspstsR = crate::BitReader;
        #[doc = "Field `SUSPSTS` writer - "]
        pub type SuspstsW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ENUMSPD` reader - "]
        pub type EnumspdR = crate::FieldReader;
        #[doc = "Field `ENUMSPD` writer - "]
        pub type EnumspdW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `ERRTICERR` reader - "]
        pub type ErrticerrR = crate::BitReader;
        #[doc = "Field `ERRTICERR` writer - "]
        pub type ErrticerrW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SOFFN` reader - "]
        pub type SoffnR = crate::FieldReader<u16>;
        #[doc = "Field `SOFFN` writer - "]
        pub type SoffnW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn suspsts(&self) -> SuspstsR {
                SuspstsR::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 1:2"]
            #[inline(always)]
            pub fn enumspd(&self) -> EnumspdR {
                EnumspdR::new(((self.bits >> 1) & 3) as u8)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn errticerr(&self) -> ErrticerrR {
                ErrticerrR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 8:21"]
            #[inline(always)]
            pub fn soffn(&self) -> SoffnR {
                SoffnR::new(((self.bits >> 8) & 0x3fff) as u16)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn suspsts(&mut self) -> SuspstsW<'_, DstsSpec> {
                SuspstsW::new(self, 0)
            }
            #[doc = "Bits 1:2"]
            #[inline(always)]
            pub fn enumspd(&mut self) -> EnumspdW<'_, DstsSpec> {
                EnumspdW::new(self, 1)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn errticerr(&mut self) -> ErrticerrW<'_, DstsSpec> {
                ErrticerrW::new(self, 3)
            }
            #[doc = "Bits 8:21"]
            #[inline(always)]
            pub fn soffn(&mut self) -> SoffnW<'_, DstsSpec> {
                SoffnW::new(self, 8)
            }
        }
        #[doc = "DOTG_DSTS\n\nYou can [`read`](crate::Reg::read) this register and get [`dsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DstsSpec;
        impl crate::RegisterSpec for DstsSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dsts::R`](R) reader structure"]
        impl crate::Readable for DstsSpec {}
        #[doc = "`write(|w| ..)` method takes [`dsts::W`](W) writer structure"]
        impl crate::Writable for DstsSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DSTS to value 0"]
        impl crate::Resettable for DstsSpec {}
    }
    #[doc = "DIEPMSK (rw) register accessor: DOTG_DIEPMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`diepmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`diepmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepmsk`] module"]
    #[doc(alias = "DIEPMSK")]
    pub type Diepmsk = crate::Reg<diepmsk::DiepmskSpec>;
    #[doc = "DOTG_DIEPMSK"]
    pub mod diepmsk {
        #[doc = "Register `DIEPMSK` reader"]
        pub type R = crate::R<DiepmskSpec>;
        #[doc = "Register `DIEPMSK` writer"]
        pub type W = crate::W<DiepmskSpec>;
        #[doc = "Field `XFERCOMPLMSK` reader - "]
        pub type XfercomplmskR = crate::BitReader;
        #[doc = "Field `XFERCOMPLMSK` writer - "]
        pub type XfercomplmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EPDISBLDMSK` reader - "]
        pub type EpdisbldmskR = crate::BitReader;
        #[doc = "Field `EPDISBLDMSK` writer - "]
        pub type EpdisbldmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AHBERRMSK` reader - "]
        pub type AhberrmskR = crate::BitReader;
        #[doc = "Field `AHBERRMSK` writer - "]
        pub type AhberrmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TIMEOUTMSK` reader - "]
        pub type TimeoutmskR = crate::BitReader;
        #[doc = "Field `TIMEOUTMSK` writer - "]
        pub type TimeoutmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INTKNTXFEMPMSK` reader - "]
        pub type IntkntxfempmskR = crate::BitReader;
        #[doc = "Field `INTKNTXFEMPMSK` writer - "]
        pub type IntkntxfempmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INTKNEPMISMSK` reader - "]
        pub type IntknepmismskR = crate::BitReader;
        #[doc = "Field `INTKNEPMISMSK` writer - "]
        pub type IntknepmismskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INEPNAKEFFMSK` reader - "]
        pub type InepnakeffmskR = crate::BitReader;
        #[doc = "Field `INEPNAKEFFMSK` writer - "]
        pub type InepnakeffmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXFIFOUNDRNMSK` reader - "]
        pub type TxfifoundrnmskR = crate::BitReader;
        #[doc = "Field `TXFIFOUNDRNMSK` writer - "]
        pub type TxfifoundrnmskW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn xfercomplmsk(&self) -> XfercomplmskR {
                XfercomplmskR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn epdisbldmsk(&self) -> EpdisbldmskR {
                EpdisbldmskR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn ahberrmsk(&self) -> AhberrmskR {
                AhberrmskR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn timeoutmsk(&self) -> TimeoutmskR {
                TimeoutmskR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn intkntxfempmsk(&self) -> IntkntxfempmskR {
                IntkntxfempmskR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn intknepmismsk(&self) -> IntknepmismskR {
                IntknepmismskR::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn inepnakeffmsk(&self) -> InepnakeffmskR {
                InepnakeffmskR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn txfifoundrnmsk(&self) -> TxfifoundrnmskR {
                TxfifoundrnmskR::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn xfercomplmsk(&mut self) -> XfercomplmskW<'_, DiepmskSpec> {
                XfercomplmskW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn epdisbldmsk(&mut self) -> EpdisbldmskW<'_, DiepmskSpec> {
                EpdisbldmskW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn ahberrmsk(&mut self) -> AhberrmskW<'_, DiepmskSpec> {
                AhberrmskW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn timeoutmsk(&mut self) -> TimeoutmskW<'_, DiepmskSpec> {
                TimeoutmskW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn intkntxfempmsk(&mut self) -> IntkntxfempmskW<'_, DiepmskSpec> {
                IntkntxfempmskW::new(self, 4)
            }
            #[doc = "Bit 5"]
            #[inline(always)]
            pub fn intknepmismsk(&mut self) -> IntknepmismskW<'_, DiepmskSpec> {
                IntknepmismskW::new(self, 5)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn inepnakeffmsk(&mut self) -> InepnakeffmskW<'_, DiepmskSpec> {
                InepnakeffmskW::new(self, 6)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn txfifoundrnmsk(&mut self) -> TxfifoundrnmskW<'_, DiepmskSpec> {
                TxfifoundrnmskW::new(self, 8)
            }
        }
        #[doc = "DOTG_DIEPMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`diepmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`diepmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DiepmskSpec;
        impl crate::RegisterSpec for DiepmskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`diepmsk::R`](R) reader structure"]
        impl crate::Readable for DiepmskSpec {}
        #[doc = "`write(|w| ..)` method takes [`diepmsk::W`](W) writer structure"]
        impl crate::Writable for DiepmskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DIEPMSK to value 0"]
        impl crate::Resettable for DiepmskSpec {}
    }
    #[doc = "DOEPMSK (rw) register accessor: DOTG_DOEPMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`doepmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doepmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepmsk`] module"]
    #[doc(alias = "DOEPMSK")]
    pub type Doepmsk = crate::Reg<doepmsk::DoepmskSpec>;
    #[doc = "DOTG_DOEPMSK"]
    pub mod doepmsk {
        #[doc = "Register `DOEPMSK` reader"]
        pub type R = crate::R<DoepmskSpec>;
        #[doc = "Register `DOEPMSK` writer"]
        pub type W = crate::W<DoepmskSpec>;
        #[doc = "Field `XFERCOMPLMSK` reader - "]
        pub type XfercomplmskR = crate::BitReader;
        #[doc = "Field `XFERCOMPLMSK` writer - "]
        pub type XfercomplmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EPDISBLDMSK` reader - "]
        pub type EpdisbldmskR = crate::BitReader;
        #[doc = "Field `EPDISBLDMSK` writer - "]
        pub type EpdisbldmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AHBERRMSK` reader - "]
        pub type AhberrmskR = crate::BitReader;
        #[doc = "Field `AHBERRMSK` writer - "]
        pub type AhberrmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SETUPMSK` reader - "]
        pub type SetupmskR = crate::BitReader;
        #[doc = "Field `SETUPMSK` writer - "]
        pub type SetupmskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OUTTKNEPDISMSK` reader - "]
        pub type OuttknepdismskR = crate::BitReader;
        #[doc = "Field `OUTTKNEPDISMSK` writer - "]
        pub type OuttknepdismskW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BACK2BACKSETUP` reader - "]
        pub type Back2backsetupR = crate::BitReader;
        #[doc = "Field `BACK2BACKSETUP` writer - "]
        pub type Back2backsetupW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OUTPKTERRMSK` reader - "]
        pub type OutpkterrmskR = crate::BitReader;
        #[doc = "Field `OUTPKTERRMSK` writer - "]
        pub type OutpkterrmskW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn xfercomplmsk(&self) -> XfercomplmskR {
                XfercomplmskR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn epdisbldmsk(&self) -> EpdisbldmskR {
                EpdisbldmskR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn ahberrmsk(&self) -> AhberrmskR {
                AhberrmskR::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn setupmsk(&self) -> SetupmskR {
                SetupmskR::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn outtknepdismsk(&self) -> OuttknepdismskR {
                OuttknepdismskR::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn back2backsetup(&self) -> Back2backsetupR {
                Back2backsetupR::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn outpkterrmsk(&self) -> OutpkterrmskR {
                OutpkterrmskR::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn xfercomplmsk(&mut self) -> XfercomplmskW<'_, DoepmskSpec> {
                XfercomplmskW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn epdisbldmsk(&mut self) -> EpdisbldmskW<'_, DoepmskSpec> {
                EpdisbldmskW::new(self, 1)
            }
            #[doc = "Bit 2"]
            #[inline(always)]
            pub fn ahberrmsk(&mut self) -> AhberrmskW<'_, DoepmskSpec> {
                AhberrmskW::new(self, 2)
            }
            #[doc = "Bit 3"]
            #[inline(always)]
            pub fn setupmsk(&mut self) -> SetupmskW<'_, DoepmskSpec> {
                SetupmskW::new(self, 3)
            }
            #[doc = "Bit 4"]
            #[inline(always)]
            pub fn outtknepdismsk(&mut self) -> OuttknepdismskW<'_, DoepmskSpec> {
                OuttknepdismskW::new(self, 4)
            }
            #[doc = "Bit 6"]
            #[inline(always)]
            pub fn back2backsetup(&mut self) -> Back2backsetupW<'_, DoepmskSpec> {
                Back2backsetupW::new(self, 6)
            }
            #[doc = "Bit 8"]
            #[inline(always)]
            pub fn outpkterrmsk(&mut self) -> OutpkterrmskW<'_, DoepmskSpec> {
                OutpkterrmskW::new(self, 8)
            }
        }
        #[doc = "DOTG_DOEPMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`doepmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doepmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DoepmskSpec;
        impl crate::RegisterSpec for DoepmskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`doepmsk::R`](R) reader structure"]
        impl crate::Readable for DoepmskSpec {}
        #[doc = "`write(|w| ..)` method takes [`doepmsk::W`](W) writer structure"]
        impl crate::Writable for DoepmskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DOEPMSK to value 0"]
        impl crate::Resettable for DoepmskSpec {}
    }
    #[doc = "DAINT (rw) register accessor: DOTG_DAINT\n\nYou can [`read`](crate::Reg::read) this register and get [`daint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daint`] module"]
    #[doc(alias = "DAINT")]
    pub type Daint = crate::Reg<daint::DaintSpec>;
    #[doc = "DOTG_DAINT"]
    pub mod daint {
        #[doc = "Register `DAINT` reader"]
        pub type R = crate::R<DaintSpec>;
        #[doc = "Register `DAINT` writer"]
        pub type W = crate::W<DaintSpec>;
        #[doc = "Field `INEPINT` reader - "]
        pub type InepintR = crate::FieldReader<u16>;
        #[doc = "Field `INEPINT` writer - "]
        pub type InepintW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn inepint(&self) -> InepintR {
                InepintR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn inepint(&mut self) -> InepintW<'_, DaintSpec> {
                InepintW::new(self, 0)
            }
        }
        #[doc = "DOTG_DAINT\n\nYou can [`read`](crate::Reg::read) this register and get [`daint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DaintSpec;
        impl crate::RegisterSpec for DaintSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`daint::R`](R) reader structure"]
        impl crate::Readable for DaintSpec {}
        #[doc = "`write(|w| ..)` method takes [`daint::W`](W) writer structure"]
        impl crate::Writable for DaintSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DAINT to value 0"]
        impl crate::Resettable for DaintSpec {}
    }
    #[doc = "DAINTMSK (rw) register accessor: DOTG_DAINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`daintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daintmsk`] module"]
    #[doc(alias = "DAINTMSK")]
    pub type Daintmsk = crate::Reg<daintmsk::DaintmskSpec>;
    #[doc = "DOTG_DAINTMSK"]
    pub mod daintmsk {
        #[doc = "Register `DAINTMSK` reader"]
        pub type R = crate::R<DaintmskSpec>;
        #[doc = "Register `DAINTMSK` writer"]
        pub type W = crate::W<DaintmskSpec>;
        #[doc = "Field `INEPINT` reader - "]
        pub type InepintR = crate::FieldReader<u16>;
        #[doc = "Field `INEPINT` writer - "]
        pub type InepintW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn inepint(&self) -> InepintR {
                InepintR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn inepint(&mut self) -> InepintW<'_, DaintmskSpec> {
                InepintW::new(self, 0)
            }
        }
        #[doc = "DOTG_DAINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`daintmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daintmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DaintmskSpec;
        impl crate::RegisterSpec for DaintmskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`daintmsk::R`](R) reader structure"]
        impl crate::Readable for DaintmskSpec {}
        #[doc = "`write(|w| ..)` method takes [`daintmsk::W`](W) writer structure"]
        impl crate::Writable for DaintmskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DAINTMSK to value 0"]
        impl crate::Resettable for DaintmskSpec {}
    }
    #[doc = "DTKNQR1 (rw) register accessor: DOTG_DTKNQR1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtknqr1`] module"]
    #[doc(alias = "DTKNQR1")]
    pub type Dtknqr1 = crate::Reg<dtknqr1::Dtknqr1Spec>;
    #[doc = "DOTG_DTKNQR1"]
    pub mod dtknqr1 {
        #[doc = "Register `DTKNQR1` reader"]
        pub type R = crate::R<Dtknqr1Spec>;
        #[doc = "Register `DTKNQR1` writer"]
        pub type W = crate::W<Dtknqr1Spec>;
        #[doc = "Field `INTKNWPTR` reader - "]
        pub type IntknwptrR = crate::FieldReader;
        #[doc = "Field `INTKNWPTR` writer - "]
        pub type IntknwptrW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `WRAPBIT` reader - "]
        pub type WrapbitR = crate::BitReader;
        #[doc = "Field `WRAPBIT` writer - "]
        pub type WrapbitW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EPTKN` reader - "]
        pub type EptknR = crate::FieldReader<u32>;
        #[doc = "Field `EPTKN` writer - "]
        pub type EptknW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bits 0:4"]
            #[inline(always)]
            pub fn intknwptr(&self) -> IntknwptrR {
                IntknwptrR::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn wrapbit(&self) -> WrapbitR {
                WrapbitR::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:31"]
            #[inline(always)]
            pub fn eptkn(&self) -> EptknR {
                EptknR::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:4"]
            #[inline(always)]
            pub fn intknwptr(&mut self) -> IntknwptrW<'_, Dtknqr1Spec> {
                IntknwptrW::new(self, 0)
            }
            #[doc = "Bit 7"]
            #[inline(always)]
            pub fn wrapbit(&mut self) -> WrapbitW<'_, Dtknqr1Spec> {
                WrapbitW::new(self, 7)
            }
            #[doc = "Bits 8:31"]
            #[inline(always)]
            pub fn eptkn(&mut self) -> EptknW<'_, Dtknqr1Spec> {
                EptknW::new(self, 8)
            }
        }
        #[doc = "DOTG_DTKNQR1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct Dtknqr1Spec;
        impl crate::RegisterSpec for Dtknqr1Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dtknqr1::R`](R) reader structure"]
        impl crate::Readable for Dtknqr1Spec {}
        #[doc = "`write(|w| ..)` method takes [`dtknqr1::W`](W) writer structure"]
        impl crate::Writable for Dtknqr1Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DTKNQR1 to value 0"]
        impl crate::Resettable for Dtknqr1Spec {}
    }
    #[doc = "DTKNQR2 (rw) register accessor: DOTG_DTKNQR2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtknqr2`] module"]
    #[doc(alias = "DTKNQR2")]
    pub type Dtknqr2 = crate::Reg<dtknqr2::Dtknqr2Spec>;
    #[doc = "DOTG_DTKNQR2"]
    pub mod dtknqr2 {
        #[doc = "Register `DTKNQR2` reader"]
        pub type R = crate::R<Dtknqr2Spec>;
        #[doc = "Register `DTKNQR2` writer"]
        pub type W = crate::W<Dtknqr2Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_DTKNQR2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct Dtknqr2Spec;
        impl crate::RegisterSpec for Dtknqr2Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dtknqr2::R`](R) reader structure"]
        impl crate::Readable for Dtknqr2Spec {}
        #[doc = "`write(|w| ..)` method takes [`dtknqr2::W`](W) writer structure"]
        impl crate::Writable for Dtknqr2Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DTKNQR2 to value 0"]
        impl crate::Resettable for Dtknqr2Spec {}
    }
    #[doc = "DVBUSDIS (rw) register accessor: DOTG_DVBUSDIS\n\nYou can [`read`](crate::Reg::read) this register and get [`dvbusdis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dvbusdis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbusdis`] module"]
    #[doc(alias = "DVBUSDIS")]
    pub type Dvbusdis = crate::Reg<dvbusdis::DvbusdisSpec>;
    #[doc = "DOTG_DVBUSDIS"]
    pub mod dvbusdis {
        #[doc = "Register `DVBUSDIS` reader"]
        pub type R = crate::R<DvbusdisSpec>;
        #[doc = "Register `DVBUSDIS` writer"]
        pub type W = crate::W<DvbusdisSpec>;
        #[doc = "Field `DVBUSDIS` reader - "]
        pub type DvbusdisR = crate::FieldReader<u16>;
        #[doc = "Field `DVBUSDIS` writer - "]
        pub type DvbusdisW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn dvbusdis(&self) -> DvbusdisR {
                DvbusdisR::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15"]
            #[inline(always)]
            pub fn dvbusdis(&mut self) -> DvbusdisW<'_, DvbusdisSpec> {
                DvbusdisW::new(self, 0)
            }
        }
        #[doc = "DOTG_DVBUSDIS\n\nYou can [`read`](crate::Reg::read) this register and get [`dvbusdis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dvbusdis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DvbusdisSpec;
        impl crate::RegisterSpec for DvbusdisSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dvbusdis::R`](R) reader structure"]
        impl crate::Readable for DvbusdisSpec {}
        #[doc = "`write(|w| ..)` method takes [`dvbusdis::W`](W) writer structure"]
        impl crate::Writable for DvbusdisSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DVBUSDIS to value 0"]
        impl crate::Resettable for DvbusdisSpec {}
    }
    #[doc = "DVBUSPULSE (rw) register accessor: DOTG_DVBUSPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`dvbuspulse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dvbuspulse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbuspulse`] module"]
    #[doc(alias = "DVBUSPULSE")]
    pub type Dvbuspulse = crate::Reg<dvbuspulse::DvbuspulseSpec>;
    #[doc = "DOTG_DVBUSPULSE"]
    pub mod dvbuspulse {
        #[doc = "Register `DVBUSPULSE` reader"]
        pub type R = crate::R<DvbuspulseSpec>;
        #[doc = "Register `DVBUSPULSE` writer"]
        pub type W = crate::W<DvbuspulseSpec>;
        #[doc = "Field `DVBUSPULSE` reader - "]
        pub type DvbuspulseR = crate::FieldReader<u16>;
        #[doc = "Field `DVBUSPULSE` writer - "]
        pub type DvbuspulseW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        impl R {
            #[doc = "Bits 0:11"]
            #[inline(always)]
            pub fn dvbuspulse(&self) -> DvbuspulseR {
                DvbuspulseR::new((self.bits & 0x0fff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:11"]
            #[inline(always)]
            pub fn dvbuspulse(&mut self) -> DvbuspulseW<'_, DvbuspulseSpec> {
                DvbuspulseW::new(self, 0)
            }
        }
        #[doc = "DOTG_DVBUSPULSE\n\nYou can [`read`](crate::Reg::read) this register and get [`dvbuspulse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dvbuspulse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DvbuspulseSpec;
        impl crate::RegisterSpec for DvbuspulseSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dvbuspulse::R`](R) reader structure"]
        impl crate::Readable for DvbuspulseSpec {}
        #[doc = "`write(|w| ..)` method takes [`dvbuspulse::W`](W) writer structure"]
        impl crate::Writable for DvbuspulseSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DVBUSPULSE to value 0"]
        impl crate::Resettable for DvbuspulseSpec {}
    }
    #[doc = "DTHRCTL (rw) register accessor: DOTG_DTHRCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`dthrctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dthrctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dthrctl`] module"]
    #[doc(alias = "DTHRCTL")]
    pub type Dthrctl = crate::Reg<dthrctl::DthrctlSpec>;
    #[doc = "DOTG_DTHRCTL"]
    pub mod dthrctl {
        #[doc = "Register `DTHRCTL` reader"]
        pub type R = crate::R<DthrctlSpec>;
        #[doc = "Register `DTHRCTL` writer"]
        pub type W = crate::W<DthrctlSpec>;
        #[doc = "Field `NONISOTHREN` reader - "]
        pub type NonisothrenR = crate::BitReader;
        #[doc = "Field `NONISOTHREN` writer - "]
        pub type NonisothrenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ISOTHREN` reader - "]
        pub type IsothrenR = crate::BitReader;
        #[doc = "Field `ISOTHREN` writer - "]
        pub type IsothrenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXTHRLEN` reader - "]
        pub type TxthrlenR = crate::FieldReader<u16>;
        #[doc = "Field `TXTHRLEN` writer - "]
        pub type TxthrlenW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `RXTHREN` reader - "]
        pub type RxthrenR = crate::BitReader;
        #[doc = "Field `RXTHREN` writer - "]
        pub type RxthrenW<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXTHRLEN` reader - "]
        pub type RxthrlenR = crate::FieldReader<u16>;
        #[doc = "Field `RXTHRLEN` writer - "]
        pub type RxthrlenW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `ARBPRKEN` reader - "]
        pub type ArbprkenR = crate::BitReader;
        #[doc = "Field `ARBPRKEN` writer - "]
        pub type ArbprkenW<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn nonisothren(&self) -> NonisothrenR {
                NonisothrenR::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn isothren(&self) -> IsothrenR {
                IsothrenR::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bits 2:10"]
            #[inline(always)]
            pub fn txthrlen(&self) -> TxthrlenR {
                TxthrlenR::new(((self.bits >> 2) & 0x01ff) as u16)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn rxthren(&self) -> RxthrenR {
                RxthrenR::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bits 17:25"]
            #[inline(always)]
            pub fn rxthrlen(&self) -> RxthrlenR {
                RxthrlenR::new(((self.bits >> 17) & 0x01ff) as u16)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn arbprken(&self) -> ArbprkenR {
                ArbprkenR::new(((self.bits >> 27) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0"]
            #[inline(always)]
            pub fn nonisothren(&mut self) -> NonisothrenW<'_, DthrctlSpec> {
                NonisothrenW::new(self, 0)
            }
            #[doc = "Bit 1"]
            #[inline(always)]
            pub fn isothren(&mut self) -> IsothrenW<'_, DthrctlSpec> {
                IsothrenW::new(self, 1)
            }
            #[doc = "Bits 2:10"]
            #[inline(always)]
            pub fn txthrlen(&mut self) -> TxthrlenW<'_, DthrctlSpec> {
                TxthrlenW::new(self, 2)
            }
            #[doc = "Bit 16"]
            #[inline(always)]
            pub fn rxthren(&mut self) -> RxthrenW<'_, DthrctlSpec> {
                RxthrenW::new(self, 16)
            }
            #[doc = "Bits 17:25"]
            #[inline(always)]
            pub fn rxthrlen(&mut self) -> RxthrlenW<'_, DthrctlSpec> {
                RxthrlenW::new(self, 17)
            }
            #[doc = "Bit 27"]
            #[inline(always)]
            pub fn arbprken(&mut self) -> ArbprkenW<'_, DthrctlSpec> {
                ArbprkenW::new(self, 27)
            }
        }
        #[doc = "DOTG_DTHRCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`dthrctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dthrctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DthrctlSpec;
        impl crate::RegisterSpec for DthrctlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dthrctl::R`](R) reader structure"]
        impl crate::Readable for DthrctlSpec {}
        #[doc = "`write(|w| ..)` method takes [`dthrctl::W`](W) writer structure"]
        impl crate::Writable for DthrctlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DTHRCTL to value 0"]
        impl crate::Resettable for DthrctlSpec {}
    }
    #[doc = "DTKNQR4 (rw) register accessor: DOTG_DTKNQR4\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtknqr4`] module"]
    #[doc(alias = "DTKNQR4")]
    pub type Dtknqr4 = crate::Reg<dtknqr4::Dtknqr4Spec>;
    #[doc = "DOTG_DTKNQR4"]
    pub mod dtknqr4 {
        #[doc = "Register `DTKNQR4` reader"]
        pub type R = crate::R<Dtknqr4Spec>;
        #[doc = "Register `DTKNQR4` writer"]
        pub type W = crate::W<Dtknqr4Spec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_DTKNQR4\n\nYou can [`read`](crate::Reg::read) this register and get [`dtknqr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtknqr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct Dtknqr4Spec;
        impl crate::RegisterSpec for Dtknqr4Spec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dtknqr4::R`](R) reader structure"]
        impl crate::Readable for Dtknqr4Spec {}
        #[doc = "`write(|w| ..)` method takes [`dtknqr4::W`](W) writer structure"]
        impl crate::Writable for Dtknqr4Spec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DTKNQR4 to value 0"]
        impl crate::Resettable for Dtknqr4Spec {}
    }
    #[doc = "DEACHINT (rw) register accessor: DOTG_DEACHINT\n\nYou can [`read`](crate::Reg::read) this register and get [`deachint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deachint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachint`] module"]
    #[doc(alias = "DEACHINT")]
    pub type Deachint = crate::Reg<deachint::DeachintSpec>;
    #[doc = "DOTG_DEACHINT"]
    pub mod deachint {
        #[doc = "Register `DEACHINT` reader"]
        pub type R = crate::R<DeachintSpec>;
        #[doc = "Register `DEACHINT` writer"]
        pub type W = crate::W<DeachintSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_DEACHINT\n\nYou can [`read`](crate::Reg::read) this register and get [`deachint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deachint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DeachintSpec;
        impl crate::RegisterSpec for DeachintSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`deachint::R`](R) reader structure"]
        impl crate::Readable for DeachintSpec {}
        #[doc = "`write(|w| ..)` method takes [`deachint::W`](W) writer structure"]
        impl crate::Writable for DeachintSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DEACHINT to value 0"]
        impl crate::Resettable for DeachintSpec {}
    }
    #[doc = "DEACHINTMSK (rw) register accessor: DOTG_DEACHINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`deachintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deachintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachintmsk`] module"]
    #[doc(alias = "DEACHINTMSK")]
    pub type Deachintmsk = crate::Reg<deachintmsk::DeachintmskSpec>;
    #[doc = "DOTG_DEACHINTMSK"]
    pub mod deachintmsk {
        #[doc = "Register `DEACHINTMSK` reader"]
        pub type R = crate::R<DeachintmskSpec>;
        #[doc = "Register `DEACHINTMSK` writer"]
        pub type W = crate::W<DeachintmskSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_DEACHINTMSK\n\nYou can [`read`](crate::Reg::read) this register and get [`deachintmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deachintmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DeachintmskSpec;
        impl crate::RegisterSpec for DeachintmskSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`deachintmsk::R`](R) reader structure"]
        impl crate::Readable for DeachintmskSpec {}
        #[doc = "`write(|w| ..)` method takes [`deachintmsk::W`](W) writer structure"]
        impl crate::Writable for DeachintmskSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets DEACHINTMSK to value 0"]
        impl crate::Resettable for DeachintmskSpec {}
    }
    #[doc = "PCGCCTL (rw) register accessor: DOTG_PCGCCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`pcgcctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcgcctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcgcctl`] module"]
    #[doc(alias = "PCGCCTL")]
    pub type Pcgcctl = crate::Reg<pcgcctl::PcgcctlSpec>;
    #[doc = "DOTG_PCGCCTL"]
    pub mod pcgcctl {
        #[doc = "Register `PCGCCTL` reader"]
        pub type R = crate::R<PcgcctlSpec>;
        #[doc = "Register `PCGCCTL` writer"]
        pub type W = crate::W<PcgcctlSpec>;
        impl core::fmt::Debug for R {
            fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
                write!(f, "{}", self.bits())
            }
        }
        impl W {}
        #[doc = "DOTG_PCGCCTL\n\nYou can [`read`](crate::Reg::read) this register and get [`pcgcctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcgcctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PcgcctlSpec;
        impl crate::RegisterSpec for PcgcctlSpec {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pcgcctl::R`](R) reader structure"]
        impl crate::Readable for PcgcctlSpec {}
        #[doc = "`write(|w| ..)` method takes [`pcgcctl::W`](W) writer structure"]
        impl crate::Writable for PcgcctlSpec {
            type Safety = crate::Unsafe;
        }
        #[doc = "`reset()` method sets PCGCCTL to value 0"]
        impl crate::Resettable for PcgcctlSpec {}
    }
}
#[unsafe(no_mangle)]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
    #[doc = "GLB_CTL_M"]
    pub glb_ctl_m: GlbCtlM,
    #[doc = "GPIO0"]
    pub gpio0: Gpio0,
    #[doc = "UART0"]
    pub uart0: Uart0,
    #[doc = "TIMER"]
    pub timer: Timer,
    #[doc = "WDT"]
    pub wdt: Wdt,
    #[doc = "TCXO"]
    pub tcxo: Tcxo,
    #[doc = "I2C0"]
    pub i2c0: I2c0,
    #[doc = "SPI0"]
    pub spi0: Spi0,
    #[doc = "PWM"]
    pub pwm: Pwm,
    #[doc = "DMA"]
    pub dma: Dma,
    #[doc = "RTC"]
    pub rtc: Rtc,
    #[doc = "TRNG"]
    pub trng: Trng,
    #[doc = "GPIO1"]
    pub gpio1: Gpio1,
    #[doc = "GPIO2"]
    pub gpio2: Gpio2,
    #[doc = "GPIO3"]
    pub gpio3: Gpio3,
    #[doc = "GPIO4"]
    pub gpio4: Gpio4,
    #[doc = "ULP_GPIO"]
    pub ulp_gpio: UlpGpio,
    #[doc = "UART1"]
    pub uart1: Uart1,
    #[doc = "UART2"]
    pub uart2: Uart2,
    #[doc = "I2C1"]
    pub i2c1: I2c1,
    #[doc = "SPI1"]
    pub spi1: Spi1,
    #[doc = "SPI2"]
    pub spi2: Spi2,
    #[doc = "SDMA"]
    pub sdma: Sdma,
    #[doc = "GADC"]
    pub gadc: Gadc,
    #[doc = "KEYSCAN"]
    pub keyscan: Keyscan,
    #[doc = "PDM"]
    pub pdm: Pdm,
    #[doc = "QDEC"]
    pub qdec: Qdec,
    #[doc = "USB"]
    pub usb: Usb,
}
impl Peripherals {
    #[doc = r" Returns all the peripherals *once*."]
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    #[doc = r" Unchecked version of `Peripherals::take`."]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Each of the returned peripherals must be used at most once."]
    #[inline]
    pub unsafe fn steal() -> Self {
        unsafe {
            DEVICE_PERIPHERALS = true;
            Peripherals {
                glb_ctl_m: GlbCtlM::steal(),
                gpio0: Gpio0::steal(),
                uart0: Uart0::steal(),
                timer: Timer::steal(),
                wdt: Wdt::steal(),
                tcxo: Tcxo::steal(),
                i2c0: I2c0::steal(),
                spi0: Spi0::steal(),
                pwm: Pwm::steal(),
                dma: Dma::steal(),
                rtc: Rtc::steal(),
                trng: Trng::steal(),
                gpio1: Gpio1::steal(),
                gpio2: Gpio2::steal(),
                gpio3: Gpio3::steal(),
                gpio4: Gpio4::steal(),
                ulp_gpio: UlpGpio::steal(),
                uart1: Uart1::steal(),
                uart2: Uart2::steal(),
                i2c1: I2c1::steal(),
                spi1: Spi1::steal(),
                spi2: Spi2::steal(),
                sdma: Sdma::steal(),
                gadc: Gadc::steal(),
                keyscan: Keyscan::steal(),
                pdm: Pdm::steal(),
                qdec: Qdec::steal(),
                usb: Usb::steal(),
            }
        }
    }
}