pub struct Registers;
#[allow(dead_code)]
impl Registers {
pub const CHIP_ID: u8 = 0x01;
pub const REV_ID: u8 = 0x02;
pub const CHIP_STATUS: u8 = 0x11;
pub const DRIVE_CONFIG: u8 = 0x13;
pub const INT_CONFIG: u8 = 0x14;
pub const INT_SOURCE: u8 = 0x15;
pub const FIFO_CONFIG: u8 = 0x16;
pub const FIFO_COUNT: u8 = 0x17;
pub const FIFO_SEL: u8 = 0x18;
pub const TEMP_DATA_XLSB: u8 = 0x1D;
pub const TEMP_DATA_LSB: u8 = 0x1E;
pub const TEMP_DATA_MSB: u8 = 0x1F;
pub const PRESS_DATA_XLSB: u8 = 0x20;
pub const PRESS_DATA_LSB: u8 = 0x21;
pub const PRESS_DATA_MSB: u8 = 0x22;
pub const INT_STATUS: u8 = 0x27;
pub const STATUS: u8 = 0x28;
pub const FIFO_DATA: u8 = 0x29;
pub const NVM_ADDR: u8 = 0x2B;
pub const NVM_DATA_LSB: u8 = 0x2C;
pub const NVM_DATA_MSB: u8 = 0x2D;
pub const DSP_CONFIG: u8 = 0x30;
pub const DSP_IIR: u8 = 0x31;
pub const OOR_THR_P_LSB: u8 = 0x32;
pub const OOR_THR_P_MSB: u8 = 0x33;
pub const OOR_RANGE: u8 = 0x34;
pub const OOR_CONFIG: u8 = 0x35;
pub const OSR_CONFIG: u8 = 0x36;
pub const ODR_CONFIG: u8 = 0x37;
pub const OSR_EFF: u8 = 0x38;
pub const CMD: u8 = 0x7E;
}