bl808_pac/i2c/
interrupt.rs

1#[doc = "Register `interrupt` reader"]
2pub struct R(crate::R<INTERRUPT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTERRUPT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTERRUPT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTERRUPT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `interrupt` writer"]
17pub struct W(crate::W<INTERRUPT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTERRUPT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTERRUPT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTERRUPT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `transfer_end_state` reader - Transfer ended interrupt state"]
38pub use FIFO_ERROR_STATE_R as TRANSFER_END_STATE_R;
39#[doc = "Field `transmit_fifo_ready_state` reader - Transmit FIFO ready interrupt state\n\n Auto cleared when data is pushed into transmit FIFO."]
40pub use FIFO_ERROR_STATE_R as TRANSMIT_FIFO_READY_STATE_R;
41#[doc = "Field `receive_fifo_ready_state` reader - Receive FIFO ready interrupt state\n\n Auto cleared when data is popped from receive FIFO."]
42pub use FIFO_ERROR_STATE_R as RECEIVE_FIFO_READY_STATE_R;
43#[doc = "Field `not_acknowledged_state` reader - Not-acknowledged response interrupt state"]
44pub use FIFO_ERROR_STATE_R as NOT_ACKNOWLEDGED_STATE_R;
45#[doc = "Field `arbitrate_lost_state` reader - Arbitration lost interrupt state"]
46pub use FIFO_ERROR_STATE_R as ARBITRATE_LOST_STATE_R;
47#[doc = "Field `fifo_error_state` reader - Transmit or receive FIFO error interrupt state\n\n Auto cleared when FIFO overflow or underflow error flag is cleared."]
48pub type FIFO_ERROR_STATE_R = crate::BitReader<INTERRUPT_STATE_A>;
49#[doc = "Transmit or receive FIFO error interrupt state\n\n Auto cleared when FIFO overflow or underflow error flag is cleared.\n\nValue on reset: 0"]
50#[derive(Clone, Copy, Debug, PartialEq, Eq)]
51pub enum INTERRUPT_STATE_A {
52    #[doc = "1: Has interrupt"]
53    HAS_INTERRUPT = 1,
54    #[doc = "0: No interrupt occurred"]
55    NO_INTERRUPT = 0,
56}
57impl From<INTERRUPT_STATE_A> for bool {
58    #[inline(always)]
59    fn from(variant: INTERRUPT_STATE_A) -> Self {
60        variant as u8 != 0
61    }
62}
63impl FIFO_ERROR_STATE_R {
64    #[doc = "Get enumerated values variant"]
65    #[inline(always)]
66    pub fn variant(&self) -> INTERRUPT_STATE_A {
67        match self.bits {
68            true => INTERRUPT_STATE_A::HAS_INTERRUPT,
69            false => INTERRUPT_STATE_A::NO_INTERRUPT,
70        }
71    }
72    #[doc = "Checks if the value of the field is `HAS_INTERRUPT`"]
73    #[inline(always)]
74    pub fn is_has_interrupt(&self) -> bool {
75        *self == INTERRUPT_STATE_A::HAS_INTERRUPT
76    }
77    #[doc = "Checks if the value of the field is `NO_INTERRUPT`"]
78    #[inline(always)]
79    pub fn is_no_interrupt(&self) -> bool {
80        *self == INTERRUPT_STATE_A::NO_INTERRUPT
81    }
82}
83#[doc = "Field `transfer_end_mask` reader - Transfer ended interrupt mask"]
84pub use FIFO_ERROR_MASK_R as TRANSFER_END_MASK_R;
85#[doc = "Field `transmit_fifo_ready_mask` reader - Transmit FIFO ready interrupt mask"]
86pub use FIFO_ERROR_MASK_R as TRANSMIT_FIFO_READY_MASK_R;
87#[doc = "Field `receive_fifo_ready_mask` reader - Receive FIFO ready interrupt mask"]
88pub use FIFO_ERROR_MASK_R as RECEIVE_FIFO_READY_MASK_R;
89#[doc = "Field `not_acknowledged_mask` reader - Not-acknowledged response interrupt mask"]
90pub use FIFO_ERROR_MASK_R as NOT_ACKNOWLEDGED_MASK_R;
91#[doc = "Field `arbitrate_lost_mask` reader - Arbitration lost interrupt mask"]
92pub use FIFO_ERROR_MASK_R as ARBITRATE_LOST_MASK_R;
93#[doc = "Field `transfer_end_mask` writer - Transfer ended interrupt mask"]
94pub use FIFO_ERROR_MASK_W as TRANSFER_END_MASK_W;
95#[doc = "Field `transmit_fifo_ready_mask` writer - Transmit FIFO ready interrupt mask"]
96pub use FIFO_ERROR_MASK_W as TRANSMIT_FIFO_READY_MASK_W;
97#[doc = "Field `receive_fifo_ready_mask` writer - Receive FIFO ready interrupt mask"]
98pub use FIFO_ERROR_MASK_W as RECEIVE_FIFO_READY_MASK_W;
99#[doc = "Field `not_acknowledged_mask` writer - Not-acknowledged response interrupt mask"]
100pub use FIFO_ERROR_MASK_W as NOT_ACKNOWLEDGED_MASK_W;
101#[doc = "Field `arbitrate_lost_mask` writer - Arbitration lost interrupt mask"]
102pub use FIFO_ERROR_MASK_W as ARBITRATE_LOST_MASK_W;
103#[doc = "Field `fifo_error_mask` reader - Transmit or receive FIFO error interrupt mask"]
104pub type FIFO_ERROR_MASK_R = crate::BitReader<INTERRUPT_MASK_A>;
105#[doc = "Transmit or receive FIFO error interrupt mask\n\nValue on reset: 1"]
106#[derive(Clone, Copy, Debug, PartialEq, Eq)]
107pub enum INTERRUPT_MASK_A {
108    #[doc = "1: Mask interrupt"]
109    MASK = 1,
110    #[doc = "0: Unmask interrupt"]
111    UNMASK = 0,
112}
113impl From<INTERRUPT_MASK_A> for bool {
114    #[inline(always)]
115    fn from(variant: INTERRUPT_MASK_A) -> Self {
116        variant as u8 != 0
117    }
118}
119impl FIFO_ERROR_MASK_R {
120    #[doc = "Get enumerated values variant"]
121    #[inline(always)]
122    pub fn variant(&self) -> INTERRUPT_MASK_A {
123        match self.bits {
124            true => INTERRUPT_MASK_A::MASK,
125            false => INTERRUPT_MASK_A::UNMASK,
126        }
127    }
128    #[doc = "Checks if the value of the field is `MASK`"]
129    #[inline(always)]
130    pub fn is_mask(&self) -> bool {
131        *self == INTERRUPT_MASK_A::MASK
132    }
133    #[doc = "Checks if the value of the field is `UNMASK`"]
134    #[inline(always)]
135    pub fn is_unmask(&self) -> bool {
136        *self == INTERRUPT_MASK_A::UNMASK
137    }
138}
139#[doc = "Field `fifo_error_mask` writer - Transmit or receive FIFO error interrupt mask"]
140pub type FIFO_ERROR_MASK_W<'a, const O: u8> =
141    crate::BitWriter<'a, u32, INTERRUPT_SPEC, INTERRUPT_MASK_A, O>;
142impl<'a, const O: u8> FIFO_ERROR_MASK_W<'a, O> {
143    #[doc = "Mask interrupt"]
144    #[inline(always)]
145    pub fn mask(self) -> &'a mut W {
146        self.variant(INTERRUPT_MASK_A::MASK)
147    }
148    #[doc = "Unmask interrupt"]
149    #[inline(always)]
150    pub fn unmask(self) -> &'a mut W {
151        self.variant(INTERRUPT_MASK_A::UNMASK)
152    }
153}
154#[doc = "Field `transfer_end_clear` writer - Write 1 to clear transfer ended"]
155pub use ARBITRATE_LOST_CLEAR_W as TRANSFER_END_CLEAR_W;
156#[doc = "Field `not_acknowledged_clear` writer - Write 1 to clear not-acknowledged response"]
157pub use ARBITRATE_LOST_CLEAR_W as NOT_ACKNOWLEDGED_CLEAR_W;
158#[doc = "Write 1 to clear arbitration lost\n\nValue on reset: 0"]
159#[derive(Clone, Copy, Debug, PartialEq, Eq)]
160pub enum INTERRUPT_CLEAR_AW {
161    #[doc = "1: Write 1 to clear interrupt state"]
162    CLEAR = 1,
163}
164impl From<INTERRUPT_CLEAR_AW> for bool {
165    #[inline(always)]
166    fn from(variant: INTERRUPT_CLEAR_AW) -> Self {
167        variant as u8 != 0
168    }
169}
170#[doc = "Field `arbitrate_lost_clear` writer - Write 1 to clear arbitration lost"]
171pub type ARBITRATE_LOST_CLEAR_W<'a, const O: u8> =
172    crate::BitWriter<'a, u32, INTERRUPT_SPEC, INTERRUPT_CLEAR_AW, O>;
173impl<'a, const O: u8> ARBITRATE_LOST_CLEAR_W<'a, O> {
174    #[doc = "Write 1 to clear interrupt state"]
175    #[inline(always)]
176    pub fn clear(self) -> &'a mut W {
177        self.variant(INTERRUPT_CLEAR_AW::CLEAR)
178    }
179}
180#[doc = "Field `transfer_end_enable` reader - Transfer ended interrupt enable"]
181pub use FIFO_ERROR_ENABLE_R as TRANSFER_END_ENABLE_R;
182#[doc = "Field `transmit_fifo_ready_enable` reader - Transmit FIFO ready interrupt enable"]
183pub use FIFO_ERROR_ENABLE_R as TRANSMIT_FIFO_READY_ENABLE_R;
184#[doc = "Field `receive_fifo_ready_enable` reader - Receive FIFO ready interrupt enable"]
185pub use FIFO_ERROR_ENABLE_R as RECEIVE_FIFO_READY_ENABLE_R;
186#[doc = "Field `not_acknowledged_enable` reader - Not-acknowledged response interrupt enable"]
187pub use FIFO_ERROR_ENABLE_R as NOT_ACKNOWLEDGED_ENABLE_R;
188#[doc = "Field `arbitrate_lost_enable` reader - Arbitration lost interrupt enable"]
189pub use FIFO_ERROR_ENABLE_R as ARBITRATE_LOST_ENABLE_R;
190#[doc = "Field `transfer_end_enable` writer - Transfer ended interrupt enable"]
191pub use FIFO_ERROR_ENABLE_W as TRANSFER_END_ENABLE_W;
192#[doc = "Field `transmit_fifo_ready_enable` writer - Transmit FIFO ready interrupt enable"]
193pub use FIFO_ERROR_ENABLE_W as TRANSMIT_FIFO_READY_ENABLE_W;
194#[doc = "Field `receive_fifo_ready_enable` writer - Receive FIFO ready interrupt enable"]
195pub use FIFO_ERROR_ENABLE_W as RECEIVE_FIFO_READY_ENABLE_W;
196#[doc = "Field `not_acknowledged_enable` writer - Not-acknowledged response interrupt enable"]
197pub use FIFO_ERROR_ENABLE_W as NOT_ACKNOWLEDGED_ENABLE_W;
198#[doc = "Field `arbitrate_lost_enable` writer - Arbitration lost interrupt enable"]
199pub use FIFO_ERROR_ENABLE_W as ARBITRATE_LOST_ENABLE_W;
200#[doc = "Field `fifo_error_enable` reader - Transmit or receive FIFO error interrupt enable"]
201pub type FIFO_ERROR_ENABLE_R = crate::BitReader<INTERRUPT_ENABLE_A>;
202#[doc = "Transmit or receive FIFO error interrupt enable\n\nValue on reset: 1"]
203#[derive(Clone, Copy, Debug, PartialEq, Eq)]
204pub enum INTERRUPT_ENABLE_A {
205    #[doc = "1: Enable interrupt"]
206    ENABLE = 1,
207    #[doc = "0: Disable interrupt"]
208    DISABLE = 0,
209}
210impl From<INTERRUPT_ENABLE_A> for bool {
211    #[inline(always)]
212    fn from(variant: INTERRUPT_ENABLE_A) -> Self {
213        variant as u8 != 0
214    }
215}
216impl FIFO_ERROR_ENABLE_R {
217    #[doc = "Get enumerated values variant"]
218    #[inline(always)]
219    pub fn variant(&self) -> INTERRUPT_ENABLE_A {
220        match self.bits {
221            true => INTERRUPT_ENABLE_A::ENABLE,
222            false => INTERRUPT_ENABLE_A::DISABLE,
223        }
224    }
225    #[doc = "Checks if the value of the field is `ENABLE`"]
226    #[inline(always)]
227    pub fn is_enable(&self) -> bool {
228        *self == INTERRUPT_ENABLE_A::ENABLE
229    }
230    #[doc = "Checks if the value of the field is `DISABLE`"]
231    #[inline(always)]
232    pub fn is_disable(&self) -> bool {
233        *self == INTERRUPT_ENABLE_A::DISABLE
234    }
235}
236#[doc = "Field `fifo_error_enable` writer - Transmit or receive FIFO error interrupt enable"]
237pub type FIFO_ERROR_ENABLE_W<'a, const O: u8> =
238    crate::BitWriter<'a, u32, INTERRUPT_SPEC, INTERRUPT_ENABLE_A, O>;
239impl<'a, const O: u8> FIFO_ERROR_ENABLE_W<'a, O> {
240    #[doc = "Enable interrupt"]
241    #[inline(always)]
242    pub fn enable(self) -> &'a mut W {
243        self.variant(INTERRUPT_ENABLE_A::ENABLE)
244    }
245    #[doc = "Disable interrupt"]
246    #[inline(always)]
247    pub fn disable(self) -> &'a mut W {
248        self.variant(INTERRUPT_ENABLE_A::DISABLE)
249    }
250}
251impl R {
252    #[doc = "Bit 0 - Transfer ended interrupt state"]
253    #[inline(always)]
254    pub fn transfer_end_state(&self) -> TRANSFER_END_STATE_R {
255        TRANSFER_END_STATE_R::new((self.bits & 1) != 0)
256    }
257    #[doc = "Bit 1 - Transmit FIFO ready interrupt state\n\n Auto cleared when data is pushed into transmit FIFO."]
258    #[inline(always)]
259    pub fn transmit_fifo_ready_state(&self) -> TRANSMIT_FIFO_READY_STATE_R {
260        TRANSMIT_FIFO_READY_STATE_R::new(((self.bits >> 1) & 1) != 0)
261    }
262    #[doc = "Bit 2 - Receive FIFO ready interrupt state\n\n Auto cleared when data is popped from receive FIFO."]
263    #[inline(always)]
264    pub fn receive_fifo_ready_state(&self) -> RECEIVE_FIFO_READY_STATE_R {
265        RECEIVE_FIFO_READY_STATE_R::new(((self.bits >> 2) & 1) != 0)
266    }
267    #[doc = "Bit 3 - Not-acknowledged response interrupt state"]
268    #[inline(always)]
269    pub fn not_acknowledged_state(&self) -> NOT_ACKNOWLEDGED_STATE_R {
270        NOT_ACKNOWLEDGED_STATE_R::new(((self.bits >> 3) & 1) != 0)
271    }
272    #[doc = "Bit 4 - Arbitration lost interrupt state"]
273    #[inline(always)]
274    pub fn arbitrate_lost_state(&self) -> ARBITRATE_LOST_STATE_R {
275        ARBITRATE_LOST_STATE_R::new(((self.bits >> 4) & 1) != 0)
276    }
277    #[doc = "Bit 5 - Transmit or receive FIFO error interrupt state\n\n Auto cleared when FIFO overflow or underflow error flag is cleared."]
278    #[inline(always)]
279    pub fn fifo_error_state(&self) -> FIFO_ERROR_STATE_R {
280        FIFO_ERROR_STATE_R::new(((self.bits >> 5) & 1) != 0)
281    }
282    #[doc = "Bit 8 - Transfer ended interrupt mask"]
283    #[inline(always)]
284    pub fn transfer_end_mask(&self) -> TRANSFER_END_MASK_R {
285        TRANSFER_END_MASK_R::new(((self.bits >> 8) & 1) != 0)
286    }
287    #[doc = "Bit 9 - Transmit FIFO ready interrupt mask"]
288    #[inline(always)]
289    pub fn transmit_fifo_ready_mask(&self) -> TRANSMIT_FIFO_READY_MASK_R {
290        TRANSMIT_FIFO_READY_MASK_R::new(((self.bits >> 9) & 1) != 0)
291    }
292    #[doc = "Bit 10 - Receive FIFO ready interrupt mask"]
293    #[inline(always)]
294    pub fn receive_fifo_ready_mask(&self) -> RECEIVE_FIFO_READY_MASK_R {
295        RECEIVE_FIFO_READY_MASK_R::new(((self.bits >> 10) & 1) != 0)
296    }
297    #[doc = "Bit 11 - Not-acknowledged response interrupt mask"]
298    #[inline(always)]
299    pub fn not_acknowledged_mask(&self) -> NOT_ACKNOWLEDGED_MASK_R {
300        NOT_ACKNOWLEDGED_MASK_R::new(((self.bits >> 11) & 1) != 0)
301    }
302    #[doc = "Bit 12 - Arbitration lost interrupt mask"]
303    #[inline(always)]
304    pub fn arbitrate_lost_mask(&self) -> ARBITRATE_LOST_MASK_R {
305        ARBITRATE_LOST_MASK_R::new(((self.bits >> 12) & 1) != 0)
306    }
307    #[doc = "Bit 13 - Transmit or receive FIFO error interrupt mask"]
308    #[inline(always)]
309    pub fn fifo_error_mask(&self) -> FIFO_ERROR_MASK_R {
310        FIFO_ERROR_MASK_R::new(((self.bits >> 13) & 1) != 0)
311    }
312    #[doc = "Bit 24 - Transfer ended interrupt enable"]
313    #[inline(always)]
314    pub fn transfer_end_enable(&self) -> TRANSFER_END_ENABLE_R {
315        TRANSFER_END_ENABLE_R::new(((self.bits >> 24) & 1) != 0)
316    }
317    #[doc = "Bit 25 - Transmit FIFO ready interrupt enable"]
318    #[inline(always)]
319    pub fn transmit_fifo_ready_enable(&self) -> TRANSMIT_FIFO_READY_ENABLE_R {
320        TRANSMIT_FIFO_READY_ENABLE_R::new(((self.bits >> 25) & 1) != 0)
321    }
322    #[doc = "Bit 26 - Receive FIFO ready interrupt enable"]
323    #[inline(always)]
324    pub fn receive_fifo_ready_enable(&self) -> RECEIVE_FIFO_READY_ENABLE_R {
325        RECEIVE_FIFO_READY_ENABLE_R::new(((self.bits >> 26) & 1) != 0)
326    }
327    #[doc = "Bit 27 - Not-acknowledged response interrupt enable"]
328    #[inline(always)]
329    pub fn not_acknowledged_enable(&self) -> NOT_ACKNOWLEDGED_ENABLE_R {
330        NOT_ACKNOWLEDGED_ENABLE_R::new(((self.bits >> 27) & 1) != 0)
331    }
332    #[doc = "Bit 28 - Arbitration lost interrupt enable"]
333    #[inline(always)]
334    pub fn arbitrate_lost_enable(&self) -> ARBITRATE_LOST_ENABLE_R {
335        ARBITRATE_LOST_ENABLE_R::new(((self.bits >> 28) & 1) != 0)
336    }
337    #[doc = "Bit 29 - Transmit or receive FIFO error interrupt enable"]
338    #[inline(always)]
339    pub fn fifo_error_enable(&self) -> FIFO_ERROR_ENABLE_R {
340        FIFO_ERROR_ENABLE_R::new(((self.bits >> 29) & 1) != 0)
341    }
342}
343impl W {
344    #[doc = "Bit 8 - Transfer ended interrupt mask"]
345    #[inline(always)]
346    pub fn transfer_end_mask(&mut self) -> TRANSFER_END_MASK_W<8> {
347        TRANSFER_END_MASK_W::new(self)
348    }
349    #[doc = "Bit 9 - Transmit FIFO ready interrupt mask"]
350    #[inline(always)]
351    pub fn transmit_fifo_ready_mask(&mut self) -> TRANSMIT_FIFO_READY_MASK_W<9> {
352        TRANSMIT_FIFO_READY_MASK_W::new(self)
353    }
354    #[doc = "Bit 10 - Receive FIFO ready interrupt mask"]
355    #[inline(always)]
356    pub fn receive_fifo_ready_mask(&mut self) -> RECEIVE_FIFO_READY_MASK_W<10> {
357        RECEIVE_FIFO_READY_MASK_W::new(self)
358    }
359    #[doc = "Bit 11 - Not-acknowledged response interrupt mask"]
360    #[inline(always)]
361    pub fn not_acknowledged_mask(&mut self) -> NOT_ACKNOWLEDGED_MASK_W<11> {
362        NOT_ACKNOWLEDGED_MASK_W::new(self)
363    }
364    #[doc = "Bit 12 - Arbitration lost interrupt mask"]
365    #[inline(always)]
366    pub fn arbitrate_lost_mask(&mut self) -> ARBITRATE_LOST_MASK_W<12> {
367        ARBITRATE_LOST_MASK_W::new(self)
368    }
369    #[doc = "Bit 13 - Transmit or receive FIFO error interrupt mask"]
370    #[inline(always)]
371    pub fn fifo_error_mask(&mut self) -> FIFO_ERROR_MASK_W<13> {
372        FIFO_ERROR_MASK_W::new(self)
373    }
374    #[doc = "Bit 16 - Write 1 to clear transfer ended"]
375    #[inline(always)]
376    pub fn transfer_end_clear(&mut self) -> TRANSFER_END_CLEAR_W<16> {
377        TRANSFER_END_CLEAR_W::new(self)
378    }
379    #[doc = "Bit 19 - Write 1 to clear not-acknowledged response"]
380    #[inline(always)]
381    pub fn not_acknowledged_clear(&mut self) -> NOT_ACKNOWLEDGED_CLEAR_W<19> {
382        NOT_ACKNOWLEDGED_CLEAR_W::new(self)
383    }
384    #[doc = "Bit 20 - Write 1 to clear arbitration lost"]
385    #[inline(always)]
386    pub fn arbitrate_lost_clear(&mut self) -> ARBITRATE_LOST_CLEAR_W<20> {
387        ARBITRATE_LOST_CLEAR_W::new(self)
388    }
389    #[doc = "Bit 24 - Transfer ended interrupt enable"]
390    #[inline(always)]
391    pub fn transfer_end_enable(&mut self) -> TRANSFER_END_ENABLE_W<24> {
392        TRANSFER_END_ENABLE_W::new(self)
393    }
394    #[doc = "Bit 25 - Transmit FIFO ready interrupt enable"]
395    #[inline(always)]
396    pub fn transmit_fifo_ready_enable(&mut self) -> TRANSMIT_FIFO_READY_ENABLE_W<25> {
397        TRANSMIT_FIFO_READY_ENABLE_W::new(self)
398    }
399    #[doc = "Bit 26 - Receive FIFO ready interrupt enable"]
400    #[inline(always)]
401    pub fn receive_fifo_ready_enable(&mut self) -> RECEIVE_FIFO_READY_ENABLE_W<26> {
402        RECEIVE_FIFO_READY_ENABLE_W::new(self)
403    }
404    #[doc = "Bit 27 - Not-acknowledged response interrupt enable"]
405    #[inline(always)]
406    pub fn not_acknowledged_enable(&mut self) -> NOT_ACKNOWLEDGED_ENABLE_W<27> {
407        NOT_ACKNOWLEDGED_ENABLE_W::new(self)
408    }
409    #[doc = "Bit 28 - Arbitration lost interrupt enable"]
410    #[inline(always)]
411    pub fn arbitrate_lost_enable(&mut self) -> ARBITRATE_LOST_ENABLE_W<28> {
412        ARBITRATE_LOST_ENABLE_W::new(self)
413    }
414    #[doc = "Bit 29 - Transmit or receive FIFO error interrupt enable"]
415    #[inline(always)]
416    pub fn fifo_error_enable(&mut self) -> FIFO_ERROR_ENABLE_W<29> {
417        FIFO_ERROR_ENABLE_W::new(self)
418    }
419    #[doc = "Writes raw bits to the register."]
420    #[inline(always)]
421    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
422        self.0.bits(bits);
423        self
424    }
425}
426#[doc = "Interrupt enables, states and masks\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt](index.html) module"]
427pub struct INTERRUPT_SPEC;
428impl crate::RegisterSpec for INTERRUPT_SPEC {
429    type Ux = u32;
430}
431#[doc = "`read()` method returns [interrupt::R](R) reader structure"]
432impl crate::Readable for INTERRUPT_SPEC {
433    type Reader = R;
434}
435#[doc = "`write(|w| ..)` method takes [interrupt::W](W) writer structure"]
436impl crate::Writable for INTERRUPT_SPEC {
437    type Writer = W;
438}
439#[doc = "`reset()` method sets interrupt to value 0x3f00_3f00"]
440impl crate::Resettable for INTERRUPT_SPEC {
441    #[inline(always)]
442    fn reset_value() -> Self::Ux {
443        0x3f00_3f00
444    }
445}
bl808_pac/i2c/interrupt.rs

bl808_pac/i2c/
interrupt.rs
