bl702_pac/i2c/
i2c_fifo_config_0.rs

1#[doc = "Register `i2c_fifo_config_0` reader"]
2pub struct R(crate::R<I2C_FIFO_CONFIG_0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<I2C_FIFO_CONFIG_0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<I2C_FIFO_CONFIG_0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<I2C_FIFO_CONFIG_0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `i2c_fifo_config_0` writer"]
17pub struct W(crate::W<I2C_FIFO_CONFIG_0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<I2C_FIFO_CONFIG_0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<I2C_FIFO_CONFIG_0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<I2C_FIFO_CONFIG_0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `i2c_dma_tx_en` reader - "]
38pub type I2C_DMA_TX_EN_R = crate::BitReader<bool>;
39#[doc = "Field `i2c_dma_tx_en` writer - "]
40pub type I2C_DMA_TX_EN_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, I2C_FIFO_CONFIG_0_SPEC, bool, O>;
42#[doc = "Field `i2c_dma_rx_en` reader - "]
43pub type I2C_DMA_RX_EN_R = crate::BitReader<bool>;
44#[doc = "Field `i2c_dma_rx_en` writer - "]
45pub type I2C_DMA_RX_EN_W<'a, const O: u8> =
46    crate::BitWriter<'a, u32, I2C_FIFO_CONFIG_0_SPEC, bool, O>;
47#[doc = "Field `tx_fifo_clr` reader - "]
48pub type TX_FIFO_CLR_R = crate::BitReader<bool>;
49#[doc = "Field `tx_fifo_clr` writer - "]
50pub type TX_FIFO_CLR_W<'a, const O: u8> =
51    crate::BitWriter<'a, u32, I2C_FIFO_CONFIG_0_SPEC, bool, O>;
52#[doc = "Field `rx_fifo_clr` reader - "]
53pub type RX_FIFO_CLR_R = crate::BitReader<bool>;
54#[doc = "Field `rx_fifo_clr` writer - "]
55pub type RX_FIFO_CLR_W<'a, const O: u8> =
56    crate::BitWriter<'a, u32, I2C_FIFO_CONFIG_0_SPEC, bool, O>;
57#[doc = "Field `tx_fifo_overflow` reader - "]
58pub type TX_FIFO_OVERFLOW_R = crate::BitReader<bool>;
59#[doc = "Field `tx_fifo_overflow` writer - "]
60pub type TX_FIFO_OVERFLOW_W<'a, const O: u8> =
61    crate::BitWriter<'a, u32, I2C_FIFO_CONFIG_0_SPEC, bool, O>;
62#[doc = "Field `tx_fifo_underflow` reader - "]
63pub type TX_FIFO_UNDERFLOW_R = crate::BitReader<bool>;
64#[doc = "Field `tx_fifo_underflow` writer - "]
65pub type TX_FIFO_UNDERFLOW_W<'a, const O: u8> =
66    crate::BitWriter<'a, u32, I2C_FIFO_CONFIG_0_SPEC, bool, O>;
67#[doc = "Field `rx_fifo_overflow` reader - "]
68pub type RX_FIFO_OVERFLOW_R = crate::BitReader<bool>;
69#[doc = "Field `rx_fifo_overflow` writer - "]
70pub type RX_FIFO_OVERFLOW_W<'a, const O: u8> =
71    crate::BitWriter<'a, u32, I2C_FIFO_CONFIG_0_SPEC, bool, O>;
72#[doc = "Field `rx_fifo_underflow` reader - "]
73pub type RX_FIFO_UNDERFLOW_R = crate::BitReader<bool>;
74#[doc = "Field `rx_fifo_underflow` writer - "]
75pub type RX_FIFO_UNDERFLOW_W<'a, const O: u8> =
76    crate::BitWriter<'a, u32, I2C_FIFO_CONFIG_0_SPEC, bool, O>;
77impl R {
78    #[doc = "Bit 0"]
79    #[inline(always)]
80    pub fn i2c_dma_tx_en(&self) -> I2C_DMA_TX_EN_R {
81        I2C_DMA_TX_EN_R::new((self.bits & 1) != 0)
82    }
83    #[doc = "Bit 1"]
84    #[inline(always)]
85    pub fn i2c_dma_rx_en(&self) -> I2C_DMA_RX_EN_R {
86        I2C_DMA_RX_EN_R::new(((self.bits >> 1) & 1) != 0)
87    }
88    #[doc = "Bit 2"]
89    #[inline(always)]
90    pub fn tx_fifo_clr(&self) -> TX_FIFO_CLR_R {
91        TX_FIFO_CLR_R::new(((self.bits >> 2) & 1) != 0)
92    }
93    #[doc = "Bit 3"]
94    #[inline(always)]
95    pub fn rx_fifo_clr(&self) -> RX_FIFO_CLR_R {
96        RX_FIFO_CLR_R::new(((self.bits >> 3) & 1) != 0)
97    }
98    #[doc = "Bit 4"]
99    #[inline(always)]
100    pub fn tx_fifo_overflow(&self) -> TX_FIFO_OVERFLOW_R {
101        TX_FIFO_OVERFLOW_R::new(((self.bits >> 4) & 1) != 0)
102    }
103    #[doc = "Bit 5"]
104    #[inline(always)]
105    pub fn tx_fifo_underflow(&self) -> TX_FIFO_UNDERFLOW_R {
106        TX_FIFO_UNDERFLOW_R::new(((self.bits >> 5) & 1) != 0)
107    }
108    #[doc = "Bit 6"]
109    #[inline(always)]
110    pub fn rx_fifo_overflow(&self) -> RX_FIFO_OVERFLOW_R {
111        RX_FIFO_OVERFLOW_R::new(((self.bits >> 6) & 1) != 0)
112    }
113    #[doc = "Bit 7"]
114    #[inline(always)]
115    pub fn rx_fifo_underflow(&self) -> RX_FIFO_UNDERFLOW_R {
116        RX_FIFO_UNDERFLOW_R::new(((self.bits >> 7) & 1) != 0)
117    }
118}
119impl W {
120    #[doc = "Bit 0"]
121    #[inline(always)]
122    #[must_use]
123    pub fn i2c_dma_tx_en(&mut self) -> I2C_DMA_TX_EN_W<0> {
124        I2C_DMA_TX_EN_W::new(self)
125    }
126    #[doc = "Bit 1"]
127    #[inline(always)]
128    #[must_use]
129    pub fn i2c_dma_rx_en(&mut self) -> I2C_DMA_RX_EN_W<1> {
130        I2C_DMA_RX_EN_W::new(self)
131    }
132    #[doc = "Bit 2"]
133    #[inline(always)]
134    #[must_use]
135    pub fn tx_fifo_clr(&mut self) -> TX_FIFO_CLR_W<2> {
136        TX_FIFO_CLR_W::new(self)
137    }
138    #[doc = "Bit 3"]
139    #[inline(always)]
140    #[must_use]
141    pub fn rx_fifo_clr(&mut self) -> RX_FIFO_CLR_W<3> {
142        RX_FIFO_CLR_W::new(self)
143    }
144    #[doc = "Bit 4"]
145    #[inline(always)]
146    #[must_use]
147    pub fn tx_fifo_overflow(&mut self) -> TX_FIFO_OVERFLOW_W<4> {
148        TX_FIFO_OVERFLOW_W::new(self)
149    }
150    #[doc = "Bit 5"]
151    #[inline(always)]
152    #[must_use]
153    pub fn tx_fifo_underflow(&mut self) -> TX_FIFO_UNDERFLOW_W<5> {
154        TX_FIFO_UNDERFLOW_W::new(self)
155    }
156    #[doc = "Bit 6"]
157    #[inline(always)]
158    #[must_use]
159    pub fn rx_fifo_overflow(&mut self) -> RX_FIFO_OVERFLOW_W<6> {
160        RX_FIFO_OVERFLOW_W::new(self)
161    }
162    #[doc = "Bit 7"]
163    #[inline(always)]
164    #[must_use]
165    pub fn rx_fifo_underflow(&mut self) -> RX_FIFO_UNDERFLOW_W<7> {
166        RX_FIFO_UNDERFLOW_W::new(self)
167    }
168    #[doc = "Writes raw bits to the register."]
169    #[inline(always)]
170    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
171        self.0.bits(bits);
172        self
173    }
174}
175#[doc = "i2c_fifo_config_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2c_fifo_config_0](index.html) module"]
176pub struct I2C_FIFO_CONFIG_0_SPEC;
177impl crate::RegisterSpec for I2C_FIFO_CONFIG_0_SPEC {
178    type Ux = u32;
179}
180#[doc = "`read()` method returns [i2c_fifo_config_0::R](R) reader structure"]
181impl crate::Readable for I2C_FIFO_CONFIG_0_SPEC {
182    type Reader = R;
183}
184#[doc = "`write(|w| ..)` method takes [i2c_fifo_config_0::W](W) writer structure"]
185impl crate::Writable for I2C_FIFO_CONFIG_0_SPEC {
186    type Writer = W;
187    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
188    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
189}
190#[doc = "`reset()` method sets i2c_fifo_config_0 to value 0"]
191impl crate::Resettable for I2C_FIFO_CONFIG_0_SPEC {
192    const RESET_VALUE: Self::Ux = 0;
193}
bl702_pac/i2c/i2c_fifo_config_0.rs

bl702_pac/i2c/
i2c_fifo_config_0.rs
