bl702_pac/glb/
clk_cfg1.rs1#[doc = "Register `clk_cfg1` reader"]
2pub struct R(crate::R<CLK_CFG1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CLK_CFG1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CLK_CFG1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CLK_CFG1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `clk_cfg1` writer"]
17pub struct W(crate::W<CLK_CFG1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CLK_CFG1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CLK_CFG1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CLK_CFG1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `qdec_clk_div` reader - "]
38pub type QDEC_CLK_DIV_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `qdec_clk_div` writer - "]
40pub type QDEC_CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG1_SPEC, u8, u8, 5, O>;
41#[doc = "Field `qdec_clk_sel` reader - "]
42pub type QDEC_CLK_SEL_R = crate::BitReader<bool>;
43#[doc = "Field `qdec_clk_sel` writer - "]
44pub type QDEC_CLK_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
45#[doc = "Field `usb_clk_en` reader - "]
46pub type USB_CLK_EN_R = crate::BitReader<bool>;
47#[doc = "Field `usb_clk_en` writer - "]
48pub type USB_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
49#[doc = "Field `dll_48m_div_en` reader - "]
50pub type DLL_48M_DIV_EN_R = crate::BitReader<bool>;
51#[doc = "Field `dll_48m_div_en` writer - "]
52pub type DLL_48M_DIV_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
53#[doc = "Field `reg_i2s_clk_sel` reader - "]
54pub type REG_I2S_CLK_SEL_R = crate::BitReader<bool>;
55#[doc = "Field `reg_i2s_clk_sel` writer - "]
56pub type REG_I2S_CLK_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
57#[doc = "Field `reg_i2s0_clk_en` reader - "]
58pub type REG_I2S0_CLK_EN_R = crate::BitReader<bool>;
59#[doc = "Field `reg_i2s0_clk_en` writer - "]
60pub type REG_I2S0_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
61#[doc = "Field `reg_i2s_0_ref_clk_oe` reader - "]
62pub type REG_I2S_0_REF_CLK_OE_R = crate::BitReader<bool>;
63#[doc = "Field `reg_i2s_0_ref_clk_oe` writer - "]
64pub type REG_I2S_0_REF_CLK_OE_W<'a, const O: u8> =
65 crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
66#[doc = "Field `ble_clk_sel` reader - "]
67pub type BLE_CLK_SEL_R = crate::FieldReader<u8, u8>;
68#[doc = "Field `ble_clk_sel` writer - "]
69pub type BLE_CLK_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG1_SPEC, u8, u8, 6, O>;
70#[doc = "Field `ble_en` reader - "]
71pub type BLE_EN_R = crate::BitReader<bool>;
72#[doc = "Field `ble_en` writer - "]
73pub type BLE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
74#[doc = "Field `m154_zbEn` reader - "]
75pub type M154_ZB_EN_R = crate::BitReader<bool>;
76#[doc = "Field `m154_zbEn` writer - "]
77pub type M154_ZB_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
78#[doc = "Field `reg_cam_ref_clk_en` reader - "]
79pub type REG_CAM_REF_CLK_EN_R = crate::BitReader<bool>;
80#[doc = "Field `reg_cam_ref_clk_en` writer - "]
81pub type REG_CAM_REF_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
82#[doc = "Field `reg_cam_ref_clk_src_sel` reader - "]
83pub type REG_CAM_REF_CLK_SRC_SEL_R = crate::BitReader<bool>;
84#[doc = "Field `reg_cam_ref_clk_src_sel` writer - "]
85pub type REG_CAM_REF_CLK_SRC_SEL_W<'a, const O: u8> =
86 crate::BitWriter<'a, u32, CLK_CFG1_SPEC, bool, O>;
87#[doc = "Field `reg_cam_ref_clk_div` reader - "]
88pub type REG_CAM_REF_CLK_DIV_R = crate::FieldReader<u8, u8>;
89#[doc = "Field `reg_cam_ref_clk_div` writer - "]
90pub type REG_CAM_REF_CLK_DIV_W<'a, const O: u8> =
91 crate::FieldWriter<'a, u32, CLK_CFG1_SPEC, u8, u8, 2, O>;
92impl R {
93 #[doc = "Bits 0:4"]
94 #[inline(always)]
95 pub fn qdec_clk_div(&self) -> QDEC_CLK_DIV_R {
96 QDEC_CLK_DIV_R::new((self.bits & 0x1f) as u8)
97 }
98 #[doc = "Bit 7"]
99 #[inline(always)]
100 pub fn qdec_clk_sel(&self) -> QDEC_CLK_SEL_R {
101 QDEC_CLK_SEL_R::new(((self.bits >> 7) & 1) != 0)
102 }
103 #[doc = "Bit 8"]
104 #[inline(always)]
105 pub fn usb_clk_en(&self) -> USB_CLK_EN_R {
106 USB_CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
107 }
108 #[doc = "Bit 9"]
109 #[inline(always)]
110 pub fn dll_48m_div_en(&self) -> DLL_48M_DIV_EN_R {
111 DLL_48M_DIV_EN_R::new(((self.bits >> 9) & 1) != 0)
112 }
113 #[doc = "Bit 12"]
114 #[inline(always)]
115 pub fn reg_i2s_clk_sel(&self) -> REG_I2S_CLK_SEL_R {
116 REG_I2S_CLK_SEL_R::new(((self.bits >> 12) & 1) != 0)
117 }
118 #[doc = "Bit 13"]
119 #[inline(always)]
120 pub fn reg_i2s0_clk_en(&self) -> REG_I2S0_CLK_EN_R {
121 REG_I2S0_CLK_EN_R::new(((self.bits >> 13) & 1) != 0)
122 }
123 #[doc = "Bit 14"]
124 #[inline(always)]
125 pub fn reg_i2s_0_ref_clk_oe(&self) -> REG_I2S_0_REF_CLK_OE_R {
126 REG_I2S_0_REF_CLK_OE_R::new(((self.bits >> 14) & 1) != 0)
127 }
128 #[doc = "Bits 16:21"]
129 #[inline(always)]
130 pub fn ble_clk_sel(&self) -> BLE_CLK_SEL_R {
131 BLE_CLK_SEL_R::new(((self.bits >> 16) & 0x3f) as u8)
132 }
133 #[doc = "Bit 24"]
134 #[inline(always)]
135 pub fn ble_en(&self) -> BLE_EN_R {
136 BLE_EN_R::new(((self.bits >> 24) & 1) != 0)
137 }
138 #[doc = "Bit 25"]
139 #[inline(always)]
140 pub fn m154_zb_en(&self) -> M154_ZB_EN_R {
141 M154_ZB_EN_R::new(((self.bits >> 25) & 1) != 0)
142 }
143 #[doc = "Bit 28"]
144 #[inline(always)]
145 pub fn reg_cam_ref_clk_en(&self) -> REG_CAM_REF_CLK_EN_R {
146 REG_CAM_REF_CLK_EN_R::new(((self.bits >> 28) & 1) != 0)
147 }
148 #[doc = "Bit 29"]
149 #[inline(always)]
150 pub fn reg_cam_ref_clk_src_sel(&self) -> REG_CAM_REF_CLK_SRC_SEL_R {
151 REG_CAM_REF_CLK_SRC_SEL_R::new(((self.bits >> 29) & 1) != 0)
152 }
153 #[doc = "Bits 30:31"]
154 #[inline(always)]
155 pub fn reg_cam_ref_clk_div(&self) -> REG_CAM_REF_CLK_DIV_R {
156 REG_CAM_REF_CLK_DIV_R::new(((self.bits >> 30) & 3) as u8)
157 }
158}
159impl W {
160 #[doc = "Bits 0:4"]
161 #[inline(always)]
162 #[must_use]
163 pub fn qdec_clk_div(&mut self) -> QDEC_CLK_DIV_W<0> {
164 QDEC_CLK_DIV_W::new(self)
165 }
166 #[doc = "Bit 7"]
167 #[inline(always)]
168 #[must_use]
169 pub fn qdec_clk_sel(&mut self) -> QDEC_CLK_SEL_W<7> {
170 QDEC_CLK_SEL_W::new(self)
171 }
172 #[doc = "Bit 8"]
173 #[inline(always)]
174 #[must_use]
175 pub fn usb_clk_en(&mut self) -> USB_CLK_EN_W<8> {
176 USB_CLK_EN_W::new(self)
177 }
178 #[doc = "Bit 9"]
179 #[inline(always)]
180 #[must_use]
181 pub fn dll_48m_div_en(&mut self) -> DLL_48M_DIV_EN_W<9> {
182 DLL_48M_DIV_EN_W::new(self)
183 }
184 #[doc = "Bit 12"]
185 #[inline(always)]
186 #[must_use]
187 pub fn reg_i2s_clk_sel(&mut self) -> REG_I2S_CLK_SEL_W<12> {
188 REG_I2S_CLK_SEL_W::new(self)
189 }
190 #[doc = "Bit 13"]
191 #[inline(always)]
192 #[must_use]
193 pub fn reg_i2s0_clk_en(&mut self) -> REG_I2S0_CLK_EN_W<13> {
194 REG_I2S0_CLK_EN_W::new(self)
195 }
196 #[doc = "Bit 14"]
197 #[inline(always)]
198 #[must_use]
199 pub fn reg_i2s_0_ref_clk_oe(&mut self) -> REG_I2S_0_REF_CLK_OE_W<14> {
200 REG_I2S_0_REF_CLK_OE_W::new(self)
201 }
202 #[doc = "Bits 16:21"]
203 #[inline(always)]
204 #[must_use]
205 pub fn ble_clk_sel(&mut self) -> BLE_CLK_SEL_W<16> {
206 BLE_CLK_SEL_W::new(self)
207 }
208 #[doc = "Bit 24"]
209 #[inline(always)]
210 #[must_use]
211 pub fn ble_en(&mut self) -> BLE_EN_W<24> {
212 BLE_EN_W::new(self)
213 }
214 #[doc = "Bit 25"]
215 #[inline(always)]
216 #[must_use]
217 pub fn m154_zb_en(&mut self) -> M154_ZB_EN_W<25> {
218 M154_ZB_EN_W::new(self)
219 }
220 #[doc = "Bit 28"]
221 #[inline(always)]
222 #[must_use]
223 pub fn reg_cam_ref_clk_en(&mut self) -> REG_CAM_REF_CLK_EN_W<28> {
224 REG_CAM_REF_CLK_EN_W::new(self)
225 }
226 #[doc = "Bit 29"]
227 #[inline(always)]
228 #[must_use]
229 pub fn reg_cam_ref_clk_src_sel(&mut self) -> REG_CAM_REF_CLK_SRC_SEL_W<29> {
230 REG_CAM_REF_CLK_SRC_SEL_W::new(self)
231 }
232 #[doc = "Bits 30:31"]
233 #[inline(always)]
234 #[must_use]
235 pub fn reg_cam_ref_clk_div(&mut self) -> REG_CAM_REF_CLK_DIV_W<30> {
236 REG_CAM_REF_CLK_DIV_W::new(self)
237 }
238 #[doc = "Writes raw bits to the register."]
239 #[inline(always)]
240 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
241 self.0.bits(bits);
242 self
243 }
244}
245#[doc = "clk_cfg1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_cfg1](index.html) module"]
246pub struct CLK_CFG1_SPEC;
247impl crate::RegisterSpec for CLK_CFG1_SPEC {
248 type Ux = u32;
249}
250#[doc = "`read()` method returns [clk_cfg1::R](R) reader structure"]
251impl crate::Readable for CLK_CFG1_SPEC {
252 type Reader = R;
253}
254#[doc = "`write(|w| ..)` method takes [clk_cfg1::W](W) writer structure"]
255impl crate::Writable for CLK_CFG1_SPEC {
256 type Writer = W;
257 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
258 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
259}
260#[doc = "`reset()` method sets clk_cfg1 to value 0"]
261impl crate::Resettable for CLK_CFG1_SPEC {
262 const RESET_VALUE: Self::Ux = 0;
263}