bl702_pac/cam/
dvp_frame_fifo_pop.rs

1#[doc = "Register `dvp_frame_fifo_pop` reader"]
2pub struct R(crate::R<DVP_FRAME_FIFO_POP_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DVP_FRAME_FIFO_POP_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DVP_FRAME_FIFO_POP_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DVP_FRAME_FIFO_POP_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `dvp_frame_fifo_pop` writer"]
17pub struct W(crate::W<DVP_FRAME_FIFO_POP_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DVP_FRAME_FIFO_POP_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DVP_FRAME_FIFO_POP_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DVP_FRAME_FIFO_POP_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `rfifo_pop_0` reader - "]
38pub type RFIFO_POP_0_R = crate::BitReader<bool>;
39#[doc = "Field `rfifo_pop_0` writer - "]
40pub type RFIFO_POP_0_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
42#[doc = "Field `rfifo_pop_1` reader - "]
43pub type RFIFO_POP_1_R = crate::BitReader<bool>;
44#[doc = "Field `rfifo_pop_1` writer - "]
45pub type RFIFO_POP_1_W<'a, const O: u8> =
46    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
47#[doc = "Field `reg_int_normal_clr_0` reader - "]
48pub type REG_INT_NORMAL_CLR_0_R = crate::BitReader<bool>;
49#[doc = "Field `reg_int_normal_clr_0` writer - "]
50pub type REG_INT_NORMAL_CLR_0_W<'a, const O: u8> =
51    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
52#[doc = "Field `reg_int_mem_clr_0` reader - "]
53pub type REG_INT_MEM_CLR_0_R = crate::BitReader<bool>;
54#[doc = "Field `reg_int_mem_clr_0` writer - "]
55pub type REG_INT_MEM_CLR_0_W<'a, const O: u8> =
56    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
57#[doc = "Field `reg_int_frame_clr_0` reader - "]
58pub type REG_INT_FRAME_CLR_0_R = crate::BitReader<bool>;
59#[doc = "Field `reg_int_frame_clr_0` writer - "]
60pub type REG_INT_FRAME_CLR_0_W<'a, const O: u8> =
61    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
62#[doc = "Field `reg_int_fifo_clr_0` reader - "]
63pub type REG_INT_FIFO_CLR_0_R = crate::BitReader<bool>;
64#[doc = "Field `reg_int_fifo_clr_0` writer - "]
65pub type REG_INT_FIFO_CLR_0_W<'a, const O: u8> =
66    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
67#[doc = "Field `reg_int_hcnt_clr_0` reader - "]
68pub type REG_INT_HCNT_CLR_0_R = crate::BitReader<bool>;
69#[doc = "Field `reg_int_hcnt_clr_0` writer - "]
70pub type REG_INT_HCNT_CLR_0_W<'a, const O: u8> =
71    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
72#[doc = "Field `reg_int_vcnt_clr_0` reader - "]
73pub type REG_INT_VCNT_CLR_0_R = crate::BitReader<bool>;
74#[doc = "Field `reg_int_vcnt_clr_0` writer - "]
75pub type REG_INT_VCNT_CLR_0_W<'a, const O: u8> =
76    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
77#[doc = "Field `reg_int_normal_clr_1` reader - "]
78pub type REG_INT_NORMAL_CLR_1_R = crate::BitReader<bool>;
79#[doc = "Field `reg_int_normal_clr_1` writer - "]
80pub type REG_INT_NORMAL_CLR_1_W<'a, const O: u8> =
81    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
82#[doc = "Field `reg_int_mem_clr_1` reader - "]
83pub type REG_INT_MEM_CLR_1_R = crate::BitReader<bool>;
84#[doc = "Field `reg_int_mem_clr_1` writer - "]
85pub type REG_INT_MEM_CLR_1_W<'a, const O: u8> =
86    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
87#[doc = "Field `reg_int_frame_clr_1` reader - "]
88pub type REG_INT_FRAME_CLR_1_R = crate::BitReader<bool>;
89#[doc = "Field `reg_int_frame_clr_1` writer - "]
90pub type REG_INT_FRAME_CLR_1_W<'a, const O: u8> =
91    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
92#[doc = "Field `reg_int_fifo_clr_1` reader - "]
93pub type REG_INT_FIFO_CLR_1_R = crate::BitReader<bool>;
94#[doc = "Field `reg_int_fifo_clr_1` writer - "]
95pub type REG_INT_FIFO_CLR_1_W<'a, const O: u8> =
96    crate::BitWriter<'a, u32, DVP_FRAME_FIFO_POP_SPEC, bool, O>;
97impl R {
98    #[doc = "Bit 0"]
99    #[inline(always)]
100    pub fn rfifo_pop_0(&self) -> RFIFO_POP_0_R {
101        RFIFO_POP_0_R::new((self.bits & 1) != 0)
102    }
103    #[doc = "Bit 1"]
104    #[inline(always)]
105    pub fn rfifo_pop_1(&self) -> RFIFO_POP_1_R {
106        RFIFO_POP_1_R::new(((self.bits >> 1) & 1) != 0)
107    }
108    #[doc = "Bit 4"]
109    #[inline(always)]
110    pub fn reg_int_normal_clr_0(&self) -> REG_INT_NORMAL_CLR_0_R {
111        REG_INT_NORMAL_CLR_0_R::new(((self.bits >> 4) & 1) != 0)
112    }
113    #[doc = "Bit 5"]
114    #[inline(always)]
115    pub fn reg_int_mem_clr_0(&self) -> REG_INT_MEM_CLR_0_R {
116        REG_INT_MEM_CLR_0_R::new(((self.bits >> 5) & 1) != 0)
117    }
118    #[doc = "Bit 6"]
119    #[inline(always)]
120    pub fn reg_int_frame_clr_0(&self) -> REG_INT_FRAME_CLR_0_R {
121        REG_INT_FRAME_CLR_0_R::new(((self.bits >> 6) & 1) != 0)
122    }
123    #[doc = "Bit 7"]
124    #[inline(always)]
125    pub fn reg_int_fifo_clr_0(&self) -> REG_INT_FIFO_CLR_0_R {
126        REG_INT_FIFO_CLR_0_R::new(((self.bits >> 7) & 1) != 0)
127    }
128    #[doc = "Bit 8"]
129    #[inline(always)]
130    pub fn reg_int_hcnt_clr_0(&self) -> REG_INT_HCNT_CLR_0_R {
131        REG_INT_HCNT_CLR_0_R::new(((self.bits >> 8) & 1) != 0)
132    }
133    #[doc = "Bit 9"]
134    #[inline(always)]
135    pub fn reg_int_vcnt_clr_0(&self) -> REG_INT_VCNT_CLR_0_R {
136        REG_INT_VCNT_CLR_0_R::new(((self.bits >> 9) & 1) != 0)
137    }
138    #[doc = "Bit 16"]
139    #[inline(always)]
140    pub fn reg_int_normal_clr_1(&self) -> REG_INT_NORMAL_CLR_1_R {
141        REG_INT_NORMAL_CLR_1_R::new(((self.bits >> 16) & 1) != 0)
142    }
143    #[doc = "Bit 17"]
144    #[inline(always)]
145    pub fn reg_int_mem_clr_1(&self) -> REG_INT_MEM_CLR_1_R {
146        REG_INT_MEM_CLR_1_R::new(((self.bits >> 17) & 1) != 0)
147    }
148    #[doc = "Bit 18"]
149    #[inline(always)]
150    pub fn reg_int_frame_clr_1(&self) -> REG_INT_FRAME_CLR_1_R {
151        REG_INT_FRAME_CLR_1_R::new(((self.bits >> 18) & 1) != 0)
152    }
153    #[doc = "Bit 19"]
154    #[inline(always)]
155    pub fn reg_int_fifo_clr_1(&self) -> REG_INT_FIFO_CLR_1_R {
156        REG_INT_FIFO_CLR_1_R::new(((self.bits >> 19) & 1) != 0)
157    }
158}
159impl W {
160    #[doc = "Bit 0"]
161    #[inline(always)]
162    #[must_use]
163    pub fn rfifo_pop_0(&mut self) -> RFIFO_POP_0_W<0> {
164        RFIFO_POP_0_W::new(self)
165    }
166    #[doc = "Bit 1"]
167    #[inline(always)]
168    #[must_use]
169    pub fn rfifo_pop_1(&mut self) -> RFIFO_POP_1_W<1> {
170        RFIFO_POP_1_W::new(self)
171    }
172    #[doc = "Bit 4"]
173    #[inline(always)]
174    #[must_use]
175    pub fn reg_int_normal_clr_0(&mut self) -> REG_INT_NORMAL_CLR_0_W<4> {
176        REG_INT_NORMAL_CLR_0_W::new(self)
177    }
178    #[doc = "Bit 5"]
179    #[inline(always)]
180    #[must_use]
181    pub fn reg_int_mem_clr_0(&mut self) -> REG_INT_MEM_CLR_0_W<5> {
182        REG_INT_MEM_CLR_0_W::new(self)
183    }
184    #[doc = "Bit 6"]
185    #[inline(always)]
186    #[must_use]
187    pub fn reg_int_frame_clr_0(&mut self) -> REG_INT_FRAME_CLR_0_W<6> {
188        REG_INT_FRAME_CLR_0_W::new(self)
189    }
190    #[doc = "Bit 7"]
191    #[inline(always)]
192    #[must_use]
193    pub fn reg_int_fifo_clr_0(&mut self) -> REG_INT_FIFO_CLR_0_W<7> {
194        REG_INT_FIFO_CLR_0_W::new(self)
195    }
196    #[doc = "Bit 8"]
197    #[inline(always)]
198    #[must_use]
199    pub fn reg_int_hcnt_clr_0(&mut self) -> REG_INT_HCNT_CLR_0_W<8> {
200        REG_INT_HCNT_CLR_0_W::new(self)
201    }
202    #[doc = "Bit 9"]
203    #[inline(always)]
204    #[must_use]
205    pub fn reg_int_vcnt_clr_0(&mut self) -> REG_INT_VCNT_CLR_0_W<9> {
206        REG_INT_VCNT_CLR_0_W::new(self)
207    }
208    #[doc = "Bit 16"]
209    #[inline(always)]
210    #[must_use]
211    pub fn reg_int_normal_clr_1(&mut self) -> REG_INT_NORMAL_CLR_1_W<16> {
212        REG_INT_NORMAL_CLR_1_W::new(self)
213    }
214    #[doc = "Bit 17"]
215    #[inline(always)]
216    #[must_use]
217    pub fn reg_int_mem_clr_1(&mut self) -> REG_INT_MEM_CLR_1_W<17> {
218        REG_INT_MEM_CLR_1_W::new(self)
219    }
220    #[doc = "Bit 18"]
221    #[inline(always)]
222    #[must_use]
223    pub fn reg_int_frame_clr_1(&mut self) -> REG_INT_FRAME_CLR_1_W<18> {
224        REG_INT_FRAME_CLR_1_W::new(self)
225    }
226    #[doc = "Bit 19"]
227    #[inline(always)]
228    #[must_use]
229    pub fn reg_int_fifo_clr_1(&mut self) -> REG_INT_FIFO_CLR_1_W<19> {
230        REG_INT_FIFO_CLR_1_W::new(self)
231    }
232    #[doc = "Writes raw bits to the register."]
233    #[inline(always)]
234    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
235        self.0.bits(bits);
236        self
237    }
238}
239#[doc = "dvp_frame_fifo_pop.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvp_frame_fifo_pop](index.html) module"]
240pub struct DVP_FRAME_FIFO_POP_SPEC;
241impl crate::RegisterSpec for DVP_FRAME_FIFO_POP_SPEC {
242    type Ux = u32;
243}
244#[doc = "`read()` method returns [dvp_frame_fifo_pop::R](R) reader structure"]
245impl crate::Readable for DVP_FRAME_FIFO_POP_SPEC {
246    type Reader = R;
247}
248#[doc = "`write(|w| ..)` method takes [dvp_frame_fifo_pop::W](W) writer structure"]
249impl crate::Writable for DVP_FRAME_FIFO_POP_SPEC {
250    type Writer = W;
251    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
252    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
253}
254#[doc = "`reset()` method sets dvp_frame_fifo_pop to value 0"]
255impl crate::Resettable for DVP_FRAME_FIFO_POP_SPEC {
256    const RESET_VALUE: Self::Ux = 0;
257}
bl702_pac/cam/dvp_frame_fifo_pop.rs

bl702_pac/cam/
dvp_frame_fifo_pop.rs
