bl702-pac 0.0.3

Embedded Rust's Peripheral Access Crate for BL702/BL704/BL706 RISC-V BLE + Zigbee microcontroller
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193

#[doc = "Register `uart_fifo_config_0` reader"]
pub struct R(crate::R<UART_FIFO_CONFIG_0_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<UART_FIFO_CONFIG_0_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<UART_FIFO_CONFIG_0_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<UART_FIFO_CONFIG_0_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `uart_fifo_config_0` writer"]
pub struct W(crate::W<UART_FIFO_CONFIG_0_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<UART_FIFO_CONFIG_0_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<UART_FIFO_CONFIG_0_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<UART_FIFO_CONFIG_0_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `uart_dma_tx_en` reader - "]
pub type UART_DMA_TX_EN_R = crate::BitReader<bool>;
#[doc = "Field `uart_dma_tx_en` writer - "]
pub type UART_DMA_TX_EN_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
#[doc = "Field `uart_dma_rx_en` reader - "]
pub type UART_DMA_RX_EN_R = crate::BitReader<bool>;
#[doc = "Field `uart_dma_rx_en` writer - "]
pub type UART_DMA_RX_EN_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
#[doc = "Field `tx_fifo_clr` reader - "]
pub type TX_FIFO_CLR_R = crate::BitReader<bool>;
#[doc = "Field `tx_fifo_clr` writer - "]
pub type TX_FIFO_CLR_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
#[doc = "Field `rx_fifo_clr` reader - "]
pub type RX_FIFO_CLR_R = crate::BitReader<bool>;
#[doc = "Field `rx_fifo_clr` writer - "]
pub type RX_FIFO_CLR_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
#[doc = "Field `tx_fifo_overflow` reader - "]
pub type TX_FIFO_OVERFLOW_R = crate::BitReader<bool>;
#[doc = "Field `tx_fifo_overflow` writer - "]
pub type TX_FIFO_OVERFLOW_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
#[doc = "Field `tx_fifo_underflow` reader - "]
pub type TX_FIFO_UNDERFLOW_R = crate::BitReader<bool>;
#[doc = "Field `tx_fifo_underflow` writer - "]
pub type TX_FIFO_UNDERFLOW_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
#[doc = "Field `rx_fifo_overflow` reader - "]
pub type RX_FIFO_OVERFLOW_R = crate::BitReader<bool>;
#[doc = "Field `rx_fifo_overflow` writer - "]
pub type RX_FIFO_OVERFLOW_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
#[doc = "Field `rx_fifo_underflow` reader - "]
pub type RX_FIFO_UNDERFLOW_R = crate::BitReader<bool>;
#[doc = "Field `rx_fifo_underflow` writer - "]
pub type RX_FIFO_UNDERFLOW_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
impl R {
    #[doc = "Bit 0"]
    #[inline(always)]
    pub fn uart_dma_tx_en(&self) -> UART_DMA_TX_EN_R {
        UART_DMA_TX_EN_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1"]
    #[inline(always)]
    pub fn uart_dma_rx_en(&self) -> UART_DMA_RX_EN_R {
        UART_DMA_RX_EN_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    pub fn tx_fifo_clr(&self) -> TX_FIFO_CLR_R {
        TX_FIFO_CLR_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3"]
    #[inline(always)]
    pub fn rx_fifo_clr(&self) -> RX_FIFO_CLR_R {
        RX_FIFO_CLR_R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4"]
    #[inline(always)]
    pub fn tx_fifo_overflow(&self) -> TX_FIFO_OVERFLOW_R {
        TX_FIFO_OVERFLOW_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5"]
    #[inline(always)]
    pub fn tx_fifo_underflow(&self) -> TX_FIFO_UNDERFLOW_R {
        TX_FIFO_UNDERFLOW_R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6"]
    #[inline(always)]
    pub fn rx_fifo_overflow(&self) -> RX_FIFO_OVERFLOW_R {
        RX_FIFO_OVERFLOW_R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7"]
    #[inline(always)]
    pub fn rx_fifo_underflow(&self) -> RX_FIFO_UNDERFLOW_R {
        RX_FIFO_UNDERFLOW_R::new(((self.bits >> 7) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0"]
    #[inline(always)]
    #[must_use]
    pub fn uart_dma_tx_en(&mut self) -> UART_DMA_TX_EN_W<0> {
        UART_DMA_TX_EN_W::new(self)
    }
    #[doc = "Bit 1"]
    #[inline(always)]
    #[must_use]
    pub fn uart_dma_rx_en(&mut self) -> UART_DMA_RX_EN_W<1> {
        UART_DMA_RX_EN_W::new(self)
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    #[must_use]
    pub fn tx_fifo_clr(&mut self) -> TX_FIFO_CLR_W<2> {
        TX_FIFO_CLR_W::new(self)
    }
    #[doc = "Bit 3"]
    #[inline(always)]
    #[must_use]
    pub fn rx_fifo_clr(&mut self) -> RX_FIFO_CLR_W<3> {
        RX_FIFO_CLR_W::new(self)
    }
    #[doc = "Bit 4"]
    #[inline(always)]
    #[must_use]
    pub fn tx_fifo_overflow(&mut self) -> TX_FIFO_OVERFLOW_W<4> {
        TX_FIFO_OVERFLOW_W::new(self)
    }
    #[doc = "Bit 5"]
    #[inline(always)]
    #[must_use]
    pub fn tx_fifo_underflow(&mut self) -> TX_FIFO_UNDERFLOW_W<5> {
        TX_FIFO_UNDERFLOW_W::new(self)
    }
    #[doc = "Bit 6"]
    #[inline(always)]
    #[must_use]
    pub fn rx_fifo_overflow(&mut self) -> RX_FIFO_OVERFLOW_W<6> {
        RX_FIFO_OVERFLOW_W::new(self)
    }
    #[doc = "Bit 7"]
    #[inline(always)]
    #[must_use]
    pub fn rx_fifo_underflow(&mut self) -> RX_FIFO_UNDERFLOW_W<7> {
        RX_FIFO_UNDERFLOW_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "uart_fifo_config_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_fifo_config_0](index.html) module"]
pub struct UART_FIFO_CONFIG_0_SPEC;
impl crate::RegisterSpec for UART_FIFO_CONFIG_0_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [uart_fifo_config_0::R](R) reader structure"]
impl crate::Readable for UART_FIFO_CONFIG_0_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [uart_fifo_config_0::W](W) writer structure"]
impl crate::Writable for UART_FIFO_CONFIG_0_SPEC {
    type Writer = W;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets uart_fifo_config_0 to value 0"]
impl crate::Resettable for UART_FIFO_CONFIG_0_SPEC {
    const RESET_VALUE: Self::Ux = 0;
}