bl702-pac 0.0.3

Embedded Rust's Peripheral Access Crate for BL702/BL704/BL706 RISC-V BLE + Zigbee microcontroller
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

#[doc = "Register `swrst_cfg2` reader"]
pub struct R(crate::R<SWRST_CFG2_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<SWRST_CFG2_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<SWRST_CFG2_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<SWRST_CFG2_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `swrst_cfg2` writer"]
pub struct W(crate::W<SWRST_CFG2_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<SWRST_CFG2_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<SWRST_CFG2_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<SWRST_CFG2_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `reg_ctrl_pwron_rst` reader - "]
pub type REG_CTRL_PWRON_RST_R = crate::BitReader<bool>;
#[doc = "Field `reg_ctrl_pwron_rst` writer - "]
pub type REG_CTRL_PWRON_RST_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, SWRST_CFG2_SPEC, bool, O>;
#[doc = "Field `reg_ctrl_cpu_reset` reader - "]
pub type REG_CTRL_CPU_RESET_R = crate::BitReader<bool>;
#[doc = "Field `reg_ctrl_cpu_reset` writer - "]
pub type REG_CTRL_CPU_RESET_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, SWRST_CFG2_SPEC, bool, O>;
#[doc = "Field `reg_ctrl_sys_reset` reader - "]
pub type REG_CTRL_SYS_RESET_R = crate::BitReader<bool>;
#[doc = "Field `reg_ctrl_sys_reset` writer - "]
pub type REG_CTRL_SYS_RESET_W<'a, const O: u8> =
    crate::BitWriter<'a, u32, SWRST_CFG2_SPEC, bool, O>;
#[doc = "Field `reg_ctrl_reset_dummy` reader - "]
pub type REG_CTRL_RESET_DUMMY_R = crate::FieldReader<u8, u8>;
#[doc = "Field `reg_ctrl_reset_dummy` writer - "]
pub type REG_CTRL_RESET_DUMMY_W<'a, const O: u8> =
    crate::FieldWriter<'a, u32, SWRST_CFG2_SPEC, u8, u8, 4, O>;
#[doc = "Field `pka_clk_sel` reader - "]
pub type PKA_CLK_SEL_R = crate::BitReader<bool>;
#[doc = "Field `pka_clk_sel` writer - "]
pub type PKA_CLK_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWRST_CFG2_SPEC, bool, O>;
impl R {
    #[doc = "Bit 0"]
    #[inline(always)]
    pub fn reg_ctrl_pwron_rst(&self) -> REG_CTRL_PWRON_RST_R {
        REG_CTRL_PWRON_RST_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1"]
    #[inline(always)]
    pub fn reg_ctrl_cpu_reset(&self) -> REG_CTRL_CPU_RESET_R {
        REG_CTRL_CPU_RESET_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    pub fn reg_ctrl_sys_reset(&self) -> REG_CTRL_SYS_RESET_R {
        REG_CTRL_SYS_RESET_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bits 4:7"]
    #[inline(always)]
    pub fn reg_ctrl_reset_dummy(&self) -> REG_CTRL_RESET_DUMMY_R {
        REG_CTRL_RESET_DUMMY_R::new(((self.bits >> 4) & 0x0f) as u8)
    }
    #[doc = "Bit 24"]
    #[inline(always)]
    pub fn pka_clk_sel(&self) -> PKA_CLK_SEL_R {
        PKA_CLK_SEL_R::new(((self.bits >> 24) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0"]
    #[inline(always)]
    #[must_use]
    pub fn reg_ctrl_pwron_rst(&mut self) -> REG_CTRL_PWRON_RST_W<0> {
        REG_CTRL_PWRON_RST_W::new(self)
    }
    #[doc = "Bit 1"]
    #[inline(always)]
    #[must_use]
    pub fn reg_ctrl_cpu_reset(&mut self) -> REG_CTRL_CPU_RESET_W<1> {
        REG_CTRL_CPU_RESET_W::new(self)
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    #[must_use]
    pub fn reg_ctrl_sys_reset(&mut self) -> REG_CTRL_SYS_RESET_W<2> {
        REG_CTRL_SYS_RESET_W::new(self)
    }
    #[doc = "Bits 4:7"]
    #[inline(always)]
    #[must_use]
    pub fn reg_ctrl_reset_dummy(&mut self) -> REG_CTRL_RESET_DUMMY_W<4> {
        REG_CTRL_RESET_DUMMY_W::new(self)
    }
    #[doc = "Bit 24"]
    #[inline(always)]
    #[must_use]
    pub fn pka_clk_sel(&mut self) -> PKA_CLK_SEL_W<24> {
        PKA_CLK_SEL_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "swrst_cfg2.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swrst_cfg2](index.html) module"]
pub struct SWRST_CFG2_SPEC;
impl crate::RegisterSpec for SWRST_CFG2_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [swrst_cfg2::R](R) reader structure"]
impl crate::Readable for SWRST_CFG2_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [swrst_cfg2::W](W) writer structure"]
impl crate::Writable for SWRST_CFG2_SPEC {
    type Writer = W;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets swrst_cfg2 to value 0"]
impl crate::Resettable for SWRST_CFG2_SPEC {
    const RESET_VALUE: Self::Ux = 0;
}