1#[doc = "Register `adda1` reader"]
2pub struct R(crate::R<ADDA1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ADDA1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ADDA1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ADDA1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `adda1` writer"]
17pub struct W(crate::W<ADDA1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ADDA1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ADDA1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ADDA1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `dac_dvdd_sel` reader - "]
38pub type DAC_DVDD_SEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `dac_dvdd_sel` writer - "]
40pub type DAC_DVDD_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDA1_SPEC, u8, u8, 2, O>;
41#[doc = "Field `dac_bias_sel` reader - "]
42pub type DAC_BIAS_SEL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `dac_bias_sel` writer - "]
44pub type DAC_BIAS_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDA1_SPEC, u8, u8, 2, O>;
45#[doc = "Field `dac_clk_sel` reader - "]
46pub type DAC_CLK_SEL_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `dac_clk_sel` writer - "]
48pub type DAC_CLK_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDA1_SPEC, u8, u8, 2, O>;
49#[doc = "Field `dac_rccalsel` reader - "]
50pub type DAC_RCCALSEL_R = crate::BitReader<bool>;
51#[doc = "Field `dac_rccalsel` writer - "]
52pub type DAC_RCCALSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA1_SPEC, bool, O>;
53#[doc = "Field `dac_clk_sync_inv` reader - "]
54pub type DAC_CLK_SYNC_INV_R = crate::BitReader<bool>;
55#[doc = "Field `dac_clk_sync_inv` writer - "]
56pub type DAC_CLK_SYNC_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA1_SPEC, bool, O>;
57#[doc = "Field `adda_ldo_byps` reader - "]
58pub type ADDA_LDO_BYPS_R = crate::BitReader<bool>;
59#[doc = "Field `adda_ldo_byps` writer - "]
60pub type ADDA_LDO_BYPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA1_SPEC, bool, O>;
61#[doc = "Field `adda_ldo_dvdd_sel` reader - "]
62pub type ADDA_LDO_DVDD_SEL_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `adda_ldo_dvdd_sel` writer - "]
64pub type ADDA_LDO_DVDD_SEL_W<'a, const O: u8> =
65 crate::FieldWriter<'a, u32, ADDA1_SPEC, u8, u8, 3, O>;
66#[doc = "Field `adda_ldo_dvdd_sel_hw` reader - "]
67pub type ADDA_LDO_DVDD_SEL_HW_R = crate::FieldReader<u8, u8>;
68#[doc = "Field `adda_ldo_dvdd_sel_hw` writer - "]
69pub type ADDA_LDO_DVDD_SEL_HW_W<'a, const O: u8> =
70 crate::FieldWriter<'a, u32, ADDA1_SPEC, u8, u8, 3, O>;
71impl R {
72 #[doc = "Bits 0:1"]
73 #[inline(always)]
74 pub fn dac_dvdd_sel(&self) -> DAC_DVDD_SEL_R {
75 DAC_DVDD_SEL_R::new((self.bits & 3) as u8)
76 }
77 #[doc = "Bits 4:5"]
78 #[inline(always)]
79 pub fn dac_bias_sel(&self) -> DAC_BIAS_SEL_R {
80 DAC_BIAS_SEL_R::new(((self.bits >> 4) & 3) as u8)
81 }
82 #[doc = "Bits 8:9"]
83 #[inline(always)]
84 pub fn dac_clk_sel(&self) -> DAC_CLK_SEL_R {
85 DAC_CLK_SEL_R::new(((self.bits >> 8) & 3) as u8)
86 }
87 #[doc = "Bit 12"]
88 #[inline(always)]
89 pub fn dac_rccalsel(&self) -> DAC_RCCALSEL_R {
90 DAC_RCCALSEL_R::new(((self.bits >> 12) & 1) != 0)
91 }
92 #[doc = "Bit 13"]
93 #[inline(always)]
94 pub fn dac_clk_sync_inv(&self) -> DAC_CLK_SYNC_INV_R {
95 DAC_CLK_SYNC_INV_R::new(((self.bits >> 13) & 1) != 0)
96 }
97 #[doc = "Bit 16"]
98 #[inline(always)]
99 pub fn adda_ldo_byps(&self) -> ADDA_LDO_BYPS_R {
100 ADDA_LDO_BYPS_R::new(((self.bits >> 16) & 1) != 0)
101 }
102 #[doc = "Bits 20:22"]
103 #[inline(always)]
104 pub fn adda_ldo_dvdd_sel(&self) -> ADDA_LDO_DVDD_SEL_R {
105 ADDA_LDO_DVDD_SEL_R::new(((self.bits >> 20) & 7) as u8)
106 }
107 #[doc = "Bits 24:26"]
108 #[inline(always)]
109 pub fn adda_ldo_dvdd_sel_hw(&self) -> ADDA_LDO_DVDD_SEL_HW_R {
110 ADDA_LDO_DVDD_SEL_HW_R::new(((self.bits >> 24) & 7) as u8)
111 }
112}
113impl W {
114 #[doc = "Bits 0:1"]
115 #[inline(always)]
116 #[must_use]
117 pub fn dac_dvdd_sel(&mut self) -> DAC_DVDD_SEL_W<0> {
118 DAC_DVDD_SEL_W::new(self)
119 }
120 #[doc = "Bits 4:5"]
121 #[inline(always)]
122 #[must_use]
123 pub fn dac_bias_sel(&mut self) -> DAC_BIAS_SEL_W<4> {
124 DAC_BIAS_SEL_W::new(self)
125 }
126 #[doc = "Bits 8:9"]
127 #[inline(always)]
128 #[must_use]
129 pub fn dac_clk_sel(&mut self) -> DAC_CLK_SEL_W<8> {
130 DAC_CLK_SEL_W::new(self)
131 }
132 #[doc = "Bit 12"]
133 #[inline(always)]
134 #[must_use]
135 pub fn dac_rccalsel(&mut self) -> DAC_RCCALSEL_W<12> {
136 DAC_RCCALSEL_W::new(self)
137 }
138 #[doc = "Bit 13"]
139 #[inline(always)]
140 #[must_use]
141 pub fn dac_clk_sync_inv(&mut self) -> DAC_CLK_SYNC_INV_W<13> {
142 DAC_CLK_SYNC_INV_W::new(self)
143 }
144 #[doc = "Bit 16"]
145 #[inline(always)]
146 #[must_use]
147 pub fn adda_ldo_byps(&mut self) -> ADDA_LDO_BYPS_W<16> {
148 ADDA_LDO_BYPS_W::new(self)
149 }
150 #[doc = "Bits 20:22"]
151 #[inline(always)]
152 #[must_use]
153 pub fn adda_ldo_dvdd_sel(&mut self) -> ADDA_LDO_DVDD_SEL_W<20> {
154 ADDA_LDO_DVDD_SEL_W::new(self)
155 }
156 #[doc = "Bits 24:26"]
157 #[inline(always)]
158 #[must_use]
159 pub fn adda_ldo_dvdd_sel_hw(&mut self) -> ADDA_LDO_DVDD_SEL_HW_W<24> {
160 ADDA_LDO_DVDD_SEL_HW_W::new(self)
161 }
162 #[doc = "Writes raw bits to the register."]
163 #[inline(always)]
164 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
165 self.0.bits(bits);
166 self
167 }
168}
169#[doc = "adda1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adda1](index.html) module"]
170pub struct ADDA1_SPEC;
171impl crate::RegisterSpec for ADDA1_SPEC {
172 type Ux = u32;
173}
174#[doc = "`read()` method returns [adda1::R](R) reader structure"]
175impl crate::Readable for ADDA1_SPEC {
176 type Reader = R;
177}
178#[doc = "`write(|w| ..)` method takes [adda1::W](W) writer structure"]
179impl crate::Writable for ADDA1_SPEC {
180 type Writer = W;
181 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
182 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
183}
184#[doc = "`reset()` method sets adda1 to value 0"]
185impl crate::Resettable for ADDA1_SPEC {
186 const RESET_VALUE: Self::Ux = 0;
187}