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bitloom_sim/
engine.rs

1//! Tick engines: AST interpreter vs a compiled assign schedule (FR32).
2
3use bitloom_hir::{AssignExpr, AssignTarget, FrozenHir, ProcessKind, Stmt};
4
5/// Select how `Sim::tick` evaluates FrozenHir.
6#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
7pub enum TickEngine {
8    /// Walk module processes each cycle (debugging-friendly).
9    #[default]
10    Interpreter,
11    /// Execute a linearized assign schedule compiled at `Sim` construction.
12    Compiled,
13}
14
15impl TickEngine {
16    /// Parse CLI / docs names: `interpreter` | `compiled`.
17    pub fn from_name(name: &str) -> Option<Self> {
18        match name {
19            "interpreter" | "interp" => Some(Self::Interpreter),
20            "compiled" | "compile" => Some(Self::Compiled),
21            _ => None,
22        }
23    }
24
25    pub fn as_str(self) -> &'static str {
26        match self {
27            Self::Interpreter => "interpreter",
28            Self::Compiled => "compiled",
29        }
30    }
31}
32
33pub(crate) struct CompiledKernel {
34    pub seq: Vec<(String, AssignExpr)>,
35    pub comb: Vec<(String, AssignExpr)>,
36}
37
38pub(crate) fn compile(hir: &FrozenHir) -> CompiledKernel {
39    let mut seq = Vec::new();
40    let mut comb = Vec::new();
41    if let Some(m) = hir.circuit().modules.first() {
42        for stmt in &m.body {
43            if let Stmt::Process(p) = stmt {
44                for a in &p.assigns {
45                    match (p.kind, &a.target) {
46                        (ProcessKind::Sequential, AssignTarget::RegD(name)) => {
47                            seq.push((name.clone(), a.expr.clone()));
48                        }
49                        (ProcessKind::Combinational, AssignTarget::Net(name)) => {
50                            comb.push((name.clone(), a.expr.clone()));
51                        }
52                        _ => {}
53                    }
54                }
55            }
56        }
57    }
58    CompiledKernel { seq, comb }
59}