bender 0.32.1

A dependency management tool for hardware projects.
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#!/usr/bin/env bash
# {{ HEADER_AUTOGEN }}
{% if abort_on_error %}# Set propagation of error to exit on first error
set -e
{% endif %}
ROOT="{{ root }}"
{# Separate compilation: one block per source group -#}
{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if group.file_type == 'verilog' or group.file_type == 'vhdl' %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
{% if group.file_type == 'verilog' %}{{ vlogan_bin }} -sverilog \
    -full64 \
    {% for tmp_arg in vlogan_args %}{{ tmp_arg }} \
    {% endfor %}{% for define in group.defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
    {% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
    {% endfor %}{% elif group.file_type == 'vhdl' %}{{ vhdlan_bin }} \
    {% for tmp_arg in vhdlan_args %}{{ tmp_arg }} \
    {% endfor %}{% endif %}{% for file in group.files %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
    {% endif %}{% endfor %}
{% else %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
# Skipping {{ group.files | length }} file(s) of unknown type (prefix with sv:/v:/vhd: to set one):
{% for file in group.files %}#   {{ file.file | replace(from=root, to='$ROOT') }}
{% endfor %}{% endif %}{% endfor %}
{# Common compilation: all files in one block -#}
{% else -%}
{# Verilog sources -#}
{%- for file in all_verilog %}{% if loop.first %}{{ vlogan_bin }} -sverilog \
    -full64 \
    {% for tmp_arg in vlogan_args %}{{ tmp_arg }} \
    {% endfor %}{% for define in all_defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
    {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
    {% endfor %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
    {% endif %}{% if loop.last %}
{% endif %}{% endfor %}
{# VHDL sources -#}
{% for file in all_vhdl %}{% if loop.first %}{{ vhdlan_bin }} \
    {% for tmp_arg in vhdlan_args %}{{ tmp_arg }} \
    {% endfor %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
    {% endif %}{% if loop.last %}
{% endif %}{% endfor %}
{% endif %}