bcinr — BranchlessCInRust (v26.9.28)

bcinr is a performance-first, research-grade systems library providing a principled calculus for branchless algorithmics. It is designed for high-performance, deterministic systems where predictable latency, memory-safety, and side-channel resilience are critical requirements.

Key Features

• Deterministic Latency: All primitives are branchless ($O(1)$ constant time), eliminating pipeline stalls and side-channel timing risks.
• $\mathcal{B}$-Calculus Formalism: Each primitive maps to a formal framework ensuring invariant-preserving state transitions.
• Hardware-Agnostic SIMD: SSE4.2 with verified portable fallbacks for ARM Neon and WebAssembly.
• Zero-Dependency Core: The logic layer is strictly no_std with zero external dependencies.
• POWL Runtime: Partially Ordered Workflow Language scheduler with cryptographic proof of execution (14 M instances/sec, single core).

Installation

[dependencies]
bcinr-logic = "26.9.28"   # core algorithms, no_std, zero deps
bcinr-powl  = "26.9.28"   # workflow scheduler + conformance gate

Quick Start

use bcinr_logic::mask::{select_u32, min_u32, max_u32};
use bcinr_logic::fix::add_sat;

// Branchless selection: mask 0xFFFFFFFF → first arg, 0x0 → second
let val = select_u32(0xFFFFFFFF, 10, 20);
assert_eq!(val, 10);

// Saturating arithmetic — never wraps past MAX
let sum = add_sat(u32::MAX, 1u32);
assert_eq!(sum, u32::MAX);

See examples/ for runnable witnesses (cargo run --example <name>).

POWL Workflow Runtime

bcinr-powl implements a formally verified, branchless scheduler for Partially Ordered Workflow Language (POWL) tapes with cryptographic proof of execution via a rolling BLAKE3 receipt chain.

Conformance gate   395 ps   (Q16.16 branchless predicate)
Scheduler tick     2.07 ns  (single op, SWAR bit-scan)
Full workflow      69.6 ns  (10-op chain, E2E with receipt)
Throughput         14 M instances/sec, single core
const_tick (N=4)  535 ps   (compile-time topology, Lever 4)

v26.6.24 — 1000× Engineering Roadmap

Three compounding performance levers, all implemented and benchmarked:

Benchmark delta (N=4 linear chain, Apple M-series):

Documentation (Diátaxis)

• Tutorials — implementing kernels, SIMD vectorization
• How-To Guides — side-channel hardening, WCET bounding
• Explanations — Branchless Calculus, architectural design
• References — full API catalog and specifications
• SA2A Boundary — bcinr_cmca::sa2a types and conservation invariants
• Anti-Patterns — structural hazards to avoid

Full Documentation Index

Formal Basis

The dual-audience arXiv/HBR paper (26 pages) covers formal proofs, Chicago TDD conformance theory, and Fortune 5 strategic framing: thesis.pdf — Agency at the Speed of Silicon

Performance

• Benchmark Charter — targets and measured baselines
• Architecture Overview — domain taxonomy and design philosophy

Development

make check    # compile all targets
make test     # full test suite
make clippy   # zero-warning lint
make bench    # Criterion benchmarks

License

Licensed under either of Apache License, Version 2.0 or MIT license at your option.