axvm 0.5.26

Virtual Machine resource management crate for ArceOS's hypervisor variant.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133

//! Transaction boundary for claiming one enabled per-CPU timer interrupt.

/// Host operations needed to configure and claim one per-CPU interrupt.
pub(crate) trait PerCpuIrqControl {
    type Claim;
    type Error;

    /// Configures the interrupt as level-triggered on one target CPU.
    fn configure_level(&mut self, cpu_id: usize, hwirq: u32) -> Result<(), Self::Error>;

    /// Exclusively claims and enables the interrupt on all target CPUs.
    fn request_enabled(
        &mut self,
        hwirq: u32,
        cpu_ids: &[usize],
    ) -> Result<Self::Claim, Self::Error>;
}

/// Configures every target CPU before publishing one enabled IRQ claim.
///
/// Level configuration is intentionally completed first. This keeps a failed
/// setup from exposing a partially configured interrupt through the host IRQ
/// registry.
pub(crate) fn claim_enabled_percpu_irq<C: PerCpuIrqControl>(
    control: &mut C,
    hwirq: u32,
    cpu_ids: &[usize],
) -> Result<C::Claim, C::Error> {
    for &cpu_id in cpu_ids {
        control.configure_level(cpu_id, hwirq)?;
    }
    control.request_enabled(hwirq, cpu_ids)
}

#[cfg(test)]
mod tests {
    use std::vec::Vec;

    use super::{PerCpuIrqControl, claim_enabled_percpu_irq};

    #[derive(Clone, Copy, Debug, Eq, PartialEq)]
    enum Operation {
        Configure { cpu_id: usize, hwirq: u32 },
        Claim { hwirq: u32, cpu_count: usize },
    }

    #[derive(Default)]
    struct RecordingControl {
        operations: Vec<Operation>,
        fail_configure_cpu: Option<usize>,
    }

    impl PerCpuIrqControl for RecordingControl {
        type Claim = u32;
        type Error = &'static str;

        fn configure_level(&mut self, cpu_id: usize, hwirq: u32) -> Result<(), Self::Error> {
            self.operations.push(Operation::Configure { cpu_id, hwirq });
            if self.fail_configure_cpu == Some(cpu_id) {
                return Err("configure failed");
            }
            Ok(())
        }

        fn request_enabled(
            &mut self,
            hwirq: u32,
            cpu_ids: &[usize],
        ) -> Result<Self::Claim, Self::Error> {
            self.operations.push(Operation::Claim {
                hwirq,
                cpu_count: cpu_ids.len(),
            });
            Ok(hwirq)
        }
    }

    #[test]
    fn configures_every_target_before_claiming_and_enabling_the_ppi() {
        let mut control = RecordingControl::default();

        let claim = claim_enabled_percpu_irq(&mut control, 27, &[0, 2, 3]).unwrap();

        assert_eq!(claim, 27);
        assert_eq!(
            control.operations,
            [
                Operation::Configure {
                    cpu_id: 0,
                    hwirq: 27,
                },
                Operation::Configure {
                    cpu_id: 2,
                    hwirq: 27,
                },
                Operation::Configure {
                    cpu_id: 3,
                    hwirq: 27,
                },
                Operation::Claim {
                    hwirq: 27,
                    cpu_count: 3,
                },
            ]
        );
    }

    #[test]
    fn configuration_failure_does_not_publish_an_irq_claim() {
        let mut control = RecordingControl {
            fail_configure_cpu: Some(2),
            ..RecordingControl::default()
        };

        assert_eq!(
            claim_enabled_percpu_irq(&mut control, 27, &[0, 2, 3]),
            Err("configure failed")
        );
        assert_eq!(
            control.operations,
            [
                Operation::Configure {
                    cpu_id: 0,
                    hwirq: 27,
                },
                Operation::Configure {
                    cpu_id: 2,
                    hwirq: 27,
                },
            ]
        );
    }
}