axi-uartlite 0.1.1

LogiCORE AXI UART Lite v2.0 driver
Documentation 
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AXI UARTLITE driver
========

This is a native Rust driver for the
[AMD AXI UART Lite v2.0 IP core](https://www.amd.com/en/products/adaptive-socs-and-fpgas/intellectual-property/axi_uartlite.html).

# Core features

- Basic driver which can be created with a given IP core base address and supports a basic
  byte-level read and write API.
- Support for [`embedded-io`](https://docs.rs/embedded-io/latest/embedded_io/) and
  [`embedded-io-async`](https://docs.rs/embedded-io-async/latest/embedded_io_async/)

# Features

If the asynchronous support for the TX side is used, the number of statically provided wakers
can be configured using the following features:

- `1-waker` which is the default
- `2-wakers`
- `4-wakers`
- `8-wakers`
- `16-wakers`
- `32-wakers`