use core::fmt::LowerHex;
use ax_memory_addr::AddrRange;
use super::{Port, SysRegAddr};
use crate::GuestPhysAddr;
pub trait DeviceAddr: Copy + Eq + Ord + core::fmt::Debug {}
pub trait DeviceAddrRange {
type Addr: DeviceAddr;
fn contains(&self, addr: Self::Addr) -> bool;
}
impl DeviceAddr for GuestPhysAddr {}
impl DeviceAddrRange for AddrRange<GuestPhysAddr> {
type Addr = GuestPhysAddr;
fn contains(&self, addr: Self::Addr) -> bool {
Self::contains(*self, addr)
}
}
impl DeviceAddr for SysRegAddr {}
#[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub struct SysRegAddrRange {
pub start: SysRegAddr,
pub end: SysRegAddr,
}
impl SysRegAddrRange {
pub fn new(start: SysRegAddr, end: SysRegAddr) -> Self {
Self { start, end }
}
}
impl DeviceAddrRange for SysRegAddrRange {
type Addr = SysRegAddr;
fn contains(&self, addr: Self::Addr) -> bool {
addr.0 >= self.start.0 && addr.0 <= self.end.0
}
}
impl LowerHex for SysRegAddrRange {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(f, "{:#x}..={:#x}", self.start.0, self.end.0)
}
}
impl DeviceAddr for Port {}
#[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub struct PortRange {
pub start: Port,
pub end: Port,
}
impl PortRange {
pub fn new(start: Port, end: Port) -> Self {
Self { start, end }
}
}
impl DeviceAddrRange for PortRange {
type Addr = Port;
fn contains(&self, addr: Self::Addr) -> bool {
addr.0 >= self.start.0 && addr.0 <= self.end.0
}
}
impl LowerHex for PortRange {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(f, "{:#x}..={:#x}", self.start.0, self.end.0)
}
}