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ax_cpu/
cap.rs

1//! CPU capability helpers.
2
3/// Returns the Linux-style `AT_HWCAP` value for the current architecture.
4///
5/// This reports only capabilities that the CPU/runtime layer can actually make
6/// available to user space. Architecture-specific auxiliary-vector layout is
7/// still owned by the OS layer.
8pub const fn elf_hwcap() -> usize {
9    #[cfg(target_arch = "loongarch64")]
10    {
11        // Linux loongarch HWCAP bits (uapi/asm/hwcap.h).
12        const HWCAP_LOONGARCH_CPUCFG: usize = 1 << 0;
13        const HWCAP_LOONGARCH_LAM: usize = 1 << 1;
14        const HWCAP_LOONGARCH_UAL: usize = 1 << 2;
15        const HWCAP_LOONGARCH_FPU: usize = 1 << 3;
16        const HWCAP_LOONGARCH_LSX: usize = 1 << 4;
17        const HWCAP_LOONGARCH_LASX: usize = 1 << 5;
18
19        HWCAP_LOONGARCH_CPUCFG
20            | HWCAP_LOONGARCH_LAM
21            | HWCAP_LOONGARCH_UAL
22            | HWCAP_LOONGARCH_FPU
23            | HWCAP_LOONGARCH_LSX
24            | HWCAP_LOONGARCH_LASX
25    }
26    #[cfg(target_arch = "riscv64")]
27    {
28        const RISCV_COMPAT_HWCAP_IMAFDC: usize = (1 << (b'I' - b'A'))
29            | (1 << (b'M' - b'A'))
30            | (1 << 0)
31            | (1 << (b'F' - b'A'))
32            | (1 << (b'D' - b'A'))
33            | (1 << (b'C' - b'A'));
34
35        RISCV_COMPAT_HWCAP_IMAFDC
36    }
37    #[cfg(not(any(target_arch = "loongarch64", target_arch = "riscv64")))]
38    {
39        0
40    }
41}
42
43/// Returns a conservative RISC-V Linux `hwprobe` value for a known key.
44///
45/// `None` means the key is unknown and the OS should report it as unsupported
46/// according to its ABI policy.
47#[cfg(target_arch = "riscv64")]
48pub const fn riscv_hwprobe(key: i64) -> Option<u64> {
49    const RISCV_HWPROBE_KEY_BASE_BEHAVIOR: i64 = 3;
50    const RISCV_HWPROBE_BASE_BEHAVIOR_IMA: u64 = 1 << 0;
51    const RISCV_HWPROBE_KEY_IMA_EXT_0: i64 = 4;
52    const RISCV_HWPROBE_IMA_FD: u64 = 1 << 0;
53    const RISCV_HWPROBE_IMA_C: u64 = 1 << 1;
54    const RISCV_HWPROBE_KEY_CPUPERF_0: i64 = 5;
55    const RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF: i64 = 9;
56    const RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF: i64 = 10;
57
58    match key {
59        RISCV_HWPROBE_KEY_BASE_BEHAVIOR => Some(RISCV_HWPROBE_BASE_BEHAVIOR_IMA),
60        RISCV_HWPROBE_KEY_IMA_EXT_0 => Some(RISCV_HWPROBE_IMA_FD | RISCV_HWPROBE_IMA_C),
61        RISCV_HWPROBE_KEY_CPUPERF_0
62        | RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF
63        | RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF => Some(0),
64        _ => None,
65    }
66}