ax-cpu 0.5.5

Privileged instruction and structure abstractions for various CPU architectures
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

.section .text

/*
 * unsigned long unaligned_read(void *addr, void *value, unsigned long n, bool sign)
 *
 * a0: addr
 * a1: value
 * a2: n
 * a3: sign
 */
.global _unaligned_read
_unaligned_read:
	beqz	$a2, 5f

	li.w	$t2, 0
	addi.d	$t0, $a2, -1
	slli.d	$t1, $t0, 3
	add.d 	$a0, $a0, $t0

	beqz	$a3, 2f
1:	ld.b	$t3, $a0, 0
	b	3f

2:	ld.bu	$t3, $a0, 0
3:	sll.d	$t3, $t3, $t1
	or	$t2, $t2, $t3
	addi.d	$t1, $t1, -8
	addi.d	$a0, $a0, -1
	addi.d	$a2, $a2, -1
	bgtz	$a2, 2b
4:	st.d	$t2, $a1, 0

	move	$a0, $a2
	jr	$ra

5:	li.w    $a0, -1
	jr	$ra

	_asm_extable 1b, 5b
	_asm_extable 2b, 5b
	_asm_extable 4b, 5b

/*
 * unsigned long unaligned_write(void *addr, unsigned long value, unsigned long n)
 *
 * a0: addr
 * a1: value
 * a2: n
 */
.global _unaligned_write
_unaligned_write:
	beqz	$a2, $3f

	li.w	$t0, 0
1:	srl.d	$t1, $a1, $t0
2:	st.b	$t1, $a0, 0
	addi.d	$t0, $t0, 8
	addi.d	$a2, $a2, -1
	addi.d	$a0, $a0, 1
	bgtz	$a2, 1b

	move	$a0, $a2
	jr	$ra

3:	li.w    $a0, -1
	jr	$ra

	_asm_extable 2b, 3b